4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
40 #else /* !CONFIG_USER_ONLY */
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
69 #include "qemu/mmap-alloc.h"
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
82 static MemoryRegion
*system_memory
;
83 static MemoryRegion
*system_io
;
85 AddressSpace address_space_io
;
86 AddressSpace address_space_memory
;
88 MemoryRegion io_mem_rom
, io_mem_notdirty
;
89 static MemoryRegion io_mem_unassigned
;
92 #ifdef TARGET_PAGE_BITS_VARY
94 bool target_page_bits_decided
;
97 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
98 /* current CPU in the current thread. It is only valid inside
100 __thread CPUState
*current_cpu
;
101 /* 0 = Do not count executed instructions.
102 1 = Precise instruction counting.
103 2 = Adaptive rate instruction counting. */
106 uintptr_t qemu_host_page_size
;
107 intptr_t qemu_host_page_mask
;
109 bool set_preferred_target_page_bits(int bits
)
111 /* The target page size is the lowest common denominator for all
112 * the CPUs in the system, so we can only make it smaller, never
113 * larger. And we can't make it smaller once we've committed to
116 #ifdef TARGET_PAGE_BITS_VARY
117 assert(bits
>= TARGET_PAGE_BITS_MIN
);
118 if (target_page_bits
== 0 || target_page_bits
> bits
) {
119 if (target_page_bits_decided
) {
122 target_page_bits
= bits
;
128 #if !defined(CONFIG_USER_ONLY)
130 static void finalize_target_page_bits(void)
132 #ifdef TARGET_PAGE_BITS_VARY
133 if (target_page_bits
== 0) {
134 target_page_bits
= TARGET_PAGE_BITS_MIN
;
136 target_page_bits_decided
= true;
140 typedef struct PhysPageEntry PhysPageEntry
;
142 struct PhysPageEntry
{
143 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
145 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
149 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
151 /* Size of the L2 (and L3, etc) page tables. */
152 #define ADDR_SPACE_BITS 64
155 #define P_L2_SIZE (1 << P_L2_BITS)
157 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
159 typedef PhysPageEntry Node
[P_L2_SIZE
];
161 typedef struct PhysPageMap
{
164 unsigned sections_nb
;
165 unsigned sections_nb_alloc
;
167 unsigned nodes_nb_alloc
;
169 MemoryRegionSection
*sections
;
172 struct AddressSpaceDispatch
{
173 MemoryRegionSection
*mru_section
;
174 /* This is a multi-level map on the physical address space.
175 * The bottom level has pointers to MemoryRegionSections.
177 PhysPageEntry phys_map
;
181 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
182 typedef struct subpage_t
{
186 uint16_t sub_section
[];
189 #define PHYS_SECTION_UNASSIGNED 0
190 #define PHYS_SECTION_NOTDIRTY 1
191 #define PHYS_SECTION_ROM 2
192 #define PHYS_SECTION_WATCH 3
194 static void io_mem_init(void);
195 static void memory_map_init(void);
196 static void tcg_commit(MemoryListener
*listener
);
198 static MemoryRegion io_mem_watch
;
201 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
202 * @cpu: the CPU whose AddressSpace this is
203 * @as: the AddressSpace itself
204 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
205 * @tcg_as_listener: listener for tracking changes to the AddressSpace
207 struct CPUAddressSpace
{
210 struct AddressSpaceDispatch
*memory_dispatch
;
211 MemoryListener tcg_as_listener
;
214 struct DirtyBitmapSnapshot
{
217 unsigned long dirty
[];
222 #if !defined(CONFIG_USER_ONLY)
224 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
226 static unsigned alloc_hint
= 16;
227 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
228 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
229 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
230 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
231 alloc_hint
= map
->nodes_nb_alloc
;
235 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
242 ret
= map
->nodes_nb
++;
244 assert(ret
!= PHYS_MAP_NODE_NIL
);
245 assert(ret
!= map
->nodes_nb_alloc
);
247 e
.skip
= leaf
? 0 : 1;
248 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
249 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
250 memcpy(&p
[i
], &e
, sizeof(e
));
255 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
256 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
260 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
262 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
263 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
265 p
= map
->nodes
[lp
->ptr
];
266 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
268 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
269 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
275 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
281 static void phys_page_set(AddressSpaceDispatch
*d
,
282 hwaddr index
, hwaddr nb
,
285 /* Wildly overreserve - it doesn't matter much. */
286 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
288 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
291 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
292 * and update our entry so we can skip it and go directly to the destination.
294 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
296 unsigned valid_ptr
= P_L2_SIZE
;
301 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
306 for (i
= 0; i
< P_L2_SIZE
; i
++) {
307 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
314 phys_page_compact(&p
[i
], nodes
);
318 /* We can only compress if there's only one child. */
323 assert(valid_ptr
< P_L2_SIZE
);
325 /* Don't compress if it won't fit in the # of bits we have. */
326 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
330 lp
->ptr
= p
[valid_ptr
].ptr
;
331 if (!p
[valid_ptr
].skip
) {
332 /* If our only child is a leaf, make this a leaf. */
333 /* By design, we should have made this node a leaf to begin with so we
334 * should never reach here.
335 * But since it's so simple to handle this, let's do it just in case we
340 lp
->skip
+= p
[valid_ptr
].skip
;
344 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
346 if (d
->phys_map
.skip
) {
347 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
351 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
354 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
355 * the section must cover the entire address space.
357 return int128_gethi(section
->size
) ||
358 range_covers_byte(section
->offset_within_address_space
,
359 int128_getlo(section
->size
), addr
);
362 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
364 PhysPageEntry lp
= d
->phys_map
, *p
;
365 Node
*nodes
= d
->map
.nodes
;
366 MemoryRegionSection
*sections
= d
->map
.sections
;
367 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
370 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
371 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
372 return §ions
[PHYS_SECTION_UNASSIGNED
];
375 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
378 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
379 return §ions
[lp
.ptr
];
381 return §ions
[PHYS_SECTION_UNASSIGNED
];
385 /* Called from RCU critical section */
386 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
388 bool resolve_subpage
)
390 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
393 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
394 !section_covers_addr(section
, addr
)) {
395 section
= phys_page_find(d
, addr
);
396 atomic_set(&d
->mru_section
, section
);
398 if (resolve_subpage
&& section
->mr
->subpage
) {
399 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
400 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
405 /* Called from RCU critical section */
406 static MemoryRegionSection
*
407 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
408 hwaddr
*plen
, bool resolve_subpage
)
410 MemoryRegionSection
*section
;
414 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
415 /* Compute offset within MemoryRegionSection */
416 addr
-= section
->offset_within_address_space
;
418 /* Compute offset within MemoryRegion */
419 *xlat
= addr
+ section
->offset_within_region
;
423 /* MMIO registers can be expected to perform full-width accesses based only
424 * on their address, without considering adjacent registers that could
425 * decode to completely different MemoryRegions. When such registers
426 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
427 * regions overlap wildly. For this reason we cannot clamp the accesses
430 * If the length is small (as is the case for address_space_ldl/stl),
431 * everything works fine. If the incoming length is large, however,
432 * the caller really has to do the clamping through memory_access_size.
434 if (memory_region_is_ram(mr
)) {
435 diff
= int128_sub(section
->size
, int128_make64(addr
));
436 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
442 * address_space_translate_iommu - translate an address through an IOMMU
443 * memory region and then through the target address space.
445 * @iommu_mr: the IOMMU memory region that we start the translation from
446 * @addr: the address to be translated through the MMU
447 * @xlat: the translated address offset within the destination memory region.
448 * It cannot be %NULL.
449 * @plen_out: valid read/write length of the translated address. It
451 * @page_mask_out: page mask for the translated address. This
452 * should only be meaningful for IOMMU translated
453 * addresses, since there may be huge pages that this bit
454 * would tell. It can be %NULL if we don't care about it.
455 * @is_write: whether the translation operation is for write
456 * @is_mmio: whether this can be MMIO, set true if it can
457 * @target_as: the address space targeted by the IOMMU
458 * @attrs: transaction attributes
460 * This function is called from RCU critical section. It is the common
461 * part of flatview_do_translate and address_space_translate_cached.
463 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
466 hwaddr
*page_mask_out
,
469 AddressSpace
**target_as
,
472 MemoryRegionSection
*section
;
473 hwaddr page_mask
= (hwaddr
)-1;
477 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
481 if (imrc
->attrs_to_index
) {
482 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
485 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
486 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
488 if (!(iotlb
.perm
& (1 << is_write
))) {
492 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
493 | (addr
& iotlb
.addr_mask
));
494 page_mask
&= iotlb
.addr_mask
;
495 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
496 *target_as
= iotlb
.target_as
;
498 section
= address_space_translate_internal(
499 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
502 iommu_mr
= memory_region_get_iommu(section
->mr
);
503 } while (unlikely(iommu_mr
));
506 *page_mask_out
= page_mask
;
511 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
515 * flatview_do_translate - translate an address in FlatView
517 * @fv: the flat view that we want to translate on
518 * @addr: the address to be translated in above address space
519 * @xlat: the translated address offset within memory region. It
521 * @plen_out: valid read/write length of the translated address. It
522 * can be @NULL when we don't care about it.
523 * @page_mask_out: page mask for the translated address. This
524 * should only be meaningful for IOMMU translated
525 * addresses, since there may be huge pages that this bit
526 * would tell. It can be @NULL if we don't care about it.
527 * @is_write: whether the translation operation is for write
528 * @is_mmio: whether this can be MMIO, set true if it can
529 * @target_as: the address space targeted by the IOMMU
530 * @attrs: memory transaction attributes
532 * This function is called from RCU critical section
534 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
538 hwaddr
*page_mask_out
,
541 AddressSpace
**target_as
,
544 MemoryRegionSection
*section
;
545 IOMMUMemoryRegion
*iommu_mr
;
546 hwaddr plen
= (hwaddr
)(-1);
552 section
= address_space_translate_internal(
553 flatview_to_dispatch(fv
), addr
, xlat
,
556 iommu_mr
= memory_region_get_iommu(section
->mr
);
557 if (unlikely(iommu_mr
)) {
558 return address_space_translate_iommu(iommu_mr
, xlat
,
559 plen_out
, page_mask_out
,
564 /* Not behind an IOMMU, use default page size. */
565 *page_mask_out
= ~TARGET_PAGE_MASK
;
571 /* Called from RCU critical section */
572 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
573 bool is_write
, MemTxAttrs attrs
)
575 MemoryRegionSection section
;
576 hwaddr xlat
, page_mask
;
579 * This can never be MMIO, and we don't really care about plen,
582 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
583 NULL
, &page_mask
, is_write
, false, &as
,
586 /* Illegal translation */
587 if (section
.mr
== &io_mem_unassigned
) {
591 /* Convert memory region offset into address space offset */
592 xlat
+= section
.offset_within_address_space
-
593 section
.offset_within_region
;
595 return (IOMMUTLBEntry
) {
597 .iova
= addr
& ~page_mask
,
598 .translated_addr
= xlat
& ~page_mask
,
599 .addr_mask
= page_mask
,
600 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
605 return (IOMMUTLBEntry
) {0};
608 /* Called from RCU critical section */
609 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
610 hwaddr
*plen
, bool is_write
,
614 MemoryRegionSection section
;
615 AddressSpace
*as
= NULL
;
617 /* This can be MMIO, so setup MMIO bit. */
618 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
619 is_write
, true, &as
, attrs
);
622 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
623 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
624 *plen
= MIN(page
, *plen
);
630 typedef struct TCGIOMMUNotifier
{
638 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
640 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
642 if (!notifier
->active
) {
645 tlb_flush(notifier
->cpu
);
646 notifier
->active
= false;
647 /* We leave the notifier struct on the list to avoid reallocating it later.
648 * Generally the number of IOMMUs a CPU deals with will be small.
649 * In any case we can't unregister the iommu notifier from a notify
654 static void tcg_register_iommu_notifier(CPUState
*cpu
,
655 IOMMUMemoryRegion
*iommu_mr
,
658 /* Make sure this CPU has an IOMMU notifier registered for this
659 * IOMMU/IOMMU index combination, so that we can flush its TLB
660 * when the IOMMU tells us the mappings we've cached have changed.
662 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
663 TCGIOMMUNotifier
*notifier
;
666 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
667 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
668 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
672 if (i
== cpu
->iommu_notifiers
->len
) {
673 /* Not found, add a new entry at the end of the array */
674 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
675 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
678 notifier
->iommu_idx
= iommu_idx
;
680 /* Rather than trying to register interest in the specific part
681 * of the iommu's address space that we've accessed and then
682 * expand it later as subsequent accesses touch more of it, we
683 * just register interest in the whole thing, on the assumption
684 * that iommu reconfiguration will be rare.
686 iommu_notifier_init(¬ifier
->n
,
687 tcg_iommu_unmap_notify
,
688 IOMMU_NOTIFIER_UNMAP
,
692 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
695 if (!notifier
->active
) {
696 notifier
->active
= true;
700 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
702 /* Destroy the CPU's notifier list */
704 TCGIOMMUNotifier
*notifier
;
706 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
707 notifier
= &g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
, i
);
708 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
710 g_array_free(cpu
->iommu_notifiers
, true);
713 /* Called from RCU critical section */
714 MemoryRegionSection
*
715 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
716 hwaddr
*xlat
, hwaddr
*plen
,
717 MemTxAttrs attrs
, int *prot
)
719 MemoryRegionSection
*section
;
720 IOMMUMemoryRegion
*iommu_mr
;
721 IOMMUMemoryRegionClass
*imrc
;
724 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
727 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
729 iommu_mr
= memory_region_get_iommu(section
->mr
);
734 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
736 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
737 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
738 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
739 * doesn't short-cut its translation table walk.
741 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
742 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
743 | (addr
& iotlb
.addr_mask
));
744 /* Update the caller's prot bits to remove permissions the IOMMU
745 * is giving us a failure response for. If we get down to no
746 * permissions left at all we can give up now.
748 if (!(iotlb
.perm
& IOMMU_RO
)) {
749 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
751 if (!(iotlb
.perm
& IOMMU_WO
)) {
752 *prot
&= ~PAGE_WRITE
;
759 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
762 assert(!memory_region_is_iommu(section
->mr
));
767 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
771 #if !defined(CONFIG_USER_ONLY)
773 static int cpu_common_post_load(void *opaque
, int version_id
)
775 CPUState
*cpu
= opaque
;
777 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
778 version_id is increased. */
779 cpu
->interrupt_request
&= ~0x01;
782 /* loadvm has just updated the content of RAM, bypassing the
783 * usual mechanisms that ensure we flush TBs for writes to
784 * memory we've translated code from. So we must flush all TBs,
785 * which will now be stale.
792 static int cpu_common_pre_load(void *opaque
)
794 CPUState
*cpu
= opaque
;
796 cpu
->exception_index
= -1;
801 static bool cpu_common_exception_index_needed(void *opaque
)
803 CPUState
*cpu
= opaque
;
805 return tcg_enabled() && cpu
->exception_index
!= -1;
808 static const VMStateDescription vmstate_cpu_common_exception_index
= {
809 .name
= "cpu_common/exception_index",
811 .minimum_version_id
= 1,
812 .needed
= cpu_common_exception_index_needed
,
813 .fields
= (VMStateField
[]) {
814 VMSTATE_INT32(exception_index
, CPUState
),
815 VMSTATE_END_OF_LIST()
819 static bool cpu_common_crash_occurred_needed(void *opaque
)
821 CPUState
*cpu
= opaque
;
823 return cpu
->crash_occurred
;
826 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
827 .name
= "cpu_common/crash_occurred",
829 .minimum_version_id
= 1,
830 .needed
= cpu_common_crash_occurred_needed
,
831 .fields
= (VMStateField
[]) {
832 VMSTATE_BOOL(crash_occurred
, CPUState
),
833 VMSTATE_END_OF_LIST()
837 const VMStateDescription vmstate_cpu_common
= {
838 .name
= "cpu_common",
840 .minimum_version_id
= 1,
841 .pre_load
= cpu_common_pre_load
,
842 .post_load
= cpu_common_post_load
,
843 .fields
= (VMStateField
[]) {
844 VMSTATE_UINT32(halted
, CPUState
),
845 VMSTATE_UINT32(interrupt_request
, CPUState
),
846 VMSTATE_END_OF_LIST()
848 .subsections
= (const VMStateDescription
*[]) {
849 &vmstate_cpu_common_exception_index
,
850 &vmstate_cpu_common_crash_occurred
,
857 CPUState
*qemu_get_cpu(int index
)
862 if (cpu
->cpu_index
== index
) {
870 #if !defined(CONFIG_USER_ONLY)
871 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
872 const char *prefix
, MemoryRegion
*mr
)
874 CPUAddressSpace
*newas
;
875 AddressSpace
*as
= g_new0(AddressSpace
, 1);
879 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
880 address_space_init(as
, mr
, as_name
);
883 /* Target code should have set num_ases before calling us */
884 assert(asidx
< cpu
->num_ases
);
887 /* address space 0 gets the convenience alias */
891 /* KVM cannot currently support multiple address spaces. */
892 assert(asidx
== 0 || !kvm_enabled());
894 if (!cpu
->cpu_ases
) {
895 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
898 newas
= &cpu
->cpu_ases
[asidx
];
902 newas
->tcg_as_listener
.commit
= tcg_commit
;
903 memory_listener_register(&newas
->tcg_as_listener
, as
);
907 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
909 /* Return the AddressSpace corresponding to the specified index */
910 return cpu
->cpu_ases
[asidx
].as
;
914 void cpu_exec_unrealizefn(CPUState
*cpu
)
916 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
918 cpu_list_remove(cpu
);
920 if (cc
->vmsd
!= NULL
) {
921 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
923 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
924 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
926 #ifndef CONFIG_USER_ONLY
927 tcg_iommu_free_notifier_list(cpu
);
931 Property cpu_common_props
[] = {
932 #ifndef CONFIG_USER_ONLY
933 /* Create a memory property for softmmu CPU object,
934 * so users can wire up its memory. (This can't go in qom/cpu.c
935 * because that file is compiled only once for both user-mode
936 * and system builds.) The default if no link is set up is to use
937 * the system address space.
939 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
942 DEFINE_PROP_END_OF_LIST(),
945 void cpu_exec_initfn(CPUState
*cpu
)
950 #ifndef CONFIG_USER_ONLY
951 cpu
->thread_id
= qemu_get_thread_id();
952 cpu
->memory
= system_memory
;
953 object_ref(OBJECT(cpu
->memory
));
957 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
959 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
960 static bool tcg_target_initialized
;
964 if (tcg_enabled() && !tcg_target_initialized
) {
965 tcg_target_initialized
= true;
966 cc
->tcg_initialize();
970 #ifndef CONFIG_USER_ONLY
971 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
972 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
974 if (cc
->vmsd
!= NULL
) {
975 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
978 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
));
982 const char *parse_cpu_model(const char *cpu_model
)
986 gchar
**model_pieces
;
987 const char *cpu_type
;
989 model_pieces
= g_strsplit(cpu_model
, ",", 2);
991 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
993 error_report("unable to find CPU model '%s'", model_pieces
[0]);
994 g_strfreev(model_pieces
);
998 cpu_type
= object_class_get_name(oc
);
1000 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1001 g_strfreev(model_pieces
);
1005 #if defined(CONFIG_USER_ONLY)
1006 void tb_invalidate_phys_addr(target_ulong addr
)
1009 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1013 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1015 tb_invalidate_phys_addr(pc
);
1018 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1020 ram_addr_t ram_addr
;
1024 if (!tcg_enabled()) {
1029 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1030 if (!(memory_region_is_ram(mr
)
1031 || memory_region_is_romd(mr
))) {
1035 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1036 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1040 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1043 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1044 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1046 /* Locks grabbed by tb_invalidate_phys_addr */
1047 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1048 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1053 #if defined(CONFIG_USER_ONLY)
1054 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1059 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1065 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1069 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1070 int flags
, CPUWatchpoint
**watchpoint
)
1075 /* Add a watchpoint. */
1076 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1077 int flags
, CPUWatchpoint
**watchpoint
)
1081 /* forbid ranges which are empty or run off the end of the address space */
1082 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1083 error_report("tried to set invalid watchpoint at %"
1084 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1087 wp
= g_malloc(sizeof(*wp
));
1093 /* keep all GDB-injected watchpoints in front */
1094 if (flags
& BP_GDB
) {
1095 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1097 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1100 tlb_flush_page(cpu
, addr
);
1107 /* Remove a specific watchpoint. */
1108 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1113 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1114 if (addr
== wp
->vaddr
&& len
== wp
->len
1115 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1116 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1123 /* Remove a specific watchpoint by reference. */
1124 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1126 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1128 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1133 /* Remove all matching watchpoints. */
1134 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1136 CPUWatchpoint
*wp
, *next
;
1138 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1139 if (wp
->flags
& mask
) {
1140 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1145 /* Return true if this watchpoint address matches the specified
1146 * access (ie the address range covered by the watchpoint overlaps
1147 * partially or completely with the address range covered by the
1150 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1154 /* We know the lengths are non-zero, but a little caution is
1155 * required to avoid errors in the case where the range ends
1156 * exactly at the top of the address space and so addr + len
1157 * wraps round to zero.
1159 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1160 vaddr addrend
= addr
+ len
- 1;
1162 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1167 /* Add a breakpoint. */
1168 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1169 CPUBreakpoint
**breakpoint
)
1173 bp
= g_malloc(sizeof(*bp
));
1178 /* keep all GDB-injected breakpoints in front */
1179 if (flags
& BP_GDB
) {
1180 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1182 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1185 breakpoint_invalidate(cpu
, pc
);
1193 /* Remove a specific breakpoint. */
1194 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1198 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1199 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1200 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1207 /* Remove a specific breakpoint by reference. */
1208 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1210 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1212 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1217 /* Remove all matching breakpoints. */
1218 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1220 CPUBreakpoint
*bp
, *next
;
1222 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1223 if (bp
->flags
& mask
) {
1224 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1229 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1230 CPU loop after each instruction */
1231 void cpu_single_step(CPUState
*cpu
, int enabled
)
1233 if (cpu
->singlestep_enabled
!= enabled
) {
1234 cpu
->singlestep_enabled
= enabled
;
1235 if (kvm_enabled()) {
1236 kvm_update_guest_debug(cpu
, 0);
1238 /* must flush all the translated code to avoid inconsistencies */
1239 /* XXX: only flush what is necessary */
1245 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1252 fprintf(stderr
, "qemu: fatal: ");
1253 vfprintf(stderr
, fmt
, ap
);
1254 fprintf(stderr
, "\n");
1255 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1256 if (qemu_log_separate()) {
1258 qemu_log("qemu: fatal: ");
1259 qemu_log_vprintf(fmt
, ap2
);
1261 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1269 #if defined(CONFIG_USER_ONLY)
1271 struct sigaction act
;
1272 sigfillset(&act
.sa_mask
);
1273 act
.sa_handler
= SIG_DFL
;
1275 sigaction(SIGABRT
, &act
, NULL
);
1281 #if !defined(CONFIG_USER_ONLY)
1282 /* Called from RCU critical section */
1283 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1287 block
= atomic_rcu_read(&ram_list
.mru_block
);
1288 if (block
&& addr
- block
->offset
< block
->max_length
) {
1291 RAMBLOCK_FOREACH(block
) {
1292 if (addr
- block
->offset
< block
->max_length
) {
1297 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1301 /* It is safe to write mru_block outside the iothread lock. This
1306 * xxx removed from list
1310 * call_rcu(reclaim_ramblock, xxx);
1313 * atomic_rcu_set is not needed here. The block was already published
1314 * when it was placed into the list. Here we're just making an extra
1315 * copy of the pointer.
1317 ram_list
.mru_block
= block
;
1321 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1328 assert(tcg_enabled());
1329 end
= TARGET_PAGE_ALIGN(start
+ length
);
1330 start
&= TARGET_PAGE_MASK
;
1333 block
= qemu_get_ram_block(start
);
1334 assert(block
== qemu_get_ram_block(end
- 1));
1335 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1337 tlb_reset_dirty(cpu
, start1
, length
);
1342 /* Note: start and end must be within the same ram block. */
1343 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1347 DirtyMemoryBlocks
*blocks
;
1348 unsigned long end
, page
;
1355 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1356 page
= start
>> TARGET_PAGE_BITS
;
1360 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1362 while (page
< end
) {
1363 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1364 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1365 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1367 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1374 if (dirty
&& tcg_enabled()) {
1375 tlb_reset_dirty_range_all(start
, length
);
1381 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1382 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1384 DirtyMemoryBlocks
*blocks
;
1385 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1386 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1387 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1388 DirtyBitmapSnapshot
*snap
;
1389 unsigned long page
, end
, dest
;
1391 snap
= g_malloc0(sizeof(*snap
) +
1392 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1393 snap
->start
= first
;
1396 page
= first
>> TARGET_PAGE_BITS
;
1397 end
= last
>> TARGET_PAGE_BITS
;
1402 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1404 while (page
< end
) {
1405 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1406 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1407 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1409 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1410 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1411 offset
>>= BITS_PER_LEVEL
;
1413 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1414 blocks
->blocks
[idx
] + offset
,
1417 dest
+= num
>> BITS_PER_LEVEL
;
1422 if (tcg_enabled()) {
1423 tlb_reset_dirty_range_all(start
, length
);
1429 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1433 unsigned long page
, end
;
1435 assert(start
>= snap
->start
);
1436 assert(start
+ length
<= snap
->end
);
1438 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1439 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1441 while (page
< end
) {
1442 if (test_bit(page
, snap
->dirty
)) {
1450 /* Called from RCU critical section */
1451 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1452 MemoryRegionSection
*section
,
1454 hwaddr paddr
, hwaddr xlat
,
1456 target_ulong
*address
)
1461 if (memory_region_is_ram(section
->mr
)) {
1463 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1464 if (!section
->readonly
) {
1465 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1467 iotlb
|= PHYS_SECTION_ROM
;
1470 AddressSpaceDispatch
*d
;
1472 d
= flatview_to_dispatch(section
->fv
);
1473 iotlb
= section
- d
->map
.sections
;
1477 /* Make accesses to pages with watchpoints go via the
1478 watchpoint trap routines. */
1479 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1480 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1481 /* Avoid trapping reads of pages with a write breakpoint. */
1482 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1483 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1484 *address
|= TLB_MMIO
;
1492 #endif /* defined(CONFIG_USER_ONLY) */
1494 #if !defined(CONFIG_USER_ONLY)
1496 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1498 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1500 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1501 qemu_anon_ram_alloc
;
1504 * Set a custom physical guest memory alloator.
1505 * Accelerators with unusual needs may need this. Hopefully, we can
1506 * get rid of it eventually.
1508 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1510 phys_mem_alloc
= alloc
;
1513 static uint16_t phys_section_add(PhysPageMap
*map
,
1514 MemoryRegionSection
*section
)
1516 /* The physical section number is ORed with a page-aligned
1517 * pointer to produce the iotlb entries. Thus it should
1518 * never overflow into the page-aligned value.
1520 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1522 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1523 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1524 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1525 map
->sections_nb_alloc
);
1527 map
->sections
[map
->sections_nb
] = *section
;
1528 memory_region_ref(section
->mr
);
1529 return map
->sections_nb
++;
1532 static void phys_section_destroy(MemoryRegion
*mr
)
1534 bool have_sub_page
= mr
->subpage
;
1536 memory_region_unref(mr
);
1538 if (have_sub_page
) {
1539 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1540 object_unref(OBJECT(&subpage
->iomem
));
1545 static void phys_sections_free(PhysPageMap
*map
)
1547 while (map
->sections_nb
> 0) {
1548 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1549 phys_section_destroy(section
->mr
);
1551 g_free(map
->sections
);
1555 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1557 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1559 hwaddr base
= section
->offset_within_address_space
1561 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1562 MemoryRegionSection subsection
= {
1563 .offset_within_address_space
= base
,
1564 .size
= int128_make64(TARGET_PAGE_SIZE
),
1568 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1570 if (!(existing
->mr
->subpage
)) {
1571 subpage
= subpage_init(fv
, base
);
1573 subsection
.mr
= &subpage
->iomem
;
1574 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1575 phys_section_add(&d
->map
, &subsection
));
1577 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1579 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1580 end
= start
+ int128_get64(section
->size
) - 1;
1581 subpage_register(subpage
, start
, end
,
1582 phys_section_add(&d
->map
, section
));
1586 static void register_multipage(FlatView
*fv
,
1587 MemoryRegionSection
*section
)
1589 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1590 hwaddr start_addr
= section
->offset_within_address_space
;
1591 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1592 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1596 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1599 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1601 MemoryRegionSection now
= *section
, remain
= *section
;
1602 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1604 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1605 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1606 - now
.offset_within_address_space
;
1608 now
.size
= int128_min(int128_make64(left
), now
.size
);
1609 register_subpage(fv
, &now
);
1611 now
.size
= int128_zero();
1613 while (int128_ne(remain
.size
, now
.size
)) {
1614 remain
.size
= int128_sub(remain
.size
, now
.size
);
1615 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1616 remain
.offset_within_region
+= int128_get64(now
.size
);
1618 if (int128_lt(remain
.size
, page_size
)) {
1619 register_subpage(fv
, &now
);
1620 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1621 now
.size
= page_size
;
1622 register_subpage(fv
, &now
);
1624 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1625 register_multipage(fv
, &now
);
1630 void qemu_flush_coalesced_mmio_buffer(void)
1633 kvm_flush_coalesced_mmio_buffer();
1636 void qemu_mutex_lock_ramlist(void)
1638 qemu_mutex_lock(&ram_list
.mutex
);
1641 void qemu_mutex_unlock_ramlist(void)
1643 qemu_mutex_unlock(&ram_list
.mutex
);
1646 void ram_block_dump(Monitor
*mon
)
1652 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1653 "Block Name", "PSize", "Offset", "Used", "Total");
1654 RAMBLOCK_FOREACH(block
) {
1655 psize
= size_to_str(block
->page_size
);
1656 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1657 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1658 (uint64_t)block
->offset
,
1659 (uint64_t)block
->used_length
,
1660 (uint64_t)block
->max_length
);
1668 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1669 * may or may not name the same files / on the same filesystem now as
1670 * when we actually open and map them. Iterate over the file
1671 * descriptors instead, and use qemu_fd_getpagesize().
1673 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1675 long *hpsize_min
= opaque
;
1677 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1678 long hpsize
= host_memory_backend_pagesize(MEMORY_BACKEND(obj
));
1680 if (hpsize
< *hpsize_min
) {
1681 *hpsize_min
= hpsize
;
1688 long qemu_getrampagesize(void)
1690 long hpsize
= LONG_MAX
;
1691 long mainrampagesize
;
1692 Object
*memdev_root
;
1694 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1696 /* it's possible we have memory-backend objects with
1697 * hugepage-backed RAM. these may get mapped into system
1698 * address space via -numa parameters or memory hotplug
1699 * hooks. we want to take these into account, but we
1700 * also want to make sure these supported hugepage
1701 * sizes are applicable across the entire range of memory
1702 * we may boot from, so we take the min across all
1703 * backends, and assume normal pages in cases where a
1704 * backend isn't backed by hugepages.
1706 memdev_root
= object_resolve_path("/objects", NULL
);
1708 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1710 if (hpsize
== LONG_MAX
) {
1711 /* No additional memory regions found ==> Report main RAM page size */
1712 return mainrampagesize
;
1715 /* If NUMA is disabled or the NUMA nodes are not backed with a
1716 * memory-backend, then there is at least one node using "normal" RAM,
1717 * so if its page size is smaller we have got to report that size instead.
1719 if (hpsize
> mainrampagesize
&&
1720 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1723 error_report("Huge page support disabled (n/a for main memory).");
1726 return mainrampagesize
;
1732 long qemu_getrampagesize(void)
1734 return getpagesize();
1739 static int64_t get_file_size(int fd
)
1741 int64_t size
= lseek(fd
, 0, SEEK_END
);
1748 static int file_ram_open(const char *path
,
1749 const char *region_name
,
1754 char *sanitized_name
;
1760 fd
= open(path
, O_RDWR
);
1762 /* @path names an existing file, use it */
1765 if (errno
== ENOENT
) {
1766 /* @path names a file that doesn't exist, create it */
1767 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1772 } else if (errno
== EISDIR
) {
1773 /* @path names a directory, create a file there */
1774 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1775 sanitized_name
= g_strdup(region_name
);
1776 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1782 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1784 g_free(sanitized_name
);
1786 fd
= mkstemp(filename
);
1794 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1795 error_setg_errno(errp
, errno
,
1796 "can't open backing store %s for guest RAM",
1801 * Try again on EINTR and EEXIST. The latter happens when
1802 * something else creates the file between our two open().
1809 static void *file_ram_alloc(RAMBlock
*block
,
1817 block
->page_size
= qemu_fd_getpagesize(fd
);
1818 if (block
->mr
->align
% block
->page_size
) {
1819 error_setg(errp
, "alignment 0x%" PRIx64
1820 " must be multiples of page size 0x%zx",
1821 block
->mr
->align
, block
->page_size
);
1823 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1824 error_setg(errp
, "alignment 0x%" PRIx64
1825 " must be a power of two", block
->mr
->align
);
1828 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1829 #if defined(__s390x__)
1830 if (kvm_enabled()) {
1831 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1835 if (memory
< block
->page_size
) {
1836 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1837 "or larger than page size 0x%zx",
1838 memory
, block
->page_size
);
1842 memory
= ROUND_UP(memory
, block
->page_size
);
1845 * ftruncate is not supported by hugetlbfs in older
1846 * hosts, so don't bother bailing out on errors.
1847 * If anything goes wrong with it under other filesystems,
1850 * Do not truncate the non-empty backend file to avoid corrupting
1851 * the existing data in the file. Disabling shrinking is not
1852 * enough. For example, the current vNVDIMM implementation stores
1853 * the guest NVDIMM labels at the end of the backend file. If the
1854 * backend file is later extended, QEMU will not be able to find
1855 * those labels. Therefore, extending the non-empty backend file
1856 * is disabled as well.
1858 if (truncate
&& ftruncate(fd
, memory
)) {
1859 perror("ftruncate");
1862 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1863 block
->flags
& RAM_SHARED
);
1864 if (area
== MAP_FAILED
) {
1865 error_setg_errno(errp
, errno
,
1866 "unable to map backing store for guest RAM");
1871 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1872 if (errp
&& *errp
) {
1873 qemu_ram_munmap(area
, memory
);
1883 /* Allocate space within the ram_addr_t space that governs the
1885 * Called with the ramlist lock held.
1887 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1889 RAMBlock
*block
, *next_block
;
1890 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1892 assert(size
!= 0); /* it would hand out same offset multiple times */
1894 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1898 RAMBLOCK_FOREACH(block
) {
1899 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1901 /* Align blocks to start on a 'long' in the bitmap
1902 * which makes the bitmap sync'ing take the fast path.
1904 candidate
= block
->offset
+ block
->max_length
;
1905 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1907 /* Search for the closest following block
1910 RAMBLOCK_FOREACH(next_block
) {
1911 if (next_block
->offset
>= candidate
) {
1912 next
= MIN(next
, next_block
->offset
);
1916 /* If it fits remember our place and remember the size
1917 * of gap, but keep going so that we might find a smaller
1918 * gap to fill so avoiding fragmentation.
1920 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1922 mingap
= next
- candidate
;
1925 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1928 if (offset
== RAM_ADDR_MAX
) {
1929 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1934 trace_find_ram_offset(size
, offset
);
1939 static unsigned long last_ram_page(void)
1942 ram_addr_t last
= 0;
1945 RAMBLOCK_FOREACH(block
) {
1946 last
= MAX(last
, block
->offset
+ block
->max_length
);
1949 return last
>> TARGET_PAGE_BITS
;
1952 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1956 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1957 if (!machine_dump_guest_core(current_machine
)) {
1958 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1960 perror("qemu_madvise");
1961 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1962 "but dump_guest_core=off specified\n");
1967 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1972 bool qemu_ram_is_shared(RAMBlock
*rb
)
1974 return rb
->flags
& RAM_SHARED
;
1977 /* Note: Only set at the start of postcopy */
1978 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
1980 return rb
->flags
& RAM_UF_ZEROPAGE
;
1983 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
1985 rb
->flags
|= RAM_UF_ZEROPAGE
;
1988 bool qemu_ram_is_migratable(RAMBlock
*rb
)
1990 return rb
->flags
& RAM_MIGRATABLE
;
1993 void qemu_ram_set_migratable(RAMBlock
*rb
)
1995 rb
->flags
|= RAM_MIGRATABLE
;
1998 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2000 rb
->flags
&= ~RAM_MIGRATABLE
;
2003 /* Called with iothread lock held. */
2004 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2009 assert(!new_block
->idstr
[0]);
2012 char *id
= qdev_get_dev_path(dev
);
2014 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2018 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2021 RAMBLOCK_FOREACH(block
) {
2022 if (block
!= new_block
&&
2023 !strcmp(block
->idstr
, new_block
->idstr
)) {
2024 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2032 /* Called with iothread lock held. */
2033 void qemu_ram_unset_idstr(RAMBlock
*block
)
2035 /* FIXME: arch_init.c assumes that this is not called throughout
2036 * migration. Ignore the problem since hot-unplug during migration
2037 * does not work anyway.
2040 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2044 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2046 return rb
->page_size
;
2049 /* Returns the largest size of page in use */
2050 size_t qemu_ram_pagesize_largest(void)
2055 RAMBLOCK_FOREACH(block
) {
2056 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2062 static int memory_try_enable_merging(void *addr
, size_t len
)
2064 if (!machine_mem_merge(current_machine
)) {
2065 /* disabled by the user */
2069 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2072 /* Only legal before guest might have detected the memory size: e.g. on
2073 * incoming migration, or right after reset.
2075 * As memory core doesn't know how is memory accessed, it is up to
2076 * resize callback to update device state and/or add assertions to detect
2077 * misuse, if necessary.
2079 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2083 newsize
= HOST_PAGE_ALIGN(newsize
);
2085 if (block
->used_length
== newsize
) {
2089 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2090 error_setg_errno(errp
, EINVAL
,
2091 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2092 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2093 newsize
, block
->used_length
);
2097 if (block
->max_length
< newsize
) {
2098 error_setg_errno(errp
, EINVAL
,
2099 "Length too large: %s: 0x" RAM_ADDR_FMT
2100 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2101 newsize
, block
->max_length
);
2105 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2106 block
->used_length
= newsize
;
2107 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2109 memory_region_set_size(block
->mr
, newsize
);
2110 if (block
->resized
) {
2111 block
->resized(block
->idstr
, newsize
, block
->host
);
2116 /* Called with ram_list.mutex held */
2117 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2118 ram_addr_t new_ram_size
)
2120 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2121 DIRTY_MEMORY_BLOCK_SIZE
);
2122 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2123 DIRTY_MEMORY_BLOCK_SIZE
);
2126 /* Only need to extend if block count increased */
2127 if (new_num_blocks
<= old_num_blocks
) {
2131 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2132 DirtyMemoryBlocks
*old_blocks
;
2133 DirtyMemoryBlocks
*new_blocks
;
2136 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2137 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2138 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2140 if (old_num_blocks
) {
2141 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2142 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2145 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2146 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2149 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2152 g_free_rcu(old_blocks
, rcu
);
2157 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2160 RAMBlock
*last_block
= NULL
;
2161 ram_addr_t old_ram_size
, new_ram_size
;
2164 old_ram_size
= last_ram_page();
2166 qemu_mutex_lock_ramlist();
2167 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2169 if (!new_block
->host
) {
2170 if (xen_enabled()) {
2171 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2172 new_block
->mr
, &err
);
2174 error_propagate(errp
, err
);
2175 qemu_mutex_unlock_ramlist();
2179 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2180 &new_block
->mr
->align
, shared
);
2181 if (!new_block
->host
) {
2182 error_setg_errno(errp
, errno
,
2183 "cannot set up guest memory '%s'",
2184 memory_region_name(new_block
->mr
));
2185 qemu_mutex_unlock_ramlist();
2188 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2192 new_ram_size
= MAX(old_ram_size
,
2193 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2194 if (new_ram_size
> old_ram_size
) {
2195 dirty_memory_extend(old_ram_size
, new_ram_size
);
2197 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2198 * QLIST (which has an RCU-friendly variant) does not have insertion at
2199 * tail, so save the last element in last_block.
2201 RAMBLOCK_FOREACH(block
) {
2203 if (block
->max_length
< new_block
->max_length
) {
2208 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2209 } else if (last_block
) {
2210 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2211 } else { /* list is empty */
2212 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2214 ram_list
.mru_block
= NULL
;
2216 /* Write list before version */
2219 qemu_mutex_unlock_ramlist();
2221 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2222 new_block
->used_length
,
2225 if (new_block
->host
) {
2226 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2227 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2228 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2229 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2230 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2235 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2236 uint32_t ram_flags
, int fd
,
2239 RAMBlock
*new_block
;
2240 Error
*local_err
= NULL
;
2243 /* Just support these ram flags by now. */
2244 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2246 if (xen_enabled()) {
2247 error_setg(errp
, "-mem-path not supported with Xen");
2251 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2253 "host lacks kvm mmu notifiers, -mem-path unsupported");
2257 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2259 * file_ram_alloc() needs to allocate just like
2260 * phys_mem_alloc, but we haven't bothered to provide
2264 "-mem-path not supported with this accelerator");
2268 size
= HOST_PAGE_ALIGN(size
);
2269 file_size
= get_file_size(fd
);
2270 if (file_size
> 0 && file_size
< size
) {
2271 error_setg(errp
, "backing store %s size 0x%" PRIx64
2272 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2273 mem_path
, file_size
, size
);
2277 new_block
= g_malloc0(sizeof(*new_block
));
2279 new_block
->used_length
= size
;
2280 new_block
->max_length
= size
;
2281 new_block
->flags
= ram_flags
;
2282 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2283 if (!new_block
->host
) {
2288 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2291 error_propagate(errp
, local_err
);
2299 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2300 uint32_t ram_flags
, const char *mem_path
,
2307 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2312 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2326 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2327 void (*resized
)(const char*,
2330 void *host
, bool resizeable
, bool share
,
2331 MemoryRegion
*mr
, Error
**errp
)
2333 RAMBlock
*new_block
;
2334 Error
*local_err
= NULL
;
2336 size
= HOST_PAGE_ALIGN(size
);
2337 max_size
= HOST_PAGE_ALIGN(max_size
);
2338 new_block
= g_malloc0(sizeof(*new_block
));
2340 new_block
->resized
= resized
;
2341 new_block
->used_length
= size
;
2342 new_block
->max_length
= max_size
;
2343 assert(max_size
>= size
);
2345 new_block
->page_size
= getpagesize();
2346 new_block
->host
= host
;
2348 new_block
->flags
|= RAM_PREALLOC
;
2351 new_block
->flags
|= RAM_RESIZEABLE
;
2353 ram_block_add(new_block
, &local_err
, share
);
2356 error_propagate(errp
, local_err
);
2362 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2363 MemoryRegion
*mr
, Error
**errp
)
2365 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2369 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2370 MemoryRegion
*mr
, Error
**errp
)
2372 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2376 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2377 void (*resized
)(const char*,
2380 MemoryRegion
*mr
, Error
**errp
)
2382 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2386 static void reclaim_ramblock(RAMBlock
*block
)
2388 if (block
->flags
& RAM_PREALLOC
) {
2390 } else if (xen_enabled()) {
2391 xen_invalidate_map_cache_entry(block
->host
);
2393 } else if (block
->fd
>= 0) {
2394 qemu_ram_munmap(block
->host
, block
->max_length
);
2398 qemu_anon_ram_free(block
->host
, block
->max_length
);
2403 void qemu_ram_free(RAMBlock
*block
)
2410 ram_block_notify_remove(block
->host
, block
->max_length
);
2413 qemu_mutex_lock_ramlist();
2414 QLIST_REMOVE_RCU(block
, next
);
2415 ram_list
.mru_block
= NULL
;
2416 /* Write list before version */
2419 call_rcu(block
, reclaim_ramblock
, rcu
);
2420 qemu_mutex_unlock_ramlist();
2424 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2431 RAMBLOCK_FOREACH(block
) {
2432 offset
= addr
- block
->offset
;
2433 if (offset
< block
->max_length
) {
2434 vaddr
= ramblock_ptr(block
, offset
);
2435 if (block
->flags
& RAM_PREALLOC
) {
2437 } else if (xen_enabled()) {
2441 if (block
->fd
>= 0) {
2442 flags
|= (block
->flags
& RAM_SHARED
?
2443 MAP_SHARED
: MAP_PRIVATE
);
2444 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2445 flags
, block
->fd
, offset
);
2448 * Remap needs to match alloc. Accelerators that
2449 * set phys_mem_alloc never remap. If they did,
2450 * we'd need a remap hook here.
2452 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2454 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2455 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2458 if (area
!= vaddr
) {
2459 error_report("Could not remap addr: "
2460 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2464 memory_try_enable_merging(vaddr
, length
);
2465 qemu_ram_setup_dump(vaddr
, length
);
2470 #endif /* !_WIN32 */
2472 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2473 * This should not be used for general purpose DMA. Use address_space_map
2474 * or address_space_rw instead. For local memory (e.g. video ram) that the
2475 * device owns, use memory_region_get_ram_ptr.
2477 * Called within RCU critical section.
2479 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2481 RAMBlock
*block
= ram_block
;
2483 if (block
== NULL
) {
2484 block
= qemu_get_ram_block(addr
);
2485 addr
-= block
->offset
;
2488 if (xen_enabled() && block
->host
== NULL
) {
2489 /* We need to check if the requested address is in the RAM
2490 * because we don't want to map the entire memory in QEMU.
2491 * In that case just map until the end of the page.
2493 if (block
->offset
== 0) {
2494 return xen_map_cache(addr
, 0, 0, false);
2497 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2499 return ramblock_ptr(block
, addr
);
2502 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2503 * but takes a size argument.
2505 * Called within RCU critical section.
2507 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2508 hwaddr
*size
, bool lock
)
2510 RAMBlock
*block
= ram_block
;
2515 if (block
== NULL
) {
2516 block
= qemu_get_ram_block(addr
);
2517 addr
-= block
->offset
;
2519 *size
= MIN(*size
, block
->max_length
- addr
);
2521 if (xen_enabled() && block
->host
== NULL
) {
2522 /* We need to check if the requested address is in the RAM
2523 * because we don't want to map the entire memory in QEMU.
2524 * In that case just map the requested area.
2526 if (block
->offset
== 0) {
2527 return xen_map_cache(addr
, *size
, lock
, lock
);
2530 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2533 return ramblock_ptr(block
, addr
);
2536 /* Return the offset of a hostpointer within a ramblock */
2537 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2539 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2540 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2541 assert(res
< rb
->max_length
);
2547 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2550 * ptr: Host pointer to look up
2551 * round_offset: If true round the result offset down to a page boundary
2552 * *ram_addr: set to result ram_addr
2553 * *offset: set to result offset within the RAMBlock
2555 * Returns: RAMBlock (or NULL if not found)
2557 * By the time this function returns, the returned pointer is not protected
2558 * by RCU anymore. If the caller is not within an RCU critical section and
2559 * does not hold the iothread lock, it must have other means of protecting the
2560 * pointer, such as a reference to the region that includes the incoming
2563 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2567 uint8_t *host
= ptr
;
2569 if (xen_enabled()) {
2570 ram_addr_t ram_addr
;
2572 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2573 block
= qemu_get_ram_block(ram_addr
);
2575 *offset
= ram_addr
- block
->offset
;
2582 block
= atomic_rcu_read(&ram_list
.mru_block
);
2583 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2587 RAMBLOCK_FOREACH(block
) {
2588 /* This case append when the block is not mapped. */
2589 if (block
->host
== NULL
) {
2592 if (host
- block
->host
< block
->max_length
) {
2601 *offset
= (host
- block
->host
);
2603 *offset
&= TARGET_PAGE_MASK
;
2610 * Finds the named RAMBlock
2612 * name: The name of RAMBlock to find
2614 * Returns: RAMBlock (or NULL if not found)
2616 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2620 RAMBLOCK_FOREACH(block
) {
2621 if (!strcmp(name
, block
->idstr
)) {
2629 /* Some of the softmmu routines need to translate from a host pointer
2630 (typically a TLB entry) back to a ram offset. */
2631 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2636 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2638 return RAM_ADDR_INVALID
;
2641 return block
->offset
+ offset
;
2644 /* Called within RCU critical section. */
2645 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2648 ram_addr_t ram_addr
,
2652 ndi
->ram_addr
= ram_addr
;
2653 ndi
->mem_vaddr
= mem_vaddr
;
2657 assert(tcg_enabled());
2658 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2659 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2660 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2664 /* Called within RCU critical section. */
2665 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2668 assert(tcg_enabled());
2669 page_collection_unlock(ndi
->pages
);
2673 /* Set both VGA and migration bits for simplicity and to remove
2674 * the notdirty callback faster.
2676 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2677 DIRTY_CLIENTS_NOCODE
);
2678 /* we remove the notdirty callback only if the code has been
2680 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2681 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2685 /* Called within RCU critical section. */
2686 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2687 uint64_t val
, unsigned size
)
2691 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2694 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2695 memory_notdirty_write_complete(&ndi
);
2698 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2699 unsigned size
, bool is_write
,
2705 static const MemoryRegionOps notdirty_mem_ops
= {
2706 .write
= notdirty_mem_write
,
2707 .valid
.accepts
= notdirty_mem_accepts
,
2708 .endianness
= DEVICE_NATIVE_ENDIAN
,
2710 .min_access_size
= 1,
2711 .max_access_size
= 8,
2715 .min_access_size
= 1,
2716 .max_access_size
= 8,
2721 /* Generate a debug exception if a watchpoint has been hit. */
2722 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2724 CPUState
*cpu
= current_cpu
;
2725 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2729 assert(tcg_enabled());
2730 if (cpu
->watchpoint_hit
) {
2731 /* We re-entered the check after replacing the TB. Now raise
2732 * the debug interrupt so that is will trigger after the
2733 * current instruction. */
2734 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2737 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2738 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2739 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2740 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2741 && (wp
->flags
& flags
)) {
2742 if (flags
== BP_MEM_READ
) {
2743 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2745 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2747 wp
->hitaddr
= vaddr
;
2748 wp
->hitattrs
= attrs
;
2749 if (!cpu
->watchpoint_hit
) {
2750 if (wp
->flags
& BP_CPU
&&
2751 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2752 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2755 cpu
->watchpoint_hit
= wp
;
2758 tb_check_watchpoint(cpu
);
2759 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2760 cpu
->exception_index
= EXCP_DEBUG
;
2764 /* Force execution of one insn next time. */
2765 cpu
->cflags_next_tb
= 1 | curr_cflags();
2767 cpu_loop_exit_noexc(cpu
);
2771 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2776 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2777 so these check for a hit then pass through to the normal out-of-line
2779 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2780 unsigned size
, MemTxAttrs attrs
)
2784 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2785 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2787 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2790 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2793 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2796 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2799 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2807 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2808 uint64_t val
, unsigned size
,
2812 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2813 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2815 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2818 address_space_stb(as
, addr
, val
, attrs
, &res
);
2821 address_space_stw(as
, addr
, val
, attrs
, &res
);
2824 address_space_stl(as
, addr
, val
, attrs
, &res
);
2827 address_space_stq(as
, addr
, val
, attrs
, &res
);
2834 static const MemoryRegionOps watch_mem_ops
= {
2835 .read_with_attrs
= watch_mem_read
,
2836 .write_with_attrs
= watch_mem_write
,
2837 .endianness
= DEVICE_NATIVE_ENDIAN
,
2839 .min_access_size
= 1,
2840 .max_access_size
= 8,
2844 .min_access_size
= 1,
2845 .max_access_size
= 8,
2850 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2851 MemTxAttrs attrs
, uint8_t *buf
, int len
);
2852 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2853 const uint8_t *buf
, int len
);
2854 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2855 bool is_write
, MemTxAttrs attrs
);
2857 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2858 unsigned len
, MemTxAttrs attrs
)
2860 subpage_t
*subpage
= opaque
;
2864 #if defined(DEBUG_SUBPAGE)
2865 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2866 subpage
, len
, addr
);
2868 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2872 *data
= ldn_p(buf
, len
);
2876 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2877 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2879 subpage_t
*subpage
= opaque
;
2882 #if defined(DEBUG_SUBPAGE)
2883 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2884 " value %"PRIx64
"\n",
2885 __func__
, subpage
, len
, addr
, value
);
2887 stn_p(buf
, len
, value
);
2888 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2891 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2892 unsigned len
, bool is_write
,
2895 subpage_t
*subpage
= opaque
;
2896 #if defined(DEBUG_SUBPAGE)
2897 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2898 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2901 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2902 len
, is_write
, attrs
);
2905 static const MemoryRegionOps subpage_ops
= {
2906 .read_with_attrs
= subpage_read
,
2907 .write_with_attrs
= subpage_write
,
2908 .impl
.min_access_size
= 1,
2909 .impl
.max_access_size
= 8,
2910 .valid
.min_access_size
= 1,
2911 .valid
.max_access_size
= 8,
2912 .valid
.accepts
= subpage_accepts
,
2913 .endianness
= DEVICE_NATIVE_ENDIAN
,
2916 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2921 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2923 idx
= SUBPAGE_IDX(start
);
2924 eidx
= SUBPAGE_IDX(end
);
2925 #if defined(DEBUG_SUBPAGE)
2926 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2927 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2929 for (; idx
<= eidx
; idx
++) {
2930 mmio
->sub_section
[idx
] = section
;
2936 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2940 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2943 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2944 NULL
, TARGET_PAGE_SIZE
);
2945 mmio
->iomem
.subpage
= true;
2946 #if defined(DEBUG_SUBPAGE)
2947 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2948 mmio
, base
, TARGET_PAGE_SIZE
);
2950 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2955 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2958 MemoryRegionSection section
= {
2961 .offset_within_address_space
= 0,
2962 .offset_within_region
= 0,
2963 .size
= int128_2_64(),
2966 return phys_section_add(map
, §ion
);
2969 static void readonly_mem_write(void *opaque
, hwaddr addr
,
2970 uint64_t val
, unsigned size
)
2972 /* Ignore any write to ROM. */
2975 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
2976 unsigned size
, bool is_write
,
2982 /* This will only be used for writes, because reads are special cased
2983 * to directly access the underlying host ram.
2985 static const MemoryRegionOps readonly_mem_ops
= {
2986 .write
= readonly_mem_write
,
2987 .valid
.accepts
= readonly_mem_accepts
,
2988 .endianness
= DEVICE_NATIVE_ENDIAN
,
2990 .min_access_size
= 1,
2991 .max_access_size
= 8,
2995 .min_access_size
= 1,
2996 .max_access_size
= 8,
3001 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3002 hwaddr index
, MemTxAttrs attrs
)
3004 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3005 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3006 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3007 MemoryRegionSection
*sections
= d
->map
.sections
;
3009 return §ions
[index
& ~TARGET_PAGE_MASK
];
3012 static void io_mem_init(void)
3014 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3015 NULL
, NULL
, UINT64_MAX
);
3016 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3019 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3020 * which can be called without the iothread mutex.
3022 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3024 memory_region_clear_global_locking(&io_mem_notdirty
);
3026 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3030 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3032 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3035 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3036 assert(n
== PHYS_SECTION_UNASSIGNED
);
3037 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3038 assert(n
== PHYS_SECTION_NOTDIRTY
);
3039 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3040 assert(n
== PHYS_SECTION_ROM
);
3041 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3042 assert(n
== PHYS_SECTION_WATCH
);
3044 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3049 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3051 phys_sections_free(&d
->map
);
3055 static void tcg_commit(MemoryListener
*listener
)
3057 CPUAddressSpace
*cpuas
;
3058 AddressSpaceDispatch
*d
;
3060 assert(tcg_enabled());
3061 /* since each CPU stores ram addresses in its TLB cache, we must
3062 reset the modified entries */
3063 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3064 cpu_reloading_memory_map();
3065 /* The CPU and TLB are protected by the iothread lock.
3066 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3067 * may have split the RCU critical section.
3069 d
= address_space_to_dispatch(cpuas
->as
);
3070 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3071 tlb_flush(cpuas
->cpu
);
3074 static void memory_map_init(void)
3076 system_memory
= g_malloc(sizeof(*system_memory
));
3078 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3079 address_space_init(&address_space_memory
, system_memory
, "memory");
3081 system_io
= g_malloc(sizeof(*system_io
));
3082 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3084 address_space_init(&address_space_io
, system_io
, "I/O");
3087 MemoryRegion
*get_system_memory(void)
3089 return system_memory
;
3092 MemoryRegion
*get_system_io(void)
3097 #endif /* !defined(CONFIG_USER_ONLY) */
3099 /* physical memory access (slow version, mainly for debug) */
3100 #if defined(CONFIG_USER_ONLY)
3101 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3102 uint8_t *buf
, int len
, int is_write
)
3109 page
= addr
& TARGET_PAGE_MASK
;
3110 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3113 flags
= page_get_flags(page
);
3114 if (!(flags
& PAGE_VALID
))
3117 if (!(flags
& PAGE_WRITE
))
3119 /* XXX: this code should not depend on lock_user */
3120 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3123 unlock_user(p
, addr
, l
);
3125 if (!(flags
& PAGE_READ
))
3127 /* XXX: this code should not depend on lock_user */
3128 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3131 unlock_user(p
, addr
, 0);
3142 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3145 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3146 addr
+= memory_region_get_ram_addr(mr
);
3148 /* No early return if dirty_log_mask is or becomes 0, because
3149 * cpu_physical_memory_set_dirty_range will still call
3150 * xen_modified_memory.
3152 if (dirty_log_mask
) {
3154 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3156 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3157 assert(tcg_enabled());
3158 tb_invalidate_phys_range(addr
, addr
+ length
);
3159 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3161 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3164 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3166 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3168 /* Regions are assumed to support 1-4 byte accesses unless
3169 otherwise specified. */
3170 if (access_size_max
== 0) {
3171 access_size_max
= 4;
3174 /* Bound the maximum access by the alignment of the address. */
3175 if (!mr
->ops
->impl
.unaligned
) {
3176 unsigned align_size_max
= addr
& -addr
;
3177 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3178 access_size_max
= align_size_max
;
3182 /* Don't attempt accesses larger than the maximum. */
3183 if (l
> access_size_max
) {
3184 l
= access_size_max
;
3191 static bool prepare_mmio_access(MemoryRegion
*mr
)
3193 bool unlocked
= !qemu_mutex_iothread_locked();
3194 bool release_lock
= false;
3196 if (unlocked
&& mr
->global_locking
) {
3197 qemu_mutex_lock_iothread();
3199 release_lock
= true;
3201 if (mr
->flush_coalesced_mmio
) {
3203 qemu_mutex_lock_iothread();
3205 qemu_flush_coalesced_mmio_buffer();
3207 qemu_mutex_unlock_iothread();
3211 return release_lock
;
3214 /* Called within RCU critical section. */
3215 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3218 int len
, hwaddr addr1
,
3219 hwaddr l
, MemoryRegion
*mr
)
3223 MemTxResult result
= MEMTX_OK
;
3224 bool release_lock
= false;
3227 if (!memory_access_is_direct(mr
, true)) {
3228 release_lock
|= prepare_mmio_access(mr
);
3229 l
= memory_access_size(mr
, l
, addr1
);
3230 /* XXX: could force current_cpu to NULL to avoid
3232 val
= ldn_p(buf
, l
);
3233 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3236 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3237 memcpy(ptr
, buf
, l
);
3238 invalidate_and_set_dirty(mr
, addr1
, l
);
3242 qemu_mutex_unlock_iothread();
3243 release_lock
= false;
3255 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3261 /* Called from RCU critical section. */
3262 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3263 const uint8_t *buf
, int len
)
3268 MemTxResult result
= MEMTX_OK
;
3271 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3272 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3278 /* Called within RCU critical section. */
3279 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3280 MemTxAttrs attrs
, uint8_t *buf
,
3281 int len
, hwaddr addr1
, hwaddr l
,
3286 MemTxResult result
= MEMTX_OK
;
3287 bool release_lock
= false;
3290 if (!memory_access_is_direct(mr
, false)) {
3292 release_lock
|= prepare_mmio_access(mr
);
3293 l
= memory_access_size(mr
, l
, addr1
);
3294 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3298 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3299 memcpy(buf
, ptr
, l
);
3303 qemu_mutex_unlock_iothread();
3304 release_lock
= false;
3316 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3322 /* Called from RCU critical section. */
3323 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3324 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3331 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3332 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3336 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3337 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3339 MemTxResult result
= MEMTX_OK
;
3344 fv
= address_space_to_flatview(as
);
3345 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3352 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3354 const uint8_t *buf
, int len
)
3356 MemTxResult result
= MEMTX_OK
;
3361 fv
= address_space_to_flatview(as
);
3362 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3369 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3370 uint8_t *buf
, int len
, bool is_write
)
3373 return address_space_write(as
, addr
, attrs
, buf
, len
);
3375 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3379 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3380 int len
, int is_write
)
3382 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3383 buf
, len
, is_write
);
3386 enum write_rom_type
{
3391 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3392 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3402 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true,
3403 MEMTXATTRS_UNSPECIFIED
);
3405 if (!(memory_region_is_ram(mr
) ||
3406 memory_region_is_romd(mr
))) {
3407 l
= memory_access_size(mr
, l
, addr1
);
3410 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3413 memcpy(ptr
, buf
, l
);
3414 invalidate_and_set_dirty(mr
, addr1
, l
);
3417 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3428 /* used for ROM loading : can write in RAM and ROM */
3429 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3430 const uint8_t *buf
, int len
)
3432 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3435 void cpu_flush_icache_range(hwaddr start
, int len
)
3438 * This function should do the same thing as an icache flush that was
3439 * triggered from within the guest. For TCG we are always cache coherent,
3440 * so there is no need to flush anything. For KVM / Xen we need to flush
3441 * the host's instruction cache at least.
3443 if (tcg_enabled()) {
3447 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3448 start
, NULL
, len
, FLUSH_CACHE
);
3459 static BounceBuffer bounce
;
3461 typedef struct MapClient
{
3463 QLIST_ENTRY(MapClient
) link
;
3466 QemuMutex map_client_list_lock
;
3467 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3468 = QLIST_HEAD_INITIALIZER(map_client_list
);
3470 static void cpu_unregister_map_client_do(MapClient
*client
)
3472 QLIST_REMOVE(client
, link
);
3476 static void cpu_notify_map_clients_locked(void)
3480 while (!QLIST_EMPTY(&map_client_list
)) {
3481 client
= QLIST_FIRST(&map_client_list
);
3482 qemu_bh_schedule(client
->bh
);
3483 cpu_unregister_map_client_do(client
);
3487 void cpu_register_map_client(QEMUBH
*bh
)
3489 MapClient
*client
= g_malloc(sizeof(*client
));
3491 qemu_mutex_lock(&map_client_list_lock
);
3493 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3494 if (!atomic_read(&bounce
.in_use
)) {
3495 cpu_notify_map_clients_locked();
3497 qemu_mutex_unlock(&map_client_list_lock
);
3500 void cpu_exec_init_all(void)
3502 qemu_mutex_init(&ram_list
.mutex
);
3503 /* The data structures we set up here depend on knowing the page size,
3504 * so no more changes can be made after this point.
3505 * In an ideal world, nothing we did before we had finished the
3506 * machine setup would care about the target page size, and we could
3507 * do this much later, rather than requiring board models to state
3508 * up front what their requirements are.
3510 finalize_target_page_bits();
3513 qemu_mutex_init(&map_client_list_lock
);
3516 void cpu_unregister_map_client(QEMUBH
*bh
)
3520 qemu_mutex_lock(&map_client_list_lock
);
3521 QLIST_FOREACH(client
, &map_client_list
, link
) {
3522 if (client
->bh
== bh
) {
3523 cpu_unregister_map_client_do(client
);
3527 qemu_mutex_unlock(&map_client_list_lock
);
3530 static void cpu_notify_map_clients(void)
3532 qemu_mutex_lock(&map_client_list_lock
);
3533 cpu_notify_map_clients_locked();
3534 qemu_mutex_unlock(&map_client_list_lock
);
3537 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3538 bool is_write
, MemTxAttrs attrs
)
3545 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3546 if (!memory_access_is_direct(mr
, is_write
)) {
3547 l
= memory_access_size(mr
, l
, addr
);
3548 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3559 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3560 int len
, bool is_write
,
3567 fv
= address_space_to_flatview(as
);
3568 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3574 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3576 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3577 bool is_write
, MemTxAttrs attrs
)
3581 MemoryRegion
*this_mr
;
3587 if (target_len
== 0) {
3592 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3593 &len
, is_write
, attrs
);
3594 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3600 /* Map a physical memory region into a host virtual address.
3601 * May map a subset of the requested range, given by and returned in *plen.
3602 * May return NULL if resources needed to perform the mapping are exhausted.
3603 * Use only for reads OR writes - not for read-modify-write operations.
3604 * Use cpu_register_map_client() to know when retrying the map operation is
3605 * likely to succeed.
3607 void *address_space_map(AddressSpace
*as
,
3625 fv
= address_space_to_flatview(as
);
3626 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3628 if (!memory_access_is_direct(mr
, is_write
)) {
3629 if (atomic_xchg(&bounce
.in_use
, true)) {
3633 /* Avoid unbounded allocations */
3634 l
= MIN(l
, TARGET_PAGE_SIZE
);
3635 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3639 memory_region_ref(mr
);
3642 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3648 return bounce
.buffer
;
3652 memory_region_ref(mr
);
3653 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3654 l
, is_write
, attrs
);
3655 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3661 /* Unmaps a memory region previously mapped by address_space_map().
3662 * Will also mark the memory as dirty if is_write == 1. access_len gives
3663 * the amount of memory that was actually read or written by the caller.
3665 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3666 int is_write
, hwaddr access_len
)
3668 if (buffer
!= bounce
.buffer
) {
3672 mr
= memory_region_from_host(buffer
, &addr1
);
3675 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3677 if (xen_enabled()) {
3678 xen_invalidate_map_cache_entry(buffer
);
3680 memory_region_unref(mr
);
3684 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3685 bounce
.buffer
, access_len
);
3687 qemu_vfree(bounce
.buffer
);
3688 bounce
.buffer
= NULL
;
3689 memory_region_unref(bounce
.mr
);
3690 atomic_mb_set(&bounce
.in_use
, false);
3691 cpu_notify_map_clients();
3694 void *cpu_physical_memory_map(hwaddr addr
,
3698 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3699 MEMTXATTRS_UNSPECIFIED
);
3702 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3703 int is_write
, hwaddr access_len
)
3705 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3708 #define ARG1_DECL AddressSpace *as
3711 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3712 #define RCU_READ_LOCK(...) rcu_read_lock()
3713 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3714 #include "memory_ldst.inc.c"
3716 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3722 AddressSpaceDispatch
*d
;
3729 cache
->fv
= address_space_get_flatview(as
);
3730 d
= flatview_to_dispatch(cache
->fv
);
3731 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3734 memory_region_ref(mr
);
3735 if (memory_access_is_direct(mr
, is_write
)) {
3736 /* We don't care about the memory attributes here as we're only
3737 * doing this if we found actual RAM, which behaves the same
3738 * regardless of attributes; so UNSPECIFIED is fine.
3740 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3741 cache
->xlat
, l
, is_write
,
3742 MEMTXATTRS_UNSPECIFIED
);
3743 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3749 cache
->is_write
= is_write
;
3753 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3757 assert(cache
->is_write
);
3758 if (likely(cache
->ptr
)) {
3759 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3763 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3765 if (!cache
->mrs
.mr
) {
3769 if (xen_enabled()) {
3770 xen_invalidate_map_cache_entry(cache
->ptr
);
3772 memory_region_unref(cache
->mrs
.mr
);
3773 flatview_unref(cache
->fv
);
3774 cache
->mrs
.mr
= NULL
;
3778 /* Called from RCU critical section. This function has the same
3779 * semantics as address_space_translate, but it only works on a
3780 * predefined range of a MemoryRegion that was mapped with
3781 * address_space_cache_init.
3783 static inline MemoryRegion
*address_space_translate_cached(
3784 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3785 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3787 MemoryRegionSection section
;
3789 IOMMUMemoryRegion
*iommu_mr
;
3790 AddressSpace
*target_as
;
3792 assert(!cache
->ptr
);
3793 *xlat
= addr
+ cache
->xlat
;
3796 iommu_mr
= memory_region_get_iommu(mr
);
3802 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3803 NULL
, is_write
, true,
3808 /* Called from RCU critical section. address_space_read_cached uses this
3809 * out of line function when the target is an MMIO or IOMMU region.
3812 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3819 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3820 MEMTXATTRS_UNSPECIFIED
);
3821 flatview_read_continue(cache
->fv
,
3822 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3826 /* Called from RCU critical section. address_space_write_cached uses this
3827 * out of line function when the target is an MMIO or IOMMU region.
3830 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3831 const void *buf
, int len
)
3837 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3838 MEMTXATTRS_UNSPECIFIED
);
3839 flatview_write_continue(cache
->fv
,
3840 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3844 #define ARG1_DECL MemoryRegionCache *cache
3846 #define SUFFIX _cached_slow
3847 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3848 #define RCU_READ_LOCK() ((void)0)
3849 #define RCU_READ_UNLOCK() ((void)0)
3850 #include "memory_ldst.inc.c"
3852 /* virtual memory access for debug (includes writing to ROM) */
3853 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3854 uint8_t *buf
, int len
, int is_write
)
3860 cpu_synchronize_state(cpu
);
3865 page
= addr
& TARGET_PAGE_MASK
;
3866 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3867 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3868 /* if no physical page mapped, return an error */
3869 if (phys_addr
== -1)
3871 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3874 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3876 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3879 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3880 MEMTXATTRS_UNSPECIFIED
,
3891 * Allows code that needs to deal with migration bitmaps etc to still be built
3892 * target independent.
3894 size_t qemu_target_page_size(void)
3896 return TARGET_PAGE_SIZE
;
3899 int qemu_target_page_bits(void)
3901 return TARGET_PAGE_BITS
;
3904 int qemu_target_page_bits_min(void)
3906 return TARGET_PAGE_BITS_MIN
;
3910 bool target_words_bigendian(void)
3912 #if defined(TARGET_WORDS_BIGENDIAN)
3919 #ifndef CONFIG_USER_ONLY
3920 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3927 mr
= address_space_translate(&address_space_memory
,
3928 phys_addr
, &phys_addr
, &l
, false,
3929 MEMTXATTRS_UNSPECIFIED
);
3931 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3936 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3942 RAMBLOCK_FOREACH(block
) {
3943 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3944 block
->used_length
, opaque
);
3953 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func
, void *opaque
)
3959 RAMBLOCK_FOREACH(block
) {
3960 if (!qemu_ram_is_migratable(block
)) {
3963 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3964 block
->used_length
, opaque
);
3974 * Unmap pages of memory from start to start+length such that
3975 * they a) read as 0, b) Trigger whatever fault mechanism
3976 * the OS provides for postcopy.
3977 * The pages must be unmapped by the end of the function.
3978 * Returns: 0 on success, none-0 on failure
3981 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
3985 uint8_t *host_startaddr
= rb
->host
+ start
;
3987 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
3988 error_report("ram_block_discard_range: Unaligned start address: %p",
3993 if ((start
+ length
) <= rb
->used_length
) {
3994 bool need_madvise
, need_fallocate
;
3995 uint8_t *host_endaddr
= host_startaddr
+ length
;
3996 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
3997 error_report("ram_block_discard_range: Unaligned end address: %p",
4002 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4004 /* The logic here is messy;
4005 * madvise DONTNEED fails for hugepages
4006 * fallocate works on hugepages and shmem
4008 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4009 need_fallocate
= rb
->fd
!= -1;
4010 if (need_fallocate
) {
4011 /* For a file, this causes the area of the file to be zero'd
4012 * if read, and for hugetlbfs also causes it to be unmapped
4013 * so a userfault will trigger.
4015 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4016 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4020 error_report("ram_block_discard_range: Failed to fallocate "
4021 "%s:%" PRIx64
" +%zx (%d)",
4022 rb
->idstr
, start
, length
, ret
);
4027 error_report("ram_block_discard_range: fallocate not available/file"
4028 "%s:%" PRIx64
" +%zx (%d)",
4029 rb
->idstr
, start
, length
, ret
);
4034 /* For normal RAM this causes it to be unmapped,
4035 * for shared memory it causes the local mapping to disappear
4036 * and to fall back on the file contents (which we just
4037 * fallocate'd away).
4039 #if defined(CONFIG_MADVISE)
4040 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4043 error_report("ram_block_discard_range: Failed to discard range "
4044 "%s:%" PRIx64
" +%zx (%d)",
4045 rb
->idstr
, start
, length
, ret
);
4050 error_report("ram_block_discard_range: MADVISE not available"
4051 "%s:%" PRIx64
" +%zx (%d)",
4052 rb
->idstr
, start
, length
, ret
);
4056 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4057 need_madvise
, need_fallocate
, ret
);
4059 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4060 "/%zx/" RAM_ADDR_FMT
")",
4061 rb
->idstr
, start
, length
, rb
->used_length
);
4068 bool ramblock_is_pmem(RAMBlock
*rb
)
4070 return rb
->flags
& RAM_PMEM
;
4075 void page_size_init(void)
4077 /* NOTE: we can always suppose that qemu_host_page_size >=
4079 if (qemu_host_page_size
== 0) {
4080 qemu_host_page_size
= qemu_real_host_page_size
;
4082 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4083 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4085 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4088 #if !defined(CONFIG_USER_ONLY)
4090 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
4091 int start
, int end
, int skip
, int ptr
)
4093 if (start
== end
- 1) {
4094 mon(f
, "\t%3d ", start
);
4096 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
4098 mon(f
, " skip=%d ", skip
);
4099 if (ptr
== PHYS_MAP_NODE_NIL
) {
4102 mon(f
, " ptr=#%d", ptr
);
4104 mon(f
, " ptr=[%d]", ptr
);
4109 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4110 int128_sub((size), int128_one())) : 0)
4112 void mtree_print_dispatch(fprintf_function mon
, void *f
,
4113 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4117 mon(f
, " Dispatch\n");
4118 mon(f
, " Physical sections\n");
4120 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4121 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4122 const char *names
[] = { " [unassigned]", " [not dirty]",
4123 " [ROM]", " [watch]" };
4125 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
4127 s
->offset_within_address_space
,
4128 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4129 s
->mr
->name
? s
->mr
->name
: "(noname)",
4130 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4131 s
->mr
== root
? " [ROOT]" : "",
4132 s
== d
->mru_section
? " [MRU]" : "",
4133 s
->mr
->is_iommu
? " [iommu]" : "");
4136 mon(f
, " alias=%s", s
->mr
->alias
->name
?
4137 s
->mr
->alias
->name
: "noname");
4142 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4143 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4144 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4147 Node
*n
= d
->map
.nodes
+ i
;
4149 mon(f
, " [%d]\n", i
);
4151 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4152 PhysPageEntry
*pe
= *n
+ j
;
4154 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4158 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
4164 if (jprev
!= ARRAY_SIZE(*n
)) {
4165 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);