json: Replace %I64d, %I64u by %PRId64, %PRIu64
[qemu/ar7.git] / hw / ssi / xilinx_spips.c
blob16f88f74029748c100a030ad4a9ccbc74936f37d
1 /*
2 * QEMU model of the Xilinx Zynq SPI controller
4 * Copyright (c) 2012 Peter A. G. Crosthwaite
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/ptimer.h"
29 #include "qemu/log.h"
30 #include "qemu/bitops.h"
31 #include "hw/ssi/xilinx_spips.h"
32 #include "qapi/error.h"
33 #include "hw/register.h"
34 #include "sysemu/dma.h"
35 #include "migration/blocker.h"
37 #ifndef XILINX_SPIPS_ERR_DEBUG
38 #define XILINX_SPIPS_ERR_DEBUG 0
39 #endif
41 #define DB_PRINT_L(level, ...) do { \
42 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
43 fprintf(stderr, ": %s: ", __func__); \
44 fprintf(stderr, ## __VA_ARGS__); \
45 } \
46 } while (0)
48 /* config register */
49 #define R_CONFIG (0x00 / 4)
50 #define IFMODE (1U << 31)
51 #define R_CONFIG_ENDIAN (1 << 26)
52 #define MODEFAIL_GEN_EN (1 << 17)
53 #define MAN_START_COM (1 << 16)
54 #define MAN_START_EN (1 << 15)
55 #define MANUAL_CS (1 << 14)
56 #define CS (0xF << 10)
57 #define CS_SHIFT (10)
58 #define PERI_SEL (1 << 9)
59 #define REF_CLK (1 << 8)
60 #define FIFO_WIDTH (3 << 6)
61 #define BAUD_RATE_DIV (7 << 3)
62 #define CLK_PH (1 << 2)
63 #define CLK_POL (1 << 1)
64 #define MODE_SEL (1 << 0)
65 #define R_CONFIG_RSVD (0x7bf40000)
67 /* interrupt mechanism */
68 #define R_INTR_STATUS (0x04 / 4)
69 #define R_INTR_STATUS_RESET (0x104)
70 #define R_INTR_EN (0x08 / 4)
71 #define R_INTR_DIS (0x0C / 4)
72 #define R_INTR_MASK (0x10 / 4)
73 #define IXR_TX_FIFO_UNDERFLOW (1 << 6)
74 /* Poll timeout not implemented */
75 #define IXR_RX_FIFO_EMPTY (1 << 11)
76 #define IXR_GENERIC_FIFO_FULL (1 << 10)
77 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
78 #define IXR_TX_FIFO_EMPTY (1 << 8)
79 #define IXR_GENERIC_FIFO_EMPTY (1 << 7)
80 #define IXR_RX_FIFO_FULL (1 << 5)
81 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
82 #define IXR_TX_FIFO_FULL (1 << 3)
83 #define IXR_TX_FIFO_NOT_FULL (1 << 2)
84 #define IXR_TX_FIFO_MODE_FAIL (1 << 1)
85 #define IXR_RX_FIFO_OVERFLOW (1 << 0)
86 #define IXR_ALL ((1 << 13) - 1)
87 #define GQSPI_IXR_MASK 0xFBE
88 #define IXR_SELF_CLEAR \
89 (IXR_GENERIC_FIFO_EMPTY \
90 | IXR_GENERIC_FIFO_FULL \
91 | IXR_GENERIC_FIFO_NOT_FULL \
92 | IXR_TX_FIFO_EMPTY \
93 | IXR_TX_FIFO_FULL \
94 | IXR_TX_FIFO_NOT_FULL \
95 | IXR_RX_FIFO_EMPTY \
96 | IXR_RX_FIFO_FULL \
97 | IXR_RX_FIFO_NOT_EMPTY)
99 #define R_EN (0x14 / 4)
100 #define R_DELAY (0x18 / 4)
101 #define R_TX_DATA (0x1C / 4)
102 #define R_RX_DATA (0x20 / 4)
103 #define R_SLAVE_IDLE_COUNT (0x24 / 4)
104 #define R_TX_THRES (0x28 / 4)
105 #define R_RX_THRES (0x2C / 4)
106 #define R_GPIO (0x30 / 4)
107 #define R_LPBK_DLY_ADJ (0x38 / 4)
108 #define R_LPBK_DLY_ADJ_RESET (0x33)
109 #define R_TXD1 (0x80 / 4)
110 #define R_TXD2 (0x84 / 4)
111 #define R_TXD3 (0x88 / 4)
113 #define R_LQSPI_CFG (0xa0 / 4)
114 #define R_LQSPI_CFG_RESET 0x03A002EB
115 #define LQSPI_CFG_LQ_MODE (1U << 31)
116 #define LQSPI_CFG_TWO_MEM (1 << 30)
117 #define LQSPI_CFG_SEP_BUS (1 << 29)
118 #define LQSPI_CFG_U_PAGE (1 << 28)
119 #define LQSPI_CFG_ADDR4 (1 << 27)
120 #define LQSPI_CFG_MODE_EN (1 << 25)
121 #define LQSPI_CFG_MODE_WIDTH 8
122 #define LQSPI_CFG_MODE_SHIFT 16
123 #define LQSPI_CFG_DUMMY_WIDTH 3
124 #define LQSPI_CFG_DUMMY_SHIFT 8
125 #define LQSPI_CFG_INST_CODE 0xFF
127 #define R_CMND (0xc0 / 4)
128 #define R_CMND_RXFIFO_DRAIN (1 << 19)
129 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3)
130 #define R_CMND_EXT_ADD (1 << 15)
131 FIELD(CMND, RX_DISCARD, 8, 7)
132 FIELD(CMND, DUMMY_CYCLES, 2, 6)
133 #define R_CMND_DMA_EN (1 << 1)
134 #define R_CMND_PUSH_WAIT (1 << 0)
135 #define R_TRANSFER_SIZE (0xc4 / 4)
136 #define R_LQSPI_STS (0xA4 / 4)
137 #define LQSPI_STS_WR_RECVD (1 << 1)
139 #define R_MOD_ID (0xFC / 4)
141 #define R_GQSPI_SELECT (0x144 / 4)
142 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
143 #define R_GQSPI_ISR (0x104 / 4)
144 #define R_GQSPI_IER (0x108 / 4)
145 #define R_GQSPI_IDR (0x10c / 4)
146 #define R_GQSPI_IMR (0x110 / 4)
147 #define R_GQSPI_IMR_RESET (0xfbe)
148 #define R_GQSPI_TX_THRESH (0x128 / 4)
149 #define R_GQSPI_RX_THRESH (0x12c / 4)
150 #define R_GQSPI_GPIO (0x130 / 4)
151 #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
152 #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
153 #define R_GQSPI_CNFG (0x100 / 4)
154 FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
155 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)
156 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1)
157 FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
158 /* Poll timeout not implemented */
159 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
160 /* QEMU doesnt care about any of these last three */
161 FIELD(GQSPI_CNFG, BR, 3, 3)
162 FIELD(GQSPI_CNFG, CPH, 2, 1)
163 FIELD(GQSPI_CNFG, CPL, 1, 1)
164 #define R_GQSPI_GEN_FIFO (0x140 / 4)
165 #define R_GQSPI_TXD (0x11c / 4)
166 #define R_GQSPI_RXD (0x120 / 4)
167 #define R_GQSPI_FIFO_CTRL (0x14c / 4)
168 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1)
169 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1)
170 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1)
171 #define R_GQSPI_GFIFO_THRESH (0x150 / 4)
172 #define R_GQSPI_DATA_STS (0x15c / 4)
173 /* We use the snapshot register to hold the core state for the currently
174 * or most recently executed command. So the generic fifo format is defined
175 * for the snapshot register
177 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
178 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1)
179 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1)
180 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1)
181 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1)
182 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2)
183 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2)
184 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2)
185 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
186 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
187 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
188 #define R_GQSPI_MOD_ID (0x1fc / 4)
189 #define R_GQSPI_MOD_ID_RESET (0x10a0000)
191 #define R_QSPIDMA_DST_CTRL (0x80c / 4)
192 #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
193 #define R_QSPIDMA_DST_I_MASK (0x820 / 4)
194 #define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
195 #define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
196 #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
198 /* size of TXRX FIFOs */
199 #define RXFF_A (128)
200 #define TXFF_A (128)
202 #define RXFF_A_Q (64 * 4)
203 #define TXFF_A_Q (64 * 4)
205 /* 16MB per linear region */
206 #define LQSPI_ADDRESS_BITS 24
208 #define SNOOP_CHECKING 0xFF
209 #define SNOOP_ADDR 0xF0
210 #define SNOOP_NONE 0xEE
211 #define SNOOP_STRIPING 0
213 #define MIN_NUM_BUSSES 1
214 #define MAX_NUM_BUSSES 2
216 static inline int num_effective_busses(XilinxSPIPS *s)
218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
222 static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
224 int i;
226 for (i = 0; i < s->num_cs * s->num_busses; i++) {
227 bool old_state = s->cs_lines_state[i];
228 bool new_state = field & (1 << i);
230 if (old_state != new_state) {
231 s->cs_lines_state[i] = new_state;
232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
233 DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i);
235 qemu_set_irq(s->cs_lines[i], !new_state);
237 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
238 s->snoop_state = SNOOP_CHECKING;
239 s->cmd_dummies = 0;
240 s->link_state = 1;
241 s->link_state_next = 1;
242 s->link_state_next_when = 0;
243 DB_PRINT_L(1, "moving to snoop check state\n");
247 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
249 if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
250 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
251 bool upper_cs_sel = field & (1 << 1);
252 bool lower_cs_sel = field & 1;
253 bool bus0_enabled;
254 bool bus1_enabled;
255 uint8_t buses;
256 int cs = 0;
258 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
259 bus0_enabled = buses & 1;
260 bus1_enabled = buses & (1 << 1);
262 if (bus0_enabled && bus1_enabled) {
263 if (lower_cs_sel) {
264 cs |= 1;
266 if (upper_cs_sel) {
267 cs |= 1 << 3;
269 } else if (bus0_enabled) {
270 if (lower_cs_sel) {
271 cs |= 1;
273 if (upper_cs_sel) {
274 cs |= 1 << 1;
276 } else if (bus1_enabled) {
277 if (lower_cs_sel) {
278 cs |= 1 << 2;
280 if (upper_cs_sel) {
281 cs |= 1 << 3;
284 xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
288 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
290 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT);
292 /* In dual parallel, mirror low CS to both */
293 if (num_effective_busses(s) == 2) {
294 /* Single bit chip-select for qspi */
295 field &= 0x1;
296 field |= field << 3;
297 /* Dual stack U-Page */
298 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
299 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
300 /* Single bit chip-select for qspi */
301 field &= 0x1;
302 /* change from CS0 to CS1 */
303 field <<= 1;
305 /* Auto CS */
306 if (!(s->regs[R_CONFIG] & MANUAL_CS) &&
307 fifo8_is_empty(&s->tx_fifo)) {
308 field = 0;
310 xilinx_spips_update_cs(s, field);
313 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
315 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
316 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR;
317 s->regs[R_INTR_STATUS] |=
318 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
319 (s->rx_fifo.num >= s->regs[R_RX_THRES] ?
320 IXR_RX_FIFO_NOT_EMPTY : 0) |
321 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
322 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) |
323 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
325 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
326 IXR_ALL);
327 if (new_irqline != s->irqline) {
328 s->irqline = new_irqline;
329 qemu_set_irq(s->irq, s->irqline);
333 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s)
335 uint32_t gqspi_int;
336 int new_irqline;
338 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR;
339 s->regs[R_GQSPI_ISR] |=
340 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) |
341 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) |
342 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ?
343 IXR_GENERIC_FIFO_NOT_FULL : 0) |
344 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) |
345 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) |
346 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ?
347 IXR_RX_FIFO_NOT_EMPTY : 0) |
348 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) |
349 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) |
350 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ?
351 IXR_TX_FIFO_NOT_FULL : 0);
353 /* GQSPI Interrupt Trigger Status */
354 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK;
355 new_irqline = !!(gqspi_int & IXR_ALL);
357 /* drive external interrupt pin */
358 if (new_irqline != s->gqspi_irqline) {
359 s->gqspi_irqline = new_irqline;
360 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline);
364 static void xilinx_spips_reset(DeviceState *d)
366 XilinxSPIPS *s = XILINX_SPIPS(d);
368 memset(s->regs, 0, sizeof(s->regs));
370 fifo8_reset(&s->rx_fifo);
371 fifo8_reset(&s->rx_fifo);
372 /* non zero resets */
373 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
374 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
375 s->regs[R_TX_THRES] = 1;
376 s->regs[R_RX_THRES] = 1;
377 /* FIXME: move magic number definition somewhere sensible */
378 s->regs[R_MOD_ID] = 0x01090106;
379 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
380 s->link_state = 1;
381 s->link_state_next = 1;
382 s->link_state_next_when = 0;
383 s->snoop_state = SNOOP_CHECKING;
384 s->cmd_dummies = 0;
385 s->man_start_com = false;
386 xilinx_spips_update_ixr(s);
387 xilinx_spips_update_cs_lines(s);
390 static void xlnx_zynqmp_qspips_reset(DeviceState *d)
392 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
394 xilinx_spips_reset(d);
396 memset(s->regs, 0, sizeof(s->regs));
398 fifo8_reset(&s->rx_fifo_g);
399 fifo8_reset(&s->rx_fifo_g);
400 fifo32_reset(&s->fifo_g);
401 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
402 s->regs[R_GPIO] = 1;
403 s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
404 s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
405 s->regs[R_MOD_ID] = 0x01090101;
406 s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
407 s->regs[R_GQSPI_TX_THRESH] = 1;
408 s->regs[R_GQSPI_RX_THRESH] = 1;
409 s->regs[R_GQSPI_GPIO] = 1;
410 s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
411 s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
412 s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
413 s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
414 s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
415 s->man_start_com_g = false;
416 s->gqspi_irqline = 0;
417 xlnx_zynqmp_qspips_update_ixr(s);
420 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB)
421 * column wise (from element 0 to N-1). num is the length of x, and dir
422 * reverses the direction of the transform. Best illustrated by example:
423 * Each digit in the below array is a single bit (num == 3):
425 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, }
426 * { hgfedcba, } { 630fcHEB, }
427 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }}
430 static inline void stripe8(uint8_t *x, int num, bool dir)
432 uint8_t r[num];
433 memset(r, 0, sizeof(uint8_t) * num);
434 int idx[2] = {0, 0};
435 int bit[2] = {0, 7};
436 int d = dir;
438 for (idx[0] = 0; idx[0] < num; ++idx[0]) {
439 for (bit[0] = 7; bit[0] >= 0; bit[0]--) {
440 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
441 idx[1] = (idx[1] + 1) % num;
442 if (!idx[1]) {
443 bit[1]--;
447 memcpy(x, r, sizeof(uint8_t) * num);
450 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
452 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) {
453 uint8_t tx_rx[2] = { 0 };
454 int num_stripes = 1;
455 uint8_t busses;
456 int i;
458 if (!s->regs[R_GQSPI_DATA_STS]) {
459 uint8_t imm;
461 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g);
462 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]);
463 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
464 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
465 continue;
467 xlnx_zynqmp_qspips_update_cs_lines(s);
469 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
470 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
471 /* immedate transfer */
472 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
473 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
474 s->regs[R_GQSPI_DATA_STS] = 1;
475 /* CS setup/hold - do nothing */
476 } else {
477 s->regs[R_GQSPI_DATA_STS] = 0;
479 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) {
480 if (imm > 31) {
481 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too"
482 " long - 2 ^ %" PRId8 " requested\n", imm);
484 s->regs[R_GQSPI_DATA_STS] = 1ul << imm;
485 } else {
486 s->regs[R_GQSPI_DATA_STS] = imm;
489 /* Zero length transfer check */
490 if (!s->regs[R_GQSPI_DATA_STS]) {
491 continue;
493 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) &&
494 fifo8_is_full(&s->rx_fifo_g)) {
495 /* No space in RX fifo for transfer - try again later */
496 return;
498 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) &&
499 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
500 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) {
501 num_stripes = 2;
503 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
504 tx_rx[0] = ARRAY_FIELD_EX32(s->regs,
505 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
506 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) {
507 for (i = 0; i < num_stripes; ++i) {
508 if (!fifo8_is_empty(&s->tx_fifo_g)) {
509 tx_rx[i] = fifo8_pop(&s->tx_fifo_g);
510 s->tx_fifo_g_align++;
511 } else {
512 return;
516 if (num_stripes == 1) {
517 /* mirror */
518 tx_rx[1] = tx_rx[0];
520 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
521 for (i = 0; i < 2; ++i) {
522 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);
523 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]);
524 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);
526 if (s->regs[R_GQSPI_DATA_STS] > 1 &&
527 busses == 0x3 && num_stripes == 2) {
528 s->regs[R_GQSPI_DATA_STS] -= 2;
529 } else if (s->regs[R_GQSPI_DATA_STS] > 0) {
530 s->regs[R_GQSPI_DATA_STS]--;
532 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
533 for (i = 0; i < 2; ++i) {
534 if (busses & (1 << i)) {
535 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]);
536 fifo8_push(&s->rx_fifo_g, tx_rx[i]);
537 s->rx_fifo_g_align++;
541 if (!s->regs[R_GQSPI_DATA_STS]) {
542 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) {
543 fifo8_pop(&s->tx_fifo_g);
545 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) {
546 fifo8_push(&s->rx_fifo_g, 0);
552 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
554 if (!qs) {
555 /* The SPI device is not a QSPI device */
556 return -1;
559 switch (command) { /* check for dummies */
560 case READ: /* no dummy bytes/cycles */
561 case PP:
562 case DPP:
563 case QPP:
564 case READ_4:
565 case PP_4:
566 case QPP_4:
567 return 0;
568 case FAST_READ:
569 case DOR:
570 case QOR:
571 case DOR_4:
572 case QOR_4:
573 return 1;
574 case DIOR:
575 case FAST_READ_4:
576 case DIOR_4:
577 return 2;
578 case QIOR:
579 case QIOR_4:
580 return 4;
581 default:
582 return -1;
586 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd)
588 switch (cmd) {
589 case PP_4:
590 case QPP_4:
591 case READ_4:
592 case QIOR_4:
593 case FAST_READ_4:
594 case DOR_4:
595 case QOR_4:
596 case DIOR_4:
597 return 4;
598 default:
599 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3;
603 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
605 int debug_level = 0;
606 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
607 TYPE_XILINX_QSPIPS);
609 for (;;) {
610 int i;
611 uint8_t tx = 0;
612 uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 };
613 uint8_t dummy_cycles = 0;
614 uint8_t addr_length;
616 if (fifo8_is_empty(&s->tx_fifo)) {
617 xilinx_spips_update_ixr(s);
618 return;
619 } else if (s->snoop_state == SNOOP_STRIPING ||
620 s->snoop_state == SNOOP_NONE) {
621 for (i = 0; i < num_effective_busses(s); ++i) {
622 tx_rx[i] = fifo8_pop(&s->tx_fifo);
624 stripe8(tx_rx, num_effective_busses(s), false);
625 } else if (s->snoop_state >= SNOOP_ADDR) {
626 tx = fifo8_pop(&s->tx_fifo);
627 for (i = 0; i < num_effective_busses(s); ++i) {
628 tx_rx[i] = tx;
630 } else {
631 /* Extract a dummy byte and generate dummy cycles according to the
632 * link state */
633 tx = fifo8_pop(&s->tx_fifo);
634 dummy_cycles = 8 / s->link_state;
637 for (i = 0; i < num_effective_busses(s); ++i) {
638 int bus = num_effective_busses(s) - 1 - i;
639 if (dummy_cycles) {
640 int d;
641 for (d = 0; d < dummy_cycles; ++d) {
642 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
644 } else {
645 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
646 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
647 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
651 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
652 DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
653 /* Do nothing */
654 } else if (s->rx_discard) {
655 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
656 s->rx_discard -= 8 / s->link_state;
657 } else if (fifo8_is_full(&s->rx_fifo)) {
658 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
659 DB_PRINT_L(0, "rx FIFO overflow");
660 } else if (s->snoop_state == SNOOP_STRIPING) {
661 stripe8(tx_rx, num_effective_busses(s), true);
662 for (i = 0; i < num_effective_busses(s); ++i) {
663 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
664 DB_PRINT_L(debug_level, "pushing striped rx byte\n");
666 } else {
667 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
668 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
671 if (s->link_state_next_when) {
672 s->link_state_next_when--;
673 if (!s->link_state_next_when) {
674 s->link_state = s->link_state_next;
678 DB_PRINT_L(debug_level, "initial snoop state: %x\n",
679 (unsigned)s->snoop_state);
680 switch (s->snoop_state) {
681 case (SNOOP_CHECKING):
682 /* Store the count of dummy bytes in the txfifo */
683 s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
684 addr_length = get_addr_length(s, tx);
685 if (s->cmd_dummies < 0) {
686 s->snoop_state = SNOOP_NONE;
687 } else {
688 s->snoop_state = SNOOP_ADDR + addr_length - 1;
690 switch (tx) {
691 case DPP:
692 case DOR:
693 case DOR_4:
694 s->link_state_next = 2;
695 s->link_state_next_when = addr_length + s->cmd_dummies;
696 break;
697 case QPP:
698 case QPP_4:
699 case QOR:
700 case QOR_4:
701 s->link_state_next = 4;
702 s->link_state_next_when = addr_length + s->cmd_dummies;
703 break;
704 case DIOR:
705 case DIOR_4:
706 s->link_state = 2;
707 break;
708 case QIOR:
709 case QIOR_4:
710 s->link_state = 4;
711 break;
713 break;
714 case (SNOOP_ADDR):
715 /* Address has been transmitted, transmit dummy cycles now if
716 * needed */
717 if (s->cmd_dummies < 0) {
718 s->snoop_state = SNOOP_NONE;
719 } else {
720 s->snoop_state = s->cmd_dummies;
722 break;
723 case (SNOOP_STRIPING):
724 case (SNOOP_NONE):
725 /* Once we hit the boring stuff - squelch debug noise */
726 if (!debug_level) {
727 DB_PRINT_L(0, "squelching debug info ....\n");
728 debug_level = 1;
730 break;
731 default:
732 s->snoop_state--;
734 DB_PRINT_L(debug_level, "final snoop state: %x\n",
735 (unsigned)s->snoop_state);
739 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be)
741 int i;
742 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) {
743 if (be) {
744 fifo8_push(fifo, (uint8_t)(value >> 24));
745 value <<= 8;
746 } else {
747 fifo8_push(fifo, (uint8_t)value);
748 value >>= 8;
753 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
755 if (!s->regs[R_TRANSFER_SIZE]) {
756 return;
758 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
759 return;
762 * The zero pump must never fill tx fifo such that rx overflow is
763 * possible
765 while (s->regs[R_TRANSFER_SIZE] &&
766 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
767 /* endianess just doesn't matter when zero pumping */
768 tx_data_bytes(&s->tx_fifo, 0, 4, false);
769 s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
770 s->regs[R_TRANSFER_SIZE] -= 4;
774 static void xilinx_spips_check_flush(XilinxSPIPS *s)
776 if (s->man_start_com ||
777 (!fifo8_is_empty(&s->tx_fifo) &&
778 !(s->regs[R_CONFIG] & MAN_START_EN))) {
779 xilinx_spips_check_zero_pump(s);
780 xilinx_spips_flush_txfifo(s);
782 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
783 s->man_start_com = false;
785 xilinx_spips_update_ixr(s);
788 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s)
790 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] ||
791 !fifo32_is_empty(&s->fifo_g);
793 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
794 if (s->man_start_com_g || (gqspi_has_work &&
795 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) {
796 xlnx_zynqmp_qspips_flush_fifo_g(s);
798 } else {
799 xilinx_spips_check_flush(XILINX_SPIPS(s));
801 if (!gqspi_has_work) {
802 s->man_start_com_g = false;
804 xlnx_zynqmp_qspips_update_ixr(s);
807 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
809 int i;
811 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) {
812 value[i] = fifo8_pop(fifo);
814 return max - i;
817 static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
819 void *ret;
821 if (max == 0 || max > fifo->num) {
822 abort();
824 *num = MIN(fifo->capacity - fifo->head, max);
825 ret = &fifo->data[fifo->head];
826 fifo->head += *num;
827 fifo->head %= fifo->capacity;
828 fifo->num -= *num;
829 return ret;
832 static void xlnx_zynqmp_qspips_notify(void *opaque)
834 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque);
835 XilinxSPIPS *s = XILINX_SPIPS(rq);
836 Fifo8 *recv_fifo;
838 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
839 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) {
840 return;
842 recv_fifo = &rq->rx_fifo_g;
843 } else {
844 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) {
845 return;
847 recv_fifo = &s->rx_fifo;
849 while (recv_fifo->num >= 4
850 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq))
852 size_t ret;
853 uint32_t num;
854 const void *rxd;
855 int len;
857 len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size :
858 recv_fifo->num;
859 rxd = pop_buf(recv_fifo, len, &num);
861 memcpy(rq->dma_buf, rxd, num);
863 ret = stream_push(rq->dma, rq->dma_buf, num);
864 assert(ret == num);
865 xlnx_zynqmp_qspips_check_flush(rq);
869 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
870 unsigned size)
872 XilinxSPIPS *s = opaque;
873 uint32_t mask = ~0;
874 uint32_t ret;
875 uint8_t rx_buf[4];
876 int shortfall;
878 addr >>= 2;
879 switch (addr) {
880 case R_CONFIG:
881 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
882 break;
883 case R_INTR_STATUS:
884 ret = s->regs[addr] & IXR_ALL;
885 s->regs[addr] = 0;
886 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
887 xilinx_spips_update_ixr(s);
888 return ret;
889 case R_INTR_MASK:
890 mask = IXR_ALL;
891 break;
892 case R_EN:
893 mask = 0x1;
894 break;
895 case R_SLAVE_IDLE_COUNT:
896 mask = 0xFF;
897 break;
898 case R_MOD_ID:
899 mask = 0x01FFFFFF;
900 break;
901 case R_INTR_EN:
902 case R_INTR_DIS:
903 case R_TX_DATA:
904 mask = 0;
905 break;
906 case R_RX_DATA:
907 memset(rx_buf, 0, sizeof(rx_buf));
908 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes);
909 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ?
910 cpu_to_be32(*(uint32_t *)rx_buf) :
911 cpu_to_le32(*(uint32_t *)rx_buf);
912 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
913 ret <<= 8 * shortfall;
915 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
916 xilinx_spips_check_flush(s);
917 xilinx_spips_update_ixr(s);
918 return ret;
920 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
921 s->regs[addr] & mask);
922 return s->regs[addr] & mask;
926 static uint64_t xlnx_zynqmp_qspips_read(void *opaque,
927 hwaddr addr, unsigned size)
929 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
930 uint32_t reg = addr / 4;
931 uint32_t ret;
932 uint8_t rx_buf[4];
933 int shortfall;
935 if (reg <= R_MOD_ID) {
936 return xilinx_spips_read(opaque, addr, size);
937 } else {
938 switch (reg) {
939 case R_GQSPI_RXD:
940 if (fifo8_is_empty(&s->rx_fifo_g)) {
941 qemu_log_mask(LOG_GUEST_ERROR,
942 "Read from empty GQSPI RX FIFO\n");
943 return 0;
945 memset(rx_buf, 0, sizeof(rx_buf));
946 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf,
947 XILINX_SPIPS(s)->num_txrx_bytes);
948 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ?
949 cpu_to_be32(*(uint32_t *)rx_buf) :
950 cpu_to_le32(*(uint32_t *)rx_buf);
951 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) {
952 ret <<= 8 * shortfall;
954 xlnx_zynqmp_qspips_check_flush(s);
955 xlnx_zynqmp_qspips_update_ixr(s);
956 return ret;
957 default:
958 return s->regs[reg];
963 static void xilinx_spips_write(void *opaque, hwaddr addr,
964 uint64_t value, unsigned size)
966 int mask = ~0;
967 XilinxSPIPS *s = opaque;
969 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
970 addr >>= 2;
971 switch (addr) {
972 case R_CONFIG:
973 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
974 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
975 s->man_start_com = true;
977 break;
978 case R_INTR_STATUS:
979 mask = IXR_ALL;
980 s->regs[R_INTR_STATUS] &= ~(mask & value);
981 goto no_reg_update;
982 case R_INTR_DIS:
983 mask = IXR_ALL;
984 s->regs[R_INTR_MASK] &= ~(mask & value);
985 goto no_reg_update;
986 case R_INTR_EN:
987 mask = IXR_ALL;
988 s->regs[R_INTR_MASK] |= mask & value;
989 goto no_reg_update;
990 case R_EN:
991 mask = 0x1;
992 break;
993 case R_SLAVE_IDLE_COUNT:
994 mask = 0xFF;
995 break;
996 case R_RX_DATA:
997 case R_INTR_MASK:
998 case R_MOD_ID:
999 mask = 0;
1000 break;
1001 case R_TX_DATA:
1002 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
1003 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1004 goto no_reg_update;
1005 case R_TXD1:
1006 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,
1007 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1008 goto no_reg_update;
1009 case R_TXD2:
1010 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,
1011 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1012 goto no_reg_update;
1013 case R_TXD3:
1014 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
1015 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1016 goto no_reg_update;
1018 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
1019 no_reg_update:
1020 xilinx_spips_update_cs_lines(s);
1021 xilinx_spips_check_flush(s);
1022 xilinx_spips_update_cs_lines(s);
1023 xilinx_spips_update_ixr(s);
1026 static const MemoryRegionOps spips_ops = {
1027 .read = xilinx_spips_read,
1028 .write = xilinx_spips_write,
1029 .endianness = DEVICE_LITTLE_ENDIAN,
1032 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
1034 q->lqspi_cached_addr = ~0ULL;
1037 static void xilinx_qspips_write(void *opaque, hwaddr addr,
1038 uint64_t value, unsigned size)
1040 XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1041 XilinxSPIPS *s = XILINX_SPIPS(opaque);
1043 xilinx_spips_write(opaque, addr, value, size);
1044 addr >>= 2;
1046 if (addr == R_LQSPI_CFG) {
1047 xilinx_qspips_invalidate_mmio_ptr(q);
1049 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1050 fifo8_reset(&s->rx_fifo);
1054 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr,
1055 uint64_t value, unsigned size)
1057 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
1058 uint32_t reg = addr / 4;
1060 if (reg <= R_MOD_ID) {
1061 xilinx_qspips_write(opaque, addr, value, size);
1062 } else {
1063 switch (reg) {
1064 case R_GQSPI_CNFG:
1065 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) &&
1066 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) {
1067 s->man_start_com_g = true;
1069 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK);
1070 break;
1071 case R_GQSPI_GEN_FIFO:
1072 if (!fifo32_is_full(&s->fifo_g)) {
1073 fifo32_push(&s->fifo_g, value);
1075 break;
1076 case R_GQSPI_TXD:
1077 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4,
1078 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN));
1079 break;
1080 case R_GQSPI_FIFO_CTRL:
1081 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) {
1082 fifo32_reset(&s->fifo_g);
1084 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) {
1085 fifo8_reset(&s->tx_fifo_g);
1087 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) {
1088 fifo8_reset(&s->rx_fifo_g);
1090 break;
1091 case R_GQSPI_IDR:
1092 s->regs[R_GQSPI_IMR] |= value;
1093 break;
1094 case R_GQSPI_IER:
1095 s->regs[R_GQSPI_IMR] &= ~value;
1096 break;
1097 case R_GQSPI_ISR:
1098 s->regs[R_GQSPI_ISR] &= ~value;
1099 break;
1100 case R_GQSPI_IMR:
1101 case R_GQSPI_RXD:
1102 case R_GQSPI_GF_SNAPSHOT:
1103 case R_GQSPI_MOD_ID:
1104 break;
1105 default:
1106 s->regs[reg] = value;
1107 break;
1109 xlnx_zynqmp_qspips_update_cs_lines(s);
1110 xlnx_zynqmp_qspips_check_flush(s);
1111 xlnx_zynqmp_qspips_update_cs_lines(s);
1112 xlnx_zynqmp_qspips_update_ixr(s);
1114 xlnx_zynqmp_qspips_notify(s);
1117 static const MemoryRegionOps qspips_ops = {
1118 .read = xilinx_spips_read,
1119 .write = xilinx_qspips_write,
1120 .endianness = DEVICE_LITTLE_ENDIAN,
1123 static const MemoryRegionOps xlnx_zynqmp_qspips_ops = {
1124 .read = xlnx_zynqmp_qspips_read,
1125 .write = xlnx_zynqmp_qspips_write,
1126 .endianness = DEVICE_LITTLE_ENDIAN,
1129 #define LQSPI_CACHE_SIZE 1024
1131 static void lqspi_load_cache(void *opaque, hwaddr addr)
1133 XilinxQSPIPS *q = opaque;
1134 XilinxSPIPS *s = opaque;
1135 int i;
1136 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
1137 / num_effective_busses(s));
1138 int slave = flash_addr >> LQSPI_ADDRESS_BITS;
1139 int cache_entry = 0;
1140 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
1142 if (addr < q->lqspi_cached_addr ||
1143 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1144 xilinx_qspips_invalidate_mmio_ptr(q);
1145 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1146 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
1148 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
1150 fifo8_reset(&s->tx_fifo);
1151 fifo8_reset(&s->rx_fifo);
1153 /* instruction */
1154 DB_PRINT_L(0, "pushing read instruction: %02x\n",
1155 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
1156 LQSPI_CFG_INST_CODE));
1157 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
1158 /* read address */
1159 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
1160 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
1161 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
1163 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
1164 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
1165 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
1166 /* mode bits */
1167 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
1168 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
1169 LQSPI_CFG_MODE_SHIFT,
1170 LQSPI_CFG_MODE_WIDTH));
1172 /* dummy bytes */
1173 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
1174 LQSPI_CFG_DUMMY_WIDTH)); ++i) {
1175 DB_PRINT_L(0, "pushing dummy byte\n");
1176 fifo8_push(&s->tx_fifo, 0);
1178 xilinx_spips_update_cs_lines(s);
1179 xilinx_spips_flush_txfifo(s);
1180 fifo8_reset(&s->rx_fifo);
1182 DB_PRINT_L(0, "starting QSPI data read\n");
1184 while (cache_entry < LQSPI_CACHE_SIZE) {
1185 for (i = 0; i < 64; ++i) {
1186 tx_data_bytes(&s->tx_fifo, 0, 1, false);
1188 xilinx_spips_flush_txfifo(s);
1189 for (i = 0; i < 64; ++i) {
1190 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1);
1194 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1195 s->regs[R_LQSPI_STS] |= u_page_save;
1196 xilinx_spips_update_cs_lines(s);
1198 q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
1202 static uint64_t
1203 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
1205 XilinxQSPIPS *q = opaque;
1206 uint32_t ret;
1208 if (addr >= q->lqspi_cached_addr &&
1209 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1210 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
1211 ret = cpu_to_le32(*(uint32_t *)retp);
1212 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
1213 (unsigned)ret);
1214 return ret;
1215 } else {
1216 lqspi_load_cache(opaque, addr);
1217 return lqspi_read(opaque, addr, size);
1221 static const MemoryRegionOps lqspi_ops = {
1222 .read = lqspi_read,
1223 .endianness = DEVICE_NATIVE_ENDIAN,
1224 .valid = {
1225 .min_access_size = 1,
1226 .max_access_size = 4
1230 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
1232 XilinxSPIPS *s = XILINX_SPIPS(dev);
1233 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1234 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1235 qemu_irq *cs;
1236 int i;
1238 DB_PRINT_L(0, "realized spips\n");
1240 if (s->num_busses > MAX_NUM_BUSSES) {
1241 error_setg(errp,
1242 "requested number of SPI busses %u exceeds maximum %d",
1243 s->num_busses, MAX_NUM_BUSSES);
1244 return;
1246 if (s->num_busses < MIN_NUM_BUSSES) {
1247 error_setg(errp,
1248 "requested number of SPI busses %u is below minimum %d",
1249 s->num_busses, MIN_NUM_BUSSES);
1250 return;
1253 s->spi = g_new(SSIBus *, s->num_busses);
1254 for (i = 0; i < s->num_busses; ++i) {
1255 char bus_name[16];
1256 snprintf(bus_name, 16, "spi%d", i);
1257 s->spi[i] = ssi_create_bus(dev, bus_name);
1260 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
1261 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
1262 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
1263 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
1266 sysbus_init_irq(sbd, &s->irq);
1267 for (i = 0; i < s->num_cs * s->num_busses; ++i) {
1268 sysbus_init_irq(sbd, &s->cs_lines[i]);
1271 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
1272 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4);
1273 sysbus_init_mmio(sbd, &s->iomem);
1275 s->irqline = -1;
1277 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
1278 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
1281 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
1283 XilinxSPIPS *s = XILINX_SPIPS(dev);
1284 XilinxQSPIPS *q = XILINX_QSPIPS(dev);
1285 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1287 DB_PRINT_L(0, "realized qspips\n");
1289 s->num_busses = 2;
1290 s->num_cs = 2;
1291 s->num_txrx_bytes = 4;
1293 xilinx_spips_realize(dev, errp);
1294 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
1295 (1 << LQSPI_ADDRESS_BITS) * 2);
1296 sysbus_init_mmio(sbd, &s->mmlqspi);
1298 q->lqspi_cached_addr = ~0ULL;
1301 static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp)
1303 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev);
1304 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1306 if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) {
1307 error_setg(errp,
1308 "qspi dma burst size %u exceeds maximum limit %d",
1309 s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE);
1310 return;
1312 xilinx_qspips_realize(dev, errp);
1313 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size);
1314 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size);
1315 fifo32_create(&s->fifo_g, 32);
1318 static void xlnx_zynqmp_qspips_init(Object *obj)
1320 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
1322 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
1323 (Object **)&rq->dma,
1324 object_property_allow_set_link,
1325 OBJ_PROP_LINK_STRONG,
1326 NULL);
1329 static int xilinx_spips_post_load(void *opaque, int version_id)
1331 xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
1332 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
1333 return 0;
1336 static const VMStateDescription vmstate_xilinx_spips = {
1337 .name = "xilinx_spips",
1338 .version_id = 2,
1339 .minimum_version_id = 2,
1340 .post_load = xilinx_spips_post_load,
1341 .fields = (VMStateField[]) {
1342 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
1343 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
1344 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
1345 VMSTATE_UINT8(snoop_state, XilinxSPIPS),
1346 VMSTATE_END_OF_LIST()
1350 static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id)
1352 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque;
1353 XilinxSPIPS *qs = XILINX_SPIPS(s);
1355 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) &&
1356 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) {
1357 xlnx_zynqmp_qspips_update_ixr(s);
1358 xlnx_zynqmp_qspips_update_cs_lines(s);
1360 return 0;
1363 static const VMStateDescription vmstate_xilinx_qspips = {
1364 .name = "xilinx_qspips",
1365 .version_id = 1,
1366 .minimum_version_id = 1,
1367 .fields = (VMStateField[]) {
1368 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0,
1369 vmstate_xilinx_spips, XilinxSPIPS),
1370 VMSTATE_END_OF_LIST()
1374 static const VMStateDescription vmstate_xlnx_zynqmp_qspips = {
1375 .name = "xlnx_zynqmp_qspips",
1376 .version_id = 1,
1377 .minimum_version_id = 1,
1378 .post_load = xlnx_zynqmp_qspips_post_load,
1379 .fields = (VMStateField[]) {
1380 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0,
1381 vmstate_xilinx_qspips, XilinxQSPIPS),
1382 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS),
1383 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS),
1384 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS),
1385 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX),
1386 VMSTATE_END_OF_LIST()
1390 static Property xilinx_zynqmp_qspips_properties[] = {
1391 DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64),
1392 DEFINE_PROP_END_OF_LIST(),
1395 static Property xilinx_spips_properties[] = {
1396 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
1397 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
1398 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
1399 DEFINE_PROP_END_OF_LIST(),
1402 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
1404 DeviceClass *dc = DEVICE_CLASS(klass);
1405 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1407 dc->realize = xilinx_qspips_realize;
1408 xsc->reg_ops = &qspips_ops;
1409 xsc->rx_fifo_size = RXFF_A_Q;
1410 xsc->tx_fifo_size = TXFF_A_Q;
1413 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
1415 DeviceClass *dc = DEVICE_CLASS(klass);
1416 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1418 dc->realize = xilinx_spips_realize;
1419 dc->reset = xilinx_spips_reset;
1420 dc->props = xilinx_spips_properties;
1421 dc->vmsd = &vmstate_xilinx_spips;
1423 xsc->reg_ops = &spips_ops;
1424 xsc->rx_fifo_size = RXFF_A;
1425 xsc->tx_fifo_size = TXFF_A;
1428 static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data)
1430 DeviceClass *dc = DEVICE_CLASS(klass);
1431 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1433 dc->realize = xlnx_zynqmp_qspips_realize;
1434 dc->reset = xlnx_zynqmp_qspips_reset;
1435 dc->vmsd = &vmstate_xlnx_zynqmp_qspips;
1436 dc->props = xilinx_zynqmp_qspips_properties;
1437 xsc->reg_ops = &xlnx_zynqmp_qspips_ops;
1438 xsc->rx_fifo_size = RXFF_A_Q;
1439 xsc->tx_fifo_size = TXFF_A_Q;
1442 static const TypeInfo xilinx_spips_info = {
1443 .name = TYPE_XILINX_SPIPS,
1444 .parent = TYPE_SYS_BUS_DEVICE,
1445 .instance_size = sizeof(XilinxSPIPS),
1446 .class_init = xilinx_spips_class_init,
1447 .class_size = sizeof(XilinxSPIPSClass),
1450 static const TypeInfo xilinx_qspips_info = {
1451 .name = TYPE_XILINX_QSPIPS,
1452 .parent = TYPE_XILINX_SPIPS,
1453 .instance_size = sizeof(XilinxQSPIPS),
1454 .class_init = xilinx_qspips_class_init,
1457 static const TypeInfo xlnx_zynqmp_qspips_info = {
1458 .name = TYPE_XLNX_ZYNQMP_QSPIPS,
1459 .parent = TYPE_XILINX_QSPIPS,
1460 .instance_size = sizeof(XlnxZynqMPQSPIPS),
1461 .instance_init = xlnx_zynqmp_qspips_init,
1462 .class_init = xlnx_zynqmp_qspips_class_init,
1465 static void xilinx_spips_register_types(void)
1467 type_register_static(&xilinx_spips_info);
1468 type_register_static(&xilinx_qspips_info);
1469 type_register_static(&xlnx_zynqmp_qspips_info);
1472 type_init(xilinx_spips_register_types)