2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "migration/vmstate.h"
30 #include "hw/scsi/esp.h"
33 #include "qemu/module.h"
36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
37 * also produced as NCR89C100. See
38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
42 * On Macintosh Quadra it is a NCR53C96.
45 static void esp_raise_irq(ESPState
*s
)
47 if (!(s
->rregs
[ESP_RSTAT
] & STAT_INT
)) {
48 s
->rregs
[ESP_RSTAT
] |= STAT_INT
;
49 qemu_irq_raise(s
->irq
);
50 trace_esp_raise_irq();
54 static void esp_lower_irq(ESPState
*s
)
56 if (s
->rregs
[ESP_RSTAT
] & STAT_INT
) {
57 s
->rregs
[ESP_RSTAT
] &= ~STAT_INT
;
58 qemu_irq_lower(s
->irq
);
59 trace_esp_lower_irq();
63 static void esp_raise_drq(ESPState
*s
)
65 qemu_irq_raise(s
->irq_data
);
66 trace_esp_raise_drq();
69 static void esp_lower_drq(ESPState
*s
)
71 qemu_irq_lower(s
->irq_data
);
72 trace_esp_lower_drq();
75 void esp_dma_enable(ESPState
*s
, int irq
, int level
)
79 trace_esp_dma_enable();
85 trace_esp_dma_disable();
90 void esp_request_cancelled(SCSIRequest
*req
)
92 ESPState
*s
= req
->hba_private
;
94 if (req
== s
->current_req
) {
95 scsi_req_unref(s
->current_req
);
96 s
->current_req
= NULL
;
97 s
->current_dev
= NULL
;
101 static void esp_fifo_push(ESPState
*s
, uint8_t val
)
103 if (fifo8_num_used(&s
->fifo
) == ESP_FIFO_SZ
) {
104 trace_esp_error_fifo_overrun();
108 fifo8_push(&s
->fifo
, val
);
111 static uint8_t esp_fifo_pop(ESPState
*s
)
113 if (fifo8_is_empty(&s
->fifo
)) {
117 return fifo8_pop(&s
->fifo
);
120 static void esp_cmdfifo_push(ESPState
*s
, uint8_t val
)
122 if (fifo8_num_used(&s
->cmdfifo
) == ESP_CMDFIFO_SZ
) {
123 trace_esp_error_fifo_overrun();
127 fifo8_push(&s
->cmdfifo
, val
);
130 static uint8_t esp_cmdfifo_pop(ESPState
*s
)
132 if (fifo8_is_empty(&s
->cmdfifo
)) {
136 return fifo8_pop(&s
->cmdfifo
);
139 static uint32_t esp_get_tc(ESPState
*s
)
143 dmalen
= s
->rregs
[ESP_TCLO
];
144 dmalen
|= s
->rregs
[ESP_TCMID
] << 8;
145 dmalen
|= s
->rregs
[ESP_TCHI
] << 16;
150 static void esp_set_tc(ESPState
*s
, uint32_t dmalen
)
152 s
->rregs
[ESP_TCLO
] = dmalen
;
153 s
->rregs
[ESP_TCMID
] = dmalen
>> 8;
154 s
->rregs
[ESP_TCHI
] = dmalen
>> 16;
157 static uint32_t esp_get_stc(ESPState
*s
)
161 dmalen
= s
->wregs
[ESP_TCLO
];
162 dmalen
|= s
->wregs
[ESP_TCMID
] << 8;
163 dmalen
|= s
->wregs
[ESP_TCHI
] << 16;
168 static uint8_t esp_pdma_read(ESPState
*s
)
173 val
= esp_cmdfifo_pop(s
);
175 val
= esp_fifo_pop(s
);
181 static void esp_pdma_write(ESPState
*s
, uint8_t val
)
183 uint32_t dmalen
= esp_get_tc(s
);
190 esp_cmdfifo_push(s
, val
);
192 esp_fifo_push(s
, val
);
196 esp_set_tc(s
, dmalen
);
199 static int esp_select(ESPState
*s
)
203 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
206 fifo8_reset(&s
->fifo
);
208 if (s
->current_req
) {
209 /* Started a new command before the old one finished. Cancel it. */
210 scsi_req_cancel(s
->current_req
);
214 s
->current_dev
= scsi_device_find(&s
->bus
, 0, target
, 0);
215 if (!s
->current_dev
) {
217 s
->rregs
[ESP_RSTAT
] = 0;
218 s
->rregs
[ESP_RINTR
] |= INTR_DC
;
219 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
225 * Note that we deliberately don't raise the IRQ here: this will be done
226 * either in do_busid_cmd() for DATA OUT transfers or by the deferred
227 * IRQ mechanism in esp_transfer_data() for DATA IN transfers
229 s
->rregs
[ESP_RINTR
] |= INTR_FC
;
230 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
234 static uint32_t get_cmd(ESPState
*s
, uint32_t maxlen
)
236 uint8_t buf
[ESP_CMDFIFO_SZ
];
240 target
= s
->wregs
[ESP_WBUSID
] & BUSID_DID
;
242 dmalen
= MIN(esp_get_tc(s
), maxlen
);
246 if (s
->dma_memory_read
) {
247 s
->dma_memory_read(s
->dma_opaque
, buf
, dmalen
);
248 fifo8_push_all(&s
->cmdfifo
, buf
, dmalen
);
250 if (esp_select(s
) < 0) {
251 fifo8_reset(&s
->cmdfifo
);
255 fifo8_reset(&s
->cmdfifo
);
259 dmalen
= MIN(fifo8_num_used(&s
->fifo
), maxlen
);
263 memcpy(buf
, fifo8_pop_buf(&s
->fifo
, dmalen
, &n
), dmalen
);
265 buf
[0] = buf
[2] >> 5;
267 fifo8_push_all(&s
->cmdfifo
, buf
, dmalen
);
269 trace_esp_get_cmd(dmalen
, target
);
271 if (esp_select(s
) < 0) {
272 fifo8_reset(&s
->cmdfifo
);
278 static void do_busid_cmd(ESPState
*s
, uint8_t busid
)
283 SCSIDevice
*current_lun
;
286 trace_esp_do_busid_cmd(busid
);
288 cmdlen
= fifo8_num_used(&s
->cmdfifo
);
289 buf
= (uint8_t *)fifo8_pop_buf(&s
->cmdfifo
, cmdlen
, &n
);
291 current_lun
= scsi_device_find(&s
->bus
, 0, s
->current_dev
->id
, lun
);
292 s
->current_req
= scsi_req_new(current_lun
, 0, lun
, buf
, s
);
293 datalen
= scsi_req_enqueue(s
->current_req
);
294 s
->ti_size
= datalen
;
295 fifo8_reset(&s
->cmdfifo
);
297 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
298 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
303 * Switch to DATA IN phase but wait until initial data xfer is
304 * complete before raising the command completion interrupt
306 s
->data_in_ready
= false;
307 s
->rregs
[ESP_RSTAT
] |= STAT_DI
;
309 s
->rregs
[ESP_RSTAT
] |= STAT_DO
;
310 s
->rregs
[ESP_RINTR
] |= INTR_BS
| INTR_FC
;
314 scsi_req_continue(s
->current_req
);
319 static void do_cmd(ESPState
*s
)
321 uint8_t busid
= fifo8_pop(&s
->cmdfifo
);
324 s
->cmdfifo_cdb_offset
--;
326 /* Ignore extended messages for now */
327 if (s
->cmdfifo_cdb_offset
) {
328 fifo8_pop_buf(&s
->cmdfifo
, s
->cmdfifo_cdb_offset
, &n
);
329 s
->cmdfifo_cdb_offset
= 0;
332 do_busid_cmd(s
, busid
);
335 static void satn_pdma_cb(ESPState
*s
)
338 if (!fifo8_is_empty(&s
->cmdfifo
)) {
339 s
->cmdfifo_cdb_offset
= 1;
344 static void handle_satn(ESPState
*s
)
348 if (s
->dma
&& !s
->dma_enabled
) {
349 s
->dma_cb
= handle_satn
;
352 s
->pdma_cb
= satn_pdma_cb
;
353 cmdlen
= get_cmd(s
, ESP_CMDFIFO_SZ
);
355 s
->cmdfifo_cdb_offset
= 1;
357 } else if (cmdlen
== 0) {
359 /* Target present, but no cmd yet - switch to command phase */
360 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
361 s
->rregs
[ESP_RSTAT
] = STAT_CD
;
365 static void s_without_satn_pdma_cb(ESPState
*s
)
370 len
= fifo8_num_used(&s
->cmdfifo
);
372 s
->cmdfifo_cdb_offset
= 0;
377 static void handle_s_without_atn(ESPState
*s
)
381 if (s
->dma
&& !s
->dma_enabled
) {
382 s
->dma_cb
= handle_s_without_atn
;
385 s
->pdma_cb
= s_without_satn_pdma_cb
;
386 cmdlen
= get_cmd(s
, ESP_CMDFIFO_SZ
);
388 s
->cmdfifo_cdb_offset
= 0;
390 } else if (cmdlen
== 0) {
392 /* Target present, but no cmd yet - switch to command phase */
393 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
394 s
->rregs
[ESP_RSTAT
] = STAT_CD
;
398 static void satn_stop_pdma_cb(ESPState
*s
)
401 if (!fifo8_is_empty(&s
->cmdfifo
)) {
402 trace_esp_handle_satn_stop(fifo8_num_used(&s
->cmdfifo
));
404 s
->cmdfifo_cdb_offset
= 1;
405 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
406 s
->rregs
[ESP_RINTR
] |= INTR_BS
| INTR_FC
;
407 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
412 static void handle_satn_stop(ESPState
*s
)
416 if (s
->dma
&& !s
->dma_enabled
) {
417 s
->dma_cb
= handle_satn_stop
;
420 s
->pdma_cb
= satn_stop_pdma_cb
;
421 cmdlen
= get_cmd(s
, 1);
423 trace_esp_handle_satn_stop(fifo8_num_used(&s
->cmdfifo
));
425 s
->cmdfifo_cdb_offset
= 1;
426 s
->rregs
[ESP_RSTAT
] = STAT_MO
;
427 s
->rregs
[ESP_RINTR
] |= INTR_BS
| INTR_FC
;
428 s
->rregs
[ESP_RSEQ
] = SEQ_MO
;
430 } else if (cmdlen
== 0) {
432 /* Target present, switch to message out phase */
433 s
->rregs
[ESP_RSEQ
] = SEQ_MO
;
434 s
->rregs
[ESP_RSTAT
] = STAT_MO
;
438 static void write_response_pdma_cb(ESPState
*s
)
440 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
441 s
->rregs
[ESP_RINTR
] |= INTR_BS
| INTR_FC
;
442 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
446 static void write_response(ESPState
*s
)
450 trace_esp_write_response(s
->status
);
452 fifo8_reset(&s
->fifo
);
453 esp_fifo_push(s
, s
->status
);
457 if (s
->dma_memory_write
) {
458 s
->dma_memory_write(s
->dma_opaque
,
459 (uint8_t *)fifo8_pop_buf(&s
->fifo
, 2, &n
), 2);
460 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_ST
;
461 s
->rregs
[ESP_RINTR
] |= INTR_BS
| INTR_FC
;
462 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
464 s
->pdma_cb
= write_response_pdma_cb
;
470 s
->rregs
[ESP_RFLAGS
] = 2;
475 static void esp_dma_done(ESPState
*s
)
477 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
478 s
->rregs
[ESP_RINTR
] |= INTR_BS
;
479 s
->rregs
[ESP_RSEQ
] = 0;
480 s
->rregs
[ESP_RFLAGS
] = 0;
485 static void do_dma_pdma_cb(ESPState
*s
)
487 int to_device
= ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_DO
);
500 /* Copy FIFO data to device */
501 len
= MIN(s
->async_len
, ESP_FIFO_SZ
);
502 len
= MIN(len
, fifo8_num_used(&s
->fifo
));
503 memcpy(s
->async_buf
, fifo8_pop_buf(&s
->fifo
, len
, &n
), len
);
509 /* Unaligned accesses can cause FIFO wraparound */
511 memcpy(s
->async_buf
, fifo8_pop_buf(&s
->fifo
, len
, &n
), len
);
517 if (s
->async_len
== 0) {
518 scsi_req_continue(s
->current_req
);
522 if (esp_get_tc(s
) == 0) {
529 if (s
->async_len
== 0) {
530 if (s
->current_req
) {
531 /* Defer until the scsi layer has completed */
532 scsi_req_continue(s
->current_req
);
533 s
->data_in_ready
= false;
538 if (esp_get_tc(s
) != 0) {
539 /* Copy device data to FIFO */
540 len
= MIN(s
->async_len
, esp_get_tc(s
));
541 len
= MIN(len
, fifo8_num_free(&s
->fifo
));
542 fifo8_push_all(&s
->fifo
, s
->async_buf
, len
);
546 esp_set_tc(s
, esp_get_tc(s
) - len
);
548 if (esp_get_tc(s
) == 0) {
549 /* Indicate transfer to FIFO is complete */
550 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
555 /* Partially filled a scsi buffer. Complete immediately. */
561 static void esp_do_dma(ESPState
*s
)
563 uint32_t len
, cmdlen
;
564 int to_device
= ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_DO
);
565 uint8_t buf
[ESP_CMDFIFO_SZ
];
570 * handle_ti_cmd() case: esp_do_dma() is called only from
571 * handle_ti_cmd() with do_cmd != NULL (see the assert())
573 cmdlen
= fifo8_num_used(&s
->cmdfifo
);
574 trace_esp_do_dma(cmdlen
, len
);
575 if (s
->dma_memory_read
) {
576 s
->dma_memory_read(s
->dma_opaque
, buf
, len
);
577 fifo8_push_all(&s
->cmdfifo
, buf
, len
);
579 s
->pdma_cb
= do_dma_pdma_cb
;
583 trace_esp_handle_ti_cmd(cmdlen
);
585 if ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_CD
) {
586 /* No command received */
587 if (s
->cmdfifo_cdb_offset
== fifo8_num_used(&s
->cmdfifo
)) {
591 /* Command has been received */
596 * Extra message out bytes received: update cmdfifo_cdb_offset
597 * and then switch to commmand phase
599 s
->cmdfifo_cdb_offset
= fifo8_num_used(&s
->cmdfifo
);
600 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
601 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
602 s
->rregs
[ESP_RINTR
] |= INTR_BS
;
607 if (s
->async_len
== 0) {
608 /* Defer until data is available. */
611 if (len
> s
->async_len
) {
615 if (s
->dma_memory_read
) {
616 s
->dma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
618 s
->pdma_cb
= do_dma_pdma_cb
;
623 if (s
->dma_memory_write
) {
624 s
->dma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
626 /* Adjust TC for any leftover data in the FIFO */
627 if (!fifo8_is_empty(&s
->fifo
)) {
628 esp_set_tc(s
, esp_get_tc(s
) - fifo8_num_used(&s
->fifo
));
631 /* Copy device data to FIFO */
632 len
= MIN(len
, fifo8_num_free(&s
->fifo
));
633 fifo8_push_all(&s
->fifo
, s
->async_buf
, len
);
639 * MacOS toolbox uses a TI length of 16 bytes for all commands, so
640 * commands shorter than this must be padded accordingly
642 if (len
< esp_get_tc(s
) && esp_get_tc(s
) <= ESP_FIFO_SZ
) {
643 while (fifo8_num_used(&s
->fifo
) < ESP_FIFO_SZ
) {
649 esp_set_tc(s
, esp_get_tc(s
) - len
);
650 s
->pdma_cb
= do_dma_pdma_cb
;
653 /* Indicate transfer to FIFO is complete */
654 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
658 esp_set_tc(s
, esp_get_tc(s
) - len
);
666 if (s
->async_len
== 0) {
667 scsi_req_continue(s
->current_req
);
669 * If there is still data to be read from the device then
670 * complete the DMA operation immediately. Otherwise defer
671 * until the scsi layer has completed.
673 if (to_device
|| esp_get_tc(s
) != 0 || s
->ti_size
== 0) {
678 /* Partially filled a scsi buffer. Complete immediately. */
683 static void esp_do_nodma(ESPState
*s
)
685 int to_device
= ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_DO
);
690 cmdlen
= fifo8_num_used(&s
->cmdfifo
);
691 trace_esp_handle_ti_cmd(cmdlen
);
693 if ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_CD
) {
694 /* No command received */
695 if (s
->cmdfifo_cdb_offset
== fifo8_num_used(&s
->cmdfifo
)) {
699 /* Command has been received */
704 * Extra message out bytes received: update cmdfifo_cdb_offset
705 * and then switch to commmand phase
707 s
->cmdfifo_cdb_offset
= fifo8_num_used(&s
->cmdfifo
);
708 s
->rregs
[ESP_RSTAT
] = STAT_TC
| STAT_CD
;
709 s
->rregs
[ESP_RSEQ
] = SEQ_CD
;
710 s
->rregs
[ESP_RINTR
] |= INTR_BS
;
716 if (s
->async_len
== 0) {
717 /* Defer until data is available. */
722 len
= MIN(fifo8_num_used(&s
->fifo
), ESP_FIFO_SZ
);
723 memcpy(s
->async_buf
, fifo8_pop_buf(&s
->fifo
, len
, &n
), len
);
728 len
= MIN(s
->ti_size
, s
->async_len
);
729 len
= MIN(len
, fifo8_num_free(&s
->fifo
));
730 fifo8_push_all(&s
->fifo
, s
->async_buf
, len
);
736 if (s
->async_len
== 0) {
737 scsi_req_continue(s
->current_req
);
739 if (to_device
|| s
->ti_size
== 0) {
744 s
->rregs
[ESP_RINTR
] |= INTR_BS
;
748 void esp_command_complete(SCSIRequest
*req
, size_t resid
)
750 ESPState
*s
= req
->hba_private
;
752 trace_esp_command_complete();
753 if (s
->ti_size
!= 0) {
754 trace_esp_command_complete_unexpected();
759 trace_esp_command_complete_fail();
761 s
->status
= req
->status
;
762 s
->rregs
[ESP_RSTAT
] = STAT_ST
;
765 if (s
->current_req
) {
766 scsi_req_unref(s
->current_req
);
767 s
->current_req
= NULL
;
768 s
->current_dev
= NULL
;
772 void esp_transfer_data(SCSIRequest
*req
, uint32_t len
)
774 ESPState
*s
= req
->hba_private
;
775 int to_device
= ((s
->rregs
[ESP_RSTAT
] & 7) == STAT_DO
);
776 uint32_t dmalen
= esp_get_tc(s
);
779 trace_esp_transfer_data(dmalen
, s
->ti_size
);
781 s
->async_buf
= scsi_req_get_buf(req
);
783 if (!to_device
&& !s
->data_in_ready
) {
785 * Initial incoming data xfer is complete so raise command
786 * completion interrupt
788 s
->data_in_ready
= true;
789 s
->rregs
[ESP_RSTAT
] |= STAT_TC
;
790 s
->rregs
[ESP_RINTR
] |= INTR_BS
;
794 * If data is ready to transfer and the TI command has already
795 * been executed, start DMA immediately. Otherwise DMA will start
796 * when host sends the TI command
798 if (s
->ti_size
&& (s
->rregs
[ESP_CMD
] == (CMD_TI
| CMD_DMA
))) {
804 if (s
->ti_cmd
== 0) {
806 * Always perform the initial transfer upon reception of the next TI
807 * command to ensure the DMA/non-DMA status of the command is correct.
808 * It is not possible to use s->dma directly in the section below as
809 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the
810 * async data transfer is delayed then s->dma is set incorrectly.
815 if (s
->ti_cmd
& CMD_DMA
) {
818 } else if (s
->ti_size
<= 0) {
820 * If this was the last part of a DMA transfer then the
821 * completion interrupt is deferred to here.
831 static void handle_ti(ESPState
*s
)
835 if (s
->dma
&& !s
->dma_enabled
) {
836 s
->dma_cb
= handle_ti
;
840 s
->ti_cmd
= s
->rregs
[ESP_CMD
];
842 dmalen
= esp_get_tc(s
);
843 trace_esp_handle_ti(dmalen
);
844 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
847 trace_esp_handle_ti(s
->ti_size
);
852 void esp_hard_reset(ESPState
*s
)
854 memset(s
->rregs
, 0, ESP_REGS
);
855 memset(s
->wregs
, 0, ESP_REGS
);
858 fifo8_reset(&s
->fifo
);
859 fifo8_reset(&s
->cmdfifo
);
864 s
->rregs
[ESP_CFG1
] = 7;
867 static void esp_soft_reset(ESPState
*s
)
869 qemu_irq_lower(s
->irq
);
870 qemu_irq_lower(s
->irq_data
);
874 static void parent_esp_reset(ESPState
*s
, int irq
, int level
)
881 uint64_t esp_reg_read(ESPState
*s
, uint32_t saddr
)
887 if (s
->dma_memory_read
&& s
->dma_memory_write
&&
888 (s
->rregs
[ESP_RSTAT
] & STAT_PIO_MASK
) == 0) {
890 qemu_log_mask(LOG_UNIMP
, "esp: PIO data read not implemented\n");
891 s
->rregs
[ESP_FIFO
] = 0;
893 s
->rregs
[ESP_FIFO
] = esp_fifo_pop(s
);
895 val
= s
->rregs
[ESP_FIFO
];
899 * Clear sequence step, interrupt register and all status bits
902 val
= s
->rregs
[ESP_RINTR
];
903 s
->rregs
[ESP_RINTR
] = 0;
904 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
905 s
->rregs
[ESP_RSEQ
] = SEQ_0
;
909 /* Return the unique id if the value has never been written */
910 if (!s
->tchi_written
) {
913 val
= s
->rregs
[saddr
];
917 /* Bottom 5 bits indicate number of bytes in FIFO */
918 val
= fifo8_num_used(&s
->fifo
);
921 val
= s
->rregs
[saddr
];
925 trace_esp_mem_readb(saddr
, val
);
929 void esp_reg_write(ESPState
*s
, uint32_t saddr
, uint64_t val
)
931 trace_esp_mem_writeb(saddr
, s
->wregs
[saddr
], val
);
934 s
->tchi_written
= true;
938 s
->rregs
[ESP_RSTAT
] &= ~STAT_TC
;
942 esp_cmdfifo_push(s
, val
);
944 esp_fifo_push(s
, val
);
947 /* Non-DMA transfers raise an interrupt after every byte */
948 if (s
->rregs
[ESP_CMD
] == CMD_TI
) {
949 s
->rregs
[ESP_RINTR
] |= INTR_FC
| INTR_BS
;
954 s
->rregs
[saddr
] = val
;
957 /* Reload DMA counter. */
958 if (esp_get_stc(s
) == 0) {
959 esp_set_tc(s
, 0x10000);
961 esp_set_tc(s
, esp_get_stc(s
));
966 switch (val
& CMD_CMD
) {
968 trace_esp_mem_writeb_cmd_nop(val
);
971 trace_esp_mem_writeb_cmd_flush(val
);
972 fifo8_reset(&s
->fifo
);
975 trace_esp_mem_writeb_cmd_reset(val
);
979 trace_esp_mem_writeb_cmd_bus_reset(val
);
980 if (!(s
->wregs
[ESP_CFG1
] & CFG1_RESREPT
)) {
981 s
->rregs
[ESP_RINTR
] |= INTR_RST
;
986 trace_esp_mem_writeb_cmd_ti(val
);
990 trace_esp_mem_writeb_cmd_iccs(val
);
992 s
->rregs
[ESP_RINTR
] |= INTR_FC
;
993 s
->rregs
[ESP_RSTAT
] |= STAT_MI
;
996 trace_esp_mem_writeb_cmd_msgacc(val
);
997 s
->rregs
[ESP_RINTR
] |= INTR_DC
;
998 s
->rregs
[ESP_RSEQ
] = 0;
999 s
->rregs
[ESP_RFLAGS
] = 0;
1003 trace_esp_mem_writeb_cmd_pad(val
);
1004 s
->rregs
[ESP_RSTAT
] = STAT_TC
;
1005 s
->rregs
[ESP_RINTR
] |= INTR_FC
;
1006 s
->rregs
[ESP_RSEQ
] = 0;
1009 trace_esp_mem_writeb_cmd_satn(val
);
1012 trace_esp_mem_writeb_cmd_rstatn(val
);
1015 trace_esp_mem_writeb_cmd_sel(val
);
1016 handle_s_without_atn(s
);
1019 trace_esp_mem_writeb_cmd_selatn(val
);
1023 trace_esp_mem_writeb_cmd_selatns(val
);
1024 handle_satn_stop(s
);
1027 trace_esp_mem_writeb_cmd_ensel(val
);
1028 s
->rregs
[ESP_RINTR
] = 0;
1031 trace_esp_mem_writeb_cmd_dissel(val
);
1032 s
->rregs
[ESP_RINTR
] = 0;
1036 trace_esp_error_unhandled_command(val
);
1040 case ESP_WBUSID
... ESP_WSYNO
:
1043 case ESP_CFG2
: case ESP_CFG3
:
1044 case ESP_RES3
: case ESP_RES4
:
1045 s
->rregs
[saddr
] = val
;
1047 case ESP_WCCF
... ESP_WTEST
:
1050 trace_esp_error_invalid_write(val
, saddr
);
1053 s
->wregs
[saddr
] = val
;
1056 static bool esp_mem_accepts(void *opaque
, hwaddr addr
,
1057 unsigned size
, bool is_write
,
1060 return (size
== 1) || (is_write
&& size
== 4);
1063 static bool esp_is_before_version_5(void *opaque
, int version_id
)
1065 ESPState
*s
= ESP(opaque
);
1067 version_id
= MIN(version_id
, s
->mig_version_id
);
1068 return version_id
< 5;
1071 static bool esp_is_version_5(void *opaque
, int version_id
)
1073 ESPState
*s
= ESP(opaque
);
1075 version_id
= MIN(version_id
, s
->mig_version_id
);
1076 return version_id
== 5;
1079 static int esp_pre_save(void *opaque
)
1081 ESPState
*s
= ESP(opaque
);
1083 s
->mig_version_id
= vmstate_esp
.version_id
;
1087 static int esp_post_load(void *opaque
, int version_id
)
1089 ESPState
*s
= ESP(opaque
);
1092 version_id
= MIN(version_id
, s
->mig_version_id
);
1094 if (version_id
< 5) {
1095 esp_set_tc(s
, s
->mig_dma_left
);
1097 /* Migrate ti_buf to fifo */
1098 len
= s
->mig_ti_wptr
- s
->mig_ti_rptr
;
1099 for (i
= 0; i
< len
; i
++) {
1100 fifo8_push(&s
->fifo
, s
->mig_ti_buf
[i
]);
1103 /* Migrate cmdbuf to cmdfifo */
1104 for (i
= 0; i
< s
->mig_cmdlen
; i
++) {
1105 fifo8_push(&s
->cmdfifo
, s
->mig_cmdbuf
[i
]);
1109 s
->mig_version_id
= vmstate_esp
.version_id
;
1113 const VMStateDescription vmstate_esp
= {
1116 .minimum_version_id
= 3,
1117 .pre_save
= esp_pre_save
,
1118 .post_load
= esp_post_load
,
1119 .fields
= (VMStateField
[]) {
1120 VMSTATE_BUFFER(rregs
, ESPState
),
1121 VMSTATE_BUFFER(wregs
, ESPState
),
1122 VMSTATE_INT32(ti_size
, ESPState
),
1123 VMSTATE_UINT32_TEST(mig_ti_rptr
, ESPState
, esp_is_before_version_5
),
1124 VMSTATE_UINT32_TEST(mig_ti_wptr
, ESPState
, esp_is_before_version_5
),
1125 VMSTATE_BUFFER_TEST(mig_ti_buf
, ESPState
, esp_is_before_version_5
),
1126 VMSTATE_UINT32(status
, ESPState
),
1127 VMSTATE_UINT32_TEST(mig_deferred_status
, ESPState
,
1128 esp_is_before_version_5
),
1129 VMSTATE_BOOL_TEST(mig_deferred_complete
, ESPState
,
1130 esp_is_before_version_5
),
1131 VMSTATE_UINT32(dma
, ESPState
),
1132 VMSTATE_STATIC_BUFFER(mig_cmdbuf
, ESPState
, 0,
1133 esp_is_before_version_5
, 0, 16),
1134 VMSTATE_STATIC_BUFFER(mig_cmdbuf
, ESPState
, 4,
1135 esp_is_before_version_5
, 16,
1136 sizeof(typeof_field(ESPState
, mig_cmdbuf
))),
1137 VMSTATE_UINT32_TEST(mig_cmdlen
, ESPState
, esp_is_before_version_5
),
1138 VMSTATE_UINT32(do_cmd
, ESPState
),
1139 VMSTATE_UINT32_TEST(mig_dma_left
, ESPState
, esp_is_before_version_5
),
1140 VMSTATE_BOOL_TEST(data_in_ready
, ESPState
, esp_is_version_5
),
1141 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset
, ESPState
, esp_is_version_5
),
1142 VMSTATE_FIFO8_TEST(fifo
, ESPState
, esp_is_version_5
),
1143 VMSTATE_FIFO8_TEST(cmdfifo
, ESPState
, esp_is_version_5
),
1144 VMSTATE_UINT8_TEST(ti_cmd
, ESPState
, esp_is_version_5
),
1145 VMSTATE_END_OF_LIST()
1149 static void sysbus_esp_mem_write(void *opaque
, hwaddr addr
,
1150 uint64_t val
, unsigned int size
)
1152 SysBusESPState
*sysbus
= opaque
;
1153 ESPState
*s
= ESP(&sysbus
->esp
);
1156 saddr
= addr
>> sysbus
->it_shift
;
1157 esp_reg_write(s
, saddr
, val
);
1160 static uint64_t sysbus_esp_mem_read(void *opaque
, hwaddr addr
,
1163 SysBusESPState
*sysbus
= opaque
;
1164 ESPState
*s
= ESP(&sysbus
->esp
);
1167 saddr
= addr
>> sysbus
->it_shift
;
1168 return esp_reg_read(s
, saddr
);
1171 static const MemoryRegionOps sysbus_esp_mem_ops
= {
1172 .read
= sysbus_esp_mem_read
,
1173 .write
= sysbus_esp_mem_write
,
1174 .endianness
= DEVICE_NATIVE_ENDIAN
,
1175 .valid
.accepts
= esp_mem_accepts
,
1178 static void sysbus_esp_pdma_write(void *opaque
, hwaddr addr
,
1179 uint64_t val
, unsigned int size
)
1181 SysBusESPState
*sysbus
= opaque
;
1182 ESPState
*s
= ESP(&sysbus
->esp
);
1185 trace_esp_pdma_write(size
);
1189 esp_pdma_write(s
, val
);
1192 esp_pdma_write(s
, val
>> 8);
1193 esp_pdma_write(s
, val
);
1196 dmalen
= esp_get_tc(s
);
1197 if (dmalen
== 0 || fifo8_num_free(&s
->fifo
) < 2) {
1202 static uint64_t sysbus_esp_pdma_read(void *opaque
, hwaddr addr
,
1205 SysBusESPState
*sysbus
= opaque
;
1206 ESPState
*s
= ESP(&sysbus
->esp
);
1209 trace_esp_pdma_read(size
);
1213 val
= esp_pdma_read(s
);
1216 val
= esp_pdma_read(s
);
1217 val
= (val
<< 8) | esp_pdma_read(s
);
1220 if (fifo8_num_used(&s
->fifo
) < 2) {
1226 static const MemoryRegionOps sysbus_esp_pdma_ops
= {
1227 .read
= sysbus_esp_pdma_read
,
1228 .write
= sysbus_esp_pdma_write
,
1229 .endianness
= DEVICE_NATIVE_ENDIAN
,
1230 .valid
.min_access_size
= 1,
1231 .valid
.max_access_size
= 4,
1232 .impl
.min_access_size
= 1,
1233 .impl
.max_access_size
= 2,
1236 static const struct SCSIBusInfo esp_scsi_info
= {
1238 .max_target
= ESP_MAX_DEVS
,
1241 .transfer_data
= esp_transfer_data
,
1242 .complete
= esp_command_complete
,
1243 .cancel
= esp_request_cancelled
1246 static void sysbus_esp_gpio_demux(void *opaque
, int irq
, int level
)
1248 SysBusESPState
*sysbus
= SYSBUS_ESP(opaque
);
1249 ESPState
*s
= ESP(&sysbus
->esp
);
1253 parent_esp_reset(s
, irq
, level
);
1256 esp_dma_enable(opaque
, irq
, level
);
1261 static void sysbus_esp_realize(DeviceState
*dev
, Error
**errp
)
1263 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1264 SysBusESPState
*sysbus
= SYSBUS_ESP(dev
);
1265 ESPState
*s
= ESP(&sysbus
->esp
);
1267 if (!qdev_realize(DEVICE(s
), NULL
, errp
)) {
1271 sysbus_init_irq(sbd
, &s
->irq
);
1272 sysbus_init_irq(sbd
, &s
->irq_data
);
1273 assert(sysbus
->it_shift
!= -1);
1275 s
->chip_id
= TCHI_FAS100A
;
1276 memory_region_init_io(&sysbus
->iomem
, OBJECT(sysbus
), &sysbus_esp_mem_ops
,
1277 sysbus
, "esp-regs", ESP_REGS
<< sysbus
->it_shift
);
1278 sysbus_init_mmio(sbd
, &sysbus
->iomem
);
1279 memory_region_init_io(&sysbus
->pdma
, OBJECT(sysbus
), &sysbus_esp_pdma_ops
,
1280 sysbus
, "esp-pdma", 4);
1281 sysbus_init_mmio(sbd
, &sysbus
->pdma
);
1283 qdev_init_gpio_in(dev
, sysbus_esp_gpio_demux
, 2);
1285 scsi_bus_new(&s
->bus
, sizeof(s
->bus
), dev
, &esp_scsi_info
, NULL
);
1288 static void sysbus_esp_hard_reset(DeviceState
*dev
)
1290 SysBusESPState
*sysbus
= SYSBUS_ESP(dev
);
1291 ESPState
*s
= ESP(&sysbus
->esp
);
1296 static void sysbus_esp_init(Object
*obj
)
1298 SysBusESPState
*sysbus
= SYSBUS_ESP(obj
);
1300 object_initialize_child(obj
, "esp", &sysbus
->esp
, TYPE_ESP
);
1303 static const VMStateDescription vmstate_sysbus_esp_scsi
= {
1304 .name
= "sysbusespscsi",
1306 .minimum_version_id
= 1,
1307 .fields
= (VMStateField
[]) {
1308 VMSTATE_UINT8_V(esp
.mig_version_id
, SysBusESPState
, 2),
1309 VMSTATE_STRUCT(esp
, SysBusESPState
, 0, vmstate_esp
, ESPState
),
1310 VMSTATE_END_OF_LIST()
1314 static void sysbus_esp_class_init(ObjectClass
*klass
, void *data
)
1316 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1318 dc
->realize
= sysbus_esp_realize
;
1319 dc
->reset
= sysbus_esp_hard_reset
;
1320 dc
->vmsd
= &vmstate_sysbus_esp_scsi
;
1321 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1324 static const TypeInfo sysbus_esp_info
= {
1325 .name
= TYPE_SYSBUS_ESP
,
1326 .parent
= TYPE_SYS_BUS_DEVICE
,
1327 .instance_init
= sysbus_esp_init
,
1328 .instance_size
= sizeof(SysBusESPState
),
1329 .class_init
= sysbus_esp_class_init
,
1332 static void esp_finalize(Object
*obj
)
1334 ESPState
*s
= ESP(obj
);
1336 fifo8_destroy(&s
->fifo
);
1337 fifo8_destroy(&s
->cmdfifo
);
1340 static void esp_init(Object
*obj
)
1342 ESPState
*s
= ESP(obj
);
1344 fifo8_create(&s
->fifo
, ESP_FIFO_SZ
);
1345 fifo8_create(&s
->cmdfifo
, ESP_CMDFIFO_SZ
);
1348 static void esp_class_init(ObjectClass
*klass
, void *data
)
1350 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1352 /* internal device for sysbusesp/pciespscsi, not user-creatable */
1353 dc
->user_creatable
= false;
1354 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1357 static const TypeInfo esp_info
= {
1359 .parent
= TYPE_DEVICE
,
1360 .instance_init
= esp_init
,
1361 .instance_finalize
= esp_finalize
,
1362 .instance_size
= sizeof(ESPState
),
1363 .class_init
= esp_class_init
,
1366 static void esp_register_types(void)
1368 type_register_static(&sysbus_esp_info
);
1369 type_register_static(&esp_info
);
1372 type_init(esp_register_types
)