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qom: Put name parameter before value / visitor parameter
[qemu/ar7.git] / hw / arm / fsl-imx6.c
blobe359ee579d5af75c5c7aaad7e158b6fec3585fcf
1 /*
2 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6 SOC emulation.
5 *
6 * Based on hw/arm/fsl-imx31.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "hw/arm/fsl-imx6.h"
25 #include "hw/usb/imx-usb-phy.h"
26 #include "hw/boards.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/sysemu.h"
29 #include "chardev/char.h"
30 #include "qemu/error-report.h"
31 #include "qemu/module.h"
32
33 #define IMX6_ESDHC_CAPABILITIES 0x057834b4
34
35 #define NAME_SIZE 20
36
37 static void fsl_imx6_init(Object *obj)
38 {
39 MachineState *ms = MACHINE(qdev_get_machine());
40 FslIMX6State *s = FSL_IMX6(obj);
41 char name[NAME_SIZE];
42 int i;
43
44 for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
45 snprintf(name, NAME_SIZE, "cpu%d", i);
46 object_initialize_child(obj, name, &s->cpu[i],
47 ARM_CPU_TYPE_NAME("cortex-a9"));
48 }
49
50 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
51
52 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM);
53
54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
55
56 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
57 snprintf(name, NAME_SIZE, "uart%d", i + 1);
58 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
59 }
60
61 object_initialize_child(obj, "gpt", &s->gpt, TYPE_IMX6_GPT);
62
63 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
64 snprintf(name, NAME_SIZE, "epit%d", i + 1);
65 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT);
66 }
67
68 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
69 snprintf(name, NAME_SIZE, "i2c%d", i + 1);
70 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
71 }
72
73 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
74 snprintf(name, NAME_SIZE, "gpio%d", i + 1);
75 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO);
76 }
77
78 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
79 snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
80 object_initialize_child(obj, name, &s->esdhc[i], TYPE_IMX_USDHC);
81 }
82
83 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
84 snprintf(name, NAME_SIZE, "usbphy%d", i);
85 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
86 }
87 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
88 snprintf(name, NAME_SIZE, "usb%d", i);
89 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
90 }
91
92 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
93 snprintf(name, NAME_SIZE, "spi%d", i + 1);
94 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
95 }
96 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
97 snprintf(name, NAME_SIZE, "wdt%d", i);
98 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);
99 }
100
101
102 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
103 }
104
105 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
106 {
107 MachineState *ms = MACHINE(qdev_get_machine());
108 FslIMX6State *s = FSL_IMX6(dev);
109 uint16_t i;
110 Error *err = NULL;
111 unsigned int smp_cpus = ms->smp.cpus;
112
113 if (smp_cpus > FSL_IMX6_NUM_CPUS) {
114 error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
115 TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
116 return;
117 }
118
119 for (i = 0; i < smp_cpus; i++) {
120
121 /* On uniprocessor, the CBAR is set to 0 */
122 if (smp_cpus > 1) {
123 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
124 FSL_IMX6_A9MPCORE_ADDR, &error_abort);
125 }
126
127 /* All CPU but CPU 0 start in power off mode */
128 if (i) {
129 object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off",
130 true, &error_abort);
131 }
132
133 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, &err)) {
134 error_propagate(errp, err);
135 return;
136 }
137 }
138
139 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus,
140 &error_abort);
141
142 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq",
143 FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
144
145 if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err)) {
146 error_propagate(errp, err);
147 return;
148 }
149 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
150
151 for (i = 0; i < smp_cpus; i++) {
152 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
153 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
154 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
155 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
156 }
157
158 if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &err)) {
159 error_propagate(errp, err);
160 return;
161 }
162 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
163
164 if (!sysbus_realize(SYS_BUS_DEVICE(&s->src), &err)) {
165 error_propagate(errp, err);
166 return;
167 }
168 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
169
170 /* Initialize all UARTs */
171 for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
172 static const struct {
173 hwaddr addr;
174 unsigned int irq;
175 } serial_table[FSL_IMX6_NUM_UARTS] = {
176 { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
177 { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
178 { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
179 { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
180 { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
181 };
182
183 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
184
185 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &err)) {
186 error_propagate(errp, err);
187 return;
188 }
189
190 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
191 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
192 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
193 serial_table[i].irq));
194 }
195
196 s->gpt.ccm = IMX_CCM(&s->ccm);
197
198 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpt), &err)) {
199 error_propagate(errp, err);
200 return;
201 }
202
203 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
204 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
205 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
206 FSL_IMX6_GPT_IRQ));
207
208 /* Initialize all EPIT timers */
209 for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
210 static const struct {
211 hwaddr addr;
212 unsigned int irq;
213 } epit_table[FSL_IMX6_NUM_EPITS] = {
214 { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
215 { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
216 };
217
218 s->epit[i].ccm = IMX_CCM(&s->ccm);
219
220 if (!sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &err)) {
221 error_propagate(errp, err);
222 return;
223 }
224
225 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
226 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
227 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
228 epit_table[i].irq));
229 }
230
231 /* Initialize all I2C */
232 for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
233 static const struct {
234 hwaddr addr;
235 unsigned int irq;
236 } i2c_table[FSL_IMX6_NUM_I2CS] = {
237 { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
238 { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
239 { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
240 };
241
242 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &err)) {
243 error_propagate(errp, err);
244 return;
245 }
246
247 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
248 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
249 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
250 i2c_table[i].irq));
251 }
252
253 /* Initialize all GPIOs */
254 for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
255 static const struct {
256 hwaddr addr;
257 unsigned int irq_low;
258 unsigned int irq_high;
259 } gpio_table[FSL_IMX6_NUM_GPIOS] = {
260 {
261 FSL_IMX6_GPIO1_ADDR,
262 FSL_IMX6_GPIO1_LOW_IRQ,
263 FSL_IMX6_GPIO1_HIGH_IRQ
264 },
265 {
266 FSL_IMX6_GPIO2_ADDR,
267 FSL_IMX6_GPIO2_LOW_IRQ,
268 FSL_IMX6_GPIO2_HIGH_IRQ
269 },
270 {
271 FSL_IMX6_GPIO3_ADDR,
272 FSL_IMX6_GPIO3_LOW_IRQ,
273 FSL_IMX6_GPIO3_HIGH_IRQ
274 },
275 {
276 FSL_IMX6_GPIO4_ADDR,
277 FSL_IMX6_GPIO4_LOW_IRQ,
278 FSL_IMX6_GPIO4_HIGH_IRQ
279 },
280 {
281 FSL_IMX6_GPIO5_ADDR,
282 FSL_IMX6_GPIO5_LOW_IRQ,
283 FSL_IMX6_GPIO5_HIGH_IRQ
284 },
285 {
286 FSL_IMX6_GPIO6_ADDR,
287 FSL_IMX6_GPIO6_LOW_IRQ,
288 FSL_IMX6_GPIO6_HIGH_IRQ
289 },
290 {
291 FSL_IMX6_GPIO7_ADDR,
292 FSL_IMX6_GPIO7_LOW_IRQ,
293 FSL_IMX6_GPIO7_HIGH_IRQ
294 },
295 };
296
297 object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true,
298 &error_abort);
299 object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq",
300 true, &error_abort);
301 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &err)) {
302 error_propagate(errp, err);
303 return;
304 }
305
306 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
308 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
309 gpio_table[i].irq_low));
310 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
311 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
312 gpio_table[i].irq_high));
313 }
314
315 /* Initialize all SDHC */
316 for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
317 static const struct {
318 hwaddr addr;
319 unsigned int irq;
320 } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
321 { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
322 { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
323 { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
324 { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
325 };
326
327 /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
328 object_property_set_uint(OBJECT(&s->esdhc[i]), "sd-spec-version", 3,
329 &error_abort);
330 object_property_set_uint(OBJECT(&s->esdhc[i]), "capareg",
331 IMX6_ESDHC_CAPABILITIES, &error_abort);
332 object_property_set_uint(OBJECT(&s->esdhc[i]), "vendor",
333 SDHCI_VENDOR_IMX, &error_abort);
334 if (!sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err)) {
335 error_propagate(errp, err);
336 return;
337 }
338 sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
339 sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
340 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
341 esdhc_table[i].irq));
342 }
343
344 /* USB */
345 for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
346 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
348 FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
349 }
350 for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
351 static const int FSL_IMX6_USBn_IRQ[] = {
352 FSL_IMX6_USB_OTG_IRQ,
353 FSL_IMX6_USB_HOST1_IRQ,
354 FSL_IMX6_USB_HOST2_IRQ,
355 FSL_IMX6_USB_HOST3_IRQ,
356 };
357
358 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
360 FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
361 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
362 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
363 FSL_IMX6_USBn_IRQ[i]));
364 }
365
366 /* Initialize all ECSPI */
367 for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
368 static const struct {
369 hwaddr addr;
370 unsigned int irq;
371 } spi_table[FSL_IMX6_NUM_ECSPIS] = {
372 { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
373 { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
374 { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
375 { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
376 { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
377 };
378
379 /* Initialize the SPI */
380 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) {
381 error_propagate(errp, err);
382 return;
383 }
384
385 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
387 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
388 spi_table[i].irq));
389 }
390
391 qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
392 if (!sysbus_realize(SYS_BUS_DEVICE(&s->eth), &err)) {
393 error_propagate(errp, err);
394 return;
395 }
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
397 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
398 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
399 FSL_IMX6_ENET_MAC_IRQ));
400 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
401 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
402 FSL_IMX6_ENET_MAC_1588_IRQ));
403
404 /*
405 * Watchdog
406 */
407 for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) {
408 static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = {
409 FSL_IMX6_WDOG1_ADDR,
410 FSL_IMX6_WDOG2_ADDR,
411 };
412 static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = {
413 FSL_IMX6_WDOG1_IRQ,
414 FSL_IMX6_WDOG2_IRQ,
415 };
416
417 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support",
418 true, &error_abort);
419 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort);
420
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
422 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
423 qdev_get_gpio_in(DEVICE(&s->a9mpcore),
424 FSL_IMX6_WDOGn_IRQ[i]));
425 }
426
427 /* ROM memory */
428 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
429 FSL_IMX6_ROM_SIZE, &err);
430 if (err) {
431 error_propagate(errp, err);
432 return;
433 }
434 memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
435 &s->rom);
436
437 /* CAAM memory */
438 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6.caam",
439 FSL_IMX6_CAAM_MEM_SIZE, &err);
440 if (err) {
441 error_propagate(errp, err);
442 return;
443 }
444 memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
445 &s->caam);
446
447 /* OCRAM memory */
448 memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
449 &err);
450 if (err) {
451 error_propagate(errp, err);
452 return;
453 }
454 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
455 &s->ocram);
456
457 /* internal OCRAM (256 KB) is aliased over 1 MB */
458 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), "imx6.ocram_alias",
459 &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
460 memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
461 &s->ocram_alias);
462 }
463
464 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
465 {
466 DeviceClass *dc = DEVICE_CLASS(oc);
467
468 dc->realize = fsl_imx6_realize;
469 dc->desc = "i.MX6 SOC";
470 /* Reason: Uses serial_hd() in the realize() function */
471 dc->user_creatable = false;
472 }
473
474 static const TypeInfo fsl_imx6_type_info = {
475 .name = TYPE_FSL_IMX6,
476 .parent = TYPE_DEVICE,
477 .instance_size = sizeof(FslIMX6State),
478 .instance_init = fsl_imx6_init,
479 .class_init = fsl_imx6_class_init,
480 };
481
482 static void fsl_imx6_register_types(void)
483 {
484 type_register_static(&fsl_imx6_type_info);
485 }
486
487 type_init(fsl_imx6_register_types)
AR7 emulation for QEMU