target/ppc/cpu-qom.h

   1 /*
   2  * QEMU PowerPC CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef QEMU_PPC_CPU_QOM_H
  21 #define QEMU_PPC_CPU_QOM_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "qom/object.h"
  25
  26 #ifdef TARGET_PPC64
  27 #define TYPE_POWERPC_CPU "powerpc64-cpu"
  28 #else
  29 #define TYPE_POWERPC_CPU "powerpc-cpu"
  30 #endif
  31
  32 OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass,
  33                     POWERPC_CPU)
  34
  35 typedef struct CPUPPCState CPUPPCState;
  36 typedef struct ppc_tb_t ppc_tb_t;
  37 typedef struct ppc_dcr_t ppc_dcr_t;
  38
  39 /*****************************************************************************/
  40 /* MMU model                                                                 */
  41 typedef enum powerpc_mmu_t powerpc_mmu_t;
  42 enum powerpc_mmu_t {
  43     POWERPC_MMU_UNKNOWN    = 0x00000000,
  44     /* Standard 32 bits PowerPC MMU                            */
  45     POWERPC_MMU_32B        = 0x00000001,
  46     /* PowerPC 6xx MMU with software TLB                       */
  47     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  48     /* PowerPC 74xx MMU with software TLB                      */
  49     POWERPC_MMU_SOFT_74xx  = 0x00000003,
  50     /* PowerPC 4xx MMU with software TLB                       */
  51     POWERPC_MMU_SOFT_4xx   = 0x00000004,
  52     /* PowerPC 4xx MMU with software TLB and zones protections */
  53     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
  54     /* PowerPC MMU in real mode only                           */
  55     POWERPC_MMU_REAL       = 0x00000006,
  56     /* Freescale MPC8xx MMU model                              */
  57     POWERPC_MMU_MPC8xx     = 0x00000007,
  58     /* BookE MMU model                                         */
  59     POWERPC_MMU_BOOKE      = 0x00000008,
  60     /* BookE 2.06 MMU model                                    */
  61     POWERPC_MMU_BOOKE206   = 0x00000009,
  62     /* PowerPC 601 MMU model (specific BATs format)            */
  63     POWERPC_MMU_601        = 0x0000000A,
  64 #define POWERPC_MMU_64       0x00010000
  65     /* 64 bits PowerPC MMU                                     */
  66     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
  67     /* Architecture 2.03 and later (has LPCR) */
  68     POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,
  69     /* Architecture 2.06 variant                               */
  70     POWERPC_MMU_2_06       = POWERPC_MMU_64 | 0x00000003,
  71     /* Architecture 2.07 variant                               */
  72     POWERPC_MMU_2_07       = POWERPC_MMU_64 | 0x00000004,
  73     /* Architecture 3.00 variant                               */
  74     POWERPC_MMU_3_00       = POWERPC_MMU_64 | 0x00000005,
  75 };
  76
  77 /*****************************************************************************/
  78 /* Exception model                                                           */
  79 typedef enum powerpc_excp_t powerpc_excp_t;
  80 enum powerpc_excp_t {
  81     POWERPC_EXCP_UNKNOWN   = 0,
  82     /* Standard PowerPC exception model */
  83     POWERPC_EXCP_STD,
  84     /* PowerPC 40x exception model      */
  85     POWERPC_EXCP_40x,
  86     /* PowerPC 601 exception model      */
  87     POWERPC_EXCP_601,
  88     /* PowerPC 602 exception model      */
  89     POWERPC_EXCP_602,
  90     /* PowerPC 603 exception model      */
  91     POWERPC_EXCP_603,
  92     /* PowerPC 603e exception model     */
  93     POWERPC_EXCP_603E,
  94     /* PowerPC G2 exception model       */
  95     POWERPC_EXCP_G2,
  96     /* PowerPC 604 exception model      */
  97     POWERPC_EXCP_604,
  98     /* PowerPC 7x0 exception model      */
  99     POWERPC_EXCP_7x0,
 100     /* PowerPC 7x5 exception model      */
 101     POWERPC_EXCP_7x5,
 102     /* PowerPC 74xx exception model     */
 103     POWERPC_EXCP_74xx,
 104     /* BookE exception model            */
 105     POWERPC_EXCP_BOOKE,
 106     /* PowerPC 970 exception model      */
 107     POWERPC_EXCP_970,
 108     /* POWER7 exception model           */
 109     POWERPC_EXCP_POWER7,
 110     /* POWER8 exception model           */
 111     POWERPC_EXCP_POWER8,
 112     /* POWER9 exception model           */
 113     POWERPC_EXCP_POWER9,
 114 };
 115
 116 /*****************************************************************************/
 117 /* PM instructions */
 118 typedef enum {
 119     PPC_PM_DOZE,
 120     PPC_PM_NAP,
 121     PPC_PM_SLEEP,
 122     PPC_PM_RVWINKLE,
 123     PPC_PM_STOP,
 124 } powerpc_pm_insn_t;
 125
 126 /*****************************************************************************/
 127 /* Input pins model                                                          */
 128 typedef enum powerpc_input_t powerpc_input_t;
 129 enum powerpc_input_t {
 130     PPC_FLAGS_INPUT_UNKNOWN = 0,
 131     /* PowerPC 6xx bus                  */
 132     PPC_FLAGS_INPUT_6xx,
 133     /* BookE bus                        */
 134     PPC_FLAGS_INPUT_BookE,
 135     /* PowerPC 405 bus                  */
 136     PPC_FLAGS_INPUT_405,
 137     /* PowerPC 970 bus                  */
 138     PPC_FLAGS_INPUT_970,
 139     /* PowerPC POWER7 bus               */
 140     PPC_FLAGS_INPUT_POWER7,
 141     /* PowerPC POWER9 bus               */
 142     PPC_FLAGS_INPUT_POWER9,
 143     /* PowerPC 401 bus                  */
 144     PPC_FLAGS_INPUT_401,
 145     /* Freescale RCPU bus               */
 146     PPC_FLAGS_INPUT_RCPU,
 147 };
 148
 149 typedef struct PPCHash64Options PPCHash64Options;
 150
 151 /**
 152  * PowerPCCPUClass:
 153  * @parent_realize: The parent class' realize handler.
 154  * @parent_reset: The parent class' reset handler.
 155  *
 156  * A PowerPC CPU model.
 157  */
 158 struct PowerPCCPUClass {
 159     /*< private >*/
 160     CPUClass parent_class;
 161     /*< public >*/
 162
 163     DeviceRealize parent_realize;
 164     DeviceUnrealize parent_unrealize;
 165     DeviceReset parent_reset;
 166     void (*parent_parse_features)(const char *type, char *str, Error **errp);
 167
 168     uint32_t pvr;
 169     bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
 170     uint64_t pcr_mask;          /* Available bits in PCR register */
 171     uint64_t pcr_supported;     /* Bits for supported PowerISA versions */
 172     uint32_t svr;
 173     uint64_t insns_flags;
 174     uint64_t insns_flags2;
 175     uint64_t msr_mask;
 176     uint64_t lpcr_mask;         /* Available bits in the LPCR */
 177     uint64_t lpcr_pm;           /* Power-saving mode Exit Cause Enable bits */
 178     powerpc_mmu_t   mmu_model;
 179     powerpc_excp_t  excp_model;
 180     powerpc_input_t bus_model;
 181     uint32_t flags;
 182     int bfd_mach;
 183     uint32_t l1_dcache_size, l1_icache_size;
 184 #ifndef CONFIG_USER_ONLY
 185     unsigned int gdb_num_sprs;
 186     const char *gdb_spr_xml;
 187 #endif
 188     const PPCHash64Options *hash64_opts;
 189     struct ppc_radix_page_info *radix_page_info;
 190     uint32_t lrg_decr_bits;
 191     int n_host_threads;
 192     void (*init_proc)(CPUPPCState *env);
 193     int  (*check_pow)(CPUPPCState *env);
 194     int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
 195     bool (*interrupts_big_endian)(PowerPCCPU *cpu);
 196 };
 197
 198 #ifndef CONFIG_USER_ONLY
 199 typedef struct PPCTimebase {
 200     uint64_t guest_timebase;
 201     int64_t time_of_the_day_ns;
 202     bool runstate_paused;
 203 } PPCTimebase;
 204
 205 extern const VMStateDescription vmstate_ppc_timebase;
 206
 207 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) {            \
 208     .name       = (stringify(_field)),                                \
 209     .version_id = (_version),                                         \
 210     .size       = sizeof(PPCTimebase),                                \
 211     .vmsd       = &vmstate_ppc_timebase,                              \
 212     .flags      = VMS_STRUCT,                                         \
 213     .offset     = vmstate_offset_value(_state, _field, PPCTimebase),  \
 214 }
 215
 216 void cpu_ppc_clock_vm_state_change(void *opaque, int running,
 217                                    RunState state);
 218 #endif
 219
 220 #endif