io: store reference to thread information in the QIOTask struct
[qemu/ar7.git] / target / arm / translate.h
blob17748ddfb9d4f102908e8f850e135b4baec3bd0e
1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 #include "exec/translator.h"
7 /* internal defines */
8 typedef struct DisasContext {
9 DisasContextBase base;
10 const ARMISARegisters *isar;
12 target_ulong pc;
13 target_ulong page_start;
14 uint32_t insn;
15 /* Nonzero if this instruction has been conditionally skipped. */
16 int condjmp;
17 /* The label that will be jumped to when the instruction is skipped. */
18 TCGLabel *condlabel;
19 /* Thumb-2 conditional execution bits. */
20 int condexec_mask;
21 int condexec_cond;
22 int thumb;
23 int sctlr_b;
24 TCGMemOp be_data;
25 #if !defined(CONFIG_USER_ONLY)
26 int user;
27 #endif
28 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
29 uint8_t tbii; /* TBI1|TBI0 for insns */
30 uint8_t tbid; /* TBI1|TBI0 for data */
31 bool ns; /* Use non-secure CPREG bank on access */
32 int fp_excp_el; /* FP exception EL or 0 if enabled */
33 int sve_excp_el; /* SVE exception EL or 0 if enabled */
34 int sve_len; /* SVE vector length in bytes */
35 /* Flag indicating that exceptions from secure mode are routed to EL3. */
36 bool secure_routed_to_el3;
37 bool vfp_enabled; /* FP enabled via FPSCR.EN */
38 int vec_len;
39 int vec_stride;
40 bool v7m_handler_mode;
41 bool v8m_secure; /* true if v8M and we're in Secure mode */
42 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
43 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
44 * so that top level loop can generate correct syndrome information.
46 uint32_t svc_imm;
47 int aarch64;
48 int current_el;
49 GHashTable *cp_regs;
50 uint64_t features; /* CPU features bits */
51 /* Because unallocated encodings generate different exception syndrome
52 * information from traps due to FP being disabled, we can't do a single
53 * "is fp access disabled" check at a high level in the decode tree.
54 * To help in catching bugs where the access check was forgotten in some
55 * code path, we set this flag when the access check is done, and assert
56 * that it is set at the point where we actually touch the FP regs.
58 bool fp_access_checked;
59 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
60 * single-step support).
62 bool ss_active;
63 bool pstate_ss;
64 /* True if the insn just emitted was a load-exclusive instruction
65 * (necessary for syndrome information for single step exceptions),
66 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
68 bool is_ldex;
69 /* True if a single-step exception will be taken to the current EL */
70 bool ss_same_el;
71 /* True if v8.3-PAuth is active. */
72 bool pauth_active;
73 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
74 bool bt;
76 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
77 * < 0, set by the current instruction.
79 int8_t btype;
80 /* True if this page is guarded. */
81 bool guarded_page;
82 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
83 int c15_cpar;
84 /* TCG op of the current insn_start. */
85 TCGOp *insn_start;
86 #define TMP_A64_MAX 16
87 int tmp_a64_count;
88 TCGv_i64 tmp_a64[TMP_A64_MAX];
89 } DisasContext;
91 typedef struct DisasCompare {
92 TCGCond cond;
93 TCGv_i32 value;
94 bool value_global;
95 } DisasCompare;
97 /* Share the TCG temporaries common between 32 and 64 bit modes. */
98 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
99 extern TCGv_i64 cpu_exclusive_addr;
100 extern TCGv_i64 cpu_exclusive_val;
102 static inline int arm_dc_feature(DisasContext *dc, int feature)
104 return (dc->features & (1ULL << feature)) != 0;
107 static inline int get_mem_index(DisasContext *s)
109 return arm_to_core_mmu_idx(s->mmu_idx);
112 /* Function used to determine the target exception EL when otherwise not known
113 * or default.
115 static inline int default_exception_el(DisasContext *s)
117 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
118 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
119 * exceptions can only be routed to ELs above 1, so we target the higher of
120 * 1 or the current EL.
122 return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
123 ? 3 : MAX(1, s->current_el);
126 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
128 /* We don't need to save all of the syndrome so we mask and shift
129 * out unneeded bits to help the sleb128 encoder do a better job.
131 syn &= ARM_INSN_START_WORD2_MASK;
132 syn >>= ARM_INSN_START_WORD2_SHIFT;
134 /* We check and clear insn_start_idx to catch multiple updates. */
135 assert(s->insn_start != NULL);
136 tcg_set_insn_start_param(s->insn_start, 2, syn);
137 s->insn_start = NULL;
140 /* is_jmp field values */
141 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
142 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
143 /* These instructions trap after executing, so the A32/T32 decoder must
144 * defer them until after the conditional execution state has been updated.
145 * WFI also needs special handling when single-stepping.
147 #define DISAS_WFI DISAS_TARGET_2
148 #define DISAS_SWI DISAS_TARGET_3
149 /* WFE */
150 #define DISAS_WFE DISAS_TARGET_4
151 #define DISAS_HVC DISAS_TARGET_5
152 #define DISAS_SMC DISAS_TARGET_6
153 #define DISAS_YIELD DISAS_TARGET_7
154 /* M profile branch which might be an exception return (and so needs
155 * custom end-of-TB code)
157 #define DISAS_BX_EXCRET DISAS_TARGET_8
158 /* For instructions which want an immediate exit to the main loop,
159 * as opposed to attempting to use lookup_and_goto_ptr. Unlike
160 * DISAS_UPDATE this doesn't write the PC on exiting the translation
161 * loop so you need to ensure something (gen_a64_set_pc_im or runtime
162 * helper) has done so before we reach return from cpu_tb_exec.
164 #define DISAS_EXIT DISAS_TARGET_9
166 #ifdef TARGET_AARCH64
167 void a64_translate_init(void);
168 void gen_a64_set_pc_im(uint64_t val);
169 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
170 fprintf_function cpu_fprintf, int flags);
171 extern const TranslatorOps aarch64_translator_ops;
172 #else
173 static inline void a64_translate_init(void)
177 static inline void gen_a64_set_pc_im(uint64_t val)
181 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
182 fprintf_function cpu_fprintf,
183 int flags)
186 #endif
188 void arm_test_cc(DisasCompare *cmp, int cc);
189 void arm_free_cc(DisasCompare *cmp);
190 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
191 void arm_gen_test_cc(int cc, TCGLabel *label);
193 /* Return state of Alternate Half-precision flag, caller frees result */
194 static inline TCGv_i32 get_ahp_flag(void)
196 TCGv_i32 ret = tcg_temp_new_i32();
198 tcg_gen_ld_i32(ret, cpu_env,
199 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
200 tcg_gen_extract_i32(ret, ret, 26, 1);
202 return ret;
206 /* Vector operations shared between ARM and AArch64. */
207 extern const GVecGen3 bsl_op;
208 extern const GVecGen3 bit_op;
209 extern const GVecGen3 bif_op;
210 extern const GVecGen3 mla_op[4];
211 extern const GVecGen3 mls_op[4];
212 extern const GVecGen3 cmtst_op[4];
213 extern const GVecGen2i ssra_op[4];
214 extern const GVecGen2i usra_op[4];
215 extern const GVecGen2i sri_op[4];
216 extern const GVecGen2i sli_op[4];
217 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
220 * Forward to the isar_feature_* tests given a DisasContext pointer.
222 #define dc_isar_feature(name, ctx) \
223 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
225 #endif /* TARGET_ARM_TRANSLATE_H */