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sparc32_dma: split esp and le into separate DMA devices
[qemu/ar7.git] / hw / sparc / sun4m.c
blob8593a8747fb54c1278c4bd18d08170fc62ecc98e
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/i386/pc.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
47 #include "elf.h"
48 #include "sysemu/block-backend.h"
49 #include "trace.h"
50 #include "qemu/cutils.h"
51
52 /*
53 * Sun4m architecture was used in the following machines:
54 *
55 * SPARCserver 6xxMP/xx
56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57 * SPARCclassic X (4/10)
58 * SPARCstation LX/ZX (4/30)
59 * SPARCstation Voyager
60 * SPARCstation 10/xx, SPARCserver 10/xx
61 * SPARCstation 5, SPARCserver 5
62 * SPARCstation 20/xx, SPARCserver 20
63 * SPARCstation 4
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #define KERNEL_LOAD_ADDR 0x00004000
69 #define CMDLINE_ADDR 0x007ff000
70 #define INITRD_LOAD_ADDR 0x00800000
71 #define PROM_SIZE_MAX (1024 * 1024)
72 #define PROM_VADDR 0xffd00000
73 #define PROM_FILENAME "openbios-sparc32"
74 #define CFG_ADDR 0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81 #define MAX_VSIMMS 4
82
83 #define ESCC_CLOCK 4915200
84
85 struct sun4m_hwdef {
86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88 hwaddr serial_base, fd_base;
89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 hwaddr bpp_base, dbri_base, sx_base;
92 struct {
93 hwaddr reg_base, vram_base;
94 } vsimm[MAX_VSIMMS];
95 hwaddr ecc_base;
96 uint64_t max_mem;
97 uint32_t ecc_version;
98 uint32_t iommu_version;
99 uint16_t machine_id;
100 uint8_t nvram_machine_id;
101 };
102
103 void DMA_init(ISABus *bus, int high_page_enable)
104 {
105 }
106
107 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
108 Error **errp)
109 {
110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
111 }
112
113 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
114 const char *cmdline, const char *boot_devices,
115 ram_addr_t RAM_size, uint32_t kernel_size,
116 int width, int height, int depth,
117 int nvram_machine_id, const char *arch)
118 {
119 unsigned int i;
120 int sysp_end;
121 uint8_t image[0x1ff0];
122 NvramClass *k = NVRAM_GET_CLASS(nvram);
123
124 memset(image, '\0', sizeof(image));
125
126 /* OpenBIOS nvram variables partition */
127 sysp_end = chrp_nvram_create_system_partition(image, 0);
128
129 /* Free space partition */
130 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
131
132 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
133 nvram_machine_id);
134
135 for (i = 0; i < sizeof(image); i++) {
136 (k->write)(nvram, i, image[i]);
137 }
138 }
139
140 void cpu_check_irqs(CPUSPARCState *env)
141 {
142 CPUState *cs;
143
144 /* We should be holding the BQL before we mess with IRQs */
145 g_assert(qemu_mutex_iothread_locked());
146
147 if (env->pil_in && (env->interrupt_index == 0 ||
148 (env->interrupt_index & ~15) == TT_EXTINT)) {
149 unsigned int i;
150
151 for (i = 15; i > 0; i--) {
152 if (env->pil_in & (1 << i)) {
153 int old_interrupt = env->interrupt_index;
154
155 env->interrupt_index = TT_EXTINT | i;
156 if (old_interrupt != env->interrupt_index) {
157 cs = CPU(sparc_env_get_cpu(env));
158 trace_sun4m_cpu_interrupt(i);
159 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
160 }
161 break;
162 }
163 }
164 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
165 cs = CPU(sparc_env_get_cpu(env));
166 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
167 env->interrupt_index = 0;
168 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
169 }
170 }
171
172 static void cpu_kick_irq(SPARCCPU *cpu)
173 {
174 CPUSPARCState *env = &cpu->env;
175 CPUState *cs = CPU(cpu);
176
177 cs->halted = 0;
178 cpu_check_irqs(env);
179 qemu_cpu_kick(cs);
180 }
181
182 static void cpu_set_irq(void *opaque, int irq, int level)
183 {
184 SPARCCPU *cpu = opaque;
185 CPUSPARCState *env = &cpu->env;
186
187 if (level) {
188 trace_sun4m_cpu_set_irq_raise(irq);
189 env->pil_in |= 1 << irq;
190 cpu_kick_irq(cpu);
191 } else {
192 trace_sun4m_cpu_set_irq_lower(irq);
193 env->pil_in &= ~(1 << irq);
194 cpu_check_irqs(env);
195 }
196 }
197
198 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
199 {
200 }
201
202 static void main_cpu_reset(void *opaque)
203 {
204 SPARCCPU *cpu = opaque;
205 CPUState *cs = CPU(cpu);
206
207 cpu_reset(cs);
208 cs->halted = 0;
209 }
210
211 static void secondary_cpu_reset(void *opaque)
212 {
213 SPARCCPU *cpu = opaque;
214 CPUState *cs = CPU(cpu);
215
216 cpu_reset(cs);
217 cs->halted = 1;
218 }
219
220 static void cpu_halt_signal(void *opaque, int irq, int level)
221 {
222 if (level && current_cpu) {
223 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
224 }
225 }
226
227 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
228 {
229 return addr - 0xf0000000ULL;
230 }
231
232 static unsigned long sun4m_load_kernel(const char *kernel_filename,
233 const char *initrd_filename,
234 ram_addr_t RAM_size)
235 {
236 int linux_boot;
237 unsigned int i;
238 long initrd_size, kernel_size;
239 uint8_t *ptr;
240
241 linux_boot = (kernel_filename != NULL);
242
243 kernel_size = 0;
244 if (linux_boot) {
245 int bswap_needed;
246
247 #ifdef BSWAP_NEEDED
248 bswap_needed = 1;
249 #else
250 bswap_needed = 0;
251 #endif
252 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
253 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
254 if (kernel_size < 0)
255 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
256 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
257 TARGET_PAGE_SIZE);
258 if (kernel_size < 0)
259 kernel_size = load_image_targphys(kernel_filename,
260 KERNEL_LOAD_ADDR,
261 RAM_size - KERNEL_LOAD_ADDR);
262 if (kernel_size < 0) {
263 fprintf(stderr, "qemu: could not load kernel '%s'\n",
264 kernel_filename);
265 exit(1);
266 }
267
268 /* load initrd */
269 initrd_size = 0;
270 if (initrd_filename) {
271 initrd_size = load_image_targphys(initrd_filename,
272 INITRD_LOAD_ADDR,
273 RAM_size - INITRD_LOAD_ADDR);
274 if (initrd_size < 0) {
275 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
276 initrd_filename);
277 exit(1);
278 }
279 }
280 if (initrd_size > 0) {
281 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
282 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
283 if (ldl_p(ptr) == 0x48647253) { // HdrS
284 stl_p(ptr + 16, INITRD_LOAD_ADDR);
285 stl_p(ptr + 20, initrd_size);
286 break;
287 }
288 }
289 }
290 }
291 return kernel_size;
292 }
293
294 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
295 {
296 DeviceState *dev;
297 SysBusDevice *s;
298
299 dev = qdev_create(NULL, "iommu");
300 qdev_prop_set_uint32(dev, "version", version);
301 qdev_init_nofail(dev);
302 s = SYS_BUS_DEVICE(dev);
303 sysbus_connect_irq(s, 0, irq);
304 sysbus_mmio_map(s, 0, addr);
305
306 return s;
307 }
308
309 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
310 void *iommu, qemu_irq *dev_irq, int is_ledma)
311 {
312 DeviceState *dev;
313 SysBusDevice *s;
314
315 dev = qdev_create(NULL, is_ledma ? "sparc32-ledma" : "sparc32-espdma");
316 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
317 qdev_init_nofail(dev);
318 s = SYS_BUS_DEVICE(dev);
319 sysbus_connect_irq(s, 0, parent_irq);
320 *dev_irq = qdev_get_gpio_in(dev, 0);
321 sysbus_mmio_map(s, 0, daddr);
322
323 return s;
324 }
325
326 static void lance_init(NICInfo *nd, hwaddr leaddr,
327 void *dma_opaque, qemu_irq irq)
328 {
329 DeviceState *dev;
330 SysBusDevice *s;
331 qemu_irq reset;
332
333 qemu_check_nic_model(&nd_table[0], "lance");
334
335 dev = qdev_create(NULL, "lance");
336 qdev_set_nic_properties(dev, nd);
337 qdev_prop_set_ptr(dev, "dma", dma_opaque);
338 qdev_init_nofail(dev);
339 s = SYS_BUS_DEVICE(dev);
340 sysbus_mmio_map(s, 0, leaddr);
341 sysbus_connect_irq(s, 0, irq);
342 reset = qdev_get_gpio_in(dev, 0);
343 qdev_connect_gpio_out(dma_opaque, 0, reset);
344 }
345
346 static DeviceState *slavio_intctl_init(hwaddr addr,
347 hwaddr addrg,
348 qemu_irq **parent_irq)
349 {
350 DeviceState *dev;
351 SysBusDevice *s;
352 unsigned int i, j;
353
354 dev = qdev_create(NULL, "slavio_intctl");
355 qdev_init_nofail(dev);
356
357 s = SYS_BUS_DEVICE(dev);
358
359 for (i = 0; i < MAX_CPUS; i++) {
360 for (j = 0; j < MAX_PILS; j++) {
361 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
362 }
363 }
364 sysbus_mmio_map(s, 0, addrg);
365 for (i = 0; i < MAX_CPUS; i++) {
366 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
367 }
368
369 return dev;
370 }
371
372 #define SYS_TIMER_OFFSET 0x10000ULL
373 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
374
375 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
376 qemu_irq *cpu_irqs, unsigned int num_cpus)
377 {
378 DeviceState *dev;
379 SysBusDevice *s;
380 unsigned int i;
381
382 dev = qdev_create(NULL, "slavio_timer");
383 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
384 qdev_init_nofail(dev);
385 s = SYS_BUS_DEVICE(dev);
386 sysbus_connect_irq(s, 0, master_irq);
387 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
388
389 for (i = 0; i < MAX_CPUS; i++) {
390 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
391 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
392 }
393 }
394
395 static qemu_irq slavio_system_powerdown;
396
397 static void slavio_powerdown_req(Notifier *n, void *opaque)
398 {
399 qemu_irq_raise(slavio_system_powerdown);
400 }
401
402 static Notifier slavio_system_powerdown_notifier = {
403 .notify = slavio_powerdown_req
404 };
405
406 #define MISC_LEDS 0x01600000
407 #define MISC_CFG 0x01800000
408 #define MISC_DIAG 0x01a00000
409 #define MISC_MDM 0x01b00000
410 #define MISC_SYS 0x01f00000
411
412 static void slavio_misc_init(hwaddr base,
413 hwaddr aux1_base,
414 hwaddr aux2_base, qemu_irq irq,
415 qemu_irq fdc_tc)
416 {
417 DeviceState *dev;
418 SysBusDevice *s;
419
420 dev = qdev_create(NULL, "slavio_misc");
421 qdev_init_nofail(dev);
422 s = SYS_BUS_DEVICE(dev);
423 if (base) {
424 /* 8 bit registers */
425 /* Slavio control */
426 sysbus_mmio_map(s, 0, base + MISC_CFG);
427 /* Diagnostics */
428 sysbus_mmio_map(s, 1, base + MISC_DIAG);
429 /* Modem control */
430 sysbus_mmio_map(s, 2, base + MISC_MDM);
431 /* 16 bit registers */
432 /* ss600mp diag LEDs */
433 sysbus_mmio_map(s, 3, base + MISC_LEDS);
434 /* 32 bit registers */
435 /* System control */
436 sysbus_mmio_map(s, 4, base + MISC_SYS);
437 }
438 if (aux1_base) {
439 /* AUX 1 (Misc System Functions) */
440 sysbus_mmio_map(s, 5, aux1_base);
441 }
442 if (aux2_base) {
443 /* AUX 2 (Software Powerdown Control) */
444 sysbus_mmio_map(s, 6, aux2_base);
445 }
446 sysbus_connect_irq(s, 0, irq);
447 sysbus_connect_irq(s, 1, fdc_tc);
448 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
449 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
450 }
451
452 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
453 {
454 DeviceState *dev;
455 SysBusDevice *s;
456
457 dev = qdev_create(NULL, "eccmemctl");
458 qdev_prop_set_uint32(dev, "version", version);
459 qdev_init_nofail(dev);
460 s = SYS_BUS_DEVICE(dev);
461 sysbus_connect_irq(s, 0, irq);
462 sysbus_mmio_map(s, 0, base);
463 if (version == 0) { // SS-600MP only
464 sysbus_mmio_map(s, 1, base + 0x1000);
465 }
466 }
467
468 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
469 {
470 DeviceState *dev;
471 SysBusDevice *s;
472
473 dev = qdev_create(NULL, "apc");
474 qdev_init_nofail(dev);
475 s = SYS_BUS_DEVICE(dev);
476 /* Power management (APC) XXX: not a Slavio device */
477 sysbus_mmio_map(s, 0, power_base);
478 sysbus_connect_irq(s, 0, cpu_halt);
479 }
480
481 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
482 int height, int depth)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "SUNW,tcx");
488 qdev_prop_set_uint32(dev, "vram_size", vram_size);
489 qdev_prop_set_uint16(dev, "width", width);
490 qdev_prop_set_uint16(dev, "height", height);
491 qdev_prop_set_uint16(dev, "depth", depth);
492 qdev_init_nofail(dev);
493 s = SYS_BUS_DEVICE(dev);
494
495 /* 10/ROM : FCode ROM */
496 sysbus_mmio_map(s, 0, addr);
497 /* 2/STIP : Stipple */
498 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
499 /* 3/BLIT : Blitter */
500 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
501 /* 5/RSTIP : Raw Stipple */
502 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
503 /* 6/RBLIT : Raw Blitter */
504 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
505 /* 7/TEC : Transform Engine */
506 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
507 /* 8/CMAP : DAC */
508 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
509 /* 9/THC : */
510 if (depth == 8) {
511 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
512 } else {
513 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
514 }
515 /* 11/DHC : */
516 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
517 /* 12/ALT : */
518 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
519 /* 0/DFB8 : 8-bit plane */
520 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
521 /* 1/DFB24 : 24bit plane */
522 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
523 /* 4/RDFB32: Raw framebuffer. Control plane */
524 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
525 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
526 if (depth == 8) {
527 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
528 }
529
530 sysbus_connect_irq(s, 0, irq);
531 }
532
533 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
534 int height, int depth)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "cgthree");
540 qdev_prop_set_uint32(dev, "vram-size", vram_size);
541 qdev_prop_set_uint16(dev, "width", width);
542 qdev_prop_set_uint16(dev, "height", height);
543 qdev_prop_set_uint16(dev, "depth", depth);
544 qdev_init_nofail(dev);
545 s = SYS_BUS_DEVICE(dev);
546
547 /* FCode ROM */
548 sysbus_mmio_map(s, 0, addr);
549 /* DAC */
550 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
551 /* 8-bit plane */
552 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
553
554 sysbus_connect_irq(s, 0, irq);
555 }
556
557 /* NCR89C100/MACIO Internal ID register */
558
559 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
560
561 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
562
563 static void idreg_init(hwaddr addr)
564 {
565 DeviceState *dev;
566 SysBusDevice *s;
567
568 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
569 qdev_init_nofail(dev);
570 s = SYS_BUS_DEVICE(dev);
571
572 sysbus_mmio_map(s, 0, addr);
573 cpu_physical_memory_write_rom(&address_space_memory,
574 addr, idreg_data, sizeof(idreg_data));
575 }
576
577 #define MACIO_ID_REGISTER(obj) \
578 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
579
580 typedef struct IDRegState {
581 SysBusDevice parent_obj;
582
583 MemoryRegion mem;
584 } IDRegState;
585
586 static void idreg_init1(Object *obj)
587 {
588 IDRegState *s = MACIO_ID_REGISTER(obj);
589 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
590
591 memory_region_init_ram_nomigrate(&s->mem, obj,
592 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
593 vmstate_register_ram_global(&s->mem);
594 memory_region_set_readonly(&s->mem, true);
595 sysbus_init_mmio(dev, &s->mem);
596 }
597
598 static const TypeInfo idreg_info = {
599 .name = TYPE_MACIO_ID_REGISTER,
600 .parent = TYPE_SYS_BUS_DEVICE,
601 .instance_size = sizeof(IDRegState),
602 .instance_init = idreg_init1,
603 };
604
605 #define TYPE_TCX_AFX "tcx_afx"
606 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
607
608 typedef struct AFXState {
609 SysBusDevice parent_obj;
610
611 MemoryRegion mem;
612 } AFXState;
613
614 /* SS-5 TCX AFX register */
615 static void afx_init(hwaddr addr)
616 {
617 DeviceState *dev;
618 SysBusDevice *s;
619
620 dev = qdev_create(NULL, TYPE_TCX_AFX);
621 qdev_init_nofail(dev);
622 s = SYS_BUS_DEVICE(dev);
623
624 sysbus_mmio_map(s, 0, addr);
625 }
626
627 static void afx_init1(Object *obj)
628 {
629 AFXState *s = TCX_AFX(obj);
630 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
631
632 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
633 vmstate_register_ram_global(&s->mem);
634 sysbus_init_mmio(dev, &s->mem);
635 }
636
637 static const TypeInfo afx_info = {
638 .name = TYPE_TCX_AFX,
639 .parent = TYPE_SYS_BUS_DEVICE,
640 .instance_size = sizeof(AFXState),
641 .instance_init = afx_init1,
642 };
643
644 #define TYPE_OPENPROM "openprom"
645 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
646
647 typedef struct PROMState {
648 SysBusDevice parent_obj;
649
650 MemoryRegion prom;
651 } PROMState;
652
653 /* Boot PROM (OpenBIOS) */
654 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
655 {
656 hwaddr *base_addr = (hwaddr *)opaque;
657 return addr + *base_addr - PROM_VADDR;
658 }
659
660 static void prom_init(hwaddr addr, const char *bios_name)
661 {
662 DeviceState *dev;
663 SysBusDevice *s;
664 char *filename;
665 int ret;
666
667 dev = qdev_create(NULL, TYPE_OPENPROM);
668 qdev_init_nofail(dev);
669 s = SYS_BUS_DEVICE(dev);
670
671 sysbus_mmio_map(s, 0, addr);
672
673 /* load boot prom */
674 if (bios_name == NULL) {
675 bios_name = PROM_FILENAME;
676 }
677 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
678 if (filename) {
679 ret = load_elf(filename, translate_prom_address, &addr, NULL,
680 NULL, NULL, 1, EM_SPARC, 0, 0);
681 if (ret < 0 || ret > PROM_SIZE_MAX) {
682 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
683 }
684 g_free(filename);
685 } else {
686 ret = -1;
687 }
688 if (ret < 0 || ret > PROM_SIZE_MAX) {
689 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
690 exit(1);
691 }
692 }
693
694 static void prom_init1(Object *obj)
695 {
696 PROMState *s = OPENPROM(obj);
697 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
698
699 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
700 &error_fatal);
701 vmstate_register_ram_global(&s->prom);
702 memory_region_set_readonly(&s->prom, true);
703 sysbus_init_mmio(dev, &s->prom);
704 }
705
706 static Property prom_properties[] = {
707 {/* end of property list */},
708 };
709
710 static void prom_class_init(ObjectClass *klass, void *data)
711 {
712 DeviceClass *dc = DEVICE_CLASS(klass);
713
714 dc->props = prom_properties;
715 }
716
717 static const TypeInfo prom_info = {
718 .name = TYPE_OPENPROM,
719 .parent = TYPE_SYS_BUS_DEVICE,
720 .instance_size = sizeof(PROMState),
721 .class_init = prom_class_init,
722 .instance_init = prom_init1,
723 };
724
725 #define TYPE_SUN4M_MEMORY "memory"
726 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
727
728 typedef struct RamDevice {
729 SysBusDevice parent_obj;
730
731 MemoryRegion ram;
732 uint64_t size;
733 } RamDevice;
734
735 /* System RAM */
736 static void ram_realize(DeviceState *dev, Error **errp)
737 {
738 RamDevice *d = SUN4M_RAM(dev);
739 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
740
741 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
742 d->size);
743 sysbus_init_mmio(sbd, &d->ram);
744 }
745
746 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
747 uint64_t max_mem)
748 {
749 DeviceState *dev;
750 SysBusDevice *s;
751 RamDevice *d;
752
753 /* allocate RAM */
754 if ((uint64_t)RAM_size > max_mem) {
755 fprintf(stderr,
756 "qemu: Too much memory for this machine: %d, maximum %d\n",
757 (unsigned int)(RAM_size / (1024 * 1024)),
758 (unsigned int)(max_mem / (1024 * 1024)));
759 exit(1);
760 }
761 dev = qdev_create(NULL, "memory");
762 s = SYS_BUS_DEVICE(dev);
763
764 d = SUN4M_RAM(dev);
765 d->size = RAM_size;
766 qdev_init_nofail(dev);
767
768 sysbus_mmio_map(s, 0, addr);
769 }
770
771 static Property ram_properties[] = {
772 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
773 DEFINE_PROP_END_OF_LIST(),
774 };
775
776 static void ram_class_init(ObjectClass *klass, void *data)
777 {
778 DeviceClass *dc = DEVICE_CLASS(klass);
779
780 dc->realize = ram_realize;
781 dc->props = ram_properties;
782 }
783
784 static const TypeInfo ram_info = {
785 .name = TYPE_SUN4M_MEMORY,
786 .parent = TYPE_SYS_BUS_DEVICE,
787 .instance_size = sizeof(RamDevice),
788 .class_init = ram_class_init,
789 };
790
791 static void cpu_devinit(const char *cpu_type, unsigned int id,
792 uint64_t prom_addr, qemu_irq **cpu_irqs)
793 {
794 CPUState *cs;
795 SPARCCPU *cpu;
796 CPUSPARCState *env;
797
798 cpu = SPARC_CPU(cpu_create(cpu_type));
799 env = &cpu->env;
800
801 cpu_sparc_set_id(env, id);
802 if (id == 0) {
803 qemu_register_reset(main_cpu_reset, cpu);
804 } else {
805 qemu_register_reset(secondary_cpu_reset, cpu);
806 cs = CPU(cpu);
807 cs->halted = 1;
808 }
809 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
810 env->prom_addr = prom_addr;
811 }
812
813 static void dummy_fdc_tc(void *opaque, int irq, int level)
814 {
815 }
816
817 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
818 MachineState *machine)
819 {
820 DeviceState *slavio_intctl;
821 unsigned int i;
822 void *iommu, *espdma, *ledma, *nvram;
823 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
824 espdma_irq, ledma_irq;
825 qemu_irq esp_reset, dma_enable;
826 qemu_irq fdc_tc;
827 unsigned long kernel_size;
828 DriveInfo *fd[MAX_FD];
829 FWCfgState *fw_cfg;
830 unsigned int num_vsimms;
831
832 /* init CPUs */
833 for(i = 0; i < smp_cpus; i++) {
834 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
835 }
836
837 for (i = smp_cpus; i < MAX_CPUS; i++)
838 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
839
840
841 /* set up devices */
842 ram_init(0, machine->ram_size, hwdef->max_mem);
843 /* models without ECC don't trap when missing ram is accessed */
844 if (!hwdef->ecc_base) {
845 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
846 }
847
848 prom_init(hwdef->slavio_base, bios_name);
849
850 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
851 hwdef->intctl_base + 0x10000ULL,
852 cpu_irqs);
853
854 for (i = 0; i < 32; i++) {
855 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
856 }
857 for (i = 0; i < MAX_CPUS; i++) {
858 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
859 }
860
861 if (hwdef->idreg_base) {
862 idreg_init(hwdef->idreg_base);
863 }
864
865 if (hwdef->afx_base) {
866 afx_init(hwdef->afx_base);
867 }
868
869 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
870 slavio_irq[30]);
871
872 if (hwdef->iommu_pad_base) {
873 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
874 Software shouldn't use aliased addresses, neither should it crash
875 when does. Using empty_slot instead of aliasing can help with
876 debugging such accesses */
877 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
878 }
879
880 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
881 iommu, &espdma_irq, 0);
882
883 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
884 slavio_irq[16], iommu, &ledma_irq, 1);
885
886 if (graphic_depth != 8 && graphic_depth != 24) {
887 error_report("Unsupported depth: %d", graphic_depth);
888 exit (1);
889 }
890 num_vsimms = 0;
891 if (num_vsimms == 0) {
892 if (vga_interface_type == VGA_CG3) {
893 if (graphic_depth != 8) {
894 error_report("Unsupported depth: %d", graphic_depth);
895 exit(1);
896 }
897
898 if (!(graphic_width == 1024 && graphic_height == 768) &&
899 !(graphic_width == 1152 && graphic_height == 900)) {
900 error_report("Unsupported resolution: %d x %d", graphic_width,
901 graphic_height);
902 exit(1);
903 }
904
905 /* sbus irq 5 */
906 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
907 graphic_width, graphic_height, graphic_depth);
908 } else {
909 /* If no display specified, default to TCX */
910 if (graphic_depth != 8 && graphic_depth != 24) {
911 error_report("Unsupported depth: %d", graphic_depth);
912 exit(1);
913 }
914
915 if (!(graphic_width == 1024 && graphic_height == 768)) {
916 error_report("Unsupported resolution: %d x %d",
917 graphic_width, graphic_height);
918 exit(1);
919 }
920
921 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
922 graphic_width, graphic_height, graphic_depth);
923 }
924 }
925
926 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
927 /* vsimm registers probed by OBP */
928 if (hwdef->vsimm[i].reg_base) {
929 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
930 }
931 }
932
933 if (hwdef->sx_base) {
934 empty_slot_init(hwdef->sx_base, 0x2000);
935 }
936
937 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
938
939 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
940
941 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
942
943 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
944 !machine->enable_graphics, ESCC_CLOCK, 1);
945 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
946 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
947 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
948 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
949
950 if (hwdef->apc_base) {
951 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
952 }
953
954 if (hwdef->fd_base) {
955 /* there is zero or one floppy drive */
956 memset(fd, 0, sizeof(fd));
957 fd[0] = drive_get(IF_FLOPPY, 0, 0);
958 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
959 &fdc_tc);
960 } else {
961 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
962 }
963
964 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
965 slavio_irq[30], fdc_tc);
966
967 esp_init(hwdef->esp_base, 2,
968 espdma_memory_read, espdma_memory_write,
969 espdma, espdma_irq, &esp_reset, &dma_enable);
970
971 qdev_connect_gpio_out(espdma, 0, esp_reset);
972 qdev_connect_gpio_out(espdma, 1, dma_enable);
973
974 if (hwdef->cs_base) {
975 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
976 slavio_irq[5]);
977 }
978
979 if (hwdef->dbri_base) {
980 /* ISDN chip with attached CS4215 audio codec */
981 /* prom space */
982 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
983 /* reg space */
984 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
985 }
986
987 if (hwdef->bpp_base) {
988 /* parallel port */
989 empty_slot_init(hwdef->bpp_base, 0x20);
990 }
991
992 kernel_size = sun4m_load_kernel(machine->kernel_filename,
993 machine->initrd_filename,
994 machine->ram_size);
995
996 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
997 machine->boot_order, machine->ram_size, kernel_size,
998 graphic_width, graphic_height, graphic_depth,
999 hwdef->nvram_machine_id, "Sun4m");
1000
1001 if (hwdef->ecc_base)
1002 ecc_init(hwdef->ecc_base, slavio_irq[28],
1003 hwdef->ecc_version);
1004
1005 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1006 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1007 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1008 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1009 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1010 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1011 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1013 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1015 if (machine->kernel_cmdline) {
1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1017 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1018 machine->kernel_cmdline);
1019 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1020 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1021 strlen(machine->kernel_cmdline) + 1);
1022 } else {
1023 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1024 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1025 }
1026 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1027 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1028 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1029 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1030 }
1031
1032 enum {
1033 ss5_id = 32,
1034 vger_id,
1035 lx_id,
1036 ss4_id,
1037 scls_id,
1038 sbook_id,
1039 ss10_id = 64,
1040 ss20_id,
1041 ss600mp_id,
1042 };
1043
1044 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1045 /* SS-5 */
1046 {
1047 .iommu_base = 0x10000000,
1048 .iommu_pad_base = 0x10004000,
1049 .iommu_pad_len = 0x0fffb000,
1050 .tcx_base = 0x50000000,
1051 .cs_base = 0x6c000000,
1052 .slavio_base = 0x70000000,
1053 .ms_kb_base = 0x71000000,
1054 .serial_base = 0x71100000,
1055 .nvram_base = 0x71200000,
1056 .fd_base = 0x71400000,
1057 .counter_base = 0x71d00000,
1058 .intctl_base = 0x71e00000,
1059 .idreg_base = 0x78000000,
1060 .dma_base = 0x78400000,
1061 .esp_base = 0x78800000,
1062 .le_base = 0x78c00000,
1063 .apc_base = 0x6a000000,
1064 .afx_base = 0x6e000000,
1065 .aux1_base = 0x71900000,
1066 .aux2_base = 0x71910000,
1067 .nvram_machine_id = 0x80,
1068 .machine_id = ss5_id,
1069 .iommu_version = 0x05000000,
1070 .max_mem = 0x10000000,
1071 },
1072 /* SS-10 */
1073 {
1074 .iommu_base = 0xfe0000000ULL,
1075 .tcx_base = 0xe20000000ULL,
1076 .slavio_base = 0xff0000000ULL,
1077 .ms_kb_base = 0xff1000000ULL,
1078 .serial_base = 0xff1100000ULL,
1079 .nvram_base = 0xff1200000ULL,
1080 .fd_base = 0xff1700000ULL,
1081 .counter_base = 0xff1300000ULL,
1082 .intctl_base = 0xff1400000ULL,
1083 .idreg_base = 0xef0000000ULL,
1084 .dma_base = 0xef0400000ULL,
1085 .esp_base = 0xef0800000ULL,
1086 .le_base = 0xef0c00000ULL,
1087 .apc_base = 0xefa000000ULL, // XXX should not exist
1088 .aux1_base = 0xff1800000ULL,
1089 .aux2_base = 0xff1a01000ULL,
1090 .ecc_base = 0xf00000000ULL,
1091 .ecc_version = 0x10000000, // version 0, implementation 1
1092 .nvram_machine_id = 0x72,
1093 .machine_id = ss10_id,
1094 .iommu_version = 0x03000000,
1095 .max_mem = 0xf00000000ULL,
1096 },
1097 /* SS-600MP */
1098 {
1099 .iommu_base = 0xfe0000000ULL,
1100 .tcx_base = 0xe20000000ULL,
1101 .slavio_base = 0xff0000000ULL,
1102 .ms_kb_base = 0xff1000000ULL,
1103 .serial_base = 0xff1100000ULL,
1104 .nvram_base = 0xff1200000ULL,
1105 .counter_base = 0xff1300000ULL,
1106 .intctl_base = 0xff1400000ULL,
1107 .dma_base = 0xef0081000ULL,
1108 .esp_base = 0xef0080000ULL,
1109 .le_base = 0xef0060000ULL,
1110 .apc_base = 0xefa000000ULL, // XXX should not exist
1111 .aux1_base = 0xff1800000ULL,
1112 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1113 .ecc_base = 0xf00000000ULL,
1114 .ecc_version = 0x00000000, // version 0, implementation 0
1115 .nvram_machine_id = 0x71,
1116 .machine_id = ss600mp_id,
1117 .iommu_version = 0x01000000,
1118 .max_mem = 0xf00000000ULL,
1119 },
1120 /* SS-20 */
1121 {
1122 .iommu_base = 0xfe0000000ULL,
1123 .tcx_base = 0xe20000000ULL,
1124 .slavio_base = 0xff0000000ULL,
1125 .ms_kb_base = 0xff1000000ULL,
1126 .serial_base = 0xff1100000ULL,
1127 .nvram_base = 0xff1200000ULL,
1128 .fd_base = 0xff1700000ULL,
1129 .counter_base = 0xff1300000ULL,
1130 .intctl_base = 0xff1400000ULL,
1131 .idreg_base = 0xef0000000ULL,
1132 .dma_base = 0xef0400000ULL,
1133 .esp_base = 0xef0800000ULL,
1134 .le_base = 0xef0c00000ULL,
1135 .bpp_base = 0xef4800000ULL,
1136 .apc_base = 0xefa000000ULL, // XXX should not exist
1137 .aux1_base = 0xff1800000ULL,
1138 .aux2_base = 0xff1a01000ULL,
1139 .dbri_base = 0xee0000000ULL,
1140 .sx_base = 0xf80000000ULL,
1141 .vsimm = {
1142 {
1143 .reg_base = 0x9c000000ULL,
1144 .vram_base = 0xfc000000ULL
1145 }, {
1146 .reg_base = 0x90000000ULL,
1147 .vram_base = 0xf0000000ULL
1148 }, {
1149 .reg_base = 0x94000000ULL
1150 }, {
1151 .reg_base = 0x98000000ULL
1152 }
1153 },
1154 .ecc_base = 0xf00000000ULL,
1155 .ecc_version = 0x20000000, // version 0, implementation 2
1156 .nvram_machine_id = 0x72,
1157 .machine_id = ss20_id,
1158 .iommu_version = 0x13000000,
1159 .max_mem = 0xf00000000ULL,
1160 },
1161 /* Voyager */
1162 {
1163 .iommu_base = 0x10000000,
1164 .tcx_base = 0x50000000,
1165 .slavio_base = 0x70000000,
1166 .ms_kb_base = 0x71000000,
1167 .serial_base = 0x71100000,
1168 .nvram_base = 0x71200000,
1169 .fd_base = 0x71400000,
1170 .counter_base = 0x71d00000,
1171 .intctl_base = 0x71e00000,
1172 .idreg_base = 0x78000000,
1173 .dma_base = 0x78400000,
1174 .esp_base = 0x78800000,
1175 .le_base = 0x78c00000,
1176 .apc_base = 0x71300000, // pmc
1177 .aux1_base = 0x71900000,
1178 .aux2_base = 0x71910000,
1179 .nvram_machine_id = 0x80,
1180 .machine_id = vger_id,
1181 .iommu_version = 0x05000000,
1182 .max_mem = 0x10000000,
1183 },
1184 /* LX */
1185 {
1186 .iommu_base = 0x10000000,
1187 .iommu_pad_base = 0x10004000,
1188 .iommu_pad_len = 0x0fffb000,
1189 .tcx_base = 0x50000000,
1190 .slavio_base = 0x70000000,
1191 .ms_kb_base = 0x71000000,
1192 .serial_base = 0x71100000,
1193 .nvram_base = 0x71200000,
1194 .fd_base = 0x71400000,
1195 .counter_base = 0x71d00000,
1196 .intctl_base = 0x71e00000,
1197 .idreg_base = 0x78000000,
1198 .dma_base = 0x78400000,
1199 .esp_base = 0x78800000,
1200 .le_base = 0x78c00000,
1201 .aux1_base = 0x71900000,
1202 .aux2_base = 0x71910000,
1203 .nvram_machine_id = 0x80,
1204 .machine_id = lx_id,
1205 .iommu_version = 0x04000000,
1206 .max_mem = 0x10000000,
1207 },
1208 /* SS-4 */
1209 {
1210 .iommu_base = 0x10000000,
1211 .tcx_base = 0x50000000,
1212 .cs_base = 0x6c000000,
1213 .slavio_base = 0x70000000,
1214 .ms_kb_base = 0x71000000,
1215 .serial_base = 0x71100000,
1216 .nvram_base = 0x71200000,
1217 .fd_base = 0x71400000,
1218 .counter_base = 0x71d00000,
1219 .intctl_base = 0x71e00000,
1220 .idreg_base = 0x78000000,
1221 .dma_base = 0x78400000,
1222 .esp_base = 0x78800000,
1223 .le_base = 0x78c00000,
1224 .apc_base = 0x6a000000,
1225 .aux1_base = 0x71900000,
1226 .aux2_base = 0x71910000,
1227 .nvram_machine_id = 0x80,
1228 .machine_id = ss4_id,
1229 .iommu_version = 0x05000000,
1230 .max_mem = 0x10000000,
1231 },
1232 /* SPARCClassic */
1233 {
1234 .iommu_base = 0x10000000,
1235 .tcx_base = 0x50000000,
1236 .slavio_base = 0x70000000,
1237 .ms_kb_base = 0x71000000,
1238 .serial_base = 0x71100000,
1239 .nvram_base = 0x71200000,
1240 .fd_base = 0x71400000,
1241 .counter_base = 0x71d00000,
1242 .intctl_base = 0x71e00000,
1243 .idreg_base = 0x78000000,
1244 .dma_base = 0x78400000,
1245 .esp_base = 0x78800000,
1246 .le_base = 0x78c00000,
1247 .apc_base = 0x6a000000,
1248 .aux1_base = 0x71900000,
1249 .aux2_base = 0x71910000,
1250 .nvram_machine_id = 0x80,
1251 .machine_id = scls_id,
1252 .iommu_version = 0x05000000,
1253 .max_mem = 0x10000000,
1254 },
1255 /* SPARCbook */
1256 {
1257 .iommu_base = 0x10000000,
1258 .tcx_base = 0x50000000, // XXX
1259 .slavio_base = 0x70000000,
1260 .ms_kb_base = 0x71000000,
1261 .serial_base = 0x71100000,
1262 .nvram_base = 0x71200000,
1263 .fd_base = 0x71400000,
1264 .counter_base = 0x71d00000,
1265 .intctl_base = 0x71e00000,
1266 .idreg_base = 0x78000000,
1267 .dma_base = 0x78400000,
1268 .esp_base = 0x78800000,
1269 .le_base = 0x78c00000,
1270 .apc_base = 0x6a000000,
1271 .aux1_base = 0x71900000,
1272 .aux2_base = 0x71910000,
1273 .nvram_machine_id = 0x80,
1274 .machine_id = sbook_id,
1275 .iommu_version = 0x05000000,
1276 .max_mem = 0x10000000,
1277 },
1278 };
1279
1280 /* SPARCstation 5 hardware initialisation */
1281 static void ss5_init(MachineState *machine)
1282 {
1283 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1284 }
1285
1286 /* SPARCstation 10 hardware initialisation */
1287 static void ss10_init(MachineState *machine)
1288 {
1289 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1290 }
1291
1292 /* SPARCserver 600MP hardware initialisation */
1293 static void ss600mp_init(MachineState *machine)
1294 {
1295 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1296 }
1297
1298 /* SPARCstation 20 hardware initialisation */
1299 static void ss20_init(MachineState *machine)
1300 {
1301 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1302 }
1303
1304 /* SPARCstation Voyager hardware initialisation */
1305 static void vger_init(MachineState *machine)
1306 {
1307 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1308 }
1309
1310 /* SPARCstation LX hardware initialisation */
1311 static void ss_lx_init(MachineState *machine)
1312 {
1313 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1314 }
1315
1316 /* SPARCstation 4 hardware initialisation */
1317 static void ss4_init(MachineState *machine)
1318 {
1319 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1320 }
1321
1322 /* SPARCClassic hardware initialisation */
1323 static void scls_init(MachineState *machine)
1324 {
1325 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1326 }
1327
1328 /* SPARCbook hardware initialisation */
1329 static void sbook_init(MachineState *machine)
1330 {
1331 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1332 }
1333
1334 static void ss5_class_init(ObjectClass *oc, void *data)
1335 {
1336 MachineClass *mc = MACHINE_CLASS(oc);
1337
1338 mc->desc = "Sun4m platform, SPARCstation 5";
1339 mc->init = ss5_init;
1340 mc->block_default_type = IF_SCSI;
1341 mc->is_default = 1;
1342 mc->default_boot_order = "c";
1343 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1344 }
1345
1346 static const TypeInfo ss5_type = {
1347 .name = MACHINE_TYPE_NAME("SS-5"),
1348 .parent = TYPE_MACHINE,
1349 .class_init = ss5_class_init,
1350 };
1351
1352 static void ss10_class_init(ObjectClass *oc, void *data)
1353 {
1354 MachineClass *mc = MACHINE_CLASS(oc);
1355
1356 mc->desc = "Sun4m platform, SPARCstation 10";
1357 mc->init = ss10_init;
1358 mc->block_default_type = IF_SCSI;
1359 mc->max_cpus = 4;
1360 mc->default_boot_order = "c";
1361 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1362 }
1363
1364 static const TypeInfo ss10_type = {
1365 .name = MACHINE_TYPE_NAME("SS-10"),
1366 .parent = TYPE_MACHINE,
1367 .class_init = ss10_class_init,
1368 };
1369
1370 static void ss600mp_class_init(ObjectClass *oc, void *data)
1371 {
1372 MachineClass *mc = MACHINE_CLASS(oc);
1373
1374 mc->desc = "Sun4m platform, SPARCserver 600MP";
1375 mc->init = ss600mp_init;
1376 mc->block_default_type = IF_SCSI;
1377 mc->max_cpus = 4;
1378 mc->default_boot_order = "c";
1379 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1380 }
1381
1382 static const TypeInfo ss600mp_type = {
1383 .name = MACHINE_TYPE_NAME("SS-600MP"),
1384 .parent = TYPE_MACHINE,
1385 .class_init = ss600mp_class_init,
1386 };
1387
1388 static void ss20_class_init(ObjectClass *oc, void *data)
1389 {
1390 MachineClass *mc = MACHINE_CLASS(oc);
1391
1392 mc->desc = "Sun4m platform, SPARCstation 20";
1393 mc->init = ss20_init;
1394 mc->block_default_type = IF_SCSI;
1395 mc->max_cpus = 4;
1396 mc->default_boot_order = "c";
1397 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1398 }
1399
1400 static const TypeInfo ss20_type = {
1401 .name = MACHINE_TYPE_NAME("SS-20"),
1402 .parent = TYPE_MACHINE,
1403 .class_init = ss20_class_init,
1404 };
1405
1406 static void voyager_class_init(ObjectClass *oc, void *data)
1407 {
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409
1410 mc->desc = "Sun4m platform, SPARCstation Voyager";
1411 mc->init = vger_init;
1412 mc->block_default_type = IF_SCSI;
1413 mc->default_boot_order = "c";
1414 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1415 }
1416
1417 static const TypeInfo voyager_type = {
1418 .name = MACHINE_TYPE_NAME("Voyager"),
1419 .parent = TYPE_MACHINE,
1420 .class_init = voyager_class_init,
1421 };
1422
1423 static void ss_lx_class_init(ObjectClass *oc, void *data)
1424 {
1425 MachineClass *mc = MACHINE_CLASS(oc);
1426
1427 mc->desc = "Sun4m platform, SPARCstation LX";
1428 mc->init = ss_lx_init;
1429 mc->block_default_type = IF_SCSI;
1430 mc->default_boot_order = "c";
1431 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1432 }
1433
1434 static const TypeInfo ss_lx_type = {
1435 .name = MACHINE_TYPE_NAME("LX"),
1436 .parent = TYPE_MACHINE,
1437 .class_init = ss_lx_class_init,
1438 };
1439
1440 static void ss4_class_init(ObjectClass *oc, void *data)
1441 {
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443
1444 mc->desc = "Sun4m platform, SPARCstation 4";
1445 mc->init = ss4_init;
1446 mc->block_default_type = IF_SCSI;
1447 mc->default_boot_order = "c";
1448 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1449 }
1450
1451 static const TypeInfo ss4_type = {
1452 .name = MACHINE_TYPE_NAME("SS-4"),
1453 .parent = TYPE_MACHINE,
1454 .class_init = ss4_class_init,
1455 };
1456
1457 static void scls_class_init(ObjectClass *oc, void *data)
1458 {
1459 MachineClass *mc = MACHINE_CLASS(oc);
1460
1461 mc->desc = "Sun4m platform, SPARCClassic";
1462 mc->init = scls_init;
1463 mc->block_default_type = IF_SCSI;
1464 mc->default_boot_order = "c";
1465 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1466 }
1467
1468 static const TypeInfo scls_type = {
1469 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1470 .parent = TYPE_MACHINE,
1471 .class_init = scls_class_init,
1472 };
1473
1474 static void sbook_class_init(ObjectClass *oc, void *data)
1475 {
1476 MachineClass *mc = MACHINE_CLASS(oc);
1477
1478 mc->desc = "Sun4m platform, SPARCbook";
1479 mc->init = sbook_init;
1480 mc->block_default_type = IF_SCSI;
1481 mc->default_boot_order = "c";
1482 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1483 }
1484
1485 static const TypeInfo sbook_type = {
1486 .name = MACHINE_TYPE_NAME("SPARCbook"),
1487 .parent = TYPE_MACHINE,
1488 .class_init = sbook_class_init,
1489 };
1490
1491 static void sun4m_register_types(void)
1492 {
1493 type_register_static(&idreg_info);
1494 type_register_static(&afx_info);
1495 type_register_static(&prom_info);
1496 type_register_static(&ram_info);
1497
1498 type_register_static(&ss5_type);
1499 type_register_static(&ss10_type);
1500 type_register_static(&ss600mp_type);
1501 type_register_static(&ss20_type);
1502 type_register_static(&voyager_type);
1503 type_register_static(&ss_lx_type);
1504 type_register_static(&ss4_type);
1505 type_register_static(&scls_type);
1506 type_register_static(&sbook_type);
1507 }
1508
1509 type_init(sun4m_register_types)
AR7 emulation for QEMU