target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7 #define TARGET_HAS_ICE 1
   8
   9 #define ELF_MACHINE     EM_MIPS
  10
  11 #define CPUArchState struct CPUMIPSState
  12
  13 #include "config.h"
  14 #include "qemu-common.h"
  15 #include "mips-defs.h"
  16 #include "exec/cpu-defs.h"
  17 #include "fpu/softfloat.h"
  18
  19 struct CPUMIPSState;
  20
  21 typedef struct r4k_tlb_t r4k_tlb_t;
  22 struct r4k_tlb_t {
  23     target_ulong VPN;
  24     uint32_t PageMask;
  25     uint_fast8_t ASID;
  26     uint_fast16_t G:1;
  27     uint_fast16_t C0:3;
  28     uint_fast16_t C1:3;
  29     uint_fast16_t V0:1;
  30     uint_fast16_t V1:1;
  31     uint_fast16_t D0:1;
  32     uint_fast16_t D1:1;
  33     target_ulong PFN[2];
  34 };
  35
  36 #if !defined(CONFIG_USER_ONLY)
  37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  38 struct CPUMIPSTLBContext {
  39     uint32_t nb_tlb;
  40     uint32_t tlb_in_use;
  41     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  42     void (*helper_tlbwi)(struct CPUMIPSState *env);
  43     void (*helper_tlbwr)(struct CPUMIPSState *env);
  44     void (*helper_tlbp)(struct CPUMIPSState *env);
  45     void (*helper_tlbr)(struct CPUMIPSState *env);
  46     union {
  47         struct {
  48             r4k_tlb_t tlb[MIPS_TLB_MAX];
  49         } r4k;
  50     } mmu;
  51 };
  52 #endif
  53
  54 typedef union fpr_t fpr_t;
  55 union fpr_t {
  56     float64  fd;   /* ieee double precision */
  57     float32  fs[2];/* ieee single precision */
  58     uint64_t d;    /* binary double fixed-point */
  59     uint32_t w[2]; /* binary single fixed-point */
  60 };
  61 /* define FP_ENDIAN_IDX to access the same location
  62  * in the fpr_t union regardless of the host endianness
  63  */
  64 #if defined(HOST_WORDS_BIGENDIAN)
  65 #  define FP_ENDIAN_IDX 1
  66 #else
  67 #  define FP_ENDIAN_IDX 0
  68 #endif
  69
  70 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  71 struct CPUMIPSFPUContext {
  72     /* Floating point registers */
  73     fpr_t fpr[32];
  74     float_status fp_status;
  75     /* fpu implementation/revision register (fir) */
  76     uint32_t fcr0;
  77 #define FCR0_UFRP 28
  78 #define FCR0_F64 22
  79 #define FCR0_L 21
  80 #define FCR0_W 20
  81 #define FCR0_3D 19
  82 #define FCR0_PS 18
  83 #define FCR0_D 17
  84 #define FCR0_S 16
  85 #define FCR0_PRID 8
  86 #define FCR0_REV 0
  87     /* fcsr */
  88     uint32_t fcr31;
  89 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  90 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  91 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  92 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  93 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  94 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  95 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  96 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  97 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  98 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  99 #define FP_INEXACT        1
 100 #define FP_UNDERFLOW      2
 101 #define FP_OVERFLOW       4
 102 #define FP_DIV0           8
 103 #define FP_INVALID        16
 104 #define FP_UNIMPLEMENTED  32
 105 };
 106
 107 #define NB_MMU_MODES 3
 108
 109 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 110 struct CPUMIPSMVPContext {
 111     int32_t CP0_MVPControl;
 112 #define CP0MVPCo_CPA    3
 113 #define CP0MVPCo_STLB   2
 114 #define CP0MVPCo_VPC    1
 115 #define CP0MVPCo_EVP    0
 116     int32_t CP0_MVPConf0;
 117 #define CP0MVPC0_M      31
 118 #define CP0MVPC0_TLBS   29
 119 #define CP0MVPC0_GS     28
 120 #define CP0MVPC0_PCP    27
 121 #define CP0MVPC0_PTLBE  16
 122 #define CP0MVPC0_TCA    15
 123 #define CP0MVPC0_PVPE   10
 124 #define CP0MVPC0_PTC    0
 125     int32_t CP0_MVPConf1;
 126 #define CP0MVPC1_CIM    31
 127 #define CP0MVPC1_CIF    30
 128 #define CP0MVPC1_PCX    20
 129 #define CP0MVPC1_PCP2   10
 130 #define CP0MVPC1_PCP1   0
 131 };
 132
 133 typedef struct mips_def_t mips_def_t;
 134
 135 #define MIPS_SHADOW_SET_MAX 16
 136 #define MIPS_TC_MAX 5
 137 #define MIPS_FPU_MAX 1
 138 #define MIPS_DSP_ACC 4
 139
 140 typedef struct TCState TCState;
 141 struct TCState {
 142     target_ulong gpr[32];
 143     target_ulong PC;
 144     target_ulong HI[MIPS_DSP_ACC];
 145     target_ulong LO[MIPS_DSP_ACC];
 146     target_ulong ACX[MIPS_DSP_ACC];
 147     target_ulong DSPControl;
 148     int32_t CP0_TCStatus;
 149 #define CP0TCSt_TCU3    31
 150 #define CP0TCSt_TCU2    30
 151 #define CP0TCSt_TCU1    29
 152 #define CP0TCSt_TCU0    28
 153 #define CP0TCSt_TMX     27
 154 #define CP0TCSt_RNST    23
 155 #define CP0TCSt_TDS     21
 156 #define CP0TCSt_DT      20
 157 #define CP0TCSt_DA      15
 158 #define CP0TCSt_A       13
 159 #define CP0TCSt_TKSU    11
 160 #define CP0TCSt_IXMT    10
 161 #define CP0TCSt_TASID   0
 162     int32_t CP0_TCBind;
 163 #define CP0TCBd_CurTC   21
 164 #define CP0TCBd_TBE     17
 165 #define CP0TCBd_CurVPE  0
 166     target_ulong CP0_TCHalt;
 167     target_ulong CP0_TCContext;
 168     target_ulong CP0_TCSchedule;
 169     target_ulong CP0_TCScheFBack;
 170     int32_t CP0_Debug_tcstatus;
 171     target_ulong CP0_UserLocal;
 172 };
 173
 174 typedef struct CPUMIPSState CPUMIPSState;
 175 struct CPUMIPSState {
 176     TCState active_tc;
 177     CPUMIPSFPUContext active_fpu;
 178
 179     uint32_t current_tc;
 180     uint32_t current_fpu;
 181
 182     uint32_t SEGBITS;
 183     uint32_t PABITS;
 184     target_ulong SEGMask;
 185     target_ulong PAMask;
 186
 187     int32_t CP0_Index;
 188     /* CP0_MVP* are per MVP registers. */
 189     int32_t CP0_Random;
 190     int32_t CP0_VPEControl;
 191 #define CP0VPECo_YSI    21
 192 #define CP0VPECo_GSI    20
 193 #define CP0VPECo_EXCPT  16
 194 #define CP0VPECo_TE     15
 195 #define CP0VPECo_TargTC 0
 196     int32_t CP0_VPEConf0;
 197 #define CP0VPEC0_M      31
 198 #define CP0VPEC0_XTC    21
 199 #define CP0VPEC0_TCS    19
 200 #define CP0VPEC0_SCS    18
 201 #define CP0VPEC0_DSC    17
 202 #define CP0VPEC0_ICS    16
 203 #define CP0VPEC0_MVP    1
 204 #define CP0VPEC0_VPA    0
 205     int32_t CP0_VPEConf1;
 206 #define CP0VPEC1_NCX    20
 207 #define CP0VPEC1_NCP2   10
 208 #define CP0VPEC1_NCP1   0
 209     target_ulong CP0_YQMask;
 210     target_ulong CP0_VPESchedule;
 211     target_ulong CP0_VPEScheFBack;
 212     int32_t CP0_VPEOpt;
 213 #define CP0VPEOpt_IWX7  15
 214 #define CP0VPEOpt_IWX6  14
 215 #define CP0VPEOpt_IWX5  13
 216 #define CP0VPEOpt_IWX4  12
 217 #define CP0VPEOpt_IWX3  11
 218 #define CP0VPEOpt_IWX2  10
 219 #define CP0VPEOpt_IWX1  9
 220 #define CP0VPEOpt_IWX0  8
 221 #define CP0VPEOpt_DWX7  7
 222 #define CP0VPEOpt_DWX6  6
 223 #define CP0VPEOpt_DWX5  5
 224 #define CP0VPEOpt_DWX4  4
 225 #define CP0VPEOpt_DWX3  3
 226 #define CP0VPEOpt_DWX2  2
 227 #define CP0VPEOpt_DWX1  1
 228 #define CP0VPEOpt_DWX0  0
 229     target_ulong CP0_EntryLo0;
 230     target_ulong CP0_EntryLo1;
 231     target_ulong CP0_Context;
 232     int32_t CP0_PageMask;
 233     int32_t CP0_PageGrain;
 234     int32_t CP0_Wired;
 235     int32_t CP0_SRSConf0_rw_bitmask;
 236     int32_t CP0_SRSConf0;
 237 #define CP0SRSC0_M      31
 238 #define CP0SRSC0_SRS3   20
 239 #define CP0SRSC0_SRS2   10
 240 #define CP0SRSC0_SRS1   0
 241     int32_t CP0_SRSConf1_rw_bitmask;
 242     int32_t CP0_SRSConf1;
 243 #define CP0SRSC1_M      31
 244 #define CP0SRSC1_SRS6   20
 245 #define CP0SRSC1_SRS5   10
 246 #define CP0SRSC1_SRS4   0
 247     int32_t CP0_SRSConf2_rw_bitmask;
 248     int32_t CP0_SRSConf2;
 249 #define CP0SRSC2_M      31
 250 #define CP0SRSC2_SRS9   20
 251 #define CP0SRSC2_SRS8   10
 252 #define CP0SRSC2_SRS7   0
 253     int32_t CP0_SRSConf3_rw_bitmask;
 254     int32_t CP0_SRSConf3;
 255 #define CP0SRSC3_M      31
 256 #define CP0SRSC3_SRS12  20
 257 #define CP0SRSC3_SRS11  10
 258 #define CP0SRSC3_SRS10  0
 259     int32_t CP0_SRSConf4_rw_bitmask;
 260     int32_t CP0_SRSConf4;
 261 #define CP0SRSC4_SRS15  20
 262 #define CP0SRSC4_SRS14  10
 263 #define CP0SRSC4_SRS13  0
 264     int32_t CP0_HWREna;
 265     target_ulong CP0_BadVAddr;
 266     int32_t CP0_Count;
 267     target_ulong CP0_EntryHi;
 268     int32_t CP0_Compare;
 269     int32_t CP0_Status;
 270 #define CP0St_CU3   31
 271 #define CP0St_CU2   30
 272 #define CP0St_CU1   29
 273 #define CP0St_CU0   28
 274 #define CP0St_RP    27
 275 #define CP0St_FR    26
 276 #define CP0St_RE    25
 277 #define CP0St_MX    24
 278 #define CP0St_PX    23
 279 #define CP0St_BEV   22
 280 #define CP0St_TS    21
 281 #define CP0St_SR    20
 282 #define CP0St_NMI   19
 283 #define CP0St_IM    8
 284 #define CP0St_KX    7
 285 #define CP0St_SX    6
 286 #define CP0St_UX    5
 287 #define CP0St_KSU   3
 288 #define CP0St_ERL   2
 289 #define CP0St_EXL   1
 290 #define CP0St_IE    0
 291     int32_t CP0_IntCtl;
 292 #define CP0IntCtl_IPTI 29
 293 #define CP0IntCtl_IPPC1 26
 294 #define CP0IntCtl_VS 5
 295     int32_t CP0_SRSCtl;
 296 #define CP0SRSCtl_HSS 26
 297 #define CP0SRSCtl_EICSS 18
 298 #define CP0SRSCtl_ESS 12
 299 #define CP0SRSCtl_PSS 6
 300 #define CP0SRSCtl_CSS 0
 301     int32_t CP0_SRSMap;
 302 #define CP0SRSMap_SSV7 28
 303 #define CP0SRSMap_SSV6 24
 304 #define CP0SRSMap_SSV5 20
 305 #define CP0SRSMap_SSV4 16
 306 #define CP0SRSMap_SSV3 12
 307 #define CP0SRSMap_SSV2 8
 308 #define CP0SRSMap_SSV1 4
 309 #define CP0SRSMap_SSV0 0
 310     int32_t CP0_Cause;
 311 #define CP0Ca_BD   31
 312 #define CP0Ca_TI   30
 313 #define CP0Ca_CE   28
 314 #define CP0Ca_DC   27
 315 #define CP0Ca_PCI  26
 316 #define CP0Ca_IV   23
 317 #define CP0Ca_WP   22
 318 #define CP0Ca_IP    8
 319 #define CP0Ca_IP_mask 0x0000FF00
 320 #define CP0Ca_EC    2
 321     target_ulong CP0_EPC;
 322     int32_t CP0_PRid;
 323     int32_t CP0_EBase;
 324     int32_t CP0_Config0;
 325 #define CP0C0_M    31
 326 #define CP0C0_K23  28
 327 #define CP0C0_KU   25
 328 #define CP0C0_MDU  20
 329 #define CP0C0_MM   17
 330 #define CP0C0_BM   16
 331 #define CP0C0_BE   15
 332 #define CP0C0_AT   13
 333 #define CP0C0_AR   10
 334 #define CP0C0_MT   7
 335 #define CP0C0_VI   3
 336 #define CP0C0_K0   0
 337     int32_t CP0_Config1;
 338 #define CP0C1_M    31
 339 #define CP0C1_MMU  25
 340 #define CP0C1_IS   22
 341 #define CP0C1_IL   19
 342 #define CP0C1_IA   16
 343 #define CP0C1_DS   13
 344 #define CP0C1_DL   10
 345 #define CP0C1_DA   7
 346 #define CP0C1_C2   6
 347 #define CP0C1_MD   5
 348 #define CP0C1_PC   4
 349 #define CP0C1_WR   3
 350 #define CP0C1_CA   2
 351 #define CP0C1_EP   1
 352 #define CP0C1_FP   0
 353     int32_t CP0_Config2;
 354 #define CP0C2_M    31
 355 #define CP0C2_TU   28
 356 #define CP0C2_TS   24
 357 #define CP0C2_TL   20
 358 #define CP0C2_TA   16
 359 #define CP0C2_SU   12
 360 #define CP0C2_SS   8
 361 #define CP0C2_SL   4
 362 #define CP0C2_SA   0
 363     int32_t CP0_Config3;
 364 #define CP0C3_M    31
 365 #define CP0C3_ISA_ON_EXC 16
 366 #define CP0C3_ULRI 13
 367 #define CP0C3_DSPP 10
 368 #define CP0C3_LPA  7
 369 #define CP0C3_VEIC 6
 370 #define CP0C3_VInt 5
 371 #define CP0C3_SP   4
 372 #define CP0C3_MT   2
 373 #define CP0C3_SM   1
 374 #define CP0C3_TL   0
 375     uint32_t CP0_Config4;
 376     uint32_t CP0_Config4_rw_bitmask;
 377 #define CP0C4_M    31
 378     uint32_t CP0_Config5;
 379     uint32_t CP0_Config5_rw_bitmask;
 380 #define CP0C5_M          31
 381 #define CP0C5_K          30
 382 #define CP0C5_CV         29
 383 #define CP0C5_EVA        28
 384 #define CP0C5_MSAEn      27
 385 #define CP0C5_UFR        2
 386 #define CP0C5_NFExists   0
 387     int32_t CP0_Config6;
 388     int32_t CP0_Config7;
 389     /* XXX: Maybe make LLAddr per-TC? */
 390     target_ulong lladdr;
 391     target_ulong llval;
 392     target_ulong llnewval;
 393     target_ulong llreg;
 394     target_ulong CP0_LLAddr_rw_bitmask;
 395     int CP0_LLAddr_shift;
 396     target_ulong CP0_WatchLo[8];
 397     int32_t CP0_WatchHi[8];
 398     target_ulong CP0_XContext;
 399     int32_t CP0_Framemask;
 400     int32_t CP0_Debug;
 401 #define CP0DB_DBD  31
 402 #define CP0DB_DM   30
 403 #define CP0DB_LSNM 28
 404 #define CP0DB_Doze 27
 405 #define CP0DB_Halt 26
 406 #define CP0DB_CNT  25
 407 #define CP0DB_IBEP 24
 408 #define CP0DB_DBEP 21
 409 #define CP0DB_IEXI 20
 410 #define CP0DB_VER  15
 411 #define CP0DB_DEC  10
 412 #define CP0DB_SSt  8
 413 #define CP0DB_DINT 5
 414 #define CP0DB_DIB  4
 415 #define CP0DB_DDBS 3
 416 #define CP0DB_DDBL 2
 417 #define CP0DB_DBp  1
 418 #define CP0DB_DSS  0
 419     target_ulong CP0_DEPC;
 420     int32_t CP0_Performance0;
 421     int32_t CP0_TagLo;
 422     int32_t CP0_DataLo;
 423     int32_t CP0_TagHi;
 424     int32_t CP0_DataHi;
 425     target_ulong CP0_ErrorEPC;
 426     int32_t CP0_DESAVE;
 427     /* We waste some space so we can handle shadow registers like TCs. */
 428     TCState tcs[MIPS_SHADOW_SET_MAX];
 429     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 430     /* QEMU */
 431     int error_code;
 432     uint32_t hflags;    /* CPU State */
 433     /* TMASK defines different execution modes */
 434 #define MIPS_HFLAG_TMASK  0xC07FF
 435 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 436     /* The KSU flags must be the lowest bits in hflags. The flag order
 437        must be the same as defined for CP0 Status. This allows to use
 438        the bits as the value of mmu_idx. */
 439 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 440 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 441 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 442 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 443 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 444 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 445 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 446 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 447 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 448     /* True if the MIPS IV COP1X instructions can be used.  This also
 449        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 450        and RSQRT.D.  */
 451 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 452 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 453 #define MIPS_HFLAG_UX     0x00200 /* 64-bit user mode                   */
 454 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 455 #define MIPS_HFLAG_M16_SHIFT 10
 456     /* If translation is interrupted between the branch instruction and
 457      * the delay slot, record what type of branch it is so that we can
 458      * resume translation properly.  It might be possible to reduce
 459      * this from three bits to two.  */
 460 #define MIPS_HFLAG_BMASK_BASE  0x03800
 461 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 462 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 463 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 464 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 465     /* Extra flags about the current pending branch.  */
 466 #define MIPS_HFLAG_BMASK_EXT 0x3C000
 467 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 468 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 469 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 470 #define MIPS_HFLAG_BX     0x20000 /* branch exchanges execution mode    */
 471 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 472     /* MIPS DSP resources access. */
 473 #define MIPS_HFLAG_DSP   0x40000  /* Enable access to MIPS DSP resources. */
 474 #define MIPS_HFLAG_DSPR2 0x80000  /* Enable access to MIPS DSPR2 resources. */
 475     /* Extra flag about HWREna register. */
 476 #define MIPS_HFLAG_HWRENA_ULR 0x100000 /* ULR bit from HWREna is set. */
 477     target_ulong btarget;        /* Jump / branch target               */
 478     target_ulong bcond;          /* Branch condition (if needed)       */
 479
 480     int SYNCI_Step; /* Address step size for SYNCI */
 481     int CCRes; /* Cycle count resolution/divisor */
 482     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 483     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 484     int insn_flags; /* Supported instruction set */
 485
 486     CPU_COMMON
 487
 488     /* Fields from here on are preserved across CPU reset. */
 489     CPUMIPSMVPContext *mvp;
 490 #if !defined(CONFIG_USER_ONLY)
 491     CPUMIPSTLBContext *tlb;
 492 #endif
 493
 494     const mips_def_t *cpu_model;
 495     void *irq[8];
 496     QEMUTimer *timer; /* Internal timer */
 497 };
 498
 499 #include "cpu-qom.h"
 500
 501 #if !defined(CONFIG_USER_ONLY)
 502 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 503                         target_ulong address, int rw, int access_type);
 504 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 505                            target_ulong address, int rw, int access_type);
 506 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 507                      target_ulong address, int rw, int access_type);
 508 void r4k_helper_tlbwi(CPUMIPSState *env);
 509 void r4k_helper_tlbwr(CPUMIPSState *env);
 510 void r4k_helper_tlbp(CPUMIPSState *env);
 511 void r4k_helper_tlbr(CPUMIPSState *env);
 512
 513 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 514                                 bool is_write, bool is_exec, int unused,
 515                                 unsigned size);
 516 #endif
 517
 518 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 519
 520 #define cpu_exec cpu_mips_exec
 521 #define cpu_gen_code cpu_mips_gen_code
 522 #define cpu_signal_handler cpu_mips_signal_handler
 523 #define cpu_list mips_cpu_list
 524
 525 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 526 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 527
 528 #define CPU_SAVE_VERSION 4
 529
 530 /* MMU modes definitions. We carefully match the indices with our
 531    hflags layout. */
 532 #define MMU_MODE0_SUFFIX _kernel
 533 #define MMU_MODE1_SUFFIX _super
 534 #define MMU_MODE2_SUFFIX _user
 535 #define MMU_USER_IDX 2
 536 static inline int cpu_mmu_index (CPUMIPSState *env)
 537 {
 538     return env->hflags & MIPS_HFLAG_KSU;
 539 }
 540
 541 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 542 {
 543     int32_t pending;
 544     int32_t status;
 545     int r;
 546
 547     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 548         (env->CP0_Status & (1 << CP0St_EXL)) ||
 549         (env->CP0_Status & (1 << CP0St_ERL)) ||
 550         /* Note that the TCStatus IXMT field is initialized to zero,
 551            and only MT capable cores can set it to one. So we don't
 552            need to check for MT capabilities here.  */
 553         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 554         (env->hflags & MIPS_HFLAG_DM)) {
 555         /* Interrupts are disabled */
 556         return 0;
 557     }
 558
 559     pending = env->CP0_Cause & CP0Ca_IP_mask;
 560     status = env->CP0_Status & CP0Ca_IP_mask;
 561
 562     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 563         /* A MIPS configured with a vectorizing external interrupt controller
 564            will feed a vector into the Cause pending lines. The core treats
 565            the status lines as a vector level, not as indiviual masks.  */
 566         r = pending > status;
 567     } else {
 568         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 569            treats the pending lines as individual interrupt lines, the status
 570            lines are individual masks.  */
 571         r = pending & status;
 572     }
 573     return r;
 574 }
 575
 576 #include "exec/cpu-all.h"
 577
 578 /* Memory access type :
 579  * may be needed for precise access rights control and precise exceptions.
 580  */
 581 enum {
 582     /* 1 bit to define user level / supervisor access */
 583     ACCESS_USER  = 0x00,
 584     ACCESS_SUPER = 0x01,
 585     /* 1 bit to indicate direction */
 586     ACCESS_STORE = 0x02,
 587     /* Type of instruction that generated the access */
 588     ACCESS_CODE  = 0x10, /* Code fetch access                */
 589     ACCESS_INT   = 0x20, /* Integer load/store access        */
 590     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 591 };
 592
 593 /* Exceptions */
 594 enum {
 595     EXCP_NONE          = -1,
 596     EXCP_RESET         = 0,
 597     EXCP_SRESET,
 598     EXCP_DSS,
 599     EXCP_DINT,
 600     EXCP_DDBL,
 601     EXCP_DDBS,
 602     EXCP_NMI,
 603     EXCP_MCHECK,
 604     EXCP_EXT_INTERRUPT, /* 8 */
 605     EXCP_DFWATCH,
 606     EXCP_DIB,
 607     EXCP_IWATCH,
 608     EXCP_AdEL,
 609     EXCP_AdES,
 610     EXCP_TLBF,
 611     EXCP_IBE,
 612     EXCP_DBp, /* 16 */
 613     EXCP_SYSCALL,
 614     EXCP_BREAK,
 615     EXCP_CpU,
 616     EXCP_RI,
 617     EXCP_OVERFLOW,
 618     EXCP_TRAP,
 619     EXCP_FPE,
 620     EXCP_DWATCH, /* 24 */
 621     EXCP_LTLBL,
 622     EXCP_TLBL,
 623     EXCP_TLBS,
 624     EXCP_DBE,
 625     EXCP_THREAD,
 626     EXCP_MDMX,
 627     EXCP_C2E,
 628     EXCP_CACHE, /* 32 */
 629     EXCP_DSPDIS,
 630
 631     EXCP_LAST = EXCP_DSPDIS,
 632 };
 633 /* Dummy exception for conditional stores.  */
 634 #define EXCP_SC 0x100
 635
 636 /*
 637  * This is an interrnally generated WAKE request line.
 638  * It is driven by the CPU itself. Raised when the MT
 639  * block wants to wake a VPE from an inactive state and
 640  * cleared when VPE goes from active to inactive.
 641  */
 642 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 643
 644 int cpu_mips_exec(CPUMIPSState *s);
 645 void mips_tcg_init(void);
 646 MIPSCPU *cpu_mips_init(const char *cpu_model);
 647 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 648
 649 static inline CPUMIPSState *cpu_init(const char *cpu_model)
 650 {
 651     MIPSCPU *cpu = cpu_mips_init(cpu_model);
 652     if (cpu == NULL) {
 653         return NULL;
 654     }
 655     return &cpu->env;
 656 }
 657
 658 /* TODO QOM'ify CPU reset and remove */
 659 void cpu_state_reset(CPUMIPSState *s);
 660
 661 /* mips_timer.c */
 662 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 663 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 664 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 665 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 666 void cpu_mips_start_count(CPUMIPSState *env);
 667 void cpu_mips_stop_count(CPUMIPSState *env);
 668
 669 /* mips_int.c */
 670 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 671
 672 /* helper.c */
 673 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 674                               int mmu_idx);
 675 #if !defined(CONFIG_USER_ONLY)
 676 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 677 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 678                                                int rw);
 679 #endif
 680 target_ulong exception_resume_pc (CPUMIPSState *env);
 681
 682 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 683                                         target_ulong *cs_base, int *flags)
 684 {
 685     *pc = env->active_tc.PC;
 686     *cs_base = 0;
 687     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 688                             MIPS_HFLAG_HWRENA_ULR);
 689 }
 690
 691 static inline int mips_vpe_active(CPUMIPSState *env)
 692 {
 693     int active = 1;
 694
 695     /* Check that the VPE is enabled.  */
 696     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 697         active = 0;
 698     }
 699     /* Check that the VPE is activated.  */
 700     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 701         active = 0;
 702     }
 703
 704     /* Now verify that there are active thread contexts in the VPE.
 705
 706        This assumes the CPU model will internally reschedule threads
 707        if the active one goes to sleep. If there are no threads available
 708        the active one will be in a sleeping state, and we can turn off
 709        the entire VPE.  */
 710     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 711         /* TC is not activated.  */
 712         active = 0;
 713     }
 714     if (env->active_tc.CP0_TCHalt & 1) {
 715         /* TC is in halt state.  */
 716         active = 0;
 717     }
 718
 719     return active;
 720 }
 721
 722 #include "exec/exec-all.h"
 723
 724 static inline void compute_hflags(CPUMIPSState *env)
 725 {
 726     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 727                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 728                      MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
 729     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 730         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 731         !(env->hflags & MIPS_HFLAG_DM)) {
 732         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 733     }
 734 #if defined(TARGET_MIPS64)
 735     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 736         (env->CP0_Status & (1 << CP0St_PX)) ||
 737         (env->CP0_Status & (1 << CP0St_UX))) {
 738         env->hflags |= MIPS_HFLAG_64;
 739     }
 740     if (env->CP0_Status & (1 << CP0St_UX)) {
 741         env->hflags |= MIPS_HFLAG_UX;
 742     }
 743 #endif
 744     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 745         !(env->hflags & MIPS_HFLAG_KSU)) {
 746         env->hflags |= MIPS_HFLAG_CP0;
 747     }
 748     if (env->CP0_Status & (1 << CP0St_CU1)) {
 749         env->hflags |= MIPS_HFLAG_FPU;
 750     }
 751     if (env->CP0_Status & (1 << CP0St_FR)) {
 752         env->hflags |= MIPS_HFLAG_F64;
 753     }
 754     if (env->insn_flags & ASE_DSPR2) {
 755         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 756            so enable to access DSPR2 resources. */
 757         if (env->CP0_Status & (1 << CP0St_MX)) {
 758             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 759         }
 760
 761     } else if (env->insn_flags & ASE_DSP) {
 762         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 763            so enable to access DSP resources. */
 764         if (env->CP0_Status & (1 << CP0St_MX)) {
 765             env->hflags |= MIPS_HFLAG_DSP;
 766         }
 767
 768     }
 769     if (env->insn_flags & ISA_MIPS32R2) {
 770         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 771             env->hflags |= MIPS_HFLAG_COP1X;
 772         }
 773     } else if (env->insn_flags & ISA_MIPS32) {
 774         if (env->hflags & MIPS_HFLAG_64) {
 775             env->hflags |= MIPS_HFLAG_COP1X;
 776         }
 777     } else if (env->insn_flags & ISA_MIPS4) {
 778         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 779            and disable the MIPS IV extensions to the MIPS III ISA.
 780            Some other MIPS IV CPUs ignore the bit, so the check here
 781            would be too restrictive for them.  */
 782         if (env->CP0_Status & (1U << CP0St_CU3)) {
 783             env->hflags |= MIPS_HFLAG_COP1X;
 784         }
 785     }
 786 }
 787
 788 #endif /* !defined (__MIPS_CPU_H__) */