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kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR
[qemu/ar7.git] / target / i386 / kvm / kvm.c
blobe364b842e6dba1536c273f13d96574a1993ea58f
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <sys/ioctl.h>
20 #include <sys/utsname.h>
21 #include <sys/syscall.h>
22
23 #include <linux/kvm.h>
24 #include "standard-headers/asm-x86/kvm_para.h"
25 #include "hw/xen/interface/arch-x86/cpuid.h"
26
27 #include "cpu.h"
28 #include "host-cpu.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/hw_accel.h"
31 #include "sysemu/kvm_int.h"
32 #include "sysemu/runstate.h"
33 #include "kvm_i386.h"
34 #include "sev.h"
35 #include "xen-emu.h"
36 #include "hyperv.h"
37 #include "hyperv-proto.h"
38
39 #include "exec/gdbstub.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/main-loop.h"
42 #include "qemu/ratelimit.h"
43 #include "qemu/config-file.h"
44 #include "qemu/error-report.h"
45 #include "qemu/memalign.h"
46 #include "hw/i386/x86.h"
47 #include "hw/i386/kvm/xen_evtchn.h"
48 #include "hw/i386/pc.h"
49 #include "hw/i386/apic.h"
50 #include "hw/i386/apic_internal.h"
51 #include "hw/i386/apic-msidef.h"
52 #include "hw/i386/intel_iommu.h"
53 #include "hw/i386/x86-iommu.h"
54 #include "hw/i386/e820_memory_layout.h"
55
56 #include "hw/xen/xen.h"
57
58 #include "hw/pci/pci.h"
59 #include "hw/pci/msi.h"
60 #include "hw/pci/msix.h"
61 #include "migration/blocker.h"
62 #include "exec/memattrs.h"
63 #include "trace.h"
64
65 #include CONFIG_DEVICES
66
67 //#define DEBUG_KVM
68
69 #ifdef DEBUG_KVM
70 #define DPRINTF(fmt, ...) \
71 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
72 #else
73 #define DPRINTF(fmt, ...) \
74 do { } while (0)
75 #endif
76
77 /* From arch/x86/kvm/lapic.h */
78 #define KVM_APIC_BUS_CYCLE_NS 1
79 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
80
81 #define MSR_KVM_WALL_CLOCK 0x11
82 #define MSR_KVM_SYSTEM_TIME 0x12
83
84 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
85 * 255 kvm_msr_entry structs */
86 #define MSR_BUF_SIZE 4096
87
88 static void kvm_init_msrs(X86CPU *cpu);
89
90 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
91 KVM_CAP_INFO(SET_TSS_ADDR),
92 KVM_CAP_INFO(EXT_CPUID),
93 KVM_CAP_INFO(MP_STATE),
94 KVM_CAP_INFO(SIGNAL_MSI),
95 KVM_CAP_INFO(IRQ_ROUTING),
96 KVM_CAP_INFO(DEBUGREGS),
97 KVM_CAP_INFO(XSAVE),
98 KVM_CAP_INFO(VCPU_EVENTS),
99 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
100 KVM_CAP_INFO(MCE),
101 KVM_CAP_INFO(ADJUST_CLOCK),
102 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
103 KVM_CAP_LAST_INFO
104 };
105
106 static bool has_msr_star;
107 static bool has_msr_hsave_pa;
108 static bool has_msr_tsc_aux;
109 static bool has_msr_tsc_adjust;
110 static bool has_msr_tsc_deadline;
111 static bool has_msr_feature_control;
112 static bool has_msr_misc_enable;
113 static bool has_msr_smbase;
114 static bool has_msr_bndcfgs;
115 static int lm_capable_kernel;
116 static bool has_msr_hv_hypercall;
117 static bool has_msr_hv_crash;
118 static bool has_msr_hv_reset;
119 static bool has_msr_hv_vpindex;
120 static bool hv_vpindex_settable;
121 static bool has_msr_hv_runtime;
122 static bool has_msr_hv_synic;
123 static bool has_msr_hv_stimer;
124 static bool has_msr_hv_frequencies;
125 static bool has_msr_hv_reenlightenment;
126 static bool has_msr_hv_syndbg_options;
127 static bool has_msr_xss;
128 static bool has_msr_umwait;
129 static bool has_msr_spec_ctrl;
130 static bool has_tsc_scale_msr;
131 static bool has_msr_tsx_ctrl;
132 static bool has_msr_virt_ssbd;
133 static bool has_msr_smi_count;
134 static bool has_msr_arch_capabs;
135 static bool has_msr_core_capabs;
136 static bool has_msr_vmx_vmfunc;
137 static bool has_msr_ucode_rev;
138 static bool has_msr_vmx_procbased_ctls2;
139 static bool has_msr_perf_capabs;
140 static bool has_msr_pkrs;
141
142 static uint32_t has_architectural_pmu_version;
143 static uint32_t num_architectural_pmu_gp_counters;
144 static uint32_t num_architectural_pmu_fixed_counters;
145
146 static int has_xsave2;
147 static int has_xcrs;
148 static int has_pit_state2;
149 static int has_sregs2;
150 static int has_exception_payload;
151 static int has_triple_fault_event;
152
153 static bool has_msr_mcg_ext_ctl;
154
155 static struct kvm_cpuid2 *cpuid_cache;
156 static struct kvm_cpuid2 *hv_cpuid_cache;
157 static struct kvm_msr_list *kvm_feature_msrs;
158
159 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
160
161 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
162 static RateLimit bus_lock_ratelimit_ctrl;
163 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
164
165 bool kvm_has_pit_state2(void)
166 {
167 return !!has_pit_state2;
168 }
169
170 bool kvm_has_smm(void)
171 {
172 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
173 }
174
175 bool kvm_has_adjust_clock_stable(void)
176 {
177 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
178
179 return (ret & KVM_CLOCK_TSC_STABLE);
180 }
181
182 bool kvm_has_exception_payload(void)
183 {
184 return has_exception_payload;
185 }
186
187 static bool kvm_x2apic_api_set_flags(uint64_t flags)
188 {
189 KVMState *s = KVM_STATE(current_accel());
190
191 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
192 }
193
194 #define MEMORIZE(fn, _result) \
195 ({ \
196 static bool _memorized; \
197 \
198 if (_memorized) { \
199 return _result; \
200 } \
201 _memorized = true; \
202 _result = fn; \
203 })
204
205 static bool has_x2apic_api;
206
207 bool kvm_has_x2apic_api(void)
208 {
209 return has_x2apic_api;
210 }
211
212 bool kvm_enable_x2apic(void)
213 {
214 return MEMORIZE(
215 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
216 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
217 has_x2apic_api);
218 }
219
220 bool kvm_hv_vpindex_settable(void)
221 {
222 return hv_vpindex_settable;
223 }
224
225 static int kvm_get_tsc(CPUState *cs)
226 {
227 X86CPU *cpu = X86_CPU(cs);
228 CPUX86State *env = &cpu->env;
229 uint64_t value;
230 int ret;
231
232 if (env->tsc_valid) {
233 return 0;
234 }
235
236 env->tsc_valid = !runstate_is_running();
237
238 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
239 if (ret < 0) {
240 return ret;
241 }
242
243 env->tsc = value;
244 return 0;
245 }
246
247 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
248 {
249 kvm_get_tsc(cpu);
250 }
251
252 void kvm_synchronize_all_tsc(void)
253 {
254 CPUState *cpu;
255
256 if (kvm_enabled()) {
257 CPU_FOREACH(cpu) {
258 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
259 }
260 }
261 }
262
263 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
264 {
265 struct kvm_cpuid2 *cpuid;
266 int r, size;
267
268 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
269 cpuid = g_malloc0(size);
270 cpuid->nent = max;
271 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
272 if (r == 0 && cpuid->nent >= max) {
273 r = -E2BIG;
274 }
275 if (r < 0) {
276 if (r == -E2BIG) {
277 g_free(cpuid);
278 return NULL;
279 } else {
280 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
281 strerror(-r));
282 exit(1);
283 }
284 }
285 return cpuid;
286 }
287
288 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
289 * for all entries.
290 */
291 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
292 {
293 struct kvm_cpuid2 *cpuid;
294 int max = 1;
295
296 if (cpuid_cache != NULL) {
297 return cpuid_cache;
298 }
299 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
300 max *= 2;
301 }
302 cpuid_cache = cpuid;
303 return cpuid;
304 }
305
306 static bool host_tsx_broken(void)
307 {
308 int family, model, stepping;\
309 char vendor[CPUID_VENDOR_SZ + 1];
310
311 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
312
313 /* Check if we are running on a Haswell host known to have broken TSX */
314 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
315 (family == 6) &&
316 ((model == 63 && stepping < 4) ||
317 model == 60 || model == 69 || model == 70);
318 }
319
320 /* Returns the value for a specific register on the cpuid entry
321 */
322 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
323 {
324 uint32_t ret = 0;
325 switch (reg) {
326 case R_EAX:
327 ret = entry->eax;
328 break;
329 case R_EBX:
330 ret = entry->ebx;
331 break;
332 case R_ECX:
333 ret = entry->ecx;
334 break;
335 case R_EDX:
336 ret = entry->edx;
337 break;
338 }
339 return ret;
340 }
341
342 /* Find matching entry for function/index on kvm_cpuid2 struct
343 */
344 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
345 uint32_t function,
346 uint32_t index)
347 {
348 int i;
349 for (i = 0; i < cpuid->nent; ++i) {
350 if (cpuid->entries[i].function == function &&
351 cpuid->entries[i].index == index) {
352 return &cpuid->entries[i];
353 }
354 }
355 /* not found: */
356 return NULL;
357 }
358
359 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
360 uint32_t index, int reg)
361 {
362 struct kvm_cpuid2 *cpuid;
363 uint32_t ret = 0;
364 uint32_t cpuid_1_edx, unused;
365 uint64_t bitmask;
366
367 cpuid = get_supported_cpuid(s);
368
369 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
370 if (entry) {
371 ret = cpuid_entry_get_reg(entry, reg);
372 }
373
374 /* Fixups for the data returned by KVM, below */
375
376 if (function == 1 && reg == R_EDX) {
377 /* KVM before 2.6.30 misreports the following features */
378 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
379 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
380 ret |= CPUID_HT;
381 } else if (function == 1 && reg == R_ECX) {
382 /* We can set the hypervisor flag, even if KVM does not return it on
383 * GET_SUPPORTED_CPUID
384 */
385 ret |= CPUID_EXT_HYPERVISOR;
386 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
387 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
388 * and the irqchip is in the kernel.
389 */
390 if (kvm_irqchip_in_kernel() &&
391 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
392 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
393 }
394
395 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
396 * without the in-kernel irqchip
397 */
398 if (!kvm_irqchip_in_kernel()) {
399 ret &= ~CPUID_EXT_X2APIC;
400 }
401
402 if (enable_cpu_pm) {
403 int disable_exits = kvm_check_extension(s,
404 KVM_CAP_X86_DISABLE_EXITS);
405
406 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
407 ret |= CPUID_EXT_MONITOR;
408 }
409 }
410 } else if (function == 6 && reg == R_EAX) {
411 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
412 } else if (function == 7 && index == 0 && reg == R_EBX) {
413 /* Not new instructions, just an optimization. */
414 uint32_t ebx;
415 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
416 ret |= ebx & CPUID_7_0_EBX_ERMS;
417
418 if (host_tsx_broken()) {
419 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
420 }
421 } else if (function == 7 && index == 0 && reg == R_EDX) {
422 /* Not new instructions, just an optimization. */
423 uint32_t edx;
424 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
425 ret |= edx & CPUID_7_0_EDX_FSRM;
426
427 /*
428 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
429 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
430 * returned by KVM_GET_MSR_INDEX_LIST.
431 */
432 if (!has_msr_arch_capabs) {
433 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
434 }
435 } else if (function == 7 && index == 1 && reg == R_EAX) {
436 /* Not new instructions, just an optimization. */
437 uint32_t eax;
438 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
439 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
440 } else if (function == 7 && index == 2 && reg == R_EDX) {
441 uint32_t edx;
442 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
443 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
444 } else if (function == 0xd && index == 0 &&
445 (reg == R_EAX || reg == R_EDX)) {
446 /*
447 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
448 * features that still have to be enabled with the arch_prctl
449 * system call. QEMU needs the full value, which is retrieved
450 * with KVM_GET_DEVICE_ATTR.
451 */
452 struct kvm_device_attr attr = {
453 .group = 0,
454 .attr = KVM_X86_XCOMP_GUEST_SUPP,
455 .addr = (unsigned long) &bitmask
456 };
457
458 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
459 if (!sys_attr) {
460 return ret;
461 }
462
463 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
464 if (rc < 0) {
465 if (rc != -ENXIO) {
466 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
467 "error: %d", rc);
468 }
469 return ret;
470 }
471 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
472 } else if (function == 0x80000001 && reg == R_ECX) {
473 /*
474 * It's safe to enable TOPOEXT even if it's not returned by
475 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
476 * us to keep CPU models including TOPOEXT runnable on older kernels.
477 */
478 ret |= CPUID_EXT3_TOPOEXT;
479 } else if (function == 0x80000001 && reg == R_EDX) {
480 /* On Intel, kvm returns cpuid according to the Intel spec,
481 * so add missing bits according to the AMD spec:
482 */
483 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
484 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
485 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
486 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
487 * be enabled without the in-kernel irqchip
488 */
489 if (!kvm_irqchip_in_kernel()) {
490 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
491 }
492 if (kvm_irqchip_is_split()) {
493 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
494 }
495 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
496 ret |= 1U << KVM_HINTS_REALTIME;
497 }
498
499 return ret;
500 }
501
502 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
503 {
504 struct {
505 struct kvm_msrs info;
506 struct kvm_msr_entry entries[1];
507 } msr_data = {};
508 uint64_t value;
509 uint32_t ret, can_be_one, must_be_one;
510
511 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
512 return 0;
513 }
514
515 /* Check if requested MSR is supported feature MSR */
516 int i;
517 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
518 if (kvm_feature_msrs->indices[i] == index) {
519 break;
520 }
521 if (i == kvm_feature_msrs->nmsrs) {
522 return 0; /* if the feature MSR is not supported, simply return 0 */
523 }
524
525 msr_data.info.nmsrs = 1;
526 msr_data.entries[0].index = index;
527
528 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
529 if (ret != 1) {
530 error_report("KVM get MSR (index=0x%x) feature failed, %s",
531 index, strerror(-ret));
532 exit(1);
533 }
534
535 value = msr_data.entries[0].data;
536 switch (index) {
537 case MSR_IA32_VMX_PROCBASED_CTLS2:
538 if (!has_msr_vmx_procbased_ctls2) {
539 /* KVM forgot to add these bits for some time, do this ourselves. */
540 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
541 CPUID_XSAVE_XSAVES) {
542 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
543 }
544 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
545 CPUID_EXT_RDRAND) {
546 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
547 }
548 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
549 CPUID_7_0_EBX_INVPCID) {
550 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
551 }
552 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
553 CPUID_7_0_EBX_RDSEED) {
554 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
555 }
556 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
557 CPUID_EXT2_RDTSCP) {
558 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
559 }
560 }
561 /* fall through */
562 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
563 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
564 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
565 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
566 /*
567 * Return true for bits that can be one, but do not have to be one.
568 * The SDM tells us which bits could have a "must be one" setting,
569 * so we can do the opposite transformation in make_vmx_msr_value.
570 */
571 must_be_one = (uint32_t)value;
572 can_be_one = (uint32_t)(value >> 32);
573 return can_be_one & ~must_be_one;
574
575 default:
576 return value;
577 }
578 }
579
580 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
581 int *max_banks)
582 {
583 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
584 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
585 }
586
587 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
588 {
589 CPUState *cs = CPU(cpu);
590 CPUX86State *env = &cpu->env;
591 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
592 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
593 uint64_t mcg_status = MCG_STATUS_MCIP;
594 int flags = 0;
595
596 if (code == BUS_MCEERR_AR) {
597 status |= MCI_STATUS_AR | 0x134;
598 mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV;
599 } else {
600 status |= 0xc0;
601 mcg_status |= MCG_STATUS_RIPV;
602 }
603
604 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
605 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
606 * guest kernel back into env->mcg_ext_ctl.
607 */
608 cpu_synchronize_state(cs);
609 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
610 mcg_status |= MCG_STATUS_LMCE;
611 flags = 0;
612 }
613
614 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
615 (MCM_ADDR_PHYS << 6) | 0xc, flags);
616 }
617
618 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
619 {
620 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
621
622 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
623 &mff);
624 }
625
626 static void hardware_memory_error(void *host_addr)
627 {
628 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
629 error_report("QEMU got Hardware memory error at addr %p", host_addr);
630 exit(1);
631 }
632
633 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
634 {
635 X86CPU *cpu = X86_CPU(c);
636 CPUX86State *env = &cpu->env;
637 ram_addr_t ram_addr;
638 hwaddr paddr;
639
640 /* If we get an action required MCE, it has been injected by KVM
641 * while the VM was running. An action optional MCE instead should
642 * be coming from the main thread, which qemu_init_sigbus identifies
643 * as the "early kill" thread.
644 */
645 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
646
647 if ((env->mcg_cap & MCG_SER_P) && addr) {
648 ram_addr = qemu_ram_addr_from_host(addr);
649 if (ram_addr != RAM_ADDR_INVALID &&
650 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
651 kvm_hwpoison_page_add(ram_addr);
652 kvm_mce_inject(cpu, paddr, code);
653
654 /*
655 * Use different logging severity based on error type.
656 * If there is additional MCE reporting on the hypervisor, QEMU VA
657 * could be another source to identify the PA and MCE details.
658 */
659 if (code == BUS_MCEERR_AR) {
660 error_report("Guest MCE Memory Error at QEMU addr %p and "
661 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
662 addr, paddr, "BUS_MCEERR_AR");
663 } else {
664 warn_report("Guest MCE Memory Error at QEMU addr %p and "
665 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
666 addr, paddr, "BUS_MCEERR_AO");
667 }
668
669 return;
670 }
671
672 if (code == BUS_MCEERR_AO) {
673 warn_report("Hardware memory error at addr %p of type %s "
674 "for memory used by QEMU itself instead of guest system!",
675 addr, "BUS_MCEERR_AO");
676 }
677 }
678
679 if (code == BUS_MCEERR_AR) {
680 hardware_memory_error(addr);
681 }
682
683 /* Hope we are lucky for AO MCE, just notify a event */
684 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
685 }
686
687 static void kvm_queue_exception(CPUX86State *env,
688 int32_t exception_nr,
689 uint8_t exception_has_payload,
690 uint64_t exception_payload)
691 {
692 assert(env->exception_nr == -1);
693 assert(!env->exception_pending);
694 assert(!env->exception_injected);
695 assert(!env->exception_has_payload);
696
697 env->exception_nr = exception_nr;
698
699 if (has_exception_payload) {
700 env->exception_pending = 1;
701
702 env->exception_has_payload = exception_has_payload;
703 env->exception_payload = exception_payload;
704 } else {
705 env->exception_injected = 1;
706
707 if (exception_nr == EXCP01_DB) {
708 assert(exception_has_payload);
709 env->dr[6] = exception_payload;
710 } else if (exception_nr == EXCP0E_PAGE) {
711 assert(exception_has_payload);
712 env->cr[2] = exception_payload;
713 } else {
714 assert(!exception_has_payload);
715 }
716 }
717 }
718
719 static void cpu_update_state(void *opaque, bool running, RunState state)
720 {
721 CPUX86State *env = opaque;
722
723 if (running) {
724 env->tsc_valid = false;
725 }
726 }
727
728 unsigned long kvm_arch_vcpu_id(CPUState *cs)
729 {
730 X86CPU *cpu = X86_CPU(cs);
731 return cpu->apic_id;
732 }
733
734 #ifndef KVM_CPUID_SIGNATURE_NEXT
735 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
736 #endif
737
738 static bool hyperv_enabled(X86CPU *cpu)
739 {
740 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
741 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
742 cpu->hyperv_features || cpu->hyperv_passthrough);
743 }
744
745 /*
746 * Check whether target_freq is within conservative
747 * ntp correctable bounds (250ppm) of freq
748 */
749 static inline bool freq_within_bounds(int freq, int target_freq)
750 {
751 int max_freq = freq + (freq * 250 / 1000000);
752 int min_freq = freq - (freq * 250 / 1000000);
753
754 if (target_freq >= min_freq && target_freq <= max_freq) {
755 return true;
756 }
757
758 return false;
759 }
760
761 static int kvm_arch_set_tsc_khz(CPUState *cs)
762 {
763 X86CPU *cpu = X86_CPU(cs);
764 CPUX86State *env = &cpu->env;
765 int r, cur_freq;
766 bool set_ioctl = false;
767
768 if (!env->tsc_khz) {
769 return 0;
770 }
771
772 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
773 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
774
775 /*
776 * If TSC scaling is supported, attempt to set TSC frequency.
777 */
778 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
779 set_ioctl = true;
780 }
781
782 /*
783 * If desired TSC frequency is within bounds of NTP correction,
784 * attempt to set TSC frequency.
785 */
786 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
787 set_ioctl = true;
788 }
789
790 r = set_ioctl ?
791 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
792 -ENOTSUP;
793
794 if (r < 0) {
795 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
796 * TSC frequency doesn't match the one we want.
797 */
798 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
799 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
800 -ENOTSUP;
801 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
802 warn_report("TSC frequency mismatch between "
803 "VM (%" PRId64 " kHz) and host (%d kHz), "
804 "and TSC scaling unavailable",
805 env->tsc_khz, cur_freq);
806 return r;
807 }
808 }
809
810 return 0;
811 }
812
813 static bool tsc_is_stable_and_known(CPUX86State *env)
814 {
815 if (!env->tsc_khz) {
816 return false;
817 }
818 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
819 || env->user_tsc_khz;
820 }
821
822 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
823
824 static struct {
825 const char *desc;
826 struct {
827 uint32_t func;
828 int reg;
829 uint32_t bits;
830 } flags[2];
831 uint64_t dependencies;
832 } kvm_hyperv_properties[] = {
833 [HYPERV_FEAT_RELAXED] = {
834 .desc = "relaxed timing (hv-relaxed)",
835 .flags = {
836 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
837 .bits = HV_RELAXED_TIMING_RECOMMENDED}
838 }
839 },
840 [HYPERV_FEAT_VAPIC] = {
841 .desc = "virtual APIC (hv-vapic)",
842 .flags = {
843 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
844 .bits = HV_APIC_ACCESS_AVAILABLE}
845 }
846 },
847 [HYPERV_FEAT_TIME] = {
848 .desc = "clocksources (hv-time)",
849 .flags = {
850 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
851 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
852 }
853 },
854 [HYPERV_FEAT_CRASH] = {
855 .desc = "crash MSRs (hv-crash)",
856 .flags = {
857 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
858 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
859 }
860 },
861 [HYPERV_FEAT_RESET] = {
862 .desc = "reset MSR (hv-reset)",
863 .flags = {
864 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
865 .bits = HV_RESET_AVAILABLE}
866 }
867 },
868 [HYPERV_FEAT_VPINDEX] = {
869 .desc = "VP_INDEX MSR (hv-vpindex)",
870 .flags = {
871 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
872 .bits = HV_VP_INDEX_AVAILABLE}
873 }
874 },
875 [HYPERV_FEAT_RUNTIME] = {
876 .desc = "VP_RUNTIME MSR (hv-runtime)",
877 .flags = {
878 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
879 .bits = HV_VP_RUNTIME_AVAILABLE}
880 }
881 },
882 [HYPERV_FEAT_SYNIC] = {
883 .desc = "synthetic interrupt controller (hv-synic)",
884 .flags = {
885 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
886 .bits = HV_SYNIC_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_STIMER] = {
890 .desc = "synthetic timers (hv-stimer)",
891 .flags = {
892 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
893 .bits = HV_SYNTIMERS_AVAILABLE}
894 },
895 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
896 },
897 [HYPERV_FEAT_FREQUENCIES] = {
898 .desc = "frequency MSRs (hv-frequencies)",
899 .flags = {
900 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
901 .bits = HV_ACCESS_FREQUENCY_MSRS},
902 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
903 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
904 }
905 },
906 [HYPERV_FEAT_REENLIGHTENMENT] = {
907 .desc = "reenlightenment MSRs (hv-reenlightenment)",
908 .flags = {
909 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
910 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
911 }
912 },
913 [HYPERV_FEAT_TLBFLUSH] = {
914 .desc = "paravirtualized TLB flush (hv-tlbflush)",
915 .flags = {
916 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
917 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
921 },
922 [HYPERV_FEAT_EVMCS] = {
923 .desc = "enlightened VMCS (hv-evmcs)",
924 .flags = {
925 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
926 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
927 },
928 .dependencies = BIT(HYPERV_FEAT_VAPIC)
929 },
930 [HYPERV_FEAT_IPI] = {
931 .desc = "paravirtualized IPI (hv-ipi)",
932 .flags = {
933 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
934 .bits = HV_CLUSTER_IPI_RECOMMENDED |
935 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
936 },
937 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
938 },
939 [HYPERV_FEAT_STIMER_DIRECT] = {
940 .desc = "direct mode synthetic timers (hv-stimer-direct)",
941 .flags = {
942 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
943 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
944 },
945 .dependencies = BIT(HYPERV_FEAT_STIMER)
946 },
947 [HYPERV_FEAT_AVIC] = {
948 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
949 .flags = {
950 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
951 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
952 }
953 },
954 #ifdef CONFIG_SYNDBG
955 [HYPERV_FEAT_SYNDBG] = {
956 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
957 .flags = {
958 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
959 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
960 },
961 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED)
962 },
963 #endif
964 [HYPERV_FEAT_MSR_BITMAP] = {
965 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
966 .flags = {
967 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
968 .bits = HV_NESTED_MSR_BITMAP}
969 }
970 },
971 [HYPERV_FEAT_XMM_INPUT] = {
972 .desc = "XMM fast hypercall input (hv-xmm-input)",
973 .flags = {
974 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
975 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
976 }
977 },
978 [HYPERV_FEAT_TLBFLUSH_EXT] = {
979 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
980 .flags = {
981 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
982 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
983 },
984 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
985 },
986 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
987 .desc = "direct TLB flush (hv-tlbflush-direct)",
988 .flags = {
989 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
990 .bits = HV_NESTED_DIRECT_FLUSH}
991 },
992 .dependencies = BIT(HYPERV_FEAT_VAPIC)
993 },
994 };
995
996 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
997 bool do_sys_ioctl)
998 {
999 struct kvm_cpuid2 *cpuid;
1000 int r, size;
1001
1002 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1003 cpuid = g_malloc0(size);
1004 cpuid->nent = max;
1005
1006 if (do_sys_ioctl) {
1007 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1008 } else {
1009 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1010 }
1011 if (r == 0 && cpuid->nent >= max) {
1012 r = -E2BIG;
1013 }
1014 if (r < 0) {
1015 if (r == -E2BIG) {
1016 g_free(cpuid);
1017 return NULL;
1018 } else {
1019 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1020 strerror(-r));
1021 exit(1);
1022 }
1023 }
1024 return cpuid;
1025 }
1026
1027 /*
1028 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1029 * for all entries.
1030 */
1031 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1032 {
1033 struct kvm_cpuid2 *cpuid;
1034 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1035 int max = 11;
1036 int i;
1037 bool do_sys_ioctl;
1038
1039 do_sys_ioctl =
1040 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1041
1042 /*
1043 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1044 * unsupported, kvm_hyperv_expand_features() checks for that.
1045 */
1046 assert(do_sys_ioctl || cs->kvm_state);
1047
1048 /*
1049 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1050 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1051 * it and re-trying until we succeed.
1052 */
1053 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1054 max++;
1055 }
1056
1057 /*
1058 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1059 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1060 * information early, just check for the capability and set the bit
1061 * manually.
1062 */
1063 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1064 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1065 for (i = 0; i < cpuid->nent; i++) {
1066 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1067 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1068 }
1069 }
1070 }
1071
1072 return cpuid;
1073 }
1074
1075 /*
1076 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1077 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1078 */
1079 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1080 {
1081 X86CPU *cpu = X86_CPU(cs);
1082 struct kvm_cpuid2 *cpuid;
1083 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1084
1085 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1086 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1087 cpuid->nent = 2;
1088
1089 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1090 entry_feat = &cpuid->entries[0];
1091 entry_feat->function = HV_CPUID_FEATURES;
1092
1093 entry_recomm = &cpuid->entries[1];
1094 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1095 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1096
1097 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1098 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1099 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1100 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1101 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1102 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1103 }
1104
1105 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1106 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1107 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1108 }
1109
1110 if (has_msr_hv_frequencies) {
1111 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1112 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1113 }
1114
1115 if (has_msr_hv_crash) {
1116 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1117 }
1118
1119 if (has_msr_hv_reenlightenment) {
1120 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1121 }
1122
1123 if (has_msr_hv_reset) {
1124 entry_feat->eax |= HV_RESET_AVAILABLE;
1125 }
1126
1127 if (has_msr_hv_vpindex) {
1128 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1129 }
1130
1131 if (has_msr_hv_runtime) {
1132 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1133 }
1134
1135 if (has_msr_hv_synic) {
1136 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1137 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1138
1139 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1140 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1141 }
1142 }
1143
1144 if (has_msr_hv_stimer) {
1145 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1146 }
1147
1148 if (has_msr_hv_syndbg_options) {
1149 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1150 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1151 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1152 }
1153
1154 if (kvm_check_extension(cs->kvm_state,
1155 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1156 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1157 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1158 }
1159
1160 if (kvm_check_extension(cs->kvm_state,
1161 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1162 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1163 }
1164
1165 if (kvm_check_extension(cs->kvm_state,
1166 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1167 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1168 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1169 }
1170
1171 return cpuid;
1172 }
1173
1174 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1175 {
1176 struct kvm_cpuid_entry2 *entry;
1177 struct kvm_cpuid2 *cpuid;
1178
1179 if (hv_cpuid_cache) {
1180 cpuid = hv_cpuid_cache;
1181 } else {
1182 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1183 cpuid = get_supported_hv_cpuid(cs);
1184 } else {
1185 /*
1186 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1187 * before KVM context is created but this is only done when
1188 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1189 * KVM_CAP_HYPERV_CPUID.
1190 */
1191 assert(cs->kvm_state);
1192
1193 cpuid = get_supported_hv_cpuid_legacy(cs);
1194 }
1195 hv_cpuid_cache = cpuid;
1196 }
1197
1198 if (!cpuid) {
1199 return 0;
1200 }
1201
1202 entry = cpuid_find_entry(cpuid, func, 0);
1203 if (!entry) {
1204 return 0;
1205 }
1206
1207 return cpuid_entry_get_reg(entry, reg);
1208 }
1209
1210 static bool hyperv_feature_supported(CPUState *cs, int feature)
1211 {
1212 uint32_t func, bits;
1213 int i, reg;
1214
1215 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1216
1217 func = kvm_hyperv_properties[feature].flags[i].func;
1218 reg = kvm_hyperv_properties[feature].flags[i].reg;
1219 bits = kvm_hyperv_properties[feature].flags[i].bits;
1220
1221 if (!func) {
1222 continue;
1223 }
1224
1225 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1226 return false;
1227 }
1228 }
1229
1230 return true;
1231 }
1232
1233 /* Checks that all feature dependencies are enabled */
1234 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1235 {
1236 uint64_t deps;
1237 int dep_feat;
1238
1239 deps = kvm_hyperv_properties[feature].dependencies;
1240 while (deps) {
1241 dep_feat = ctz64(deps);
1242 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1243 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1244 kvm_hyperv_properties[feature].desc,
1245 kvm_hyperv_properties[dep_feat].desc);
1246 return false;
1247 }
1248 deps &= ~(1ull << dep_feat);
1249 }
1250
1251 return true;
1252 }
1253
1254 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1255 {
1256 X86CPU *cpu = X86_CPU(cs);
1257 uint32_t r = 0;
1258 int i, j;
1259
1260 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1261 if (!hyperv_feat_enabled(cpu, i)) {
1262 continue;
1263 }
1264
1265 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1266 if (kvm_hyperv_properties[i].flags[j].func != func) {
1267 continue;
1268 }
1269 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1270 continue;
1271 }
1272
1273 r |= kvm_hyperv_properties[i].flags[j].bits;
1274 }
1275 }
1276
1277 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1278 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1279 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1280 r |= DEFAULT_EVMCS_VERSION;
1281 }
1282 }
1283
1284 return r;
1285 }
1286
1287 /*
1288 * Expand Hyper-V CPU features. In partucular, check that all the requested
1289 * features are supported by the host and the sanity of the configuration
1290 * (that all the required dependencies are included). Also, this takes care
1291 * of 'hv_passthrough' mode and fills the environment with all supported
1292 * Hyper-V features.
1293 */
1294 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1295 {
1296 CPUState *cs = CPU(cpu);
1297 Error *local_err = NULL;
1298 int feat;
1299
1300 if (!hyperv_enabled(cpu))
1301 return true;
1302
1303 /*
1304 * When kvm_hyperv_expand_features is called at CPU feature expansion
1305 * time per-CPU kvm_state is not available yet so we can only proceed
1306 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1307 */
1308 if (!cs->kvm_state &&
1309 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1310 return true;
1311
1312 if (cpu->hyperv_passthrough) {
1313 cpu->hyperv_vendor_id[0] =
1314 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1315 cpu->hyperv_vendor_id[1] =
1316 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1317 cpu->hyperv_vendor_id[2] =
1318 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1319 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1320 sizeof(cpu->hyperv_vendor_id) + 1);
1321 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1322 sizeof(cpu->hyperv_vendor_id));
1323 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1324
1325 cpu->hyperv_interface_id[0] =
1326 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1327 cpu->hyperv_interface_id[1] =
1328 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1329 cpu->hyperv_interface_id[2] =
1330 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1331 cpu->hyperv_interface_id[3] =
1332 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1333
1334 cpu->hyperv_ver_id_build =
1335 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1336 cpu->hyperv_ver_id_major =
1337 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1338 cpu->hyperv_ver_id_minor =
1339 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1340 cpu->hyperv_ver_id_sp =
1341 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1342 cpu->hyperv_ver_id_sb =
1343 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1344 cpu->hyperv_ver_id_sn =
1345 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1346
1347 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1348 R_EAX);
1349 cpu->hyperv_limits[0] =
1350 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1351 cpu->hyperv_limits[1] =
1352 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1353 cpu->hyperv_limits[2] =
1354 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1355
1356 cpu->hyperv_spinlock_attempts =
1357 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1358
1359 /*
1360 * Mark feature as enabled in 'cpu->hyperv_features' as
1361 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1362 */
1363 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1364 if (hyperv_feature_supported(cs, feat)) {
1365 cpu->hyperv_features |= BIT(feat);
1366 }
1367 }
1368 } else {
1369 /* Check features availability and dependencies */
1370 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1371 /* If the feature was not requested skip it. */
1372 if (!hyperv_feat_enabled(cpu, feat)) {
1373 continue;
1374 }
1375
1376 /* Check if the feature is supported by KVM */
1377 if (!hyperv_feature_supported(cs, feat)) {
1378 error_setg(errp, "Hyper-V %s is not supported by kernel",
1379 kvm_hyperv_properties[feat].desc);
1380 return false;
1381 }
1382
1383 /* Check dependencies */
1384 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1385 error_propagate(errp, local_err);
1386 return false;
1387 }
1388 }
1389 }
1390
1391 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1392 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1393 !cpu->hyperv_synic_kvm_only &&
1394 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1395 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1396 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1397 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1398 return false;
1399 }
1400
1401 return true;
1402 }
1403
1404 /*
1405 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1406 */
1407 static int hyperv_fill_cpuids(CPUState *cs,
1408 struct kvm_cpuid_entry2 *cpuid_ent)
1409 {
1410 X86CPU *cpu = X86_CPU(cs);
1411 struct kvm_cpuid_entry2 *c;
1412 uint32_t signature[3];
1413 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1414 uint32_t nested_eax =
1415 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1416
1417 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1418 HV_CPUID_IMPLEMENT_LIMITS;
1419
1420 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1421 max_cpuid_leaf =
1422 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1423 }
1424
1425 c = &cpuid_ent[cpuid_i++];
1426 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1427 c->eax = max_cpuid_leaf;
1428 c->ebx = cpu->hyperv_vendor_id[0];
1429 c->ecx = cpu->hyperv_vendor_id[1];
1430 c->edx = cpu->hyperv_vendor_id[2];
1431
1432 c = &cpuid_ent[cpuid_i++];
1433 c->function = HV_CPUID_INTERFACE;
1434 c->eax = cpu->hyperv_interface_id[0];
1435 c->ebx = cpu->hyperv_interface_id[1];
1436 c->ecx = cpu->hyperv_interface_id[2];
1437 c->edx = cpu->hyperv_interface_id[3];
1438
1439 c = &cpuid_ent[cpuid_i++];
1440 c->function = HV_CPUID_VERSION;
1441 c->eax = cpu->hyperv_ver_id_build;
1442 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1443 cpu->hyperv_ver_id_minor;
1444 c->ecx = cpu->hyperv_ver_id_sp;
1445 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1446 (cpu->hyperv_ver_id_sn & 0xffffff);
1447
1448 c = &cpuid_ent[cpuid_i++];
1449 c->function = HV_CPUID_FEATURES;
1450 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1451 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1452 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1453
1454 /* Unconditionally required with any Hyper-V enlightenment */
1455 c->eax |= HV_HYPERCALL_AVAILABLE;
1456
1457 /* SynIC and Vmbus devices require messages/signals hypercalls */
1458 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1459 !cpu->hyperv_synic_kvm_only) {
1460 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1461 }
1462
1463
1464 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1465 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1466
1467 c = &cpuid_ent[cpuid_i++];
1468 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1469 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1470 c->ebx = cpu->hyperv_spinlock_attempts;
1471
1472 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1473 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1474 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1475 }
1476
1477 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1478 c->eax |= HV_NO_NONARCH_CORESHARING;
1479 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1480 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1481 HV_NO_NONARCH_CORESHARING;
1482 }
1483
1484 c = &cpuid_ent[cpuid_i++];
1485 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1486 c->eax = cpu->hv_max_vps;
1487 c->ebx = cpu->hyperv_limits[0];
1488 c->ecx = cpu->hyperv_limits[1];
1489 c->edx = cpu->hyperv_limits[2];
1490
1491 if (nested_eax) {
1492 uint32_t function;
1493
1494 /* Create zeroed 0x40000006..0x40000009 leaves */
1495 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1496 function < HV_CPUID_NESTED_FEATURES; function++) {
1497 c = &cpuid_ent[cpuid_i++];
1498 c->function = function;
1499 }
1500
1501 c = &cpuid_ent[cpuid_i++];
1502 c->function = HV_CPUID_NESTED_FEATURES;
1503 c->eax = nested_eax;
1504 }
1505
1506 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1507 c = &cpuid_ent[cpuid_i++];
1508 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1509 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1510 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1511 memcpy(signature, "Microsoft VS", 12);
1512 c->eax = 0;
1513 c->ebx = signature[0];
1514 c->ecx = signature[1];
1515 c->edx = signature[2];
1516
1517 c = &cpuid_ent[cpuid_i++];
1518 c->function = HV_CPUID_SYNDBG_INTERFACE;
1519 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1520 c->eax = signature[0];
1521 c->ebx = 0;
1522 c->ecx = 0;
1523 c->edx = 0;
1524
1525 c = &cpuid_ent[cpuid_i++];
1526 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1527 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1528 c->ebx = 0;
1529 c->ecx = 0;
1530 c->edx = 0;
1531 }
1532
1533 return cpuid_i;
1534 }
1535
1536 static Error *hv_passthrough_mig_blocker;
1537 static Error *hv_no_nonarch_cs_mig_blocker;
1538
1539 /* Checks that the exposed eVMCS version range is supported by KVM */
1540 static bool evmcs_version_supported(uint16_t evmcs_version,
1541 uint16_t supported_evmcs_version)
1542 {
1543 uint8_t min_version = evmcs_version & 0xff;
1544 uint8_t max_version = evmcs_version >> 8;
1545 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1546 uint8_t max_supported_version = supported_evmcs_version >> 8;
1547
1548 return (min_version >= min_supported_version) &&
1549 (max_version <= max_supported_version);
1550 }
1551
1552 static int hyperv_init_vcpu(X86CPU *cpu)
1553 {
1554 CPUState *cs = CPU(cpu);
1555 Error *local_err = NULL;
1556 int ret;
1557
1558 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1559 error_setg(&hv_passthrough_mig_blocker,
1560 "'hv-passthrough' CPU flag prevents migration, use explicit"
1561 " set of hv-* flags instead");
1562 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1563 if (ret < 0) {
1564 error_report_err(local_err);
1565 return ret;
1566 }
1567 }
1568
1569 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1570 hv_no_nonarch_cs_mig_blocker == NULL) {
1571 error_setg(&hv_no_nonarch_cs_mig_blocker,
1572 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1573 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1574 " make sure SMT is disabled and/or that vCPUs are properly"
1575 " pinned)");
1576 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1577 if (ret < 0) {
1578 error_report_err(local_err);
1579 return ret;
1580 }
1581 }
1582
1583 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1584 /*
1585 * the kernel doesn't support setting vp_index; assert that its value
1586 * is in sync
1587 */
1588 uint64_t value;
1589
1590 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1591 if (ret < 0) {
1592 return ret;
1593 }
1594
1595 if (value != hyperv_vp_index(CPU(cpu))) {
1596 error_report("kernel's vp_index != QEMU's vp_index");
1597 return -ENXIO;
1598 }
1599 }
1600
1601 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1602 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1603 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1604 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1605 if (ret < 0) {
1606 error_report("failed to turn on HyperV SynIC in KVM: %s",
1607 strerror(-ret));
1608 return ret;
1609 }
1610
1611 if (!cpu->hyperv_synic_kvm_only) {
1612 ret = hyperv_x86_synic_add(cpu);
1613 if (ret < 0) {
1614 error_report("failed to create HyperV SynIC: %s",
1615 strerror(-ret));
1616 return ret;
1617 }
1618 }
1619 }
1620
1621 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1622 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1623 uint16_t supported_evmcs_version;
1624
1625 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1626 (uintptr_t)&supported_evmcs_version);
1627
1628 /*
1629 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1630 * option sets. Note: we hardcode the maximum supported eVMCS version
1631 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1632 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1633 * to be added.
1634 */
1635 if (ret < 0) {
1636 error_report("Hyper-V %s is not supported by kernel",
1637 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1638 return ret;
1639 }
1640
1641 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1642 error_report("eVMCS version range [%d..%d] is not supported by "
1643 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1644 evmcs_version >> 8, supported_evmcs_version & 0xff,
1645 supported_evmcs_version >> 8);
1646 return -ENOTSUP;
1647 }
1648 }
1649
1650 if (cpu->hyperv_enforce_cpuid) {
1651 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1652 if (ret < 0) {
1653 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1654 strerror(-ret));
1655 return ret;
1656 }
1657 }
1658
1659 return 0;
1660 }
1661
1662 static Error *invtsc_mig_blocker;
1663
1664 #define KVM_MAX_CPUID_ENTRIES 100
1665
1666 static void kvm_init_xsave(CPUX86State *env)
1667 {
1668 if (has_xsave2) {
1669 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1670 } else {
1671 env->xsave_buf_len = sizeof(struct kvm_xsave);
1672 }
1673
1674 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1675 memset(env->xsave_buf, 0, env->xsave_buf_len);
1676 /*
1677 * The allocated storage must be large enough for all of the
1678 * possible XSAVE state components.
1679 */
1680 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1681 env->xsave_buf_len);
1682 }
1683
1684 static void kvm_init_nested_state(CPUX86State *env)
1685 {
1686 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1687 uint32_t size;
1688
1689 if (!env->nested_state) {
1690 return;
1691 }
1692
1693 size = env->nested_state->size;
1694
1695 memset(env->nested_state, 0, size);
1696 env->nested_state->size = size;
1697
1698 if (cpu_has_vmx(env)) {
1699 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1700 vmx_hdr = &env->nested_state->hdr.vmx;
1701 vmx_hdr->vmxon_pa = -1ull;
1702 vmx_hdr->vmcs12_pa = -1ull;
1703 } else if (cpu_has_svm(env)) {
1704 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1705 }
1706 }
1707
1708 int kvm_arch_init_vcpu(CPUState *cs)
1709 {
1710 struct {
1711 struct kvm_cpuid2 cpuid;
1712 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1713 } cpuid_data;
1714 /*
1715 * The kernel defines these structs with padding fields so there
1716 * should be no extra padding in our cpuid_data struct.
1717 */
1718 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1719 sizeof(struct kvm_cpuid2) +
1720 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1721
1722 X86CPU *cpu = X86_CPU(cs);
1723 CPUX86State *env = &cpu->env;
1724 uint32_t limit, i, j, cpuid_i;
1725 uint32_t unused;
1726 struct kvm_cpuid_entry2 *c;
1727 uint32_t signature[3];
1728 int kvm_base = KVM_CPUID_SIGNATURE;
1729 int max_nested_state_len;
1730 int r;
1731 Error *local_err = NULL;
1732
1733 memset(&cpuid_data, 0, sizeof(cpuid_data));
1734
1735 cpuid_i = 0;
1736
1737 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
1738
1739 r = kvm_arch_set_tsc_khz(cs);
1740 if (r < 0) {
1741 return r;
1742 }
1743
1744 /* vcpu's TSC frequency is either specified by user, or following
1745 * the value used by KVM if the former is not present. In the
1746 * latter case, we query it from KVM and record in env->tsc_khz,
1747 * so that vcpu's TSC frequency can be migrated later via this field.
1748 */
1749 if (!env->tsc_khz) {
1750 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1751 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1752 -ENOTSUP;
1753 if (r > 0) {
1754 env->tsc_khz = r;
1755 }
1756 }
1757
1758 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1759
1760 /*
1761 * kvm_hyperv_expand_features() is called here for the second time in case
1762 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
1763 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
1764 * check which Hyper-V enlightenments are supported and which are not, we
1765 * can still proceed and check/expand Hyper-V enlightenments here so legacy
1766 * behavior is preserved.
1767 */
1768 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
1769 error_report_err(local_err);
1770 return -ENOSYS;
1771 }
1772
1773 if (hyperv_enabled(cpu)) {
1774 r = hyperv_init_vcpu(cpu);
1775 if (r) {
1776 return r;
1777 }
1778
1779 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
1780 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1781 has_msr_hv_hypercall = true;
1782 }
1783
1784 if (cs->kvm_state->xen_version) {
1785 #ifdef CONFIG_XEN_EMU
1786 struct kvm_cpuid_entry2 *xen_max_leaf;
1787
1788 memcpy(signature, "XenVMMXenVMM", 12);
1789
1790 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
1791 c->function = kvm_base + XEN_CPUID_SIGNATURE;
1792 c->eax = kvm_base + XEN_CPUID_TIME;
1793 c->ebx = signature[0];
1794 c->ecx = signature[1];
1795 c->edx = signature[2];
1796
1797 c = &cpuid_data.entries[cpuid_i++];
1798 c->function = kvm_base + XEN_CPUID_VENDOR;
1799 c->eax = cs->kvm_state->xen_version;
1800 c->ebx = 0;
1801 c->ecx = 0;
1802 c->edx = 0;
1803
1804 c = &cpuid_data.entries[cpuid_i++];
1805 c->function = kvm_base + XEN_CPUID_HVM_MSR;
1806 /* Number of hypercall-transfer pages */
1807 c->eax = 1;
1808 /* Hypercall MSR base address */
1809 if (hyperv_enabled(cpu)) {
1810 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
1811 kvm_xen_init(cs->kvm_state, c->ebx);
1812 } else {
1813 c->ebx = XEN_HYPERCALL_MSR;
1814 }
1815 c->ecx = 0;
1816 c->edx = 0;
1817
1818 c = &cpuid_data.entries[cpuid_i++];
1819 c->function = kvm_base + XEN_CPUID_TIME;
1820 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
1821 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
1822 /* default=0 (emulate if necessary) */
1823 c->ebx = 0;
1824 /* guest tsc frequency */
1825 c->ecx = env->user_tsc_khz;
1826 /* guest tsc incarnation (migration count) */
1827 c->edx = 0;
1828
1829 c = &cpuid_data.entries[cpuid_i++];
1830 c->function = kvm_base + XEN_CPUID_HVM;
1831 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
1832 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
1833 c->function = kvm_base + XEN_CPUID_HVM;
1834
1835 if (cpu->xen_vapic) {
1836 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
1837 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
1838 }
1839
1840 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
1841
1842 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
1843 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
1844 c->ebx = cs->cpu_index;
1845 }
1846 }
1847
1848 r = kvm_xen_init_vcpu(cs);
1849 if (r) {
1850 return r;
1851 }
1852
1853 kvm_base += 0x100;
1854 #else /* CONFIG_XEN_EMU */
1855 /* This should never happen as kvm_arch_init() would have died first. */
1856 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
1857 abort();
1858 #endif
1859 } else if (cpu->expose_kvm) {
1860 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1861 c = &cpuid_data.entries[cpuid_i++];
1862 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1863 c->eax = KVM_CPUID_FEATURES | kvm_base;
1864 c->ebx = signature[0];
1865 c->ecx = signature[1];
1866 c->edx = signature[2];
1867
1868 c = &cpuid_data.entries[cpuid_i++];
1869 c->function = KVM_CPUID_FEATURES | kvm_base;
1870 c->eax = env->features[FEAT_KVM];
1871 c->edx = env->features[FEAT_KVM_HINTS];
1872 }
1873
1874 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1875
1876 if (cpu->kvm_pv_enforce_cpuid) {
1877 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
1878 if (r < 0) {
1879 fprintf(stderr,
1880 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
1881 strerror(-r));
1882 abort();
1883 }
1884 }
1885
1886 for (i = 0; i <= limit; i++) {
1887 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1888 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1889 abort();
1890 }
1891 c = &cpuid_data.entries[cpuid_i++];
1892
1893 switch (i) {
1894 case 2: {
1895 /* Keep reading function 2 till all the input is received */
1896 int times;
1897
1898 c->function = i;
1899 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1900 KVM_CPUID_FLAG_STATE_READ_NEXT;
1901 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1902 times = c->eax & 0xff;
1903
1904 for (j = 1; j < times; ++j) {
1905 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1906 fprintf(stderr, "cpuid_data is full, no space for "
1907 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1908 abort();
1909 }
1910 c = &cpuid_data.entries[cpuid_i++];
1911 c->function = i;
1912 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1913 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1914 }
1915 break;
1916 }
1917 case 0x1f:
1918 if (env->nr_dies < 2) {
1919 break;
1920 }
1921 /* fallthrough */
1922 case 4:
1923 case 0xb:
1924 case 0xd:
1925 for (j = 0; ; j++) {
1926 if (i == 0xd && j == 64) {
1927 break;
1928 }
1929
1930 if (i == 0x1f && j == 64) {
1931 break;
1932 }
1933
1934 c->function = i;
1935 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1936 c->index = j;
1937 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1938
1939 if (i == 4 && c->eax == 0) {
1940 break;
1941 }
1942 if (i == 0xb && !(c->ecx & 0xff00)) {
1943 break;
1944 }
1945 if (i == 0x1f && !(c->ecx & 0xff00)) {
1946 break;
1947 }
1948 if (i == 0xd && c->eax == 0) {
1949 continue;
1950 }
1951 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1952 fprintf(stderr, "cpuid_data is full, no space for "
1953 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1954 abort();
1955 }
1956 c = &cpuid_data.entries[cpuid_i++];
1957 }
1958 break;
1959 case 0x7:
1960 case 0x12:
1961 for (j = 0; ; j++) {
1962 c->function = i;
1963 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1964 c->index = j;
1965 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1966
1967 if (j > 1 && (c->eax & 0xf) != 1) {
1968 break;
1969 }
1970
1971 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1972 fprintf(stderr, "cpuid_data is full, no space for "
1973 "cpuid(eax:0x12,ecx:0x%x)\n", j);
1974 abort();
1975 }
1976 c = &cpuid_data.entries[cpuid_i++];
1977 }
1978 break;
1979 case 0x14:
1980 case 0x1d:
1981 case 0x1e: {
1982 uint32_t times;
1983
1984 c->function = i;
1985 c->index = 0;
1986 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1987 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1988 times = c->eax;
1989
1990 for (j = 1; j <= times; ++j) {
1991 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1992 fprintf(stderr, "cpuid_data is full, no space for "
1993 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1994 abort();
1995 }
1996 c = &cpuid_data.entries[cpuid_i++];
1997 c->function = i;
1998 c->index = j;
1999 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2000 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2001 }
2002 break;
2003 }
2004 default:
2005 c->function = i;
2006 c->flags = 0;
2007 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2008 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2009 /*
2010 * KVM already returns all zeroes if a CPUID entry is missing,
2011 * so we can omit it and avoid hitting KVM's 80-entry limit.
2012 */
2013 cpuid_i--;
2014 }
2015 break;
2016 }
2017 }
2018
2019 if (limit >= 0x0a) {
2020 uint32_t eax, edx;
2021
2022 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
2023
2024 has_architectural_pmu_version = eax & 0xff;
2025 if (has_architectural_pmu_version > 0) {
2026 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
2027
2028 /* Shouldn't be more than 32, since that's the number of bits
2029 * available in EBX to tell us _which_ counters are available.
2030 * Play it safe.
2031 */
2032 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
2033 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
2034 }
2035
2036 if (has_architectural_pmu_version > 1) {
2037 num_architectural_pmu_fixed_counters = edx & 0x1f;
2038
2039 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
2040 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
2041 }
2042 }
2043 }
2044 }
2045
2046 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
2047
2048 for (i = 0x80000000; i <= limit; i++) {
2049 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2050 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
2051 abort();
2052 }
2053 c = &cpuid_data.entries[cpuid_i++];
2054
2055 switch (i) {
2056 case 0x8000001d:
2057 /* Query for all AMD cache information leaves */
2058 for (j = 0; ; j++) {
2059 c->function = i;
2060 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2061 c->index = j;
2062 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2063
2064 if (c->eax == 0) {
2065 break;
2066 }
2067 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2068 fprintf(stderr, "cpuid_data is full, no space for "
2069 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2070 abort();
2071 }
2072 c = &cpuid_data.entries[cpuid_i++];
2073 }
2074 break;
2075 default:
2076 c->function = i;
2077 c->flags = 0;
2078 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2079 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2080 /*
2081 * KVM already returns all zeroes if a CPUID entry is missing,
2082 * so we can omit it and avoid hitting KVM's 80-entry limit.
2083 */
2084 cpuid_i--;
2085 }
2086 break;
2087 }
2088 }
2089
2090 /* Call Centaur's CPUID instructions they are supported. */
2091 if (env->cpuid_xlevel2 > 0) {
2092 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2093
2094 for (i = 0xC0000000; i <= limit; i++) {
2095 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2096 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
2097 abort();
2098 }
2099 c = &cpuid_data.entries[cpuid_i++];
2100
2101 c->function = i;
2102 c->flags = 0;
2103 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2104 }
2105 }
2106
2107 cpuid_data.cpuid.nent = cpuid_i;
2108
2109 if (((env->cpuid_version >> 8)&0xF) >= 6
2110 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2111 (CPUID_MCE | CPUID_MCA)) {
2112 uint64_t mcg_cap, unsupported_caps;
2113 int banks;
2114 int ret;
2115
2116 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2117 if (ret < 0) {
2118 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2119 return ret;
2120 }
2121
2122 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2123 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2124 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2125 return -ENOTSUP;
2126 }
2127
2128 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2129 if (unsupported_caps) {
2130 if (unsupported_caps & MCG_LMCE_P) {
2131 error_report("kvm: LMCE not supported");
2132 return -ENOTSUP;
2133 }
2134 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2135 unsupported_caps);
2136 }
2137
2138 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2139 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2140 if (ret < 0) {
2141 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2142 return ret;
2143 }
2144 }
2145
2146 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2147
2148 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2149 if (c) {
2150 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2151 !!(c->ecx & CPUID_EXT_SMX);
2152 }
2153
2154 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2155 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2156 has_msr_feature_control = true;
2157 }
2158
2159 if (env->mcg_cap & MCG_LMCE_P) {
2160 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2161 }
2162
2163 if (!env->user_tsc_khz) {
2164 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2165 invtsc_mig_blocker == NULL) {
2166 error_setg(&invtsc_mig_blocker,
2167 "State blocked by non-migratable CPU device"
2168 " (invtsc flag)");
2169 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2170 if (r < 0) {
2171 error_report_err(local_err);
2172 return r;
2173 }
2174 }
2175 }
2176
2177 if (cpu->vmware_cpuid_freq
2178 /* Guests depend on 0x40000000 to detect this feature, so only expose
2179 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2180 && cpu->expose_kvm
2181 && kvm_base == KVM_CPUID_SIGNATURE
2182 /* TSC clock must be stable and known for this feature. */
2183 && tsc_is_stable_and_known(env)) {
2184
2185 c = &cpuid_data.entries[cpuid_i++];
2186 c->function = KVM_CPUID_SIGNATURE | 0x10;
2187 c->eax = env->tsc_khz;
2188 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2189 c->ecx = c->edx = 0;
2190
2191 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2192 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2193 }
2194
2195 cpuid_data.cpuid.nent = cpuid_i;
2196
2197 cpuid_data.cpuid.padding = 0;
2198 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2199 if (r) {
2200 goto fail;
2201 }
2202 kvm_init_xsave(env);
2203
2204 max_nested_state_len = kvm_max_nested_state_length();
2205 if (max_nested_state_len > 0) {
2206 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2207
2208 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2209 env->nested_state = g_malloc0(max_nested_state_len);
2210 env->nested_state->size = max_nested_state_len;
2211
2212 kvm_init_nested_state(env);
2213 }
2214 }
2215
2216 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2217
2218 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2219 has_msr_tsc_aux = false;
2220 }
2221
2222 kvm_init_msrs(cpu);
2223
2224 return 0;
2225
2226 fail:
2227 migrate_del_blocker(&invtsc_mig_blocker);
2228
2229 return r;
2230 }
2231
2232 int kvm_arch_destroy_vcpu(CPUState *cs)
2233 {
2234 X86CPU *cpu = X86_CPU(cs);
2235 CPUX86State *env = &cpu->env;
2236
2237 g_free(env->xsave_buf);
2238
2239 g_free(cpu->kvm_msr_buf);
2240 cpu->kvm_msr_buf = NULL;
2241
2242 g_free(env->nested_state);
2243 env->nested_state = NULL;
2244
2245 qemu_del_vm_change_state_handler(cpu->vmsentry);
2246
2247 return 0;
2248 }
2249
2250 void kvm_arch_reset_vcpu(X86CPU *cpu)
2251 {
2252 CPUX86State *env = &cpu->env;
2253
2254 env->xcr0 = 1;
2255 if (kvm_irqchip_in_kernel()) {
2256 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2257 KVM_MP_STATE_UNINITIALIZED;
2258 } else {
2259 env->mp_state = KVM_MP_STATE_RUNNABLE;
2260 }
2261
2262 /* enabled by default */
2263 env->poll_control_msr = 1;
2264
2265 kvm_init_nested_state(env);
2266
2267 sev_es_set_reset_vector(CPU(cpu));
2268 }
2269
2270 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2271 {
2272 CPUX86State *env = &cpu->env;
2273 int i;
2274
2275 /*
2276 * Reset SynIC after all other devices have been reset to let them remove
2277 * their SINT routes first.
2278 */
2279 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2280 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2281 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2282 }
2283
2284 hyperv_x86_synic_reset(cpu);
2285 }
2286 }
2287
2288 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2289 {
2290 CPUX86State *env = &cpu->env;
2291
2292 /* APs get directly into wait-for-SIPI state. */
2293 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2294 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2295 }
2296 }
2297
2298 static int kvm_get_supported_feature_msrs(KVMState *s)
2299 {
2300 int ret = 0;
2301
2302 if (kvm_feature_msrs != NULL) {
2303 return 0;
2304 }
2305
2306 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2307 return 0;
2308 }
2309
2310 struct kvm_msr_list msr_list;
2311
2312 msr_list.nmsrs = 0;
2313 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2314 if (ret < 0 && ret != -E2BIG) {
2315 error_report("Fetch KVM feature MSR list failed: %s",
2316 strerror(-ret));
2317 return ret;
2318 }
2319
2320 assert(msr_list.nmsrs > 0);
2321 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2322 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2323
2324 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2325 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2326
2327 if (ret < 0) {
2328 error_report("Fetch KVM feature MSR list failed: %s",
2329 strerror(-ret));
2330 g_free(kvm_feature_msrs);
2331 kvm_feature_msrs = NULL;
2332 return ret;
2333 }
2334
2335 return 0;
2336 }
2337
2338 static int kvm_get_supported_msrs(KVMState *s)
2339 {
2340 int ret = 0;
2341 struct kvm_msr_list msr_list, *kvm_msr_list;
2342
2343 /*
2344 * Obtain MSR list from KVM. These are the MSRs that we must
2345 * save/restore.
2346 */
2347 msr_list.nmsrs = 0;
2348 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2349 if (ret < 0 && ret != -E2BIG) {
2350 return ret;
2351 }
2352 /*
2353 * Old kernel modules had a bug and could write beyond the provided
2354 * memory. Allocate at least a safe amount of 1K.
2355 */
2356 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2357 msr_list.nmsrs *
2358 sizeof(msr_list.indices[0])));
2359
2360 kvm_msr_list->nmsrs = msr_list.nmsrs;
2361 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2362 if (ret >= 0) {
2363 int i;
2364
2365 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2366 switch (kvm_msr_list->indices[i]) {
2367 case MSR_STAR:
2368 has_msr_star = true;
2369 break;
2370 case MSR_VM_HSAVE_PA:
2371 has_msr_hsave_pa = true;
2372 break;
2373 case MSR_TSC_AUX:
2374 has_msr_tsc_aux = true;
2375 break;
2376 case MSR_TSC_ADJUST:
2377 has_msr_tsc_adjust = true;
2378 break;
2379 case MSR_IA32_TSCDEADLINE:
2380 has_msr_tsc_deadline = true;
2381 break;
2382 case MSR_IA32_SMBASE:
2383 has_msr_smbase = true;
2384 break;
2385 case MSR_SMI_COUNT:
2386 has_msr_smi_count = true;
2387 break;
2388 case MSR_IA32_MISC_ENABLE:
2389 has_msr_misc_enable = true;
2390 break;
2391 case MSR_IA32_BNDCFGS:
2392 has_msr_bndcfgs = true;
2393 break;
2394 case MSR_IA32_XSS:
2395 has_msr_xss = true;
2396 break;
2397 case MSR_IA32_UMWAIT_CONTROL:
2398 has_msr_umwait = true;
2399 break;
2400 case HV_X64_MSR_CRASH_CTL:
2401 has_msr_hv_crash = true;
2402 break;
2403 case HV_X64_MSR_RESET:
2404 has_msr_hv_reset = true;
2405 break;
2406 case HV_X64_MSR_VP_INDEX:
2407 has_msr_hv_vpindex = true;
2408 break;
2409 case HV_X64_MSR_VP_RUNTIME:
2410 has_msr_hv_runtime = true;
2411 break;
2412 case HV_X64_MSR_SCONTROL:
2413 has_msr_hv_synic = true;
2414 break;
2415 case HV_X64_MSR_STIMER0_CONFIG:
2416 has_msr_hv_stimer = true;
2417 break;
2418 case HV_X64_MSR_TSC_FREQUENCY:
2419 has_msr_hv_frequencies = true;
2420 break;
2421 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2422 has_msr_hv_reenlightenment = true;
2423 break;
2424 case HV_X64_MSR_SYNDBG_OPTIONS:
2425 has_msr_hv_syndbg_options = true;
2426 break;
2427 case MSR_IA32_SPEC_CTRL:
2428 has_msr_spec_ctrl = true;
2429 break;
2430 case MSR_AMD64_TSC_RATIO:
2431 has_tsc_scale_msr = true;
2432 break;
2433 case MSR_IA32_TSX_CTRL:
2434 has_msr_tsx_ctrl = true;
2435 break;
2436 case MSR_VIRT_SSBD:
2437 has_msr_virt_ssbd = true;
2438 break;
2439 case MSR_IA32_ARCH_CAPABILITIES:
2440 has_msr_arch_capabs = true;
2441 break;
2442 case MSR_IA32_CORE_CAPABILITY:
2443 has_msr_core_capabs = true;
2444 break;
2445 case MSR_IA32_PERF_CAPABILITIES:
2446 has_msr_perf_capabs = true;
2447 break;
2448 case MSR_IA32_VMX_VMFUNC:
2449 has_msr_vmx_vmfunc = true;
2450 break;
2451 case MSR_IA32_UCODE_REV:
2452 has_msr_ucode_rev = true;
2453 break;
2454 case MSR_IA32_VMX_PROCBASED_CTLS2:
2455 has_msr_vmx_procbased_ctls2 = true;
2456 break;
2457 case MSR_IA32_PKRS:
2458 has_msr_pkrs = true;
2459 break;
2460 }
2461 }
2462 }
2463
2464 g_free(kvm_msr_list);
2465
2466 return ret;
2467 }
2468
2469 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu, uint32_t msr,
2470 uint64_t *val)
2471 {
2472 CPUState *cs = CPU(cpu);
2473
2474 *val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
2475 *val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
2476
2477 return true;
2478 }
2479
2480 static Notifier smram_machine_done;
2481 static KVMMemoryListener smram_listener;
2482 static AddressSpace smram_address_space;
2483 static MemoryRegion smram_as_root;
2484 static MemoryRegion smram_as_mem;
2485
2486 static void register_smram_listener(Notifier *n, void *unused)
2487 {
2488 MemoryRegion *smram =
2489 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2490
2491 /* Outer container... */
2492 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2493 memory_region_set_enabled(&smram_as_root, true);
2494
2495 /* ... with two regions inside: normal system memory with low
2496 * priority, and...
2497 */
2498 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2499 get_system_memory(), 0, ~0ull);
2500 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2501 memory_region_set_enabled(&smram_as_mem, true);
2502
2503 if (smram) {
2504 /* ... SMRAM with higher priority */
2505 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2506 memory_region_set_enabled(smram, true);
2507 }
2508
2509 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2510 kvm_memory_listener_register(kvm_state, &smram_listener,
2511 &smram_address_space, 1, "kvm-smram");
2512 }
2513
2514 int kvm_arch_get_default_type(MachineState *ms)
2515 {
2516 return 0;
2517 }
2518
2519 int kvm_arch_init(MachineState *ms, KVMState *s)
2520 {
2521 uint64_t identity_base = 0xfffbc000;
2522 uint64_t shadow_mem;
2523 int ret;
2524 struct utsname utsname;
2525 Error *local_err = NULL;
2526
2527 /*
2528 * Initialize SEV context, if required
2529 *
2530 * If no memory encryption is requested (ms->cgs == NULL) this is
2531 * a no-op.
2532 *
2533 * It's also a no-op if a non-SEV confidential guest support
2534 * mechanism is selected. SEV is the only mechanism available to
2535 * select on x86 at present, so this doesn't arise, but if new
2536 * mechanisms are supported in future (e.g. TDX), they'll need
2537 * their own initialization either here or elsewhere.
2538 */
2539 ret = sev_kvm_init(ms->cgs, &local_err);
2540 if (ret < 0) {
2541 error_report_err(local_err);
2542 return ret;
2543 }
2544
2545 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2546 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2547 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
2548
2549 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2550
2551 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2552 if (has_exception_payload) {
2553 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2554 if (ret < 0) {
2555 error_report("kvm: Failed to enable exception payload cap: %s",
2556 strerror(-ret));
2557 return ret;
2558 }
2559 }
2560
2561 has_triple_fault_event = kvm_check_extension(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT);
2562 if (has_triple_fault_event) {
2563 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
2564 if (ret < 0) {
2565 error_report("kvm: Failed to enable triple fault event cap: %s",
2566 strerror(-ret));
2567 return ret;
2568 }
2569 }
2570
2571 if (s->xen_version) {
2572 #ifdef CONFIG_XEN_EMU
2573 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
2574 error_report("kvm: Xen support only available in PC machine");
2575 return -ENOTSUP;
2576 }
2577 /* hyperv_enabled() doesn't work yet. */
2578 uint32_t msr = XEN_HYPERCALL_MSR;
2579 ret = kvm_xen_init(s, msr);
2580 if (ret < 0) {
2581 return ret;
2582 }
2583 #else
2584 error_report("kvm: Xen support not enabled in qemu");
2585 return -ENOTSUP;
2586 #endif
2587 }
2588
2589 ret = kvm_get_supported_msrs(s);
2590 if (ret < 0) {
2591 return ret;
2592 }
2593
2594 kvm_get_supported_feature_msrs(s);
2595
2596 uname(&utsname);
2597 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2598
2599 /*
2600 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2601 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2602 * Since these must be part of guest physical memory, we need to allocate
2603 * them, both by setting their start addresses in the kernel and by
2604 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
2605 * so this value allows up to 16M BIOSes.
2606 */
2607 identity_base = 0xfeffc000;
2608 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2609 if (ret < 0) {
2610 return ret;
2611 }
2612
2613 /* Set TSS base one page after EPT identity map. */
2614 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2615 if (ret < 0) {
2616 return ret;
2617 }
2618
2619 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2620 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2621 if (ret < 0) {
2622 fprintf(stderr, "e820_add_entry() table is full\n");
2623 return ret;
2624 }
2625
2626 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
2627 if (shadow_mem != -1) {
2628 shadow_mem /= 4096;
2629 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2630 if (ret < 0) {
2631 return ret;
2632 }
2633 }
2634
2635 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2636 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
2637 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
2638 smram_machine_done.notify = register_smram_listener;
2639 qemu_add_machine_init_done_notifier(&smram_machine_done);
2640 }
2641
2642 if (enable_cpu_pm) {
2643 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2644 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2645 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2646 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2647 #endif
2648 if (disable_exits) {
2649 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2650 KVM_X86_DISABLE_EXITS_HLT |
2651 KVM_X86_DISABLE_EXITS_PAUSE |
2652 KVM_X86_DISABLE_EXITS_CSTATE);
2653 }
2654
2655 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2656 disable_exits);
2657 if (ret < 0) {
2658 error_report("kvm: guest stopping CPU not supported: %s",
2659 strerror(-ret));
2660 }
2661 }
2662
2663 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2664 X86MachineState *x86ms = X86_MACHINE(ms);
2665
2666 if (x86ms->bus_lock_ratelimit > 0) {
2667 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2668 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2669 error_report("kvm: bus lock detection unsupported");
2670 return -ENOTSUP;
2671 }
2672 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2673 KVM_BUS_LOCK_DETECTION_EXIT);
2674 if (ret < 0) {
2675 error_report("kvm: Failed to enable bus lock detection cap: %s",
2676 strerror(-ret));
2677 return ret;
2678 }
2679 ratelimit_init(&bus_lock_ratelimit_ctrl);
2680 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2681 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2682 }
2683 }
2684
2685 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE &&
2686 kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
2687 uint64_t notify_window_flags =
2688 ((uint64_t)s->notify_window << 32) |
2689 KVM_X86_NOTIFY_VMEXIT_ENABLED |
2690 KVM_X86_NOTIFY_VMEXIT_USER;
2691 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
2692 notify_window_flags);
2693 if (ret < 0) {
2694 error_report("kvm: Failed to enable notify vmexit cap: %s",
2695 strerror(-ret));
2696 return ret;
2697 }
2698 }
2699 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
2700 bool r;
2701
2702 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
2703 KVM_MSR_EXIT_REASON_FILTER);
2704 if (ret) {
2705 error_report("Could not enable user space MSRs: %s",
2706 strerror(-ret));
2707 exit(1);
2708 }
2709
2710 r = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
2711 kvm_rdmsr_core_thread_count, NULL);
2712 if (!r) {
2713 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
2714 strerror(-ret));
2715 exit(1);
2716 }
2717 }
2718
2719 return 0;
2720 }
2721
2722 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2723 {
2724 lhs->selector = rhs->selector;
2725 lhs->base = rhs->base;
2726 lhs->limit = rhs->limit;
2727 lhs->type = 3;
2728 lhs->present = 1;
2729 lhs->dpl = 3;
2730 lhs->db = 0;
2731 lhs->s = 1;
2732 lhs->l = 0;
2733 lhs->g = 0;
2734 lhs->avl = 0;
2735 lhs->unusable = 0;
2736 }
2737
2738 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2739 {
2740 unsigned flags = rhs->flags;
2741 lhs->selector = rhs->selector;
2742 lhs->base = rhs->base;
2743 lhs->limit = rhs->limit;
2744 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2745 lhs->present = (flags & DESC_P_MASK) != 0;
2746 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2747 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2748 lhs->s = (flags & DESC_S_MASK) != 0;
2749 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2750 lhs->g = (flags & DESC_G_MASK) != 0;
2751 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2752 lhs->unusable = !lhs->present;
2753 lhs->padding = 0;
2754 }
2755
2756 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2757 {
2758 lhs->selector = rhs->selector;
2759 lhs->base = rhs->base;
2760 lhs->limit = rhs->limit;
2761 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2762 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2763 (rhs->dpl << DESC_DPL_SHIFT) |
2764 (rhs->db << DESC_B_SHIFT) |
2765 (rhs->s * DESC_S_MASK) |
2766 (rhs->l << DESC_L_SHIFT) |
2767 (rhs->g * DESC_G_MASK) |
2768 (rhs->avl * DESC_AVL_MASK);
2769 }
2770
2771 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2772 {
2773 if (set) {
2774 *kvm_reg = *qemu_reg;
2775 } else {
2776 *qemu_reg = *kvm_reg;
2777 }
2778 }
2779
2780 static int kvm_getput_regs(X86CPU *cpu, int set)
2781 {
2782 CPUX86State *env = &cpu->env;
2783 struct kvm_regs regs;
2784 int ret = 0;
2785
2786 if (!set) {
2787 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2788 if (ret < 0) {
2789 return ret;
2790 }
2791 }
2792
2793 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2794 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2795 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2796 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2797 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2798 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2799 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2800 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2801 #ifdef TARGET_X86_64
2802 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2803 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2804 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2805 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2806 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2807 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2808 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2809 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2810 #endif
2811
2812 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2813 kvm_getput_reg(&regs.rip, &env->eip, set);
2814
2815 if (set) {
2816 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2817 }
2818
2819 return ret;
2820 }
2821
2822 static int kvm_put_xsave(X86CPU *cpu)
2823 {
2824 CPUX86State *env = &cpu->env;
2825 void *xsave = env->xsave_buf;
2826
2827 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
2828
2829 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2830 }
2831
2832 static int kvm_put_xcrs(X86CPU *cpu)
2833 {
2834 CPUX86State *env = &cpu->env;
2835 struct kvm_xcrs xcrs = {};
2836
2837 if (!has_xcrs) {
2838 return 0;
2839 }
2840
2841 xcrs.nr_xcrs = 1;
2842 xcrs.flags = 0;
2843 xcrs.xcrs[0].xcr = 0;
2844 xcrs.xcrs[0].value = env->xcr0;
2845 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2846 }
2847
2848 static int kvm_put_sregs(X86CPU *cpu)
2849 {
2850 CPUX86State *env = &cpu->env;
2851 struct kvm_sregs sregs;
2852
2853 /*
2854 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
2855 * always followed by KVM_SET_VCPU_EVENTS.
2856 */
2857 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2858
2859 if ((env->eflags & VM_MASK)) {
2860 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2861 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2862 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2863 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2864 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2865 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2866 } else {
2867 set_seg(&sregs.cs, &env->segs[R_CS]);
2868 set_seg(&sregs.ds, &env->segs[R_DS]);
2869 set_seg(&sregs.es, &env->segs[R_ES]);
2870 set_seg(&sregs.fs, &env->segs[R_FS]);
2871 set_seg(&sregs.gs, &env->segs[R_GS]);
2872 set_seg(&sregs.ss, &env->segs[R_SS]);
2873 }
2874
2875 set_seg(&sregs.tr, &env->tr);
2876 set_seg(&sregs.ldt, &env->ldt);
2877
2878 sregs.idt.limit = env->idt.limit;
2879 sregs.idt.base = env->idt.base;
2880 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2881 sregs.gdt.limit = env->gdt.limit;
2882 sregs.gdt.base = env->gdt.base;
2883 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2884
2885 sregs.cr0 = env->cr[0];
2886 sregs.cr2 = env->cr[2];
2887 sregs.cr3 = env->cr[3];
2888 sregs.cr4 = env->cr[4];
2889
2890 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2891 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2892
2893 sregs.efer = env->efer;
2894
2895 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2896 }
2897
2898 static int kvm_put_sregs2(X86CPU *cpu)
2899 {
2900 CPUX86State *env = &cpu->env;
2901 struct kvm_sregs2 sregs;
2902 int i;
2903
2904 sregs.flags = 0;
2905
2906 if ((env->eflags & VM_MASK)) {
2907 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2908 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2909 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2910 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2911 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2912 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2913 } else {
2914 set_seg(&sregs.cs, &env->segs[R_CS]);
2915 set_seg(&sregs.ds, &env->segs[R_DS]);
2916 set_seg(&sregs.es, &env->segs[R_ES]);
2917 set_seg(&sregs.fs, &env->segs[R_FS]);
2918 set_seg(&sregs.gs, &env->segs[R_GS]);
2919 set_seg(&sregs.ss, &env->segs[R_SS]);
2920 }
2921
2922 set_seg(&sregs.tr, &env->tr);
2923 set_seg(&sregs.ldt, &env->ldt);
2924
2925 sregs.idt.limit = env->idt.limit;
2926 sregs.idt.base = env->idt.base;
2927 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2928 sregs.gdt.limit = env->gdt.limit;
2929 sregs.gdt.base = env->gdt.base;
2930 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2931
2932 sregs.cr0 = env->cr[0];
2933 sregs.cr2 = env->cr[2];
2934 sregs.cr3 = env->cr[3];
2935 sregs.cr4 = env->cr[4];
2936
2937 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2938 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2939
2940 sregs.efer = env->efer;
2941
2942 if (env->pdptrs_valid) {
2943 for (i = 0; i < 4; i++) {
2944 sregs.pdptrs[i] = env->pdptrs[i];
2945 }
2946 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
2947 }
2948
2949 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
2950 }
2951
2952
2953 static void kvm_msr_buf_reset(X86CPU *cpu)
2954 {
2955 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2956 }
2957
2958 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2959 {
2960 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2961 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2962 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2963
2964 assert((void *)(entry + 1) <= limit);
2965
2966 entry->index = index;
2967 entry->reserved = 0;
2968 entry->data = value;
2969 msrs->nmsrs++;
2970 }
2971
2972 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2973 {
2974 kvm_msr_buf_reset(cpu);
2975 kvm_msr_entry_add(cpu, index, value);
2976
2977 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2978 }
2979
2980 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
2981 {
2982 int ret;
2983 struct {
2984 struct kvm_msrs info;
2985 struct kvm_msr_entry entries[1];
2986 } msr_data = {
2987 .info.nmsrs = 1,
2988 .entries[0].index = index,
2989 };
2990
2991 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2992 if (ret < 0) {
2993 return ret;
2994 }
2995 assert(ret == 1);
2996 *value = msr_data.entries[0].data;
2997 return ret;
2998 }
2999 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3000 {
3001 int ret;
3002
3003 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3004 assert(ret == 1);
3005 }
3006
3007 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3008 {
3009 CPUX86State *env = &cpu->env;
3010 int ret;
3011
3012 if (!has_msr_tsc_deadline) {
3013 return 0;
3014 }
3015
3016 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3017 if (ret < 0) {
3018 return ret;
3019 }
3020
3021 assert(ret == 1);
3022 return 0;
3023 }
3024
3025 /*
3026 * Provide a separate write service for the feature control MSR in order to
3027 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3028 * before writing any other state because forcibly leaving nested mode
3029 * invalidates the VCPU state.
3030 */
3031 static int kvm_put_msr_feature_control(X86CPU *cpu)
3032 {
3033 int ret;
3034
3035 if (!has_msr_feature_control) {
3036 return 0;
3037 }
3038
3039 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3040 cpu->env.msr_ia32_feature_control);
3041 if (ret < 0) {
3042 return ret;
3043 }
3044
3045 assert(ret == 1);
3046 return 0;
3047 }
3048
3049 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3050 {
3051 uint32_t default1, can_be_one, can_be_zero;
3052 uint32_t must_be_one;
3053
3054 switch (index) {
3055 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3056 default1 = 0x00000016;
3057 break;
3058 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3059 default1 = 0x0401e172;
3060 break;
3061 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3062 default1 = 0x000011ff;
3063 break;
3064 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3065 default1 = 0x00036dff;
3066 break;
3067 case MSR_IA32_VMX_PROCBASED_CTLS2:
3068 default1 = 0;
3069 break;
3070 default:
3071 abort();
3072 }
3073
3074 /* If a feature bit is set, the control can be either set or clear.
3075 * Otherwise the value is limited to either 0 or 1 by default1.
3076 */
3077 can_be_one = features | default1;
3078 can_be_zero = features | ~default1;
3079 must_be_one = ~can_be_zero;
3080
3081 /*
3082 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3083 * Bit 32:63 -> 1 if the control bit can be one.
3084 */
3085 return must_be_one | (((uint64_t)can_be_one) << 32);
3086 }
3087
3088 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3089 {
3090 uint64_t kvm_vmx_basic =
3091 kvm_arch_get_supported_msr_feature(kvm_state,
3092 MSR_IA32_VMX_BASIC);
3093
3094 if (!kvm_vmx_basic) {
3095 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3096 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3097 */
3098 return;
3099 }
3100
3101 uint64_t kvm_vmx_misc =
3102 kvm_arch_get_supported_msr_feature(kvm_state,
3103 MSR_IA32_VMX_MISC);
3104 uint64_t kvm_vmx_ept_vpid =
3105 kvm_arch_get_supported_msr_feature(kvm_state,
3106 MSR_IA32_VMX_EPT_VPID_CAP);
3107
3108 /*
3109 * If the guest is 64-bit, a value of 1 is allowed for the host address
3110 * space size vmexit control.
3111 */
3112 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3113 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3114
3115 /*
3116 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3117 * not change them for backwards compatibility.
3118 */
3119 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3120 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3121 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3122 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3123
3124 /*
3125 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3126 * change in the future but are always zero for now, clear them to be
3127 * future proof. Bits 32-63 in theory could change, though KVM does
3128 * not support dual-monitor treatment and probably never will; mask
3129 * them out as well.
3130 */
3131 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3132 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3133 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3134
3135 /*
3136 * EPT memory types should not change either, so we do not bother
3137 * adding features for them.
3138 */
3139 uint64_t fixed_vmx_ept_mask =
3140 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3141 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3142 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3143
3144 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3145 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3146 f[FEAT_VMX_PROCBASED_CTLS]));
3147 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3148 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3149 f[FEAT_VMX_PINBASED_CTLS]));
3150 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3151 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3152 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3153 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3154 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3155 f[FEAT_VMX_ENTRY_CTLS]));
3156 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3157 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3158 f[FEAT_VMX_SECONDARY_CTLS]));
3159 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3160 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3161 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3162 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3163 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3164 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3165 if (has_msr_vmx_vmfunc) {
3166 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3167 }
3168
3169 /*
3170 * Just to be safe, write these with constant values. The CRn_FIXED1
3171 * MSRs are generated by KVM based on the vCPU's CPUID.
3172 */
3173 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3174 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3175 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3176 CR4_VMXE_MASK);
3177
3178 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3179 /* TSC multiplier (0x2032). */
3180 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3181 } else {
3182 /* Preemption timer (0x482E). */
3183 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3184 }
3185 }
3186
3187 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3188 {
3189 uint64_t kvm_perf_cap =
3190 kvm_arch_get_supported_msr_feature(kvm_state,
3191 MSR_IA32_PERF_CAPABILITIES);
3192
3193 if (kvm_perf_cap) {
3194 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3195 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3196 }
3197 }
3198
3199 static int kvm_buf_set_msrs(X86CPU *cpu)
3200 {
3201 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3202 if (ret < 0) {
3203 return ret;
3204 }
3205
3206 if (ret < cpu->kvm_msr_buf->nmsrs) {
3207 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3208 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3209 (uint32_t)e->index, (uint64_t)e->data);
3210 }
3211
3212 assert(ret == cpu->kvm_msr_buf->nmsrs);
3213 return 0;
3214 }
3215
3216 static void kvm_init_msrs(X86CPU *cpu)
3217 {
3218 CPUX86State *env = &cpu->env;
3219
3220 kvm_msr_buf_reset(cpu);
3221 if (has_msr_arch_capabs) {
3222 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3223 env->features[FEAT_ARCH_CAPABILITIES]);
3224 }
3225
3226 if (has_msr_core_capabs) {
3227 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3228 env->features[FEAT_CORE_CAPABILITY]);
3229 }
3230
3231 if (has_msr_perf_capabs && cpu->enable_pmu) {
3232 kvm_msr_entry_add_perf(cpu, env->features);
3233 }
3234
3235 if (has_msr_ucode_rev) {
3236 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3237 }
3238
3239 /*
3240 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3241 * all kernels with MSR features should have them.
3242 */
3243 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3244 kvm_msr_entry_add_vmx(cpu, env->features);
3245 }
3246
3247 assert(kvm_buf_set_msrs(cpu) == 0);
3248 }
3249
3250 static int kvm_put_msrs(X86CPU *cpu, int level)
3251 {
3252 CPUX86State *env = &cpu->env;
3253 int i;
3254
3255 kvm_msr_buf_reset(cpu);
3256
3257 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3258 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3259 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3260 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3261 if (has_msr_star) {
3262 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3263 }
3264 if (has_msr_hsave_pa) {
3265 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3266 }
3267 if (has_msr_tsc_aux) {
3268 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3269 }
3270 if (has_msr_tsc_adjust) {
3271 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3272 }
3273 if (has_msr_misc_enable) {
3274 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3275 env->msr_ia32_misc_enable);
3276 }
3277 if (has_msr_smbase) {
3278 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3279 }
3280 if (has_msr_smi_count) {
3281 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3282 }
3283 if (has_msr_pkrs) {
3284 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3285 }
3286 if (has_msr_bndcfgs) {
3287 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3288 }
3289 if (has_msr_xss) {
3290 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3291 }
3292 if (has_msr_umwait) {
3293 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3294 }
3295 if (has_msr_spec_ctrl) {
3296 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3297 }
3298 if (has_tsc_scale_msr) {
3299 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3300 }
3301
3302 if (has_msr_tsx_ctrl) {
3303 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3304 }
3305 if (has_msr_virt_ssbd) {
3306 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3307 }
3308
3309 #ifdef TARGET_X86_64
3310 if (lm_capable_kernel) {
3311 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3312 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3313 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3314 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3315 }
3316 #endif
3317
3318 /*
3319 * The following MSRs have side effects on the guest or are too heavy
3320 * for normal writeback. Limit them to reset or full state updates.
3321 */
3322 if (level >= KVM_PUT_RESET_STATE) {
3323 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3324 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3325 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
3326 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3327 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3328 }
3329 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3330 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
3331 }
3332 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3333 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
3334 }
3335 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3336 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
3337 }
3338
3339 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3340 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3341 }
3342
3343 if (has_architectural_pmu_version > 0) {
3344 if (has_architectural_pmu_version > 1) {
3345 /* Stop the counter. */
3346 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3347 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3348 }
3349
3350 /* Set the counter values. */
3351 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3352 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
3353 env->msr_fixed_counters[i]);
3354 }
3355 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3356 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
3357 env->msr_gp_counters[i]);
3358 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
3359 env->msr_gp_evtsel[i]);
3360 }
3361 if (has_architectural_pmu_version > 1) {
3362 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
3363 env->msr_global_status);
3364 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
3365 env->msr_global_ovf_ctrl);
3366
3367 /* Now start the PMU. */
3368 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
3369 env->msr_fixed_ctr_ctrl);
3370 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
3371 env->msr_global_ctrl);
3372 }
3373 }
3374 /*
3375 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
3376 * only sync them to KVM on the first cpu
3377 */
3378 if (current_cpu == first_cpu) {
3379 if (has_msr_hv_hypercall) {
3380 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
3381 env->msr_hv_guest_os_id);
3382 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
3383 env->msr_hv_hypercall);
3384 }
3385 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3386 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
3387 env->msr_hv_tsc);
3388 }
3389 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3390 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
3391 env->msr_hv_reenlightenment_control);
3392 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
3393 env->msr_hv_tsc_emulation_control);
3394 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
3395 env->msr_hv_tsc_emulation_status);
3396 }
3397 #ifdef CONFIG_SYNDBG
3398 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
3399 has_msr_hv_syndbg_options) {
3400 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
3401 hyperv_syndbg_query_options());
3402 }
3403 #endif
3404 }
3405 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3406 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
3407 env->msr_hv_vapic);
3408 }
3409 if (has_msr_hv_crash) {
3410 int j;
3411
3412 for (j = 0; j < HV_CRASH_PARAMS; j++)
3413 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
3414 env->msr_hv_crash_params[j]);
3415
3416 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
3417 }
3418 if (has_msr_hv_runtime) {
3419 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
3420 }
3421 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
3422 && hv_vpindex_settable) {
3423 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
3424 hyperv_vp_index(CPU(cpu)));
3425 }
3426 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3427 int j;
3428
3429 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
3430
3431 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
3432 env->msr_hv_synic_control);
3433 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
3434 env->msr_hv_synic_evt_page);
3435 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
3436 env->msr_hv_synic_msg_page);
3437
3438 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
3439 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
3440 env->msr_hv_synic_sint[j]);
3441 }
3442 }
3443 if (has_msr_hv_stimer) {
3444 int j;
3445
3446 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
3447 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
3448 env->msr_hv_stimer_config[j]);
3449 }
3450
3451 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
3452 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
3453 env->msr_hv_stimer_count[j]);
3454 }
3455 }
3456 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3457 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3458
3459 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3460 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3461 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3462 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3463 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3464 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3465 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3466 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3467 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3468 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3469 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3470 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
3471 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3472 /* The CPU GPs if we write to a bit above the physical limit of
3473 * the host CPU (and KVM emulates that)
3474 */
3475 uint64_t mask = env->mtrr_var[i].mask;
3476 mask &= phys_mask;
3477
3478 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3479 env->mtrr_var[i].base);
3480 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
3481 }
3482 }
3483 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3484 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3485 0x14, 1, R_EAX) & 0x7;
3486
3487 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3488 env->msr_rtit_ctrl);
3489 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3490 env->msr_rtit_status);
3491 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3492 env->msr_rtit_output_base);
3493 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3494 env->msr_rtit_output_mask);
3495 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3496 env->msr_rtit_cr3_match);
3497 for (i = 0; i < addr_num; i++) {
3498 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3499 env->msr_rtit_addrs[i]);
3500 }
3501 }
3502
3503 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3504 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
3505 env->msr_ia32_sgxlepubkeyhash[0]);
3506 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
3507 env->msr_ia32_sgxlepubkeyhash[1]);
3508 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
3509 env->msr_ia32_sgxlepubkeyhash[2]);
3510 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
3511 env->msr_ia32_sgxlepubkeyhash[3]);
3512 }
3513
3514 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3515 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
3516 env->msr_xfd);
3517 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
3518 env->msr_xfd_err);
3519 }
3520
3521 if (kvm_enabled() && cpu->enable_pmu &&
3522 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3523 uint64_t depth;
3524 int ret;
3525
3526 /*
3527 * Only migrate Arch LBR states when the host Arch LBR depth
3528 * equals that of source guest's, this is to avoid mismatch
3529 * of guest/host config for the msr hence avoid unexpected
3530 * misbehavior.
3531 */
3532 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3533
3534 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
3535 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
3536 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
3537
3538 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3539 if (!env->lbr_records[i].from) {
3540 continue;
3541 }
3542 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
3543 env->lbr_records[i].from);
3544 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
3545 env->lbr_records[i].to);
3546 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
3547 env->lbr_records[i].info);
3548 }
3549 }
3550 }
3551
3552 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3553 * kvm_put_msr_feature_control. */
3554 }
3555
3556 if (env->mcg_cap) {
3557 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3558 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
3559 if (has_msr_mcg_ext_ctl) {
3560 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3561 }
3562 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3563 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
3564 }
3565 }
3566
3567 return kvm_buf_set_msrs(cpu);
3568 }
3569
3570
3571 static int kvm_get_xsave(X86CPU *cpu)
3572 {
3573 CPUX86State *env = &cpu->env;
3574 void *xsave = env->xsave_buf;
3575 int type, ret;
3576
3577 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
3578 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
3579 if (ret < 0) {
3580 return ret;
3581 }
3582 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
3583
3584 return 0;
3585 }
3586
3587 static int kvm_get_xcrs(X86CPU *cpu)
3588 {
3589 CPUX86State *env = &cpu->env;
3590 int i, ret;
3591 struct kvm_xcrs xcrs;
3592
3593 if (!has_xcrs) {
3594 return 0;
3595 }
3596
3597 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
3598 if (ret < 0) {
3599 return ret;
3600 }
3601
3602 for (i = 0; i < xcrs.nr_xcrs; i++) {
3603 /* Only support xcr0 now */
3604 if (xcrs.xcrs[i].xcr == 0) {
3605 env->xcr0 = xcrs.xcrs[i].value;
3606 break;
3607 }
3608 }
3609 return 0;
3610 }
3611
3612 static int kvm_get_sregs(X86CPU *cpu)
3613 {
3614 CPUX86State *env = &cpu->env;
3615 struct kvm_sregs sregs;
3616 int ret;
3617
3618 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3619 if (ret < 0) {
3620 return ret;
3621 }
3622
3623 /*
3624 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
3625 * always preceded by KVM_GET_VCPU_EVENTS.
3626 */
3627
3628 get_seg(&env->segs[R_CS], &sregs.cs);
3629 get_seg(&env->segs[R_DS], &sregs.ds);
3630 get_seg(&env->segs[R_ES], &sregs.es);
3631 get_seg(&env->segs[R_FS], &sregs.fs);
3632 get_seg(&env->segs[R_GS], &sregs.gs);
3633 get_seg(&env->segs[R_SS], &sregs.ss);
3634
3635 get_seg(&env->tr, &sregs.tr);
3636 get_seg(&env->ldt, &sregs.ldt);
3637
3638 env->idt.limit = sregs.idt.limit;
3639 env->idt.base = sregs.idt.base;
3640 env->gdt.limit = sregs.gdt.limit;
3641 env->gdt.base = sregs.gdt.base;
3642
3643 env->cr[0] = sregs.cr0;
3644 env->cr[2] = sregs.cr2;
3645 env->cr[3] = sregs.cr3;
3646 env->cr[4] = sregs.cr4;
3647
3648 env->efer = sregs.efer;
3649
3650 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3651 x86_update_hflags(env);
3652
3653 return 0;
3654 }
3655
3656 static int kvm_get_sregs2(X86CPU *cpu)
3657 {
3658 CPUX86State *env = &cpu->env;
3659 struct kvm_sregs2 sregs;
3660 int i, ret;
3661
3662 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
3663 if (ret < 0) {
3664 return ret;
3665 }
3666
3667 get_seg(&env->segs[R_CS], &sregs.cs);
3668 get_seg(&env->segs[R_DS], &sregs.ds);
3669 get_seg(&env->segs[R_ES], &sregs.es);
3670 get_seg(&env->segs[R_FS], &sregs.fs);
3671 get_seg(&env->segs[R_GS], &sregs.gs);
3672 get_seg(&env->segs[R_SS], &sregs.ss);
3673
3674 get_seg(&env->tr, &sregs.tr);
3675 get_seg(&env->ldt, &sregs.ldt);
3676
3677 env->idt.limit = sregs.idt.limit;
3678 env->idt.base = sregs.idt.base;
3679 env->gdt.limit = sregs.gdt.limit;
3680 env->gdt.base = sregs.gdt.base;
3681
3682 env->cr[0] = sregs.cr0;
3683 env->cr[2] = sregs.cr2;
3684 env->cr[3] = sregs.cr3;
3685 env->cr[4] = sregs.cr4;
3686
3687 env->efer = sregs.efer;
3688
3689 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
3690
3691 if (env->pdptrs_valid) {
3692 for (i = 0; i < 4; i++) {
3693 env->pdptrs[i] = sregs.pdptrs[i];
3694 }
3695 }
3696
3697 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3698 x86_update_hflags(env);
3699
3700 return 0;
3701 }
3702
3703 static int kvm_get_msrs(X86CPU *cpu)
3704 {
3705 CPUX86State *env = &cpu->env;
3706 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3707 int ret, i;
3708 uint64_t mtrr_top_bits;
3709
3710 kvm_msr_buf_reset(cpu);
3711
3712 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3713 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3714 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3715 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3716 if (has_msr_star) {
3717 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3718 }
3719 if (has_msr_hsave_pa) {
3720 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3721 }
3722 if (has_msr_tsc_aux) {
3723 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3724 }
3725 if (has_msr_tsc_adjust) {
3726 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3727 }
3728 if (has_msr_tsc_deadline) {
3729 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3730 }
3731 if (has_msr_misc_enable) {
3732 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3733 }
3734 if (has_msr_smbase) {
3735 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3736 }
3737 if (has_msr_smi_count) {
3738 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3739 }
3740 if (has_msr_feature_control) {
3741 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3742 }
3743 if (has_msr_pkrs) {
3744 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3745 }
3746 if (has_msr_bndcfgs) {
3747 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3748 }
3749 if (has_msr_xss) {
3750 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3751 }
3752 if (has_msr_umwait) {
3753 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3754 }
3755 if (has_msr_spec_ctrl) {
3756 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3757 }
3758 if (has_tsc_scale_msr) {
3759 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
3760 }
3761
3762 if (has_msr_tsx_ctrl) {
3763 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3764 }
3765 if (has_msr_virt_ssbd) {
3766 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3767 }
3768 if (!env->tsc_valid) {
3769 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3770 env->tsc_valid = !runstate_is_running();
3771 }
3772
3773 #ifdef TARGET_X86_64
3774 if (lm_capable_kernel) {
3775 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3776 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3777 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3778 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3779 }
3780 #endif
3781 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3782 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3783 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3784 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3785 }
3786 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3787 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3788 }
3789 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3790 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3791 }
3792 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3793 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3794 }
3795 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3796 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3797 }
3798 if (has_architectural_pmu_version > 0) {
3799 if (has_architectural_pmu_version > 1) {
3800 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3801 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3802 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3803 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3804 }
3805 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3806 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3807 }
3808 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3809 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3810 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3811 }
3812 }
3813
3814 if (env->mcg_cap) {
3815 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3816 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3817 if (has_msr_mcg_ext_ctl) {
3818 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3819 }
3820 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3821 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3822 }
3823 }
3824
3825 if (has_msr_hv_hypercall) {
3826 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3827 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3828 }
3829 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3830 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3831 }
3832 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3833 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3834 }
3835 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3836 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3837 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3838 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3839 }
3840 if (has_msr_hv_syndbg_options) {
3841 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
3842 }
3843 if (has_msr_hv_crash) {
3844 int j;
3845
3846 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3847 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3848 }
3849 }
3850 if (has_msr_hv_runtime) {
3851 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3852 }
3853 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3854 uint32_t msr;
3855
3856 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3857 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3858 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3859 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3860 kvm_msr_entry_add(cpu, msr, 0);
3861 }
3862 }
3863 if (has_msr_hv_stimer) {
3864 uint32_t msr;
3865
3866 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3867 msr++) {
3868 kvm_msr_entry_add(cpu, msr, 0);
3869 }
3870 }
3871 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3872 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3873 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3874 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3875 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3876 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3877 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3878 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3879 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3880 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3881 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3882 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3883 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3884 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3885 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3886 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3887 }
3888 }
3889
3890 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3891 int addr_num =
3892 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3893
3894 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3895 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3896 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3897 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3898 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3899 for (i = 0; i < addr_num; i++) {
3900 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3901 }
3902 }
3903
3904 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3905 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
3906 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
3907 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
3908 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
3909 }
3910
3911 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3912 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
3913 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
3914 }
3915
3916 if (kvm_enabled() && cpu->enable_pmu &&
3917 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3918 uint64_t depth;
3919
3920 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3921 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
3922 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
3923 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
3924
3925 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3926 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
3927 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
3928 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
3929 }
3930 }
3931 }
3932
3933 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3934 if (ret < 0) {
3935 return ret;
3936 }
3937
3938 if (ret < cpu->kvm_msr_buf->nmsrs) {
3939 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3940 error_report("error: failed to get MSR 0x%" PRIx32,
3941 (uint32_t)e->index);
3942 }
3943
3944 assert(ret == cpu->kvm_msr_buf->nmsrs);
3945 /*
3946 * MTRR masks: Each mask consists of 5 parts
3947 * a 10..0: must be zero
3948 * b 11 : valid bit
3949 * c n-1.12: actual mask bits
3950 * d 51..n: reserved must be zero
3951 * e 63.52: reserved must be zero
3952 *
3953 * 'n' is the number of physical bits supported by the CPU and is
3954 * apparently always <= 52. We know our 'n' but don't know what
3955 * the destinations 'n' is; it might be smaller, in which case
3956 * it masks (c) on loading. It might be larger, in which case
3957 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3958 * we're migrating to.
3959 */
3960
3961 if (cpu->fill_mtrr_mask) {
3962 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3963 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3964 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3965 } else {
3966 mtrr_top_bits = 0;
3967 }
3968
3969 for (i = 0; i < ret; i++) {
3970 uint32_t index = msrs[i].index;
3971 switch (index) {
3972 case MSR_IA32_SYSENTER_CS:
3973 env->sysenter_cs = msrs[i].data;
3974 break;
3975 case MSR_IA32_SYSENTER_ESP:
3976 env->sysenter_esp = msrs[i].data;
3977 break;
3978 case MSR_IA32_SYSENTER_EIP:
3979 env->sysenter_eip = msrs[i].data;
3980 break;
3981 case MSR_PAT:
3982 env->pat = msrs[i].data;
3983 break;
3984 case MSR_STAR:
3985 env->star = msrs[i].data;
3986 break;
3987 #ifdef TARGET_X86_64
3988 case MSR_CSTAR:
3989 env->cstar = msrs[i].data;
3990 break;
3991 case MSR_KERNELGSBASE:
3992 env->kernelgsbase = msrs[i].data;
3993 break;
3994 case MSR_FMASK:
3995 env->fmask = msrs[i].data;
3996 break;
3997 case MSR_LSTAR:
3998 env->lstar = msrs[i].data;
3999 break;
4000 #endif
4001 case MSR_IA32_TSC:
4002 env->tsc = msrs[i].data;
4003 break;
4004 case MSR_TSC_AUX:
4005 env->tsc_aux = msrs[i].data;
4006 break;
4007 case MSR_TSC_ADJUST:
4008 env->tsc_adjust = msrs[i].data;
4009 break;
4010 case MSR_IA32_TSCDEADLINE:
4011 env->tsc_deadline = msrs[i].data;
4012 break;
4013 case MSR_VM_HSAVE_PA:
4014 env->vm_hsave = msrs[i].data;
4015 break;
4016 case MSR_KVM_SYSTEM_TIME:
4017 env->system_time_msr = msrs[i].data;
4018 break;
4019 case MSR_KVM_WALL_CLOCK:
4020 env->wall_clock_msr = msrs[i].data;
4021 break;
4022 case MSR_MCG_STATUS:
4023 env->mcg_status = msrs[i].data;
4024 break;
4025 case MSR_MCG_CTL:
4026 env->mcg_ctl = msrs[i].data;
4027 break;
4028 case MSR_MCG_EXT_CTL:
4029 env->mcg_ext_ctl = msrs[i].data;
4030 break;
4031 case MSR_IA32_MISC_ENABLE:
4032 env->msr_ia32_misc_enable = msrs[i].data;
4033 break;
4034 case MSR_IA32_SMBASE:
4035 env->smbase = msrs[i].data;
4036 break;
4037 case MSR_SMI_COUNT:
4038 env->msr_smi_count = msrs[i].data;
4039 break;
4040 case MSR_IA32_FEATURE_CONTROL:
4041 env->msr_ia32_feature_control = msrs[i].data;
4042 break;
4043 case MSR_IA32_BNDCFGS:
4044 env->msr_bndcfgs = msrs[i].data;
4045 break;
4046 case MSR_IA32_XSS:
4047 env->xss = msrs[i].data;
4048 break;
4049 case MSR_IA32_UMWAIT_CONTROL:
4050 env->umwait = msrs[i].data;
4051 break;
4052 case MSR_IA32_PKRS:
4053 env->pkrs = msrs[i].data;
4054 break;
4055 default:
4056 if (msrs[i].index >= MSR_MC0_CTL &&
4057 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4058 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4059 }
4060 break;
4061 case MSR_KVM_ASYNC_PF_EN:
4062 env->async_pf_en_msr = msrs[i].data;
4063 break;
4064 case MSR_KVM_ASYNC_PF_INT:
4065 env->async_pf_int_msr = msrs[i].data;
4066 break;
4067 case MSR_KVM_PV_EOI_EN:
4068 env->pv_eoi_en_msr = msrs[i].data;
4069 break;
4070 case MSR_KVM_STEAL_TIME:
4071 env->steal_time_msr = msrs[i].data;
4072 break;
4073 case MSR_KVM_POLL_CONTROL: {
4074 env->poll_control_msr = msrs[i].data;
4075 break;
4076 }
4077 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4078 env->msr_fixed_ctr_ctrl = msrs[i].data;
4079 break;
4080 case MSR_CORE_PERF_GLOBAL_CTRL:
4081 env->msr_global_ctrl = msrs[i].data;
4082 break;
4083 case MSR_CORE_PERF_GLOBAL_STATUS:
4084 env->msr_global_status = msrs[i].data;
4085 break;
4086 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4087 env->msr_global_ovf_ctrl = msrs[i].data;
4088 break;
4089 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4090 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4091 break;
4092 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4093 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4094 break;
4095 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4096 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4097 break;
4098 case HV_X64_MSR_HYPERCALL:
4099 env->msr_hv_hypercall = msrs[i].data;
4100 break;
4101 case HV_X64_MSR_GUEST_OS_ID:
4102 env->msr_hv_guest_os_id = msrs[i].data;
4103 break;
4104 case HV_X64_MSR_APIC_ASSIST_PAGE:
4105 env->msr_hv_vapic = msrs[i].data;
4106 break;
4107 case HV_X64_MSR_REFERENCE_TSC:
4108 env->msr_hv_tsc = msrs[i].data;
4109 break;
4110 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4111 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4112 break;
4113 case HV_X64_MSR_VP_RUNTIME:
4114 env->msr_hv_runtime = msrs[i].data;
4115 break;
4116 case HV_X64_MSR_SCONTROL:
4117 env->msr_hv_synic_control = msrs[i].data;
4118 break;
4119 case HV_X64_MSR_SIEFP:
4120 env->msr_hv_synic_evt_page = msrs[i].data;
4121 break;
4122 case HV_X64_MSR_SIMP:
4123 env->msr_hv_synic_msg_page = msrs[i].data;
4124 break;
4125 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4126 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4127 break;
4128 case HV_X64_MSR_STIMER0_CONFIG:
4129 case HV_X64_MSR_STIMER1_CONFIG:
4130 case HV_X64_MSR_STIMER2_CONFIG:
4131 case HV_X64_MSR_STIMER3_CONFIG:
4132 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4133 msrs[i].data;
4134 break;
4135 case HV_X64_MSR_STIMER0_COUNT:
4136 case HV_X64_MSR_STIMER1_COUNT:
4137 case HV_X64_MSR_STIMER2_COUNT:
4138 case HV_X64_MSR_STIMER3_COUNT:
4139 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4140 msrs[i].data;
4141 break;
4142 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4143 env->msr_hv_reenlightenment_control = msrs[i].data;
4144 break;
4145 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4146 env->msr_hv_tsc_emulation_control = msrs[i].data;
4147 break;
4148 case HV_X64_MSR_TSC_EMULATION_STATUS:
4149 env->msr_hv_tsc_emulation_status = msrs[i].data;
4150 break;
4151 case HV_X64_MSR_SYNDBG_OPTIONS:
4152 env->msr_hv_syndbg_options = msrs[i].data;
4153 break;
4154 case MSR_MTRRdefType:
4155 env->mtrr_deftype = msrs[i].data;
4156 break;
4157 case MSR_MTRRfix64K_00000:
4158 env->mtrr_fixed[0] = msrs[i].data;
4159 break;
4160 case MSR_MTRRfix16K_80000:
4161 env->mtrr_fixed[1] = msrs[i].data;
4162 break;
4163 case MSR_MTRRfix16K_A0000:
4164 env->mtrr_fixed[2] = msrs[i].data;
4165 break;
4166 case MSR_MTRRfix4K_C0000:
4167 env->mtrr_fixed[3] = msrs[i].data;
4168 break;
4169 case MSR_MTRRfix4K_C8000:
4170 env->mtrr_fixed[4] = msrs[i].data;
4171 break;
4172 case MSR_MTRRfix4K_D0000:
4173 env->mtrr_fixed[5] = msrs[i].data;
4174 break;
4175 case MSR_MTRRfix4K_D8000:
4176 env->mtrr_fixed[6] = msrs[i].data;
4177 break;
4178 case MSR_MTRRfix4K_E0000:
4179 env->mtrr_fixed[7] = msrs[i].data;
4180 break;
4181 case MSR_MTRRfix4K_E8000:
4182 env->mtrr_fixed[8] = msrs[i].data;
4183 break;
4184 case MSR_MTRRfix4K_F0000:
4185 env->mtrr_fixed[9] = msrs[i].data;
4186 break;
4187 case MSR_MTRRfix4K_F8000:
4188 env->mtrr_fixed[10] = msrs[i].data;
4189 break;
4190 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4191 if (index & 1) {
4192 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4193 mtrr_top_bits;
4194 } else {
4195 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4196 }
4197 break;
4198 case MSR_IA32_SPEC_CTRL:
4199 env->spec_ctrl = msrs[i].data;
4200 break;
4201 case MSR_AMD64_TSC_RATIO:
4202 env->amd_tsc_scale_msr = msrs[i].data;
4203 break;
4204 case MSR_IA32_TSX_CTRL:
4205 env->tsx_ctrl = msrs[i].data;
4206 break;
4207 case MSR_VIRT_SSBD:
4208 env->virt_ssbd = msrs[i].data;
4209 break;
4210 case MSR_IA32_RTIT_CTL:
4211 env->msr_rtit_ctrl = msrs[i].data;
4212 break;
4213 case MSR_IA32_RTIT_STATUS:
4214 env->msr_rtit_status = msrs[i].data;
4215 break;
4216 case MSR_IA32_RTIT_OUTPUT_BASE:
4217 env->msr_rtit_output_base = msrs[i].data;
4218 break;
4219 case MSR_IA32_RTIT_OUTPUT_MASK:
4220 env->msr_rtit_output_mask = msrs[i].data;
4221 break;
4222 case MSR_IA32_RTIT_CR3_MATCH:
4223 env->msr_rtit_cr3_match = msrs[i].data;
4224 break;
4225 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4226 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4227 break;
4228 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4229 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4230 msrs[i].data;
4231 break;
4232 case MSR_IA32_XFD:
4233 env->msr_xfd = msrs[i].data;
4234 break;
4235 case MSR_IA32_XFD_ERR:
4236 env->msr_xfd_err = msrs[i].data;
4237 break;
4238 case MSR_ARCH_LBR_CTL:
4239 env->msr_lbr_ctl = msrs[i].data;
4240 break;
4241 case MSR_ARCH_LBR_DEPTH:
4242 env->msr_lbr_depth = msrs[i].data;
4243 break;
4244 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4245 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4246 break;
4247 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4248 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4249 break;
4250 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4251 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4252 break;
4253 }
4254 }
4255
4256 return 0;
4257 }
4258
4259 static int kvm_put_mp_state(X86CPU *cpu)
4260 {
4261 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4262
4263 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4264 }
4265
4266 static int kvm_get_mp_state(X86CPU *cpu)
4267 {
4268 CPUState *cs = CPU(cpu);
4269 CPUX86State *env = &cpu->env;
4270 struct kvm_mp_state mp_state;
4271 int ret;
4272
4273 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
4274 if (ret < 0) {
4275 return ret;
4276 }
4277 env->mp_state = mp_state.mp_state;
4278 if (kvm_irqchip_in_kernel()) {
4279 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
4280 }
4281 return 0;
4282 }
4283
4284 static int kvm_get_apic(X86CPU *cpu)
4285 {
4286 DeviceState *apic = cpu->apic_state;
4287 struct kvm_lapic_state kapic;
4288 int ret;
4289
4290 if (apic && kvm_irqchip_in_kernel()) {
4291 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
4292 if (ret < 0) {
4293 return ret;
4294 }
4295
4296 kvm_get_apic_state(apic, &kapic);
4297 }
4298 return 0;
4299 }
4300
4301 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
4302 {
4303 CPUState *cs = CPU(cpu);
4304 CPUX86State *env = &cpu->env;
4305 struct kvm_vcpu_events events = {};
4306
4307 events.flags = 0;
4308
4309 if (has_exception_payload) {
4310 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4311 events.exception.pending = env->exception_pending;
4312 events.exception_has_payload = env->exception_has_payload;
4313 events.exception_payload = env->exception_payload;
4314 }
4315 events.exception.nr = env->exception_nr;
4316 events.exception.injected = env->exception_injected;
4317 events.exception.has_error_code = env->has_error_code;
4318 events.exception.error_code = env->error_code;
4319
4320 events.interrupt.injected = (env->interrupt_injected >= 0);
4321 events.interrupt.nr = env->interrupt_injected;
4322 events.interrupt.soft = env->soft_interrupt;
4323
4324 events.nmi.injected = env->nmi_injected;
4325 events.nmi.pending = env->nmi_pending;
4326 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
4327
4328 events.sipi_vector = env->sipi_vector;
4329
4330 if (has_msr_smbase) {
4331 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
4332 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
4333 if (kvm_irqchip_in_kernel()) {
4334 /* As soon as these are moved to the kernel, remove them
4335 * from cs->interrupt_request.
4336 */
4337 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
4338 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
4339 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
4340 } else {
4341 /* Keep these in cs->interrupt_request. */
4342 events.smi.pending = 0;
4343 events.smi.latched_init = 0;
4344 }
4345 /* Stop SMI delivery on old machine types to avoid a reboot
4346 * on an inward migration of an old VM.
4347 */
4348 if (!cpu->kvm_no_smi_migration) {
4349 events.flags |= KVM_VCPUEVENT_VALID_SMM;
4350 }
4351 }
4352
4353 if (level >= KVM_PUT_RESET_STATE) {
4354 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
4355 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
4356 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
4357 }
4358 }
4359
4360 if (has_triple_fault_event) {
4361 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
4362 events.triple_fault.pending = env->triple_fault_pending;
4363 }
4364
4365 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
4366 }
4367
4368 static int kvm_get_vcpu_events(X86CPU *cpu)
4369 {
4370 CPUX86State *env = &cpu->env;
4371 struct kvm_vcpu_events events;
4372 int ret;
4373
4374 memset(&events, 0, sizeof(events));
4375 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
4376 if (ret < 0) {
4377 return ret;
4378 }
4379
4380 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4381 env->exception_pending = events.exception.pending;
4382 env->exception_has_payload = events.exception_has_payload;
4383 env->exception_payload = events.exception_payload;
4384 } else {
4385 env->exception_pending = 0;
4386 env->exception_has_payload = false;
4387 }
4388 env->exception_injected = events.exception.injected;
4389 env->exception_nr =
4390 (env->exception_pending || env->exception_injected) ?
4391 events.exception.nr : -1;
4392 env->has_error_code = events.exception.has_error_code;
4393 env->error_code = events.exception.error_code;
4394
4395 env->interrupt_injected =
4396 events.interrupt.injected ? events.interrupt.nr : -1;
4397 env->soft_interrupt = events.interrupt.soft;
4398
4399 env->nmi_injected = events.nmi.injected;
4400 env->nmi_pending = events.nmi.pending;
4401 if (events.nmi.masked) {
4402 env->hflags2 |= HF2_NMI_MASK;
4403 } else {
4404 env->hflags2 &= ~HF2_NMI_MASK;
4405 }
4406
4407 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
4408 if (events.smi.smm) {
4409 env->hflags |= HF_SMM_MASK;
4410 } else {
4411 env->hflags &= ~HF_SMM_MASK;
4412 }
4413 if (events.smi.pending) {
4414 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4415 } else {
4416 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4417 }
4418 if (events.smi.smm_inside_nmi) {
4419 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
4420 } else {
4421 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
4422 }
4423 if (events.smi.latched_init) {
4424 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4425 } else {
4426 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4427 }
4428 }
4429
4430 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
4431 env->triple_fault_pending = events.triple_fault.pending;
4432 }
4433
4434 env->sipi_vector = events.sipi_vector;
4435
4436 return 0;
4437 }
4438
4439 static int kvm_put_debugregs(X86CPU *cpu)
4440 {
4441 CPUX86State *env = &cpu->env;
4442 struct kvm_debugregs dbgregs;
4443 int i;
4444
4445 memset(&dbgregs, 0, sizeof(dbgregs));
4446 for (i = 0; i < 4; i++) {
4447 dbgregs.db[i] = env->dr[i];
4448 }
4449 dbgregs.dr6 = env->dr[6];
4450 dbgregs.dr7 = env->dr[7];
4451 dbgregs.flags = 0;
4452
4453 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
4454 }
4455
4456 static int kvm_get_debugregs(X86CPU *cpu)
4457 {
4458 CPUX86State *env = &cpu->env;
4459 struct kvm_debugregs dbgregs;
4460 int i, ret;
4461
4462 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
4463 if (ret < 0) {
4464 return ret;
4465 }
4466 for (i = 0; i < 4; i++) {
4467 env->dr[i] = dbgregs.db[i];
4468 }
4469 env->dr[4] = env->dr[6] = dbgregs.dr6;
4470 env->dr[5] = env->dr[7] = dbgregs.dr7;
4471
4472 return 0;
4473 }
4474
4475 static int kvm_put_nested_state(X86CPU *cpu)
4476 {
4477 CPUX86State *env = &cpu->env;
4478 int max_nested_state_len = kvm_max_nested_state_length();
4479
4480 if (!env->nested_state) {
4481 return 0;
4482 }
4483
4484 /*
4485 * Copy flags that are affected by reset from env->hflags and env->hflags2.
4486 */
4487 if (env->hflags & HF_GUEST_MASK) {
4488 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
4489 } else {
4490 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
4491 }
4492
4493 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
4494 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
4495 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
4496 } else {
4497 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
4498 }
4499
4500 assert(env->nested_state->size <= max_nested_state_len);
4501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
4502 }
4503
4504 static int kvm_get_nested_state(X86CPU *cpu)
4505 {
4506 CPUX86State *env = &cpu->env;
4507 int max_nested_state_len = kvm_max_nested_state_length();
4508 int ret;
4509
4510 if (!env->nested_state) {
4511 return 0;
4512 }
4513
4514 /*
4515 * It is possible that migration restored a smaller size into
4516 * nested_state->hdr.size than what our kernel support.
4517 * We preserve migration origin nested_state->hdr.size for
4518 * call to KVM_SET_NESTED_STATE but wish that our next call
4519 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4520 */
4521 env->nested_state->size = max_nested_state_len;
4522
4523 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4524 if (ret < 0) {
4525 return ret;
4526 }
4527
4528 /*
4529 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4530 */
4531 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4532 env->hflags |= HF_GUEST_MASK;
4533 } else {
4534 env->hflags &= ~HF_GUEST_MASK;
4535 }
4536
4537 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4538 if (cpu_has_svm(env)) {
4539 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4540 env->hflags2 |= HF2_GIF_MASK;
4541 } else {
4542 env->hflags2 &= ~HF2_GIF_MASK;
4543 }
4544 }
4545
4546 return ret;
4547 }
4548
4549 int kvm_arch_put_registers(CPUState *cpu, int level)
4550 {
4551 X86CPU *x86_cpu = X86_CPU(cpu);
4552 int ret;
4553
4554 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
4555
4556 /*
4557 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
4558 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
4559 * precede kvm_put_nested_state() when 'real' nested state is set.
4560 */
4561 if (level >= KVM_PUT_RESET_STATE) {
4562 ret = kvm_put_msr_feature_control(x86_cpu);
4563 if (ret < 0) {
4564 return ret;
4565 }
4566 }
4567
4568 /* must be before kvm_put_nested_state so that EFER.SVME is set */
4569 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
4570 if (ret < 0) {
4571 return ret;
4572 }
4573
4574 if (level >= KVM_PUT_RESET_STATE) {
4575 ret = kvm_put_nested_state(x86_cpu);
4576 if (ret < 0) {
4577 return ret;
4578 }
4579 }
4580
4581 if (level == KVM_PUT_FULL_STATE) {
4582 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4583 * because TSC frequency mismatch shouldn't abort migration,
4584 * unless the user explicitly asked for a more strict TSC
4585 * setting (e.g. using an explicit "tsc-freq" option).
4586 */
4587 kvm_arch_set_tsc_khz(cpu);
4588 }
4589
4590 #ifdef CONFIG_XEN_EMU
4591 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
4592 ret = kvm_put_xen_state(cpu);
4593 if (ret < 0) {
4594 return ret;
4595 }
4596 }
4597 #endif
4598
4599 ret = kvm_getput_regs(x86_cpu, 1);
4600 if (ret < 0) {
4601 return ret;
4602 }
4603 ret = kvm_put_xsave(x86_cpu);
4604 if (ret < 0) {
4605 return ret;
4606 }
4607 ret = kvm_put_xcrs(x86_cpu);
4608 if (ret < 0) {
4609 return ret;
4610 }
4611 ret = kvm_put_msrs(x86_cpu, level);
4612 if (ret < 0) {
4613 return ret;
4614 }
4615 ret = kvm_put_vcpu_events(x86_cpu, level);
4616 if (ret < 0) {
4617 return ret;
4618 }
4619 if (level >= KVM_PUT_RESET_STATE) {
4620 ret = kvm_put_mp_state(x86_cpu);
4621 if (ret < 0) {
4622 return ret;
4623 }
4624 }
4625
4626 ret = kvm_put_tscdeadline_msr(x86_cpu);
4627 if (ret < 0) {
4628 return ret;
4629 }
4630 ret = kvm_put_debugregs(x86_cpu);
4631 if (ret < 0) {
4632 return ret;
4633 }
4634 return 0;
4635 }
4636
4637 int kvm_arch_get_registers(CPUState *cs)
4638 {
4639 X86CPU *cpu = X86_CPU(cs);
4640 int ret;
4641
4642 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
4643
4644 ret = kvm_get_vcpu_events(cpu);
4645 if (ret < 0) {
4646 goto out;
4647 }
4648 /*
4649 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4650 * KVM_GET_REGS and KVM_GET_SREGS.
4651 */
4652 ret = kvm_get_mp_state(cpu);
4653 if (ret < 0) {
4654 goto out;
4655 }
4656 ret = kvm_getput_regs(cpu, 0);
4657 if (ret < 0) {
4658 goto out;
4659 }
4660 ret = kvm_get_xsave(cpu);
4661 if (ret < 0) {
4662 goto out;
4663 }
4664 ret = kvm_get_xcrs(cpu);
4665 if (ret < 0) {
4666 goto out;
4667 }
4668 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
4669 if (ret < 0) {
4670 goto out;
4671 }
4672 ret = kvm_get_msrs(cpu);
4673 if (ret < 0) {
4674 goto out;
4675 }
4676 ret = kvm_get_apic(cpu);
4677 if (ret < 0) {
4678 goto out;
4679 }
4680 ret = kvm_get_debugregs(cpu);
4681 if (ret < 0) {
4682 goto out;
4683 }
4684 ret = kvm_get_nested_state(cpu);
4685 if (ret < 0) {
4686 goto out;
4687 }
4688 #ifdef CONFIG_XEN_EMU
4689 if (xen_mode == XEN_EMULATE) {
4690 ret = kvm_get_xen_state(cs);
4691 if (ret < 0) {
4692 goto out;
4693 }
4694 }
4695 #endif
4696 ret = 0;
4697 out:
4698 cpu_sync_bndcs_hflags(&cpu->env);
4699 return ret;
4700 }
4701
4702 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
4703 {
4704 X86CPU *x86_cpu = X86_CPU(cpu);
4705 CPUX86State *env = &x86_cpu->env;
4706 int ret;
4707
4708 /* Inject NMI */
4709 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4710 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4711 qemu_mutex_lock_iothread();
4712 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4713 qemu_mutex_unlock_iothread();
4714 DPRINTF("injected NMI\n");
4715 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4716 if (ret < 0) {
4717 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4718 strerror(-ret));
4719 }
4720 }
4721 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4722 qemu_mutex_lock_iothread();
4723 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4724 qemu_mutex_unlock_iothread();
4725 DPRINTF("injected SMI\n");
4726 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4727 if (ret < 0) {
4728 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4729 strerror(-ret));
4730 }
4731 }
4732 }
4733
4734 if (!kvm_pic_in_kernel()) {
4735 qemu_mutex_lock_iothread();
4736 }
4737
4738 /* Force the VCPU out of its inner loop to process any INIT requests
4739 * or (for userspace APIC, but it is cheap to combine the checks here)
4740 * pending TPR access reports.
4741 */
4742 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4743 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4744 !(env->hflags & HF_SMM_MASK)) {
4745 cpu->exit_request = 1;
4746 }
4747 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4748 cpu->exit_request = 1;
4749 }
4750 }
4751
4752 if (!kvm_pic_in_kernel()) {
4753 /* Try to inject an interrupt if the guest can accept it */
4754 if (run->ready_for_interrupt_injection &&
4755 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4756 (env->eflags & IF_MASK)) {
4757 int irq;
4758
4759 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4760 irq = cpu_get_pic_interrupt(env);
4761 if (irq >= 0) {
4762 struct kvm_interrupt intr;
4763
4764 intr.irq = irq;
4765 DPRINTF("injected interrupt %d\n", irq);
4766 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4767 if (ret < 0) {
4768 fprintf(stderr,
4769 "KVM: injection failed, interrupt lost (%s)\n",
4770 strerror(-ret));
4771 }
4772 }
4773 }
4774
4775 /* If we have an interrupt but the guest is not ready to receive an
4776 * interrupt, request an interrupt window exit. This will
4777 * cause a return to userspace as soon as the guest is ready to
4778 * receive interrupts. */
4779 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4780 run->request_interrupt_window = 1;
4781 } else {
4782 run->request_interrupt_window = 0;
4783 }
4784
4785 DPRINTF("setting tpr\n");
4786 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4787
4788 qemu_mutex_unlock_iothread();
4789 }
4790 }
4791
4792 static void kvm_rate_limit_on_bus_lock(void)
4793 {
4794 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4795
4796 if (delay_ns) {
4797 g_usleep(delay_ns / SCALE_US);
4798 }
4799 }
4800
4801 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4802 {
4803 X86CPU *x86_cpu = X86_CPU(cpu);
4804 CPUX86State *env = &x86_cpu->env;
4805
4806 if (run->flags & KVM_RUN_X86_SMM) {
4807 env->hflags |= HF_SMM_MASK;
4808 } else {
4809 env->hflags &= ~HF_SMM_MASK;
4810 }
4811 if (run->if_flag) {
4812 env->eflags |= IF_MASK;
4813 } else {
4814 env->eflags &= ~IF_MASK;
4815 }
4816 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4817 kvm_rate_limit_on_bus_lock();
4818 }
4819
4820 #ifdef CONFIG_XEN_EMU
4821 /*
4822 * If the callback is asserted as a GSI (or PCI INTx) then check if
4823 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
4824 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
4825 * EOI and only resample then, exactly how the VFIO eventfd pairs
4826 * are designed to work for level triggered interrupts.
4827 */
4828 if (x86_cpu->env.xen_callback_asserted) {
4829 kvm_xen_maybe_deassert_callback(cpu);
4830 }
4831 #endif
4832
4833 /* We need to protect the apic state against concurrent accesses from
4834 * different threads in case the userspace irqchip is used. */
4835 if (!kvm_irqchip_in_kernel()) {
4836 qemu_mutex_lock_iothread();
4837 }
4838 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4839 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4840 if (!kvm_irqchip_in_kernel()) {
4841 qemu_mutex_unlock_iothread();
4842 }
4843 return cpu_get_mem_attrs(env);
4844 }
4845
4846 int kvm_arch_process_async_events(CPUState *cs)
4847 {
4848 X86CPU *cpu = X86_CPU(cs);
4849 CPUX86State *env = &cpu->env;
4850
4851 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4852 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4853 assert(env->mcg_cap);
4854
4855 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4856
4857 kvm_cpu_synchronize_state(cs);
4858
4859 if (env->exception_nr == EXCP08_DBLE) {
4860 /* this means triple fault */
4861 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4862 cs->exit_request = 1;
4863 return 0;
4864 }
4865 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4866 env->has_error_code = 0;
4867
4868 cs->halted = 0;
4869 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4870 env->mp_state = KVM_MP_STATE_RUNNABLE;
4871 }
4872 }
4873
4874 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4875 !(env->hflags & HF_SMM_MASK)) {
4876 kvm_cpu_synchronize_state(cs);
4877 do_cpu_init(cpu);
4878 }
4879
4880 if (kvm_irqchip_in_kernel()) {
4881 return 0;
4882 }
4883
4884 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4885 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4886 apic_poll_irq(cpu->apic_state);
4887 }
4888 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4889 (env->eflags & IF_MASK)) ||
4890 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4891 cs->halted = 0;
4892 }
4893 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4894 kvm_cpu_synchronize_state(cs);
4895 do_cpu_sipi(cpu);
4896 }
4897 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4898 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4899 kvm_cpu_synchronize_state(cs);
4900 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4901 env->tpr_access_type);
4902 }
4903
4904 return cs->halted;
4905 }
4906
4907 static int kvm_handle_halt(X86CPU *cpu)
4908 {
4909 CPUState *cs = CPU(cpu);
4910 CPUX86State *env = &cpu->env;
4911
4912 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4913 (env->eflags & IF_MASK)) &&
4914 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4915 cs->halted = 1;
4916 return EXCP_HLT;
4917 }
4918
4919 return 0;
4920 }
4921
4922 static int kvm_handle_tpr_access(X86CPU *cpu)
4923 {
4924 CPUState *cs = CPU(cpu);
4925 struct kvm_run *run = cs->kvm_run;
4926
4927 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4928 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4929 : TPR_ACCESS_READ);
4930 return 1;
4931 }
4932
4933 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4934 {
4935 static const uint8_t int3 = 0xcc;
4936
4937 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4938 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4939 return -EINVAL;
4940 }
4941 return 0;
4942 }
4943
4944 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4945 {
4946 uint8_t int3;
4947
4948 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4949 return -EINVAL;
4950 }
4951 if (int3 != 0xcc) {
4952 return 0;
4953 }
4954 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4955 return -EINVAL;
4956 }
4957 return 0;
4958 }
4959
4960 static struct {
4961 target_ulong addr;
4962 int len;
4963 int type;
4964 } hw_breakpoint[4];
4965
4966 static int nb_hw_breakpoint;
4967
4968 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4969 {
4970 int n;
4971
4972 for (n = 0; n < nb_hw_breakpoint; n++) {
4973 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4974 (hw_breakpoint[n].len == len || len == -1)) {
4975 return n;
4976 }
4977 }
4978 return -1;
4979 }
4980
4981 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
4982 {
4983 switch (type) {
4984 case GDB_BREAKPOINT_HW:
4985 len = 1;
4986 break;
4987 case GDB_WATCHPOINT_WRITE:
4988 case GDB_WATCHPOINT_ACCESS:
4989 switch (len) {
4990 case 1:
4991 break;
4992 case 2:
4993 case 4:
4994 case 8:
4995 if (addr & (len - 1)) {
4996 return -EINVAL;
4997 }
4998 break;
4999 default:
5000 return -EINVAL;
5001 }
5002 break;
5003 default:
5004 return -ENOSYS;
5005 }
5006
5007 if (nb_hw_breakpoint == 4) {
5008 return -ENOBUFS;
5009 }
5010 if (find_hw_breakpoint(addr, len, type) >= 0) {
5011 return -EEXIST;
5012 }
5013 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5014 hw_breakpoint[nb_hw_breakpoint].len = len;
5015 hw_breakpoint[nb_hw_breakpoint].type = type;
5016 nb_hw_breakpoint++;
5017
5018 return 0;
5019 }
5020
5021 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5022 {
5023 int n;
5024
5025 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5026 if (n < 0) {
5027 return -ENOENT;
5028 }
5029 nb_hw_breakpoint--;
5030 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5031
5032 return 0;
5033 }
5034
5035 void kvm_arch_remove_all_hw_breakpoints(void)
5036 {
5037 nb_hw_breakpoint = 0;
5038 }
5039
5040 static CPUWatchpoint hw_watchpoint;
5041
5042 static int kvm_handle_debug(X86CPU *cpu,
5043 struct kvm_debug_exit_arch *arch_info)
5044 {
5045 CPUState *cs = CPU(cpu);
5046 CPUX86State *env = &cpu->env;
5047 int ret = 0;
5048 int n;
5049
5050 if (arch_info->exception == EXCP01_DB) {
5051 if (arch_info->dr6 & DR6_BS) {
5052 if (cs->singlestep_enabled) {
5053 ret = EXCP_DEBUG;
5054 }
5055 } else {
5056 for (n = 0; n < 4; n++) {
5057 if (arch_info->dr6 & (1 << n)) {
5058 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5059 case 0x0:
5060 ret = EXCP_DEBUG;
5061 break;
5062 case 0x1:
5063 ret = EXCP_DEBUG;
5064 cs->watchpoint_hit = &hw_watchpoint;
5065 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5066 hw_watchpoint.flags = BP_MEM_WRITE;
5067 break;
5068 case 0x3:
5069 ret = EXCP_DEBUG;
5070 cs->watchpoint_hit = &hw_watchpoint;
5071 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5072 hw_watchpoint.flags = BP_MEM_ACCESS;
5073 break;
5074 }
5075 }
5076 }
5077 }
5078 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5079 ret = EXCP_DEBUG;
5080 }
5081 if (ret == 0) {
5082 cpu_synchronize_state(cs);
5083 assert(env->exception_nr == -1);
5084
5085 /* pass to guest */
5086 kvm_queue_exception(env, arch_info->exception,
5087 arch_info->exception == EXCP01_DB,
5088 arch_info->dr6);
5089 env->has_error_code = 0;
5090 }
5091
5092 return ret;
5093 }
5094
5095 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5096 {
5097 const uint8_t type_code[] = {
5098 [GDB_BREAKPOINT_HW] = 0x0,
5099 [GDB_WATCHPOINT_WRITE] = 0x1,
5100 [GDB_WATCHPOINT_ACCESS] = 0x3
5101 };
5102 const uint8_t len_code[] = {
5103 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5104 };
5105 int n;
5106
5107 if (kvm_sw_breakpoints_active(cpu)) {
5108 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5109 }
5110 if (nb_hw_breakpoint > 0) {
5111 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5112 dbg->arch.debugreg[7] = 0x0600;
5113 for (n = 0; n < nb_hw_breakpoint; n++) {
5114 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5115 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5116 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5117 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5118 }
5119 }
5120 }
5121
5122 static bool kvm_install_msr_filters(KVMState *s)
5123 {
5124 uint64_t zero = 0;
5125 struct kvm_msr_filter filter = {
5126 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5127 };
5128 int r, i, j = 0;
5129
5130 for (i = 0; i < KVM_MSR_FILTER_MAX_RANGES; i++) {
5131 KVMMSRHandlers *handler = &msr_handlers[i];
5132 if (handler->msr) {
5133 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5134
5135 *range = (struct kvm_msr_filter_range) {
5136 .flags = 0,
5137 .nmsrs = 1,
5138 .base = handler->msr,
5139 .bitmap = (__u8 *)&zero,
5140 };
5141
5142 if (handler->rdmsr) {
5143 range->flags |= KVM_MSR_FILTER_READ;
5144 }
5145
5146 if (handler->wrmsr) {
5147 range->flags |= KVM_MSR_FILTER_WRITE;
5148 }
5149 }
5150 }
5151
5152 r = kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5153 if (r) {
5154 return false;
5155 }
5156
5157 return true;
5158 }
5159
5160 bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5161 QEMUWRMSRHandler *wrmsr)
5162 {
5163 int i;
5164
5165 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5166 if (!msr_handlers[i].msr) {
5167 msr_handlers[i] = (KVMMSRHandlers) {
5168 .msr = msr,
5169 .rdmsr = rdmsr,
5170 .wrmsr = wrmsr,
5171 };
5172
5173 if (!kvm_install_msr_filters(s)) {
5174 msr_handlers[i] = (KVMMSRHandlers) { };
5175 return false;
5176 }
5177
5178 return true;
5179 }
5180 }
5181
5182 return false;
5183 }
5184
5185 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5186 {
5187 int i;
5188 bool r;
5189
5190 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5191 KVMMSRHandlers *handler = &msr_handlers[i];
5192 if (run->msr.index == handler->msr) {
5193 if (handler->rdmsr) {
5194 r = handler->rdmsr(cpu, handler->msr,
5195 (uint64_t *)&run->msr.data);
5196 run->msr.error = r ? 0 : 1;
5197 return 0;
5198 }
5199 }
5200 }
5201
5202 assert(false);
5203 }
5204
5205 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5206 {
5207 int i;
5208 bool r;
5209
5210 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5211 KVMMSRHandlers *handler = &msr_handlers[i];
5212 if (run->msr.index == handler->msr) {
5213 if (handler->wrmsr) {
5214 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5215 run->msr.error = r ? 0 : 1;
5216 return 0;
5217 }
5218 }
5219 }
5220
5221 assert(false);
5222 }
5223
5224 static bool has_sgx_provisioning;
5225
5226 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5227 {
5228 int fd, ret;
5229
5230 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5231 return false;
5232 }
5233
5234 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5235 if (fd < 0) {
5236 return false;
5237 }
5238
5239 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5240 if (ret) {
5241 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5242 exit(1);
5243 }
5244 close(fd);
5245 return true;
5246 }
5247
5248 bool kvm_enable_sgx_provisioning(KVMState *s)
5249 {
5250 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5251 }
5252
5253 static bool host_supports_vmx(void)
5254 {
5255 uint32_t ecx, unused;
5256
5257 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5258 return ecx & CPUID_EXT_VMX;
5259 }
5260
5261 #define VMX_INVALID_GUEST_STATE 0x80000021
5262
5263 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
5264 {
5265 X86CPU *cpu = X86_CPU(cs);
5266 uint64_t code;
5267 int ret;
5268 bool ctx_invalid;
5269 char str[256];
5270 KVMState *state;
5271
5272 switch (run->exit_reason) {
5273 case KVM_EXIT_HLT:
5274 DPRINTF("handle_hlt\n");
5275 qemu_mutex_lock_iothread();
5276 ret = kvm_handle_halt(cpu);
5277 qemu_mutex_unlock_iothread();
5278 break;
5279 case KVM_EXIT_SET_TPR:
5280 ret = 0;
5281 break;
5282 case KVM_EXIT_TPR_ACCESS:
5283 qemu_mutex_lock_iothread();
5284 ret = kvm_handle_tpr_access(cpu);
5285 qemu_mutex_unlock_iothread();
5286 break;
5287 case KVM_EXIT_FAIL_ENTRY:
5288 code = run->fail_entry.hardware_entry_failure_reason;
5289 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
5290 code);
5291 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
5292 fprintf(stderr,
5293 "\nIf you're running a guest on an Intel machine without "
5294 "unrestricted mode\n"
5295 "support, the failure can be most likely due to the guest "
5296 "entering an invalid\n"
5297 "state for Intel VT. For example, the guest maybe running "
5298 "in big real mode\n"
5299 "which is not supported on less recent Intel processors."
5300 "\n\n");
5301 }
5302 ret = -1;
5303 break;
5304 case KVM_EXIT_EXCEPTION:
5305 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
5306 run->ex.exception, run->ex.error_code);
5307 ret = -1;
5308 break;
5309 case KVM_EXIT_DEBUG:
5310 DPRINTF("kvm_exit_debug\n");
5311 qemu_mutex_lock_iothread();
5312 ret = kvm_handle_debug(cpu, &run->debug.arch);
5313 qemu_mutex_unlock_iothread();
5314 break;
5315 case KVM_EXIT_HYPERV:
5316 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
5317 break;
5318 case KVM_EXIT_IOAPIC_EOI:
5319 ioapic_eoi_broadcast(run->eoi.vector);
5320 ret = 0;
5321 break;
5322 case KVM_EXIT_X86_BUS_LOCK:
5323 /* already handled in kvm_arch_post_run */
5324 ret = 0;
5325 break;
5326 case KVM_EXIT_NOTIFY:
5327 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
5328 state = KVM_STATE(current_accel());
5329 sprintf(str, "Encounter a notify exit with %svalid context in"
5330 " guest. There can be possible misbehaves in guest."
5331 " Please have a look.", ctx_invalid ? "in" : "");
5332 if (ctx_invalid ||
5333 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
5334 warn_report("KVM internal error: %s", str);
5335 ret = -1;
5336 } else {
5337 warn_report_once("KVM: %s", str);
5338 ret = 0;
5339 }
5340 break;
5341 case KVM_EXIT_X86_RDMSR:
5342 /* We only enable MSR filtering, any other exit is bogus */
5343 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
5344 ret = kvm_handle_rdmsr(cpu, run);
5345 break;
5346 case KVM_EXIT_X86_WRMSR:
5347 /* We only enable MSR filtering, any other exit is bogus */
5348 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
5349 ret = kvm_handle_wrmsr(cpu, run);
5350 break;
5351 #ifdef CONFIG_XEN_EMU
5352 case KVM_EXIT_XEN:
5353 ret = kvm_xen_handle_exit(cpu, &run->xen);
5354 break;
5355 #endif
5356 default:
5357 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
5358 ret = -1;
5359 break;
5360 }
5361
5362 return ret;
5363 }
5364
5365 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
5366 {
5367 X86CPU *cpu = X86_CPU(cs);
5368 CPUX86State *env = &cpu->env;
5369
5370 kvm_cpu_synchronize_state(cs);
5371 return !(env->cr[0] & CR0_PE_MASK) ||
5372 ((env->segs[R_CS].selector & 3) != 3);
5373 }
5374
5375 void kvm_arch_init_irq_routing(KVMState *s)
5376 {
5377 /* We know at this point that we're using the in-kernel
5378 * irqchip, so we can use irqfds, and on x86 we know
5379 * we can use msi via irqfd and GSI routing.
5380 */
5381 kvm_msi_via_irqfd_allowed = true;
5382 kvm_gsi_routing_allowed = true;
5383
5384 if (kvm_irqchip_is_split()) {
5385 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
5386 int i;
5387
5388 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
5389 MSI routes for signaling interrupts to the local apics. */
5390 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
5391 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
5392 error_report("Could not enable split IRQ mode.");
5393 exit(1);
5394 }
5395 }
5396 kvm_irqchip_commit_route_changes(&c);
5397 }
5398 }
5399
5400 int kvm_arch_irqchip_create(KVMState *s)
5401 {
5402 int ret;
5403 if (kvm_kernel_irqchip_split()) {
5404 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
5405 if (ret) {
5406 error_report("Could not enable split irqchip mode: %s",
5407 strerror(-ret));
5408 exit(1);
5409 } else {
5410 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
5411 kvm_split_irqchip = true;
5412 return 1;
5413 }
5414 } else {
5415 return 0;
5416 }
5417 }
5418
5419 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
5420 {
5421 CPUX86State *env;
5422 uint64_t ext_id;
5423
5424 if (!first_cpu) {
5425 return address;
5426 }
5427 env = &X86_CPU(first_cpu)->env;
5428 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
5429 return address;
5430 }
5431
5432 /*
5433 * If the remappable format bit is set, or the upper bits are
5434 * already set in address_hi, or the low extended bits aren't
5435 * there anyway, do nothing.
5436 */
5437 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
5438 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
5439 return address;
5440 }
5441
5442 address &= ~ext_id;
5443 address |= ext_id << 35;
5444 return address;
5445 }
5446
5447 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
5448 uint64_t address, uint32_t data, PCIDevice *dev)
5449 {
5450 X86IOMMUState *iommu = x86_iommu_get_default();
5451
5452 if (iommu) {
5453 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
5454
5455 if (class->int_remap) {
5456 int ret;
5457 MSIMessage src, dst;
5458
5459 src.address = route->u.msi.address_hi;
5460 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
5461 src.address |= route->u.msi.address_lo;
5462 src.data = route->u.msi.data;
5463
5464 ret = class->int_remap(iommu, &src, &dst, dev ? \
5465 pci_requester_id(dev) : \
5466 X86_IOMMU_SID_INVALID);
5467 if (ret) {
5468 trace_kvm_x86_fixup_msi_error(route->gsi);
5469 return 1;
5470 }
5471
5472 /*
5473 * Handled untranslated compatibility format interrupt with
5474 * extended destination ID in the low bits 11-5. */
5475 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
5476
5477 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
5478 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
5479 route->u.msi.data = dst.data;
5480 return 0;
5481 }
5482 }
5483
5484 #ifdef CONFIG_XEN_EMU
5485 if (xen_mode == XEN_EMULATE) {
5486 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
5487
5488 /*
5489 * If it was a PIRQ and successfully routed (handled == 0) or it was
5490 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
5491 */
5492 if (handled <= 0) {
5493 return handled;
5494 }
5495 }
5496 #endif
5497
5498 address = kvm_swizzle_msi_ext_dest_id(address);
5499 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
5500 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
5501 return 0;
5502 }
5503
5504 typedef struct MSIRouteEntry MSIRouteEntry;
5505
5506 struct MSIRouteEntry {
5507 PCIDevice *dev; /* Device pointer */
5508 int vector; /* MSI/MSIX vector index */
5509 int virq; /* Virtual IRQ index */
5510 QLIST_ENTRY(MSIRouteEntry) list;
5511 };
5512
5513 /* List of used GSI routes */
5514 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
5515 QLIST_HEAD_INITIALIZER(msi_route_list);
5516
5517 void kvm_update_msi_routes_all(void *private, bool global,
5518 uint32_t index, uint32_t mask)
5519 {
5520 int cnt = 0, vector;
5521 MSIRouteEntry *entry;
5522 MSIMessage msg;
5523 PCIDevice *dev;
5524
5525 /* TODO: explicit route update */
5526 QLIST_FOREACH(entry, &msi_route_list, list) {
5527 cnt++;
5528 vector = entry->vector;
5529 dev = entry->dev;
5530 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
5531 msg = msix_get_message(dev, vector);
5532 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
5533 msg = msi_get_message(dev, vector);
5534 } else {
5535 /*
5536 * Either MSI/MSIX is disabled for the device, or the
5537 * specific message was masked out. Skip this one.
5538 */
5539 continue;
5540 }
5541 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
5542 }
5543 kvm_irqchip_commit_routes(kvm_state);
5544 trace_kvm_x86_update_msi_routes(cnt);
5545 }
5546
5547 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
5548 int vector, PCIDevice *dev)
5549 {
5550 static bool notify_list_inited = false;
5551 MSIRouteEntry *entry;
5552
5553 if (!dev) {
5554 /* These are (possibly) IOAPIC routes only used for split
5555 * kernel irqchip mode, while what we are housekeeping are
5556 * PCI devices only. */
5557 return 0;
5558 }
5559
5560 entry = g_new0(MSIRouteEntry, 1);
5561 entry->dev = dev;
5562 entry->vector = vector;
5563 entry->virq = route->gsi;
5564 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
5565
5566 trace_kvm_x86_add_msi_route(route->gsi);
5567
5568 if (!notify_list_inited) {
5569 /* For the first time we do add route, add ourselves into
5570 * IOMMU's IEC notify list if needed. */
5571 X86IOMMUState *iommu = x86_iommu_get_default();
5572 if (iommu) {
5573 x86_iommu_iec_register_notifier(iommu,
5574 kvm_update_msi_routes_all,
5575 NULL);
5576 }
5577 notify_list_inited = true;
5578 }
5579 return 0;
5580 }
5581
5582 int kvm_arch_release_virq_post(int virq)
5583 {
5584 MSIRouteEntry *entry, *next;
5585 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
5586 if (entry->virq == virq) {
5587 trace_kvm_x86_remove_msi_route(virq);
5588 QLIST_REMOVE(entry, list);
5589 g_free(entry);
5590 break;
5591 }
5592 }
5593 return 0;
5594 }
5595
5596 int kvm_arch_msi_data_to_gsi(uint32_t data)
5597 {
5598 abort();
5599 }
5600
5601 bool kvm_has_waitpkg(void)
5602 {
5603 return has_msr_umwait;
5604 }
5605
5606 bool kvm_arch_cpu_check_are_resettable(void)
5607 {
5608 return !sev_es_enabled();
5609 }
5610
5611 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
5612
5613 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
5614 {
5615 KVMState *s = kvm_state;
5616 uint64_t supported;
5617
5618 mask &= XSTATE_DYNAMIC_MASK;
5619 if (!mask) {
5620 return;
5621 }
5622 /*
5623 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
5624 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
5625 * about them already because they are not supported features.
5626 */
5627 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
5628 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
5629 mask &= supported;
5630
5631 while (mask) {
5632 int bit = ctz64(mask);
5633 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
5634 if (rc) {
5635 /*
5636 * Older kernel version (<5.17) do not support
5637 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
5638 * any dynamic feature from kvm_arch_get_supported_cpuid.
5639 */
5640 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
5641 "for feature bit %d", bit);
5642 }
5643 mask &= ~BIT_ULL(bit);
5644 }
5645 }
5646
5647 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
5648 {
5649 KVMState *s = KVM_STATE(obj);
5650 return s->notify_vmexit;
5651 }
5652
5653 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
5654 {
5655 KVMState *s = KVM_STATE(obj);
5656
5657 if (s->fd != -1) {
5658 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
5659 return;
5660 }
5661
5662 s->notify_vmexit = value;
5663 }
5664
5665 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
5666 const char *name, void *opaque,
5667 Error **errp)
5668 {
5669 KVMState *s = KVM_STATE(obj);
5670 uint32_t value = s->notify_window;
5671
5672 visit_type_uint32(v, name, &value, errp);
5673 }
5674
5675 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
5676 const char *name, void *opaque,
5677 Error **errp)
5678 {
5679 KVMState *s = KVM_STATE(obj);
5680 uint32_t value;
5681
5682 if (s->fd != -1) {
5683 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
5684 return;
5685 }
5686
5687 if (!visit_type_uint32(v, name, &value, errp)) {
5688 return;
5689 }
5690
5691 s->notify_window = value;
5692 }
5693
5694 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
5695 const char *name, void *opaque,
5696 Error **errp)
5697 {
5698 KVMState *s = KVM_STATE(obj);
5699 uint32_t value = s->xen_version;
5700
5701 visit_type_uint32(v, name, &value, errp);
5702 }
5703
5704 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
5705 const char *name, void *opaque,
5706 Error **errp)
5707 {
5708 KVMState *s = KVM_STATE(obj);
5709 Error *error = NULL;
5710 uint32_t value;
5711
5712 visit_type_uint32(v, name, &value, &error);
5713 if (error) {
5714 error_propagate(errp, error);
5715 return;
5716 }
5717
5718 s->xen_version = value;
5719 if (value && xen_mode == XEN_DISABLED) {
5720 xen_mode = XEN_EMULATE;
5721 }
5722 }
5723
5724 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
5725 const char *name, void *opaque,
5726 Error **errp)
5727 {
5728 KVMState *s = KVM_STATE(obj);
5729 uint16_t value = s->xen_gnttab_max_frames;
5730
5731 visit_type_uint16(v, name, &value, errp);
5732 }
5733
5734 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
5735 const char *name, void *opaque,
5736 Error **errp)
5737 {
5738 KVMState *s = KVM_STATE(obj);
5739 Error *error = NULL;
5740 uint16_t value;
5741
5742 visit_type_uint16(v, name, &value, &error);
5743 if (error) {
5744 error_propagate(errp, error);
5745 return;
5746 }
5747
5748 s->xen_gnttab_max_frames = value;
5749 }
5750
5751 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
5752 const char *name, void *opaque,
5753 Error **errp)
5754 {
5755 KVMState *s = KVM_STATE(obj);
5756 uint16_t value = s->xen_evtchn_max_pirq;
5757
5758 visit_type_uint16(v, name, &value, errp);
5759 }
5760
5761 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
5762 const char *name, void *opaque,
5763 Error **errp)
5764 {
5765 KVMState *s = KVM_STATE(obj);
5766 Error *error = NULL;
5767 uint16_t value;
5768
5769 visit_type_uint16(v, name, &value, &error);
5770 if (error) {
5771 error_propagate(errp, error);
5772 return;
5773 }
5774
5775 s->xen_evtchn_max_pirq = value;
5776 }
5777
5778 void kvm_arch_accel_class_init(ObjectClass *oc)
5779 {
5780 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
5781 &NotifyVmexitOption_lookup,
5782 kvm_arch_get_notify_vmexit,
5783 kvm_arch_set_notify_vmexit);
5784 object_class_property_set_description(oc, "notify-vmexit",
5785 "Enable notify VM exit");
5786
5787 object_class_property_add(oc, "notify-window", "uint32",
5788 kvm_arch_get_notify_window,
5789 kvm_arch_set_notify_window,
5790 NULL, NULL);
5791 object_class_property_set_description(oc, "notify-window",
5792 "Clock cycles without an event window "
5793 "after which a notification VM exit occurs");
5794
5795 object_class_property_add(oc, "xen-version", "uint32",
5796 kvm_arch_get_xen_version,
5797 kvm_arch_set_xen_version,
5798 NULL, NULL);
5799 object_class_property_set_description(oc, "xen-version",
5800 "Xen version to be emulated "
5801 "(in XENVER_version form "
5802 "e.g. 0x4000a for 4.10)");
5803
5804 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
5805 kvm_arch_get_xen_gnttab_max_frames,
5806 kvm_arch_set_xen_gnttab_max_frames,
5807 NULL, NULL);
5808 object_class_property_set_description(oc, "xen-gnttab-max-frames",
5809 "Maximum number of grant table frames");
5810
5811 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
5812 kvm_arch_get_xen_evtchn_max_pirq,
5813 kvm_arch_set_xen_evtchn_max_pirq,
5814 NULL, NULL);
5815 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
5816 "Maximum number of Xen PIRQs");
5817 }
5818
5819 void kvm_set_max_apic_id(uint32_t max_apic_id)
5820 {
5821 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
5822 }
AR7 emulation for QEMU