migration/postcopy: start_postcopy could be true only when migrate_postcopy() return...
[qemu/ar7.git] / tcg / tcg.h
blobb411e17a28f34f0ab7ea5247daa23aa6cedcf1f3
1 /*
2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #ifndef TCG_H
26 #define TCG_H
28 #include "cpu.h"
29 #include "exec/tb-context.h"
30 #include "qemu/bitops.h"
31 #include "qemu/queue.h"
32 #include "tcg-mo.h"
33 #include "tcg-target.h"
34 #include "qemu/int128.h"
36 /* XXX: make safe guess about sizes */
37 #define MAX_OP_PER_INSTR 266
39 #if HOST_LONG_BITS == 32
40 #define MAX_OPC_PARAM_PER_ARG 2
41 #else
42 #define MAX_OPC_PARAM_PER_ARG 1
43 #endif
44 #define MAX_OPC_PARAM_IARGS 6
45 #define MAX_OPC_PARAM_OARGS 1
46 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
48 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
49 * and up to 4 + N parameters on 64-bit archs
50 * (N = number of input arguments + output arguments). */
51 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
53 #define CPU_TEMP_BUF_NLONGS 128
55 /* Default target word size to pointer size. */
56 #ifndef TCG_TARGET_REG_BITS
57 # if UINTPTR_MAX == UINT32_MAX
58 # define TCG_TARGET_REG_BITS 32
59 # elif UINTPTR_MAX == UINT64_MAX
60 # define TCG_TARGET_REG_BITS 64
61 # else
62 # error Unknown pointer size for tcg target
63 # endif
64 #endif
66 #if TCG_TARGET_REG_BITS == 32
67 typedef int32_t tcg_target_long;
68 typedef uint32_t tcg_target_ulong;
69 #define TCG_PRIlx PRIx32
70 #define TCG_PRIld PRId32
71 #elif TCG_TARGET_REG_BITS == 64
72 typedef int64_t tcg_target_long;
73 typedef uint64_t tcg_target_ulong;
74 #define TCG_PRIlx PRIx64
75 #define TCG_PRIld PRId64
76 #else
77 #error unsupported
78 #endif
80 /* Oversized TCG guests make things like MTTCG hard
81 * as we can't use atomics for cputlb updates.
83 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
84 #define TCG_OVERSIZED_GUEST 1
85 #else
86 #define TCG_OVERSIZED_GUEST 0
87 #endif
89 #if TCG_TARGET_NB_REGS <= 32
90 typedef uint32_t TCGRegSet;
91 #elif TCG_TARGET_NB_REGS <= 64
92 typedef uint64_t TCGRegSet;
93 #else
94 #error unsupported
95 #endif
97 #if TCG_TARGET_REG_BITS == 32
98 /* Turn some undef macros into false macros. */
99 #define TCG_TARGET_HAS_extrl_i64_i32 0
100 #define TCG_TARGET_HAS_extrh_i64_i32 0
101 #define TCG_TARGET_HAS_div_i64 0
102 #define TCG_TARGET_HAS_rem_i64 0
103 #define TCG_TARGET_HAS_div2_i64 0
104 #define TCG_TARGET_HAS_rot_i64 0
105 #define TCG_TARGET_HAS_ext8s_i64 0
106 #define TCG_TARGET_HAS_ext16s_i64 0
107 #define TCG_TARGET_HAS_ext32s_i64 0
108 #define TCG_TARGET_HAS_ext8u_i64 0
109 #define TCG_TARGET_HAS_ext16u_i64 0
110 #define TCG_TARGET_HAS_ext32u_i64 0
111 #define TCG_TARGET_HAS_bswap16_i64 0
112 #define TCG_TARGET_HAS_bswap32_i64 0
113 #define TCG_TARGET_HAS_bswap64_i64 0
114 #define TCG_TARGET_HAS_neg_i64 0
115 #define TCG_TARGET_HAS_not_i64 0
116 #define TCG_TARGET_HAS_andc_i64 0
117 #define TCG_TARGET_HAS_orc_i64 0
118 #define TCG_TARGET_HAS_eqv_i64 0
119 #define TCG_TARGET_HAS_nand_i64 0
120 #define TCG_TARGET_HAS_nor_i64 0
121 #define TCG_TARGET_HAS_clz_i64 0
122 #define TCG_TARGET_HAS_ctz_i64 0
123 #define TCG_TARGET_HAS_ctpop_i64 0
124 #define TCG_TARGET_HAS_deposit_i64 0
125 #define TCG_TARGET_HAS_extract_i64 0
126 #define TCG_TARGET_HAS_sextract_i64 0
127 #define TCG_TARGET_HAS_extract2_i64 0
128 #define TCG_TARGET_HAS_movcond_i64 0
129 #define TCG_TARGET_HAS_add2_i64 0
130 #define TCG_TARGET_HAS_sub2_i64 0
131 #define TCG_TARGET_HAS_mulu2_i64 0
132 #define TCG_TARGET_HAS_muls2_i64 0
133 #define TCG_TARGET_HAS_muluh_i64 0
134 #define TCG_TARGET_HAS_mulsh_i64 0
135 /* Turn some undef macros into true macros. */
136 #define TCG_TARGET_HAS_add2_i32 1
137 #define TCG_TARGET_HAS_sub2_i32 1
138 #endif
140 #ifndef TCG_TARGET_deposit_i32_valid
141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
142 #endif
143 #ifndef TCG_TARGET_deposit_i64_valid
144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
145 #endif
146 #ifndef TCG_TARGET_extract_i32_valid
147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
148 #endif
149 #ifndef TCG_TARGET_extract_i64_valid
150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
151 #endif
153 /* Only one of DIV or DIV2 should be defined. */
154 #if defined(TCG_TARGET_HAS_div_i32)
155 #define TCG_TARGET_HAS_div2_i32 0
156 #elif defined(TCG_TARGET_HAS_div2_i32)
157 #define TCG_TARGET_HAS_div_i32 0
158 #define TCG_TARGET_HAS_rem_i32 0
159 #endif
160 #if defined(TCG_TARGET_HAS_div_i64)
161 #define TCG_TARGET_HAS_div2_i64 0
162 #elif defined(TCG_TARGET_HAS_div2_i64)
163 #define TCG_TARGET_HAS_div_i64 0
164 #define TCG_TARGET_HAS_rem_i64 0
165 #endif
167 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
168 #if TCG_TARGET_REG_BITS == 32 \
169 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
170 || defined(TCG_TARGET_HAS_muluh_i32))
171 # error "Missing unsigned widening multiply"
172 #endif
174 #if !defined(TCG_TARGET_HAS_v64) \
175 && !defined(TCG_TARGET_HAS_v128) \
176 && !defined(TCG_TARGET_HAS_v256)
177 #define TCG_TARGET_MAYBE_vec 0
178 #define TCG_TARGET_HAS_abs_vec 0
179 #define TCG_TARGET_HAS_neg_vec 0
180 #define TCG_TARGET_HAS_not_vec 0
181 #define TCG_TARGET_HAS_andc_vec 0
182 #define TCG_TARGET_HAS_orc_vec 0
183 #define TCG_TARGET_HAS_shi_vec 0
184 #define TCG_TARGET_HAS_shs_vec 0
185 #define TCG_TARGET_HAS_shv_vec 0
186 #define TCG_TARGET_HAS_mul_vec 0
187 #define TCG_TARGET_HAS_sat_vec 0
188 #define TCG_TARGET_HAS_minmax_vec 0
189 #define TCG_TARGET_HAS_bitsel_vec 0
190 #define TCG_TARGET_HAS_cmpsel_vec 0
191 #else
192 #define TCG_TARGET_MAYBE_vec 1
193 #endif
194 #ifndef TCG_TARGET_HAS_v64
195 #define TCG_TARGET_HAS_v64 0
196 #endif
197 #ifndef TCG_TARGET_HAS_v128
198 #define TCG_TARGET_HAS_v128 0
199 #endif
200 #ifndef TCG_TARGET_HAS_v256
201 #define TCG_TARGET_HAS_v256 0
202 #endif
204 #ifndef TARGET_INSN_START_EXTRA_WORDS
205 # define TARGET_INSN_START_WORDS 1
206 #else
207 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
208 #endif
210 typedef enum TCGOpcode {
211 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
212 #include "tcg-opc.h"
213 #undef DEF
214 NB_OPS,
215 } TCGOpcode;
217 #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r))
218 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
219 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
221 #ifndef TCG_TARGET_INSN_UNIT_SIZE
222 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
223 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
224 typedef uint8_t tcg_insn_unit;
225 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
226 typedef uint16_t tcg_insn_unit;
227 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
228 typedef uint32_t tcg_insn_unit;
229 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
230 typedef uint64_t tcg_insn_unit;
231 #else
232 /* The port better have done this. */
233 #endif
236 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
237 # define tcg_debug_assert(X) do { assert(X); } while (0)
238 #else
239 # define tcg_debug_assert(X) \
240 do { if (!(X)) { __builtin_unreachable(); } } while (0)
241 #endif
243 typedef struct TCGRelocation TCGRelocation;
244 struct TCGRelocation {
245 QSIMPLEQ_ENTRY(TCGRelocation) next;
246 tcg_insn_unit *ptr;
247 intptr_t addend;
248 int type;
251 typedef struct TCGLabel TCGLabel;
252 struct TCGLabel {
253 unsigned present : 1;
254 unsigned has_value : 1;
255 unsigned id : 14;
256 unsigned refs : 16;
257 union {
258 uintptr_t value;
259 tcg_insn_unit *value_ptr;
260 } u;
261 QSIMPLEQ_HEAD(, TCGRelocation) relocs;
262 QSIMPLEQ_ENTRY(TCGLabel) next;
265 typedef struct TCGPool {
266 struct TCGPool *next;
267 int size;
268 uint8_t data[0] __attribute__ ((aligned));
269 } TCGPool;
271 #define TCG_POOL_CHUNK_SIZE 32768
273 #define TCG_MAX_TEMPS 512
274 #define TCG_MAX_INSNS 512
276 /* when the size of the arguments of a called function is smaller than
277 this value, they are statically allocated in the TB stack frame */
278 #define TCG_STATIC_CALL_ARGS_SIZE 128
280 typedef enum TCGType {
281 TCG_TYPE_I32,
282 TCG_TYPE_I64,
284 TCG_TYPE_V64,
285 TCG_TYPE_V128,
286 TCG_TYPE_V256,
288 TCG_TYPE_COUNT, /* number of different types */
290 /* An alias for the size of the host register. */
291 #if TCG_TARGET_REG_BITS == 32
292 TCG_TYPE_REG = TCG_TYPE_I32,
293 #else
294 TCG_TYPE_REG = TCG_TYPE_I64,
295 #endif
297 /* An alias for the size of the native pointer. */
298 #if UINTPTR_MAX == UINT32_MAX
299 TCG_TYPE_PTR = TCG_TYPE_I32,
300 #else
301 TCG_TYPE_PTR = TCG_TYPE_I64,
302 #endif
304 /* An alias for the size of the target "long", aka register. */
305 #if TARGET_LONG_BITS == 64
306 TCG_TYPE_TL = TCG_TYPE_I64,
307 #else
308 TCG_TYPE_TL = TCG_TYPE_I32,
309 #endif
310 } TCGType;
312 /* Constants for qemu_ld and qemu_st for the Memory Operation field. */
313 typedef enum TCGMemOp {
314 MO_8 = 0,
315 MO_16 = 1,
316 MO_32 = 2,
317 MO_64 = 3,
318 MO_SIZE = 3, /* Mask for the above. */
320 MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
322 MO_BSWAP = 8, /* Host reverse endian. */
323 #ifdef HOST_WORDS_BIGENDIAN
324 MO_LE = MO_BSWAP,
325 MO_BE = 0,
326 #else
327 MO_LE = 0,
328 MO_BE = MO_BSWAP,
329 #endif
330 #ifdef TARGET_WORDS_BIGENDIAN
331 MO_TE = MO_BE,
332 #else
333 MO_TE = MO_LE,
334 #endif
336 /* MO_UNALN accesses are never checked for alignment.
337 * MO_ALIGN accesses will result in a call to the CPU's
338 * do_unaligned_access hook if the guest address is not aligned.
339 * The default depends on whether the target CPU defines ALIGNED_ONLY.
341 * Some architectures (e.g. ARMv8) need the address which is aligned
342 * to a size more than the size of the memory access.
343 * Some architectures (e.g. SPARCv9) need an address which is aligned,
344 * but less strictly than the natural alignment.
346 * MO_ALIGN supposes the alignment size is the size of a memory access.
348 * There are three options:
349 * - unaligned access permitted (MO_UNALN).
350 * - an alignment to the size of an access (MO_ALIGN);
351 * - an alignment to a specified size, which may be more or less than
352 * the access size (MO_ALIGN_x where 'x' is a size in bytes);
354 MO_ASHIFT = 4,
355 MO_AMASK = 7 << MO_ASHIFT,
356 #ifdef ALIGNED_ONLY
357 MO_ALIGN = 0,
358 MO_UNALN = MO_AMASK,
359 #else
360 MO_ALIGN = MO_AMASK,
361 MO_UNALN = 0,
362 #endif
363 MO_ALIGN_2 = 1 << MO_ASHIFT,
364 MO_ALIGN_4 = 2 << MO_ASHIFT,
365 MO_ALIGN_8 = 3 << MO_ASHIFT,
366 MO_ALIGN_16 = 4 << MO_ASHIFT,
367 MO_ALIGN_32 = 5 << MO_ASHIFT,
368 MO_ALIGN_64 = 6 << MO_ASHIFT,
370 /* Combinations of the above, for ease of use. */
371 MO_UB = MO_8,
372 MO_UW = MO_16,
373 MO_UL = MO_32,
374 MO_SB = MO_SIGN | MO_8,
375 MO_SW = MO_SIGN | MO_16,
376 MO_SL = MO_SIGN | MO_32,
377 MO_Q = MO_64,
379 MO_LEUW = MO_LE | MO_UW,
380 MO_LEUL = MO_LE | MO_UL,
381 MO_LESW = MO_LE | MO_SW,
382 MO_LESL = MO_LE | MO_SL,
383 MO_LEQ = MO_LE | MO_Q,
385 MO_BEUW = MO_BE | MO_UW,
386 MO_BEUL = MO_BE | MO_UL,
387 MO_BESW = MO_BE | MO_SW,
388 MO_BESL = MO_BE | MO_SL,
389 MO_BEQ = MO_BE | MO_Q,
391 MO_TEUW = MO_TE | MO_UW,
392 MO_TEUL = MO_TE | MO_UL,
393 MO_TESW = MO_TE | MO_SW,
394 MO_TESL = MO_TE | MO_SL,
395 MO_TEQ = MO_TE | MO_Q,
397 MO_SSIZE = MO_SIZE | MO_SIGN,
398 } TCGMemOp;
401 * get_alignment_bits
402 * @memop: TCGMemOp value
404 * Extract the alignment size from the memop.
406 static inline unsigned get_alignment_bits(TCGMemOp memop)
408 unsigned a = memop & MO_AMASK;
410 if (a == MO_UNALN) {
411 /* No alignment required. */
412 a = 0;
413 } else if (a == MO_ALIGN) {
414 /* A natural alignment requirement. */
415 a = memop & MO_SIZE;
416 } else {
417 /* A specific alignment requirement. */
418 a = a >> MO_ASHIFT;
420 #if defined(CONFIG_SOFTMMU)
421 /* The requested alignment cannot overlap the TLB flags. */
422 tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
423 #endif
424 return a;
427 typedef tcg_target_ulong TCGArg;
429 /* Define type and accessor macros for TCG variables.
431 TCG variables are the inputs and outputs of TCG ops, as described
432 in tcg/README. Target CPU front-end code uses these types to deal
433 with TCG variables as it emits TCG code via the tcg_gen_* functions.
434 They come in several flavours:
435 * TCGv_i32 : 32 bit integer type
436 * TCGv_i64 : 64 bit integer type
437 * TCGv_ptr : a host pointer type
438 * TCGv_vec : a host vector type; the exact size is not exposed
439 to the CPU front-end code.
440 * TCGv : an integer type the same size as target_ulong
441 (an alias for either TCGv_i32 or TCGv_i64)
442 The compiler's type checking will complain if you mix them
443 up and pass the wrong sized TCGv to a function.
445 Users of tcg_gen_* don't need to know about any of the internal
446 details of these, and should treat them as opaque types.
447 You won't be able to look inside them in a debugger either.
449 Internal implementation details follow:
451 Note that there is no definition of the structs TCGv_i32_d etc anywhere.
452 This is deliberate, because the values we store in variables of type
453 TCGv_i32 are not really pointers-to-structures. They're just small
454 integers, but keeping them in pointer types like this means that the
455 compiler will complain if you accidentally pass a TCGv_i32 to a
456 function which takes a TCGv_i64, and so on. Only the internals of
457 TCG need to care about the actual contents of the types. */
459 typedef struct TCGv_i32_d *TCGv_i32;
460 typedef struct TCGv_i64_d *TCGv_i64;
461 typedef struct TCGv_ptr_d *TCGv_ptr;
462 typedef struct TCGv_vec_d *TCGv_vec;
463 typedef TCGv_ptr TCGv_env;
464 #if TARGET_LONG_BITS == 32
465 #define TCGv TCGv_i32
466 #elif TARGET_LONG_BITS == 64
467 #define TCGv TCGv_i64
468 #else
469 #error Unhandled TARGET_LONG_BITS value
470 #endif
472 /* call flags */
473 /* Helper does not read globals (either directly or through an exception). It
474 implies TCG_CALL_NO_WRITE_GLOBALS. */
475 #define TCG_CALL_NO_READ_GLOBALS 0x0001
476 /* Helper does not write globals */
477 #define TCG_CALL_NO_WRITE_GLOBALS 0x0002
478 /* Helper can be safely suppressed if the return value is not used. */
479 #define TCG_CALL_NO_SIDE_EFFECTS 0x0004
480 /* Helper is QEMU_NORETURN. */
481 #define TCG_CALL_NO_RETURN 0x0008
483 /* convenience version of most used call flags */
484 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
485 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
486 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
487 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
488 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
490 /* Used to align parameters. See the comment before tcgv_i32_temp. */
491 #define TCG_CALL_DUMMY_ARG ((TCGArg)0)
493 /* Conditions. Note that these are laid out for easy manipulation by
494 the functions below:
495 bit 0 is used for inverting;
496 bit 1 is signed,
497 bit 2 is unsigned,
498 bit 3 is used with bit 0 for swapping signed/unsigned. */
499 typedef enum {
500 /* non-signed */
501 TCG_COND_NEVER = 0 | 0 | 0 | 0,
502 TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
503 TCG_COND_EQ = 8 | 0 | 0 | 0,
504 TCG_COND_NE = 8 | 0 | 0 | 1,
505 /* signed */
506 TCG_COND_LT = 0 | 0 | 2 | 0,
507 TCG_COND_GE = 0 | 0 | 2 | 1,
508 TCG_COND_LE = 8 | 0 | 2 | 0,
509 TCG_COND_GT = 8 | 0 | 2 | 1,
510 /* unsigned */
511 TCG_COND_LTU = 0 | 4 | 0 | 0,
512 TCG_COND_GEU = 0 | 4 | 0 | 1,
513 TCG_COND_LEU = 8 | 4 | 0 | 0,
514 TCG_COND_GTU = 8 | 4 | 0 | 1,
515 } TCGCond;
517 /* Invert the sense of the comparison. */
518 static inline TCGCond tcg_invert_cond(TCGCond c)
520 return (TCGCond)(c ^ 1);
523 /* Swap the operands in a comparison. */
524 static inline TCGCond tcg_swap_cond(TCGCond c)
526 return c & 6 ? (TCGCond)(c ^ 9) : c;
529 /* Create an "unsigned" version of a "signed" comparison. */
530 static inline TCGCond tcg_unsigned_cond(TCGCond c)
532 return c & 2 ? (TCGCond)(c ^ 6) : c;
535 /* Create a "signed" version of an "unsigned" comparison. */
536 static inline TCGCond tcg_signed_cond(TCGCond c)
538 return c & 4 ? (TCGCond)(c ^ 6) : c;
541 /* Must a comparison be considered unsigned? */
542 static inline bool is_unsigned_cond(TCGCond c)
544 return (c & 4) != 0;
547 /* Create a "high" version of a double-word comparison.
548 This removes equality from a LTE or GTE comparison. */
549 static inline TCGCond tcg_high_cond(TCGCond c)
551 switch (c) {
552 case TCG_COND_GE:
553 case TCG_COND_LE:
554 case TCG_COND_GEU:
555 case TCG_COND_LEU:
556 return (TCGCond)(c ^ 8);
557 default:
558 return c;
562 typedef enum TCGTempVal {
563 TEMP_VAL_DEAD,
564 TEMP_VAL_REG,
565 TEMP_VAL_MEM,
566 TEMP_VAL_CONST,
567 } TCGTempVal;
569 typedef struct TCGTemp {
570 TCGReg reg:8;
571 TCGTempVal val_type:8;
572 TCGType base_type:8;
573 TCGType type:8;
574 unsigned int fixed_reg:1;
575 unsigned int indirect_reg:1;
576 unsigned int indirect_base:1;
577 unsigned int mem_coherent:1;
578 unsigned int mem_allocated:1;
579 /* If true, the temp is saved across both basic blocks and
580 translation blocks. */
581 unsigned int temp_global:1;
582 /* If true, the temp is saved across basic blocks but dead
583 at the end of translation blocks. If false, the temp is
584 dead at the end of basic blocks. */
585 unsigned int temp_local:1;
586 unsigned int temp_allocated:1;
588 tcg_target_long val;
589 struct TCGTemp *mem_base;
590 intptr_t mem_offset;
591 const char *name;
593 /* Pass-specific information that can be stored for a temporary.
594 One word worth of integer data, and one pointer to data
595 allocated separately. */
596 uintptr_t state;
597 void *state_ptr;
598 } TCGTemp;
600 typedef struct TCGContext TCGContext;
602 typedef struct TCGTempSet {
603 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
604 } TCGTempSet;
606 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
607 this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
608 There are never more than 2 outputs, which means that we can store all
609 dead + sync data within 16 bits. */
610 #define DEAD_ARG 4
611 #define SYNC_ARG 1
612 typedef uint16_t TCGLifeData;
614 /* The layout here is designed to avoid a bitfield crossing of
615 a 32-bit boundary, which would cause GCC to add extra padding. */
616 typedef struct TCGOp {
617 TCGOpcode opc : 8; /* 8 */
619 /* Parameters for this opcode. See below. */
620 unsigned param1 : 4; /* 12 */
621 unsigned param2 : 4; /* 16 */
623 /* Lifetime data of the operands. */
624 unsigned life : 16; /* 32 */
626 /* Next and previous opcodes. */
627 QTAILQ_ENTRY(TCGOp) link;
629 /* Arguments for the opcode. */
630 TCGArg args[MAX_OPC_PARAM];
632 /* Register preferences for the output(s). */
633 TCGRegSet output_pref[2];
634 } TCGOp;
636 #define TCGOP_CALLI(X) (X)->param1
637 #define TCGOP_CALLO(X) (X)->param2
639 #define TCGOP_VECL(X) (X)->param1
640 #define TCGOP_VECE(X) (X)->param2
642 /* Make sure operands fit in the bitfields above. */
643 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
645 typedef struct TCGProfile {
646 int64_t cpu_exec_time;
647 int64_t tb_count1;
648 int64_t tb_count;
649 int64_t op_count; /* total insn count */
650 int op_count_max; /* max insn per TB */
651 int temp_count_max;
652 int64_t temp_count;
653 int64_t del_op_count;
654 int64_t code_in_len;
655 int64_t code_out_len;
656 int64_t search_out_len;
657 int64_t interm_time;
658 int64_t code_time;
659 int64_t la_time;
660 int64_t opt_time;
661 int64_t restore_count;
662 int64_t restore_time;
663 int64_t table_op_count[NB_OPS];
664 } TCGProfile;
666 struct TCGContext {
667 uint8_t *pool_cur, *pool_end;
668 TCGPool *pool_first, *pool_current, *pool_first_large;
669 int nb_labels;
670 int nb_globals;
671 int nb_temps;
672 int nb_indirects;
673 int nb_ops;
675 /* goto_tb support */
676 tcg_insn_unit *code_buf;
677 uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
678 uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
679 uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
681 TCGRegSet reserved_regs;
682 uint32_t tb_cflags; /* cflags of the current TB */
683 intptr_t current_frame_offset;
684 intptr_t frame_start;
685 intptr_t frame_end;
686 TCGTemp *frame_temp;
688 tcg_insn_unit *code_ptr;
690 #ifdef CONFIG_PROFILER
691 TCGProfile prof;
692 #endif
694 #ifdef CONFIG_DEBUG_TCG
695 int temps_in_use;
696 int goto_tb_issue_mask;
697 const TCGOpcode *vecop_list;
698 #endif
700 /* Code generation. Note that we specifically do not use tcg_insn_unit
701 here, because there's too much arithmetic throughout that relies
702 on addition and subtraction working on bytes. Rely on the GCC
703 extension that allows arithmetic on void*. */
704 void *code_gen_prologue;
705 void *code_gen_epilogue;
706 void *code_gen_buffer;
707 size_t code_gen_buffer_size;
708 void *code_gen_ptr;
709 void *data_gen_ptr;
711 /* Threshold to flush the translated code buffer. */
712 void *code_gen_highwater;
714 size_t tb_phys_invalidate_count;
716 /* Track which vCPU triggers events */
717 CPUState *cpu; /* *_trans */
719 /* These structures are private to tcg-target.inc.c. */
720 #ifdef TCG_TARGET_NEED_LDST_LABELS
721 QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
722 #endif
723 #ifdef TCG_TARGET_NEED_POOL_LABELS
724 struct TCGLabelPoolData *pool_labels;
725 #endif
727 TCGLabel *exitreq_label;
729 TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
730 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
732 QTAILQ_HEAD(, TCGOp) ops, free_ops;
733 QSIMPLEQ_HEAD(, TCGLabel) labels;
735 /* Tells which temporary holds a given register.
736 It does not take into account fixed registers */
737 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
739 uint16_t gen_insn_end_off[TCG_MAX_INSNS];
740 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
743 extern TCGContext tcg_init_ctx;
744 extern __thread TCGContext *tcg_ctx;
745 extern TCGv_env cpu_env;
747 static inline size_t temp_idx(TCGTemp *ts)
749 ptrdiff_t n = ts - tcg_ctx->temps;
750 tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
751 return n;
754 static inline TCGArg temp_arg(TCGTemp *ts)
756 return (uintptr_t)ts;
759 static inline TCGTemp *arg_temp(TCGArg a)
761 return (TCGTemp *)(uintptr_t)a;
764 /* Using the offset of a temporary, relative to TCGContext, rather than
765 its index means that we don't use 0. That leaves offset 0 free for
766 a NULL representation without having to leave index 0 unused. */
767 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
769 uintptr_t o = (uintptr_t)v;
770 TCGTemp *t = (void *)tcg_ctx + o;
771 tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
772 return t;
775 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
777 return tcgv_i32_temp((TCGv_i32)v);
780 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
782 return tcgv_i32_temp((TCGv_i32)v);
785 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
787 return tcgv_i32_temp((TCGv_i32)v);
790 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
792 return temp_arg(tcgv_i32_temp(v));
795 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
797 return temp_arg(tcgv_i64_temp(v));
800 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
802 return temp_arg(tcgv_ptr_temp(v));
805 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
807 return temp_arg(tcgv_vec_temp(v));
810 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
812 (void)temp_idx(t); /* trigger embedded assert */
813 return (TCGv_i32)((void *)t - (void *)tcg_ctx);
816 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
818 return (TCGv_i64)temp_tcgv_i32(t);
821 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
823 return (TCGv_ptr)temp_tcgv_i32(t);
826 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
828 return (TCGv_vec)temp_tcgv_i32(t);
831 #if TCG_TARGET_REG_BITS == 32
832 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
834 return temp_tcgv_i32(tcgv_i64_temp(t));
837 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
839 return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
841 #endif
843 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
845 op->args[arg] = v;
848 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
850 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
851 tcg_set_insn_param(op, arg, v);
852 #else
853 tcg_set_insn_param(op, arg * 2, v);
854 tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
855 #endif
858 /* The last op that was emitted. */
859 static inline TCGOp *tcg_last_op(void)
861 return QTAILQ_LAST(&tcg_ctx->ops);
864 /* Test for whether to terminate the TB for using too many opcodes. */
865 static inline bool tcg_op_buf_full(void)
867 /* This is not a hard limit, it merely stops translation when
868 * we have produced "enough" opcodes. We want to limit TB size
869 * such that a RISC host can reasonably use a 16-bit signed
870 * branch within the TB. We also need to be mindful of the
871 * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
872 * and TCGContext.gen_insn_end_off[].
874 return tcg_ctx->nb_ops >= 4000;
877 /* pool based memory allocation */
879 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
880 void *tcg_malloc_internal(TCGContext *s, int size);
881 void tcg_pool_reset(TCGContext *s);
882 TranslationBlock *tcg_tb_alloc(TCGContext *s);
884 void tcg_region_init(void);
885 void tcg_region_reset_all(void);
887 size_t tcg_code_size(void);
888 size_t tcg_code_capacity(void);
890 void tcg_tb_insert(TranslationBlock *tb);
891 void tcg_tb_remove(TranslationBlock *tb);
892 size_t tcg_tb_phys_invalidate_count(void);
893 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
894 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
895 size_t tcg_nb_tbs(void);
897 /* user-mode: Called with mmap_lock held. */
898 static inline void *tcg_malloc(int size)
900 TCGContext *s = tcg_ctx;
901 uint8_t *ptr, *ptr_end;
903 /* ??? This is a weak placeholder for minimum malloc alignment. */
904 size = QEMU_ALIGN_UP(size, 8);
906 ptr = s->pool_cur;
907 ptr_end = ptr + size;
908 if (unlikely(ptr_end > s->pool_end)) {
909 return tcg_malloc_internal(tcg_ctx, size);
910 } else {
911 s->pool_cur = ptr_end;
912 return ptr;
916 void tcg_context_init(TCGContext *s);
917 void tcg_register_thread(void);
918 void tcg_prologue_init(TCGContext *s);
919 void tcg_func_start(TCGContext *s);
921 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
923 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
925 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
926 intptr_t, const char *);
927 TCGTemp *tcg_temp_new_internal(TCGType, bool);
928 void tcg_temp_free_internal(TCGTemp *);
929 TCGv_vec tcg_temp_new_vec(TCGType type);
930 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
932 static inline void tcg_temp_free_i32(TCGv_i32 arg)
934 tcg_temp_free_internal(tcgv_i32_temp(arg));
937 static inline void tcg_temp_free_i64(TCGv_i64 arg)
939 tcg_temp_free_internal(tcgv_i64_temp(arg));
942 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
944 tcg_temp_free_internal(tcgv_ptr_temp(arg));
947 static inline void tcg_temp_free_vec(TCGv_vec arg)
949 tcg_temp_free_internal(tcgv_vec_temp(arg));
952 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
953 const char *name)
955 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
956 return temp_tcgv_i32(t);
959 static inline TCGv_i32 tcg_temp_new_i32(void)
961 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
962 return temp_tcgv_i32(t);
965 static inline TCGv_i32 tcg_temp_local_new_i32(void)
967 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
968 return temp_tcgv_i32(t);
971 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
972 const char *name)
974 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
975 return temp_tcgv_i64(t);
978 static inline TCGv_i64 tcg_temp_new_i64(void)
980 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
981 return temp_tcgv_i64(t);
984 static inline TCGv_i64 tcg_temp_local_new_i64(void)
986 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
987 return temp_tcgv_i64(t);
990 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
991 const char *name)
993 TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
994 return temp_tcgv_ptr(t);
997 static inline TCGv_ptr tcg_temp_new_ptr(void)
999 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
1000 return temp_tcgv_ptr(t);
1003 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
1005 TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
1006 return temp_tcgv_ptr(t);
1009 #if defined(CONFIG_DEBUG_TCG)
1010 /* If you call tcg_clear_temp_count() at the start of a section of
1011 * code which is not supposed to leak any TCG temporaries, then
1012 * calling tcg_check_temp_count() at the end of the section will
1013 * return 1 if the section did in fact leak a temporary.
1015 void tcg_clear_temp_count(void);
1016 int tcg_check_temp_count(void);
1017 #else
1018 #define tcg_clear_temp_count() do { } while (0)
1019 #define tcg_check_temp_count() 0
1020 #endif
1022 int64_t tcg_cpu_exec_time(void);
1023 void tcg_dump_info(void);
1024 void tcg_dump_op_count(void);
1026 #define TCG_CT_ALIAS 0x80
1027 #define TCG_CT_IALIAS 0x40
1028 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1029 #define TCG_CT_REG 0x01
1030 #define TCG_CT_CONST 0x02 /* any constant of register size */
1032 typedef struct TCGArgConstraint {
1033 uint16_t ct;
1034 uint8_t alias_index;
1035 union {
1036 TCGRegSet regs;
1037 } u;
1038 } TCGArgConstraint;
1040 #define TCG_MAX_OP_ARGS 16
1042 /* Bits for TCGOpDef->flags, 8 bits available. */
1043 enum {
1044 /* Instruction exits the translation block. */
1045 TCG_OPF_BB_EXIT = 0x01,
1046 /* Instruction defines the end of a basic block. */
1047 TCG_OPF_BB_END = 0x02,
1048 /* Instruction clobbers call registers and potentially update globals. */
1049 TCG_OPF_CALL_CLOBBER = 0x04,
1050 /* Instruction has side effects: it cannot be removed if its outputs
1051 are not used, and might trigger exceptions. */
1052 TCG_OPF_SIDE_EFFECTS = 0x08,
1053 /* Instruction operands are 64-bits (otherwise 32-bits). */
1054 TCG_OPF_64BIT = 0x10,
1055 /* Instruction is optional and not implemented by the host, or insn
1056 is generic and should not be implemened by the host. */
1057 TCG_OPF_NOT_PRESENT = 0x20,
1058 /* Instruction operands are vectors. */
1059 TCG_OPF_VECTOR = 0x40,
1062 typedef struct TCGOpDef {
1063 const char *name;
1064 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1065 uint8_t flags;
1066 TCGArgConstraint *args_ct;
1067 int *sorted_args;
1068 #if defined(CONFIG_DEBUG_TCG)
1069 int used;
1070 #endif
1071 } TCGOpDef;
1073 extern TCGOpDef tcg_op_defs[];
1074 extern const size_t tcg_op_defs_max;
1076 typedef struct TCGTargetOpDef {
1077 TCGOpcode op;
1078 const char *args_ct_str[TCG_MAX_OP_ARGS];
1079 } TCGTargetOpDef;
1081 #define tcg_abort() \
1082 do {\
1083 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1084 abort();\
1085 } while (0)
1087 bool tcg_op_supported(TCGOpcode op);
1089 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1091 TCGOp *tcg_emit_op(TCGOpcode opc);
1092 void tcg_op_remove(TCGContext *s, TCGOp *op);
1093 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1094 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1096 void tcg_optimize(TCGContext *s);
1098 TCGv_i32 tcg_const_i32(int32_t val);
1099 TCGv_i64 tcg_const_i64(int64_t val);
1100 TCGv_i32 tcg_const_local_i32(int32_t val);
1101 TCGv_i64 tcg_const_local_i64(int64_t val);
1102 TCGv_vec tcg_const_zeros_vec(TCGType);
1103 TCGv_vec tcg_const_ones_vec(TCGType);
1104 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1105 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1107 #if UINTPTR_MAX == UINT32_MAX
1108 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1109 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1110 #else
1111 # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1112 # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1113 #endif
1115 TCGLabel *gen_new_label(void);
1118 * label_arg
1119 * @l: label
1121 * Encode a label for storage in the TCG opcode stream.
1124 static inline TCGArg label_arg(TCGLabel *l)
1126 return (uintptr_t)l;
1130 * arg_label
1131 * @i: value
1133 * The opposite of label_arg. Retrieve a label from the
1134 * encoding of the TCG opcode stream.
1137 static inline TCGLabel *arg_label(TCGArg i)
1139 return (TCGLabel *)(uintptr_t)i;
1143 * tcg_ptr_byte_diff
1144 * @a, @b: addresses to be differenced
1146 * There are many places within the TCG backends where we need a byte
1147 * difference between two pointers. While this can be accomplished
1148 * with local casting, it's easy to get wrong -- especially if one is
1149 * concerned with the signedness of the result.
1151 * This version relies on GCC's void pointer arithmetic to get the
1152 * correct result.
1155 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1157 return a - b;
1161 * tcg_pcrel_diff
1162 * @s: the tcg context
1163 * @target: address of the target
1165 * Produce a pc-relative difference, from the current code_ptr
1166 * to the destination address.
1169 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1171 return tcg_ptr_byte_diff(target, s->code_ptr);
1175 * tcg_current_code_size
1176 * @s: the tcg context
1178 * Compute the current code size within the translation block.
1179 * This is used to fill in qemu's data structures for goto_tb.
1182 static inline size_t tcg_current_code_size(TCGContext *s)
1184 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1187 /* Combine the TCGMemOp and mmu_idx parameters into a single value. */
1188 typedef uint32_t TCGMemOpIdx;
1191 * make_memop_idx
1192 * @op: memory operation
1193 * @idx: mmu index
1195 * Encode these values into a single parameter.
1197 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1199 tcg_debug_assert(idx <= 15);
1200 return (op << 4) | idx;
1204 * get_memop
1205 * @oi: combined op/idx parameter
1207 * Extract the memory operation from the combined value.
1209 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1211 return oi >> 4;
1215 * get_mmuidx
1216 * @oi: combined op/idx parameter
1218 * Extract the mmu index from the combined value.
1220 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1222 return oi & 15;
1226 * tcg_qemu_tb_exec:
1227 * @env: pointer to CPUArchState for the CPU
1228 * @tb_ptr: address of generated code for the TB to execute
1230 * Start executing code from a given translation block.
1231 * Where translation blocks have been linked, execution
1232 * may proceed from the given TB into successive ones.
1233 * Control eventually returns only when some action is needed
1234 * from the top-level loop: either control must pass to a TB
1235 * which has not yet been directly linked, or an asynchronous
1236 * event such as an interrupt needs handling.
1238 * Return: The return value is the value passed to the corresponding
1239 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1240 * The value is either zero or a 4-byte aligned pointer to that TB combined
1241 * with additional information in its two least significant bits. The
1242 * additional information is encoded as follows:
1243 * 0, 1: the link between this TB and the next is via the specified
1244 * TB index (0 or 1). That is, we left the TB via (the equivalent
1245 * of) "goto_tb <index>". The main loop uses this to determine
1246 * how to link the TB just executed to the next.
1247 * 2: we are using instruction counting code generation, and we
1248 * did not start executing this TB because the instruction counter
1249 * would hit zero midway through it. In this case the pointer
1250 * returned is the TB we were about to execute, and the caller must
1251 * arrange to execute the remaining count of instructions.
1252 * 3: we stopped because the CPU's exit_request flag was set
1253 * (usually meaning that there is an interrupt that needs to be
1254 * handled). The pointer returned is the TB we were about to execute
1255 * when we noticed the pending exit request.
1257 * If the bottom two bits indicate an exit-via-index then the CPU
1258 * state is correctly synchronised and ready for execution of the next
1259 * TB (and in particular the guest PC is the address to execute next).
1260 * Otherwise, we gave up on execution of this TB before it started, and
1261 * the caller must fix up the CPU state by calling the CPU's
1262 * synchronize_from_tb() method with the TB pointer we return (falling
1263 * back to calling the CPU's set_pc method with tb->pb if no
1264 * synchronize_from_tb() method exists).
1266 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1267 * to this default (which just calls the prologue.code emitted by
1268 * tcg_target_qemu_prologue()).
1270 #define TB_EXIT_MASK 3
1271 #define TB_EXIT_IDX0 0
1272 #define TB_EXIT_IDX1 1
1273 #define TB_EXIT_IDXMAX 1
1274 #define TB_EXIT_REQUESTED 3
1276 #ifdef HAVE_TCG_QEMU_TB_EXEC
1277 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1278 #else
1279 # define tcg_qemu_tb_exec(env, tb_ptr) \
1280 ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1281 #endif
1283 void tcg_register_jit(void *buf, size_t buf_size);
1285 #if TCG_TARGET_MAYBE_vec
1286 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1287 return > 0 if it is directly supportable;
1288 return < 0 if we must call tcg_expand_vec_op. */
1289 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1290 #else
1291 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1293 return 0;
1295 #endif
1297 /* Expand the tuple (opc, type, vece) on the given arguments. */
1298 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1300 /* Replicate a constant C accoring to the log2 of the element size. */
1301 uint64_t dup_const(unsigned vece, uint64_t c);
1303 #define dup_const(VECE, C) \
1304 (__builtin_constant_p(VECE) \
1305 ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
1306 : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
1307 : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
1308 : dup_const(VECE, C)) \
1309 : dup_const(VECE, C))
1313 * Memory helpers that will be used by TCG generated code.
1315 #ifdef CONFIG_SOFTMMU
1316 /* Value zero-extended to tcg register size. */
1317 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1318 TCGMemOpIdx oi, uintptr_t retaddr);
1319 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1320 TCGMemOpIdx oi, uintptr_t retaddr);
1321 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1322 TCGMemOpIdx oi, uintptr_t retaddr);
1323 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1324 TCGMemOpIdx oi, uintptr_t retaddr);
1325 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1326 TCGMemOpIdx oi, uintptr_t retaddr);
1327 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1328 TCGMemOpIdx oi, uintptr_t retaddr);
1329 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1330 TCGMemOpIdx oi, uintptr_t retaddr);
1332 /* Value sign-extended to tcg register size. */
1333 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1334 TCGMemOpIdx oi, uintptr_t retaddr);
1335 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1336 TCGMemOpIdx oi, uintptr_t retaddr);
1337 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1338 TCGMemOpIdx oi, uintptr_t retaddr);
1339 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1340 TCGMemOpIdx oi, uintptr_t retaddr);
1341 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1342 TCGMemOpIdx oi, uintptr_t retaddr);
1344 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1345 TCGMemOpIdx oi, uintptr_t retaddr);
1346 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1347 TCGMemOpIdx oi, uintptr_t retaddr);
1348 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1349 TCGMemOpIdx oi, uintptr_t retaddr);
1350 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1351 TCGMemOpIdx oi, uintptr_t retaddr);
1352 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1353 TCGMemOpIdx oi, uintptr_t retaddr);
1354 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1355 TCGMemOpIdx oi, uintptr_t retaddr);
1356 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1357 TCGMemOpIdx oi, uintptr_t retaddr);
1359 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1360 TCGMemOpIdx oi, uintptr_t retaddr);
1361 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1362 TCGMemOpIdx oi, uintptr_t retaddr);
1363 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1364 TCGMemOpIdx oi, uintptr_t retaddr);
1365 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1366 TCGMemOpIdx oi, uintptr_t retaddr);
1367 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1368 TCGMemOpIdx oi, uintptr_t retaddr);
1369 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1370 TCGMemOpIdx oi, uintptr_t retaddr);
1371 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1372 TCGMemOpIdx oi, uintptr_t retaddr);
1374 /* Temporary aliases until backends are converted. */
1375 #ifdef TARGET_WORDS_BIGENDIAN
1376 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1377 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1378 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1379 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1380 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1381 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1382 # define helper_ret_stw_mmu helper_be_stw_mmu
1383 # define helper_ret_stl_mmu helper_be_stl_mmu
1384 # define helper_ret_stq_mmu helper_be_stq_mmu
1385 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1386 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1387 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1388 #else
1389 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1390 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1391 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1392 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1393 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1394 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1395 # define helper_ret_stw_mmu helper_le_stw_mmu
1396 # define helper_ret_stl_mmu helper_le_stl_mmu
1397 # define helper_ret_stq_mmu helper_le_stq_mmu
1398 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1399 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1400 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1401 #endif
1403 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1404 uint32_t cmpv, uint32_t newv,
1405 TCGMemOpIdx oi, uintptr_t retaddr);
1406 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1407 uint32_t cmpv, uint32_t newv,
1408 TCGMemOpIdx oi, uintptr_t retaddr);
1409 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1410 uint32_t cmpv, uint32_t newv,
1411 TCGMemOpIdx oi, uintptr_t retaddr);
1412 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1413 uint64_t cmpv, uint64_t newv,
1414 TCGMemOpIdx oi, uintptr_t retaddr);
1415 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1416 uint32_t cmpv, uint32_t newv,
1417 TCGMemOpIdx oi, uintptr_t retaddr);
1418 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1419 uint32_t cmpv, uint32_t newv,
1420 TCGMemOpIdx oi, uintptr_t retaddr);
1421 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1422 uint64_t cmpv, uint64_t newv,
1423 TCGMemOpIdx oi, uintptr_t retaddr);
1425 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
1426 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
1427 (CPUArchState *env, target_ulong addr, TYPE val, \
1428 TCGMemOpIdx oi, uintptr_t retaddr);
1430 #ifdef CONFIG_ATOMIC64
1431 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1432 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1433 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1434 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1435 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1436 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
1437 GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
1438 GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1439 #else
1440 #define GEN_ATOMIC_HELPER_ALL(NAME) \
1441 GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
1442 GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
1443 GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
1444 GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
1445 GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1446 #endif
1448 GEN_ATOMIC_HELPER_ALL(fetch_add)
1449 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1450 GEN_ATOMIC_HELPER_ALL(fetch_and)
1451 GEN_ATOMIC_HELPER_ALL(fetch_or)
1452 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1453 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1454 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1455 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1456 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1458 GEN_ATOMIC_HELPER_ALL(add_fetch)
1459 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1460 GEN_ATOMIC_HELPER_ALL(and_fetch)
1461 GEN_ATOMIC_HELPER_ALL(or_fetch)
1462 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1463 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1464 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1465 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1466 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1468 GEN_ATOMIC_HELPER_ALL(xchg)
1470 #undef GEN_ATOMIC_HELPER_ALL
1471 #undef GEN_ATOMIC_HELPER
1472 #endif /* CONFIG_SOFTMMU */
1475 * These aren't really a "proper" helpers because TCG cannot manage Int128.
1476 * However, use the same format as the others, for use by the backends.
1478 * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1479 * the ld/st functions are only defined if HAVE_ATOMIC128,
1480 * as defined by <qemu/atomic128.h>.
1482 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1483 Int128 cmpv, Int128 newv,
1484 TCGMemOpIdx oi, uintptr_t retaddr);
1485 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1486 Int128 cmpv, Int128 newv,
1487 TCGMemOpIdx oi, uintptr_t retaddr);
1489 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1490 TCGMemOpIdx oi, uintptr_t retaddr);
1491 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1492 TCGMemOpIdx oi, uintptr_t retaddr);
1493 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1494 TCGMemOpIdx oi, uintptr_t retaddr);
1495 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1496 TCGMemOpIdx oi, uintptr_t retaddr);
1498 #ifdef CONFIG_DEBUG_TCG
1499 void tcg_assert_listed_vecop(TCGOpcode);
1500 #else
1501 static inline void tcg_assert_listed_vecop(TCGOpcode op) { }
1502 #endif
1504 static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n)
1506 #ifdef CONFIG_DEBUG_TCG
1507 const TCGOpcode *o = tcg_ctx->vecop_list;
1508 tcg_ctx->vecop_list = n;
1509 return o;
1510 #else
1511 return NULL;
1512 #endif
1515 bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned);
1517 #endif /* TCG_H */