4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
15 #include "hw/timer/imx_epit.h"
16 #include "hw/misc/imx_ccm.h"
17 #include "qemu/main-loop.h"
19 #ifndef DEBUG_IMX_EPIT
20 #define DEBUG_IMX_EPIT 0
23 #define DPRINTF(fmt, args...) \
25 if (DEBUG_IMX_EPIT) { \
26 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \
31 static char const *imx_epit_reg_name(uint32_t reg
)
50 * Exact clock frequencies vary from board to board.
53 static const IMXClk imx_epit_clocks
[] = {
54 NOCLK
, /* 00 disabled */
55 CLK_IPG
, /* 01 ipg_clk, ~532MHz */
56 CLK_IPG
, /* 10 ipg_clk_highfreq */
57 CLK_32k
, /* 11 ipg_clk_32k -- ~32kHz */
61 * Update interrupt status
63 static void imx_epit_update_int(IMXEPITState
*s
)
65 if (s
->sr
&& (s
->cr
& CR_OCIEN
) && (s
->cr
& CR_EN
)) {
66 qemu_irq_raise(s
->irq
);
68 qemu_irq_lower(s
->irq
);
72 static void imx_epit_set_freq(IMXEPITState
*s
)
77 clksrc
= extract32(s
->cr
, CR_CLKSRC_SHIFT
, 2);
78 prescaler
= 1 + extract32(s
->cr
, CR_PRESCALE_SHIFT
, 12);
80 s
->freq
= imx_ccm_get_clock_frequency(s
->ccm
,
81 imx_epit_clocks
[clksrc
]) / prescaler
;
83 DPRINTF("Setting ptimer frequency to %u\n", s
->freq
);
86 ptimer_set_freq(s
->timer_reload
, s
->freq
);
87 ptimer_set_freq(s
->timer_cmp
, s
->freq
);
91 static void imx_epit_reset(DeviceState
*dev
)
93 IMXEPITState
*s
= IMX_EPIT(dev
);
96 * Soft reset doesn't touch some bits; hard reset clears them
98 s
->cr
&= (CR_EN
|CR_ENMOD
|CR_STOPEN
|CR_DOZEN
|CR_WAITEN
|CR_DBGEN
);
100 s
->lr
= EPIT_TIMER_MAX
;
103 /* stop both timers */
104 ptimer_stop(s
->timer_cmp
);
105 ptimer_stop(s
->timer_reload
);
106 /* compute new frequency */
107 imx_epit_set_freq(s
);
108 /* init both timers to EPIT_TIMER_MAX */
109 ptimer_set_limit(s
->timer_cmp
, EPIT_TIMER_MAX
, 1);
110 ptimer_set_limit(s
->timer_reload
, EPIT_TIMER_MAX
, 1);
111 if (s
->freq
&& (s
->cr
& CR_EN
)) {
112 /* if the timer is still enabled, restart it */
113 ptimer_run(s
->timer_reload
, 0);
117 static uint32_t imx_epit_update_count(IMXEPITState
*s
)
119 s
->cnt
= ptimer_get_count(s
->timer_reload
);
124 static uint64_t imx_epit_read(void *opaque
, hwaddr offset
, unsigned size
)
126 IMXEPITState
*s
= IMX_EPIT(opaque
);
127 uint32_t reg_value
= 0;
129 switch (offset
>> 2) {
130 case 0: /* Control Register */
134 case 1: /* Status Register */
138 case 2: /* LR - ticks*/
147 imx_epit_update_count(s
);
152 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
153 HWADDR_PRIx
"\n", TYPE_IMX_EPIT
, __func__
, offset
);
157 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset
>> 2), reg_value
);
162 static void imx_epit_reload_compare_timer(IMXEPITState
*s
)
164 if ((s
->cr
& (CR_EN
| CR_OCIEN
)) == (CR_EN
| CR_OCIEN
)) {
165 /* if the compare feature is on and timers are running */
166 uint32_t tmp
= imx_epit_update_count(s
);
169 /* It'll fire in this round of the timer */
171 } else { /* catch it next time around */
172 next
= tmp
- s
->cmp
+ ((s
->cr
& CR_RLD
) ? EPIT_TIMER_MAX
: s
->lr
);
174 ptimer_set_count(s
->timer_cmp
, next
);
178 static void imx_epit_write(void *opaque
, hwaddr offset
, uint64_t value
,
181 IMXEPITState
*s
= IMX_EPIT(opaque
);
184 DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset
>> 2),
187 switch (offset
>> 2) {
191 s
->cr
= value
& 0x03ffffff;
192 if (s
->cr
& CR_SWR
) {
193 /* handle the reset */
194 imx_epit_reset(DEVICE(s
));
196 imx_epit_set_freq(s
);
199 if (s
->freq
&& (s
->cr
& CR_EN
) && !(oldcr
& CR_EN
)) {
200 if (s
->cr
& CR_ENMOD
) {
201 if (s
->cr
& CR_RLD
) {
202 ptimer_set_limit(s
->timer_reload
, s
->lr
, 1);
203 ptimer_set_limit(s
->timer_cmp
, s
->lr
, 1);
205 ptimer_set_limit(s
->timer_reload
, EPIT_TIMER_MAX
, 1);
206 ptimer_set_limit(s
->timer_cmp
, EPIT_TIMER_MAX
, 1);
210 imx_epit_reload_compare_timer(s
);
211 ptimer_run(s
->timer_reload
, 0);
212 if (s
->cr
& CR_OCIEN
) {
213 ptimer_run(s
->timer_cmp
, 0);
215 ptimer_stop(s
->timer_cmp
);
217 } else if (!(s
->cr
& CR_EN
)) {
218 /* stop both timers */
219 ptimer_stop(s
->timer_reload
);
220 ptimer_stop(s
->timer_cmp
);
221 } else if (s
->cr
& CR_OCIEN
) {
222 if (!(oldcr
& CR_OCIEN
)) {
223 imx_epit_reload_compare_timer(s
);
224 ptimer_run(s
->timer_cmp
, 0);
227 ptimer_stop(s
->timer_cmp
);
231 case 1: /* SR - ACK*/
232 /* writing 1 to OCIF clear the OCIF bit */
235 imx_epit_update_int(s
);
239 case 2: /* LR - set ticks */
242 if (s
->cr
& CR_RLD
) {
243 /* Also set the limit if the LRD bit is set */
244 /* If IOVW bit is set then set the timer value */
245 ptimer_set_limit(s
->timer_reload
, s
->lr
, s
->cr
& CR_IOVW
);
246 ptimer_set_limit(s
->timer_cmp
, s
->lr
, 0);
247 } else if (s
->cr
& CR_IOVW
) {
248 /* If IOVW bit is set then set the timer value */
249 ptimer_set_count(s
->timer_reload
, s
->lr
);
252 imx_epit_reload_compare_timer(s
);
258 imx_epit_reload_compare_timer(s
);
263 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
264 HWADDR_PRIx
"\n", TYPE_IMX_EPIT
, __func__
, offset
);
269 static void imx_epit_cmp(void *opaque
)
271 IMXEPITState
*s
= IMX_EPIT(opaque
);
273 DPRINTF("sr was %d\n", s
->sr
);
276 imx_epit_update_int(s
);
279 static const MemoryRegionOps imx_epit_ops
= {
280 .read
= imx_epit_read
,
281 .write
= imx_epit_write
,
282 .endianness
= DEVICE_NATIVE_ENDIAN
,
285 static const VMStateDescription vmstate_imx_timer_epit
= {
286 .name
= TYPE_IMX_EPIT
,
288 .minimum_version_id
= 2,
289 .fields
= (VMStateField
[]) {
290 VMSTATE_UINT32(cr
, IMXEPITState
),
291 VMSTATE_UINT32(sr
, IMXEPITState
),
292 VMSTATE_UINT32(lr
, IMXEPITState
),
293 VMSTATE_UINT32(cmp
, IMXEPITState
),
294 VMSTATE_UINT32(cnt
, IMXEPITState
),
295 VMSTATE_UINT32(freq
, IMXEPITState
),
296 VMSTATE_PTIMER(timer_reload
, IMXEPITState
),
297 VMSTATE_PTIMER(timer_cmp
, IMXEPITState
),
298 VMSTATE_END_OF_LIST()
302 static void imx_epit_realize(DeviceState
*dev
, Error
**errp
)
304 IMXEPITState
*s
= IMX_EPIT(dev
);
305 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
310 sysbus_init_irq(sbd
, &s
->irq
);
311 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_epit_ops
, s
, TYPE_IMX_EPIT
,
313 sysbus_init_mmio(sbd
, &s
->iomem
);
315 s
->timer_reload
= ptimer_init(NULL
);
317 bh
= qemu_bh_new(imx_epit_cmp
, s
);
318 s
->timer_cmp
= ptimer_init(bh
);
321 static void imx_epit_class_init(ObjectClass
*klass
, void *data
)
323 DeviceClass
*dc
= DEVICE_CLASS(klass
);
325 dc
->realize
= imx_epit_realize
;
326 dc
->reset
= imx_epit_reset
;
327 dc
->vmsd
= &vmstate_imx_timer_epit
;
328 dc
->desc
= "i.MX periodic timer";
331 static const TypeInfo imx_epit_info
= {
332 .name
= TYPE_IMX_EPIT
,
333 .parent
= TYPE_SYS_BUS_DEVICE
,
334 .instance_size
= sizeof(IMXEPITState
),
335 .class_init
= imx_epit_class_init
,
338 static void imx_epit_register_types(void)
340 type_register_static(&imx_epit_info
);
343 type_init(imx_epit_register_types
)