target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "cpu.h"
  27 #include "gdbstub.h"
  28 #include "host-utils.h"
  29 #include "hw/pc.h"
  30 #include "hw/apic.h"
  31 #include "ioport.h"
  32 #include "hyperv.h"
  33
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifndef BUS_MCEERR_AR
  48 #define BUS_MCEERR_AR 4
  49 #endif
  50 #ifndef BUS_MCEERR_AO
  51 #define BUS_MCEERR_AO 5
  52 #endif
  53
  54 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  55     KVM_CAP_INFO(SET_TSS_ADDR),
  56     KVM_CAP_INFO(EXT_CPUID),
  57     KVM_CAP_INFO(MP_STATE),
  58     KVM_CAP_LAST_INFO
  59 };
  60
  61 static bool has_msr_star;
  62 static bool has_msr_hsave_pa;
  63 static bool has_msr_tsc_deadline;
  64 static bool has_msr_async_pf_en;
  65 static bool has_msr_misc_enable;
  66 static int lm_capable_kernel;
  67
  68 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  69 {
  70     struct kvm_cpuid2 *cpuid;
  71     int r, size;
  72
  73     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  74     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  75     cpuid->nent = max;
  76     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  77     if (r == 0 && cpuid->nent >= max) {
  78         r = -E2BIG;
  79     }
  80     if (r < 0) {
  81         if (r == -E2BIG) {
  82             g_free(cpuid);
  83             return NULL;
  84         } else {
  85             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  86                     strerror(-r));
  87             exit(1);
  88         }
  89     }
  90     return cpuid;
  91 }
  92
  93 struct kvm_para_features {
  94     int cap;
  95     int feature;
  96 } para_features[] = {
  97     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
  98     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
  99     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 100     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 101     { -1, -1 }
 102 };
 103
 104 static int get_para_features(KVMState *s)
 105 {
 106     int i, features = 0;
 107
 108     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 109         if (kvm_check_extension(s, para_features[i].cap)) {
 110             features |= (1 << para_features[i].feature);
 111         }
 112     }
 113
 114     return features;
 115 }
 116
 117
 118 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 119                                       uint32_t index, int reg)
 120 {
 121     struct kvm_cpuid2 *cpuid;
 122     int i, max;
 123     uint32_t ret = 0;
 124     uint32_t cpuid_1_edx;
 125     int has_kvm_features = 0;
 126
 127     max = 1;
 128     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 129         max *= 2;
 130     }
 131
 132     for (i = 0; i < cpuid->nent; ++i) {
 133         if (cpuid->entries[i].function == function &&
 134             cpuid->entries[i].index == index) {
 135             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 136                 has_kvm_features = 1;
 137             }
 138             switch (reg) {
 139             case R_EAX:
 140                 ret = cpuid->entries[i].eax;
 141                 break;
 142             case R_EBX:
 143                 ret = cpuid->entries[i].ebx;
 144                 break;
 145             case R_ECX:
 146                 ret = cpuid->entries[i].ecx;
 147                 break;
 148             case R_EDX:
 149                 ret = cpuid->entries[i].edx;
 150                 switch (function) {
 151                 case 1:
 152                     /* KVM before 2.6.30 misreports the following features */
 153                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 154                     break;
 155                 case 0x80000001:
 156                     /* On Intel, kvm returns cpuid according to the Intel spec,
 157                      * so add missing bits according to the AMD spec:
 158                      */
 159                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 160                     ret |= cpuid_1_edx & 0x183f7ff;
 161                     break;
 162                 }
 163                 break;
 164             }
 165         }
 166     }
 167
 168     g_free(cpuid);
 169
 170     /* fallback for older kernels */
 171     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 172         ret = get_para_features(s);
 173     }
 174
 175     return ret;
 176 }
 177
 178 typedef struct HWPoisonPage {
 179     ram_addr_t ram_addr;
 180     QLIST_ENTRY(HWPoisonPage) list;
 181 } HWPoisonPage;
 182
 183 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 184     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 185
 186 static void kvm_unpoison_all(void *param)
 187 {
 188     HWPoisonPage *page, *next_page;
 189
 190     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 191         QLIST_REMOVE(page, list);
 192         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 193         g_free(page);
 194     }
 195 }
 196
 197 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 198 {
 199     HWPoisonPage *page;
 200
 201     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 202         if (page->ram_addr == ram_addr) {
 203             return;
 204         }
 205     }
 206     page = g_malloc(sizeof(HWPoisonPage));
 207     page->ram_addr = ram_addr;
 208     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 209 }
 210
 211 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 212                                      int *max_banks)
 213 {
 214     int r;
 215
 216     r = kvm_check_extension(s, KVM_CAP_MCE);
 217     if (r > 0) {
 218         *max_banks = r;
 219         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 220     }
 221     return -ENOSYS;
 222 }
 223
 224 static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code)
 225 {
 226     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 227                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 228     uint64_t mcg_status = MCG_STATUS_MCIP;
 229
 230     if (code == BUS_MCEERR_AR) {
 231         status |= MCI_STATUS_AR | 0x134;
 232         mcg_status |= MCG_STATUS_EIPV;
 233     } else {
 234         status |= 0xc0;
 235         mcg_status |= MCG_STATUS_RIPV;
 236     }
 237     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 238                        (MCM_ADDR_PHYS << 6) | 0xc,
 239                        cpu_x86_support_mca_broadcast(env) ?
 240                        MCE_INJECT_BROADCAST : 0);
 241 }
 242
 243 static void hardware_memory_error(void)
 244 {
 245     fprintf(stderr, "Hardware memory error!\n");
 246     exit(1);
 247 }
 248
 249 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 250 {
 251     ram_addr_t ram_addr;
 252     target_phys_addr_t paddr;
 253
 254     if ((env->mcg_cap & MCG_SER_P) && addr
 255         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 256         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 257             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 258             fprintf(stderr, "Hardware memory error for memory used by "
 259                     "QEMU itself instead of guest system!\n");
 260             /* Hope we are lucky for AO MCE */
 261             if (code == BUS_MCEERR_AO) {
 262                 return 0;
 263             } else {
 264                 hardware_memory_error();
 265             }
 266         }
 267         kvm_hwpoison_page_add(ram_addr);
 268         kvm_mce_inject(env, paddr, code);
 269     } else {
 270         if (code == BUS_MCEERR_AO) {
 271             return 0;
 272         } else if (code == BUS_MCEERR_AR) {
 273             hardware_memory_error();
 274         } else {
 275             return 1;
 276         }
 277     }
 278     return 0;
 279 }
 280
 281 int kvm_arch_on_sigbus(int code, void *addr)
 282 {
 283     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 284         ram_addr_t ram_addr;
 285         target_phys_addr_t paddr;
 286
 287         /* Hope we are lucky for AO MCE */
 288         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 289             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 290                                                 &paddr)) {
 291             fprintf(stderr, "Hardware memory error for memory used by "
 292                     "QEMU itself instead of guest system!: %p\n", addr);
 293             return 0;
 294         }
 295         kvm_hwpoison_page_add(ram_addr);
 296         kvm_mce_inject(first_cpu, paddr, code);
 297     } else {
 298         if (code == BUS_MCEERR_AO) {
 299             return 0;
 300         } else if (code == BUS_MCEERR_AR) {
 301             hardware_memory_error();
 302         } else {
 303             return 1;
 304         }
 305     }
 306     return 0;
 307 }
 308
 309 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 310 {
 311     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 312         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 313         struct kvm_x86_mce mce;
 314
 315         env->exception_injected = -1;
 316
 317         /*
 318          * There must be at least one bank in use if an MCE is pending.
 319          * Find it and use its values for the event injection.
 320          */
 321         for (bank = 0; bank < bank_num; bank++) {
 322             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 323                 break;
 324             }
 325         }
 326         assert(bank < bank_num);
 327
 328         mce.bank = bank;
 329         mce.status = env->mce_banks[bank * 4 + 1];
 330         mce.mcg_status = env->mcg_status;
 331         mce.addr = env->mce_banks[bank * 4 + 2];
 332         mce.misc = env->mce_banks[bank * 4 + 3];
 333
 334         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 335     }
 336     return 0;
 337 }
 338
 339 static void cpu_update_state(void *opaque, int running, RunState state)
 340 {
 341     CPUX86State *env = opaque;
 342
 343     if (running) {
 344         env->tsc_valid = false;
 345     }
 346 }
 347
 348 int kvm_arch_init_vcpu(CPUX86State *env)
 349 {
 350     struct {
 351         struct kvm_cpuid2 cpuid;
 352         struct kvm_cpuid_entry2 entries[100];
 353     } QEMU_PACKED cpuid_data;
 354     KVMState *s = env->kvm_state;
 355     uint32_t limit, i, j, cpuid_i;
 356     uint32_t unused;
 357     struct kvm_cpuid_entry2 *c;
 358     uint32_t signature[3];
 359     int r;
 360
 361     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 362
 363     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 364     j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER;
 365     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 366     env->cpuid_ext_features |= i;
 367     if (j && kvm_irqchip_in_kernel() &&
 368         kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 369         env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER;
 370     }
 371
 372     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 373                                                              0, R_EDX);
 374     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 375                                                              0, R_ECX);
 376     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 377                                                              0, R_EDX);
 378
 379     cpuid_i = 0;
 380
 381     /* Paravirtualization CPUIDs */
 382     c = &cpuid_data.entries[cpuid_i++];
 383     memset(c, 0, sizeof(*c));
 384     c->function = KVM_CPUID_SIGNATURE;
 385     if (!hyperv_enabled()) {
 386         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 387         c->eax = 0;
 388     } else {
 389         memcpy(signature, "Microsoft Hv", 12);
 390         c->eax = HYPERV_CPUID_MIN;
 391     }
 392     c->ebx = signature[0];
 393     c->ecx = signature[1];
 394     c->edx = signature[2];
 395
 396     c = &cpuid_data.entries[cpuid_i++];
 397     memset(c, 0, sizeof(*c));
 398     c->function = KVM_CPUID_FEATURES;
 399     c->eax = env->cpuid_kvm_features &
 400         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 401
 402     if (hyperv_enabled()) {
 403         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 404         c->eax = signature[0];
 405
 406         c = &cpuid_data.entries[cpuid_i++];
 407         memset(c, 0, sizeof(*c));
 408         c->function = HYPERV_CPUID_VERSION;
 409         c->eax = 0x00001bbc;
 410         c->ebx = 0x00060001;
 411
 412         c = &cpuid_data.entries[cpuid_i++];
 413         memset(c, 0, sizeof(*c));
 414         c->function = HYPERV_CPUID_FEATURES;
 415         if (hyperv_relaxed_timing_enabled()) {
 416             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 417         }
 418         if (hyperv_vapic_recommended()) {
 419             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 420             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 421         }
 422
 423         c = &cpuid_data.entries[cpuid_i++];
 424         memset(c, 0, sizeof(*c));
 425         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 426         if (hyperv_relaxed_timing_enabled()) {
 427             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 428         }
 429         if (hyperv_vapic_recommended()) {
 430             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 431         }
 432         c->ebx = hyperv_get_spinlock_retries();
 433
 434         c = &cpuid_data.entries[cpuid_i++];
 435         memset(c, 0, sizeof(*c));
 436         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 437         c->eax = 0x40;
 438         c->ebx = 0x40;
 439
 440         c = &cpuid_data.entries[cpuid_i++];
 441         memset(c, 0, sizeof(*c));
 442         c->function = KVM_CPUID_SIGNATURE_NEXT;
 443         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 444         c->eax = 0;
 445         c->ebx = signature[0];
 446         c->ecx = signature[1];
 447         c->edx = signature[2];
 448     }
 449
 450     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 451
 452     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 453
 454     for (i = 0; i <= limit; i++) {
 455         c = &cpuid_data.entries[cpuid_i++];
 456
 457         switch (i) {
 458         case 2: {
 459             /* Keep reading function 2 till all the input is received */
 460             int times;
 461
 462             c->function = i;
 463             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 464                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 465             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 466             times = c->eax & 0xff;
 467
 468             for (j = 1; j < times; ++j) {
 469                 c = &cpuid_data.entries[cpuid_i++];
 470                 c->function = i;
 471                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 472                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 473             }
 474             break;
 475         }
 476         case 4:
 477         case 0xb:
 478         case 0xd:
 479             for (j = 0; ; j++) {
 480                 if (i == 0xd && j == 64) {
 481                     break;
 482                 }
 483                 c->function = i;
 484                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 485                 c->index = j;
 486                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 487
 488                 if (i == 4 && c->eax == 0) {
 489                     break;
 490                 }
 491                 if (i == 0xb && !(c->ecx & 0xff00)) {
 492                     break;
 493                 }
 494                 if (i == 0xd && c->eax == 0) {
 495                     continue;
 496                 }
 497                 c = &cpuid_data.entries[cpuid_i++];
 498             }
 499             break;
 500         default:
 501             c->function = i;
 502             c->flags = 0;
 503             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 504             break;
 505         }
 506     }
 507     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 508
 509     for (i = 0x80000000; i <= limit; i++) {
 510         c = &cpuid_data.entries[cpuid_i++];
 511
 512         c->function = i;
 513         c->flags = 0;
 514         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 515     }
 516
 517     /* Call Centaur's CPUID instructions they are supported. */
 518     if (env->cpuid_xlevel2 > 0) {
 519         env->cpuid_ext4_features &=
 520             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 521         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 522
 523         for (i = 0xC0000000; i <= limit; i++) {
 524             c = &cpuid_data.entries[cpuid_i++];
 525
 526             c->function = i;
 527             c->flags = 0;
 528             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 529         }
 530     }
 531
 532     cpuid_data.cpuid.nent = cpuid_i;
 533
 534     if (((env->cpuid_version >> 8)&0xF) >= 6
 535         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 536         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 537         uint64_t mcg_cap;
 538         int banks;
 539         int ret;
 540
 541         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 542         if (ret < 0) {
 543             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 544             return ret;
 545         }
 546
 547         if (banks > MCE_BANKS_DEF) {
 548             banks = MCE_BANKS_DEF;
 549         }
 550         mcg_cap &= MCE_CAP_DEF;
 551         mcg_cap |= banks;
 552         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 553         if (ret < 0) {
 554             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 555             return ret;
 556         }
 557
 558         env->mcg_cap = mcg_cap;
 559     }
 560
 561     qemu_add_vm_change_state_handler(cpu_update_state, env);
 562
 563     cpuid_data.cpuid.padding = 0;
 564     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 565     if (r) {
 566         return r;
 567     }
 568
 569     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 570     if (r && env->tsc_khz) {
 571         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 572         if (r < 0) {
 573             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 574             return r;
 575         }
 576     }
 577
 578     if (kvm_has_xsave()) {
 579         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 580     }
 581
 582     return 0;
 583 }
 584
 585 void kvm_arch_reset_vcpu(CPUX86State *env)
 586 {
 587     X86CPU *cpu = x86_env_get_cpu(env);
 588
 589     env->exception_injected = -1;
 590     env->interrupt_injected = -1;
 591     env->xcr0 = 1;
 592     if (kvm_irqchip_in_kernel()) {
 593         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 594                                           KVM_MP_STATE_UNINITIALIZED;
 595     } else {
 596         env->mp_state = KVM_MP_STATE_RUNNABLE;
 597     }
 598 }
 599
 600 static int kvm_get_supported_msrs(KVMState *s)
 601 {
 602     static int kvm_supported_msrs;
 603     int ret = 0;
 604
 605     /* first time */
 606     if (kvm_supported_msrs == 0) {
 607         struct kvm_msr_list msr_list, *kvm_msr_list;
 608
 609         kvm_supported_msrs = -1;
 610
 611         /* Obtain MSR list from KVM.  These are the MSRs that we must
 612          * save/restore */
 613         msr_list.nmsrs = 0;
 614         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 615         if (ret < 0 && ret != -E2BIG) {
 616             return ret;
 617         }
 618         /* Old kernel modules had a bug and could write beyond the provided
 619            memory. Allocate at least a safe amount of 1K. */
 620         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 621                                               msr_list.nmsrs *
 622                                               sizeof(msr_list.indices[0])));
 623
 624         kvm_msr_list->nmsrs = msr_list.nmsrs;
 625         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 626         if (ret >= 0) {
 627             int i;
 628
 629             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 630                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 631                     has_msr_star = true;
 632                     continue;
 633                 }
 634                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 635                     has_msr_hsave_pa = true;
 636                     continue;
 637                 }
 638                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 639                     has_msr_tsc_deadline = true;
 640                     continue;
 641                 }
 642                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 643                     has_msr_misc_enable = true;
 644                     continue;
 645                 }
 646             }
 647         }
 648
 649         g_free(kvm_msr_list);
 650     }
 651
 652     return ret;
 653 }
 654
 655 int kvm_arch_init(KVMState *s)
 656 {
 657     QemuOptsList *list = qemu_find_opts("machine");
 658     uint64_t identity_base = 0xfffbc000;
 659     uint64_t shadow_mem;
 660     int ret;
 661     struct utsname utsname;
 662
 663     ret = kvm_get_supported_msrs(s);
 664     if (ret < 0) {
 665         return ret;
 666     }
 667
 668     uname(&utsname);
 669     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 670
 671     /*
 672      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 673      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 674      * Since these must be part of guest physical memory, we need to allocate
 675      * them, both by setting their start addresses in the kernel and by
 676      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 677      *
 678      * Older KVM versions may not support setting the identity map base. In
 679      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 680      * size.
 681      */
 682     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 683         /* Allows up to 16M BIOSes. */
 684         identity_base = 0xfeffc000;
 685
 686         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 687         if (ret < 0) {
 688             return ret;
 689         }
 690     }
 691
 692     /* Set TSS base one page after EPT identity map. */
 693     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 694     if (ret < 0) {
 695         return ret;
 696     }
 697
 698     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 699     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 700     if (ret < 0) {
 701         fprintf(stderr, "e820_add_entry() table is full\n");
 702         return ret;
 703     }
 704     qemu_register_reset(kvm_unpoison_all, NULL);
 705
 706     if (!QTAILQ_EMPTY(&list->head)) {
 707         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 708                                        "kvm_shadow_mem", -1);
 709         if (shadow_mem != -1) {
 710             shadow_mem /= 4096;
 711             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 712             if (ret < 0) {
 713                 return ret;
 714             }
 715         }
 716     }
 717     return 0;
 718 }
 719
 720 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 721 {
 722     lhs->selector = rhs->selector;
 723     lhs->base = rhs->base;
 724     lhs->limit = rhs->limit;
 725     lhs->type = 3;
 726     lhs->present = 1;
 727     lhs->dpl = 3;
 728     lhs->db = 0;
 729     lhs->s = 1;
 730     lhs->l = 0;
 731     lhs->g = 0;
 732     lhs->avl = 0;
 733     lhs->unusable = 0;
 734 }
 735
 736 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 737 {
 738     unsigned flags = rhs->flags;
 739     lhs->selector = rhs->selector;
 740     lhs->base = rhs->base;
 741     lhs->limit = rhs->limit;
 742     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 743     lhs->present = (flags & DESC_P_MASK) != 0;
 744     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 745     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 746     lhs->s = (flags & DESC_S_MASK) != 0;
 747     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 748     lhs->g = (flags & DESC_G_MASK) != 0;
 749     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 750     lhs->unusable = 0;
 751     lhs->padding = 0;
 752 }
 753
 754 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 755 {
 756     lhs->selector = rhs->selector;
 757     lhs->base = rhs->base;
 758     lhs->limit = rhs->limit;
 759     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 760                  (rhs->present * DESC_P_MASK) |
 761                  (rhs->dpl << DESC_DPL_SHIFT) |
 762                  (rhs->db << DESC_B_SHIFT) |
 763                  (rhs->s * DESC_S_MASK) |
 764                  (rhs->l << DESC_L_SHIFT) |
 765                  (rhs->g * DESC_G_MASK) |
 766                  (rhs->avl * DESC_AVL_MASK);
 767 }
 768
 769 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 770 {
 771     if (set) {
 772         *kvm_reg = *qemu_reg;
 773     } else {
 774         *qemu_reg = *kvm_reg;
 775     }
 776 }
 777
 778 static int kvm_getput_regs(CPUX86State *env, int set)
 779 {
 780     struct kvm_regs regs;
 781     int ret = 0;
 782
 783     if (!set) {
 784         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 785         if (ret < 0) {
 786             return ret;
 787         }
 788     }
 789
 790     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 791     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 792     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 793     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 794     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 795     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 796     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 797     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 798 #ifdef TARGET_X86_64
 799     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 800     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 801     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 802     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 803     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 804     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 805     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 806     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 807 #endif
 808
 809     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 810     kvm_getput_reg(&regs.rip, &env->eip, set);
 811
 812     if (set) {
 813         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 814     }
 815
 816     return ret;
 817 }
 818
 819 static int kvm_put_fpu(CPUX86State *env)
 820 {
 821     struct kvm_fpu fpu;
 822     int i;
 823
 824     memset(&fpu, 0, sizeof fpu);
 825     fpu.fsw = env->fpus & ~(7 << 11);
 826     fpu.fsw |= (env->fpstt & 7) << 11;
 827     fpu.fcw = env->fpuc;
 828     fpu.last_opcode = env->fpop;
 829     fpu.last_ip = env->fpip;
 830     fpu.last_dp = env->fpdp;
 831     for (i = 0; i < 8; ++i) {
 832         fpu.ftwx |= (!env->fptags[i]) << i;
 833     }
 834     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 835     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 836     fpu.mxcsr = env->mxcsr;
 837
 838     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 839 }
 840
 841 #define XSAVE_FCW_FSW     0
 842 #define XSAVE_FTW_FOP     1
 843 #define XSAVE_CWD_RIP     2
 844 #define XSAVE_CWD_RDP     4
 845 #define XSAVE_MXCSR       6
 846 #define XSAVE_ST_SPACE    8
 847 #define XSAVE_XMM_SPACE   40
 848 #define XSAVE_XSTATE_BV   128
 849 #define XSAVE_YMMH_SPACE  144
 850
 851 static int kvm_put_xsave(CPUX86State *env)
 852 {
 853     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 854     uint16_t cwd, swd, twd;
 855     int i, r;
 856
 857     if (!kvm_has_xsave()) {
 858         return kvm_put_fpu(env);
 859     }
 860
 861     memset(xsave, 0, sizeof(struct kvm_xsave));
 862     twd = 0;
 863     swd = env->fpus & ~(7 << 11);
 864     swd |= (env->fpstt & 7) << 11;
 865     cwd = env->fpuc;
 866     for (i = 0; i < 8; ++i) {
 867         twd |= (!env->fptags[i]) << i;
 868     }
 869     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 870     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 871     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 872     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 873     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 874             sizeof env->fpregs);
 875     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 876             sizeof env->xmm_regs);
 877     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 878     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 879     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 880             sizeof env->ymmh_regs);
 881     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 882     return r;
 883 }
 884
 885 static int kvm_put_xcrs(CPUX86State *env)
 886 {
 887     struct kvm_xcrs xcrs;
 888
 889     if (!kvm_has_xcrs()) {
 890         return 0;
 891     }
 892
 893     xcrs.nr_xcrs = 1;
 894     xcrs.flags = 0;
 895     xcrs.xcrs[0].xcr = 0;
 896     xcrs.xcrs[0].value = env->xcr0;
 897     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 898 }
 899
 900 static int kvm_put_sregs(CPUX86State *env)
 901 {
 902     struct kvm_sregs sregs;
 903
 904     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 905     if (env->interrupt_injected >= 0) {
 906         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 907                 (uint64_t)1 << (env->interrupt_injected % 64);
 908     }
 909
 910     if ((env->eflags & VM_MASK)) {
 911         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 912         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 913         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 914         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 915         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 916         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 917     } else {
 918         set_seg(&sregs.cs, &env->segs[R_CS]);
 919         set_seg(&sregs.ds, &env->segs[R_DS]);
 920         set_seg(&sregs.es, &env->segs[R_ES]);
 921         set_seg(&sregs.fs, &env->segs[R_FS]);
 922         set_seg(&sregs.gs, &env->segs[R_GS]);
 923         set_seg(&sregs.ss, &env->segs[R_SS]);
 924     }
 925
 926     set_seg(&sregs.tr, &env->tr);
 927     set_seg(&sregs.ldt, &env->ldt);
 928
 929     sregs.idt.limit = env->idt.limit;
 930     sregs.idt.base = env->idt.base;
 931     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 932     sregs.gdt.limit = env->gdt.limit;
 933     sregs.gdt.base = env->gdt.base;
 934     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 935
 936     sregs.cr0 = env->cr[0];
 937     sregs.cr2 = env->cr[2];
 938     sregs.cr3 = env->cr[3];
 939     sregs.cr4 = env->cr[4];
 940
 941     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 942     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 943
 944     sregs.efer = env->efer;
 945
 946     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 947 }
 948
 949 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 950                               uint32_t index, uint64_t value)
 951 {
 952     entry->index = index;
 953     entry->data = value;
 954 }
 955
 956 static int kvm_put_msrs(CPUX86State *env, int level)
 957 {
 958     struct {
 959         struct kvm_msrs info;
 960         struct kvm_msr_entry entries[100];
 961     } msr_data;
 962     struct kvm_msr_entry *msrs = msr_data.entries;
 963     int n = 0;
 964
 965     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 966     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 967     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 968     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 969     if (has_msr_star) {
 970         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 971     }
 972     if (has_msr_hsave_pa) {
 973         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 974     }
 975     if (has_msr_tsc_deadline) {
 976         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 977     }
 978     if (has_msr_misc_enable) {
 979         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 980                           env->msr_ia32_misc_enable);
 981     }
 982 #ifdef TARGET_X86_64
 983     if (lm_capable_kernel) {
 984         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 985         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 986         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 987         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 988     }
 989 #endif
 990     if (level == KVM_PUT_FULL_STATE) {
 991         /*
 992          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 993          * writeback. Until this is fixed, we only write the offset to SMP
 994          * guests after migration, desynchronizing the VCPUs, but avoiding
 995          * huge jump-backs that would occur without any writeback at all.
 996          */
 997         if (smp_cpus == 1 || env->tsc != 0) {
 998             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 999         }
1000     }
1001     /*
1002      * The following paravirtual MSRs have side effects on the guest or are
1003      * too heavy for normal writeback. Limit them to reset or full state
1004      * updates.
1005      */
1006     if (level >= KVM_PUT_RESET_STATE) {
1007         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1008                           env->system_time_msr);
1009         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1010         if (has_msr_async_pf_en) {
1011             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1012                               env->async_pf_en_msr);
1013         }
1014         if (hyperv_hypercall_available()) {
1015             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1016             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1017         }
1018         if (hyperv_vapic_recommended()) {
1019             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1020         }
1021     }
1022     if (env->mcg_cap) {
1023         int i;
1024
1025         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1026         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1027         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1028             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1029         }
1030     }
1031
1032     msr_data.info.nmsrs = n;
1033
1034     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1035
1036 }
1037
1038
1039 static int kvm_get_fpu(CPUX86State *env)
1040 {
1041     struct kvm_fpu fpu;
1042     int i, ret;
1043
1044     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1045     if (ret < 0) {
1046         return ret;
1047     }
1048
1049     env->fpstt = (fpu.fsw >> 11) & 7;
1050     env->fpus = fpu.fsw;
1051     env->fpuc = fpu.fcw;
1052     env->fpop = fpu.last_opcode;
1053     env->fpip = fpu.last_ip;
1054     env->fpdp = fpu.last_dp;
1055     for (i = 0; i < 8; ++i) {
1056         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1057     }
1058     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1059     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1060     env->mxcsr = fpu.mxcsr;
1061
1062     return 0;
1063 }
1064
1065 static int kvm_get_xsave(CPUX86State *env)
1066 {
1067     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1068     int ret, i;
1069     uint16_t cwd, swd, twd;
1070
1071     if (!kvm_has_xsave()) {
1072         return kvm_get_fpu(env);
1073     }
1074
1075     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1076     if (ret < 0) {
1077         return ret;
1078     }
1079
1080     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1081     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1082     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1083     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1084     env->fpstt = (swd >> 11) & 7;
1085     env->fpus = swd;
1086     env->fpuc = cwd;
1087     for (i = 0; i < 8; ++i) {
1088         env->fptags[i] = !((twd >> i) & 1);
1089     }
1090     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1091     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1092     env->mxcsr = xsave->region[XSAVE_MXCSR];
1093     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1094             sizeof env->fpregs);
1095     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1096             sizeof env->xmm_regs);
1097     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1098     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1099             sizeof env->ymmh_regs);
1100     return 0;
1101 }
1102
1103 static int kvm_get_xcrs(CPUX86State *env)
1104 {
1105     int i, ret;
1106     struct kvm_xcrs xcrs;
1107
1108     if (!kvm_has_xcrs()) {
1109         return 0;
1110     }
1111
1112     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1113     if (ret < 0) {
1114         return ret;
1115     }
1116
1117     for (i = 0; i < xcrs.nr_xcrs; i++) {
1118         /* Only support xcr0 now */
1119         if (xcrs.xcrs[0].xcr == 0) {
1120             env->xcr0 = xcrs.xcrs[0].value;
1121             break;
1122         }
1123     }
1124     return 0;
1125 }
1126
1127 static int kvm_get_sregs(CPUX86State *env)
1128 {
1129     struct kvm_sregs sregs;
1130     uint32_t hflags;
1131     int bit, i, ret;
1132
1133     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1134     if (ret < 0) {
1135         return ret;
1136     }
1137
1138     /* There can only be one pending IRQ set in the bitmap at a time, so try
1139        to find it and save its number instead (-1 for none). */
1140     env->interrupt_injected = -1;
1141     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1142         if (sregs.interrupt_bitmap[i]) {
1143             bit = ctz64(sregs.interrupt_bitmap[i]);
1144             env->interrupt_injected = i * 64 + bit;
1145             break;
1146         }
1147     }
1148
1149     get_seg(&env->segs[R_CS], &sregs.cs);
1150     get_seg(&env->segs[R_DS], &sregs.ds);
1151     get_seg(&env->segs[R_ES], &sregs.es);
1152     get_seg(&env->segs[R_FS], &sregs.fs);
1153     get_seg(&env->segs[R_GS], &sregs.gs);
1154     get_seg(&env->segs[R_SS], &sregs.ss);
1155
1156     get_seg(&env->tr, &sregs.tr);
1157     get_seg(&env->ldt, &sregs.ldt);
1158
1159     env->idt.limit = sregs.idt.limit;
1160     env->idt.base = sregs.idt.base;
1161     env->gdt.limit = sregs.gdt.limit;
1162     env->gdt.base = sregs.gdt.base;
1163
1164     env->cr[0] = sregs.cr0;
1165     env->cr[2] = sregs.cr2;
1166     env->cr[3] = sregs.cr3;
1167     env->cr[4] = sregs.cr4;
1168
1169     env->efer = sregs.efer;
1170
1171     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1172
1173 #define HFLAG_COPY_MASK \
1174     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1175        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1176        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1177        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1178
1179     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1180     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1181     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1182                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1183     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1184     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1185                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1186
1187     if (env->efer & MSR_EFER_LMA) {
1188         hflags |= HF_LMA_MASK;
1189     }
1190
1191     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1192         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1193     } else {
1194         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1195                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1196         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1197                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1198         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1199             !(hflags & HF_CS32_MASK)) {
1200             hflags |= HF_ADDSEG_MASK;
1201         } else {
1202             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1203                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1204         }
1205     }
1206     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1207
1208     return 0;
1209 }
1210
1211 static int kvm_get_msrs(CPUX86State *env)
1212 {
1213     struct {
1214         struct kvm_msrs info;
1215         struct kvm_msr_entry entries[100];
1216     } msr_data;
1217     struct kvm_msr_entry *msrs = msr_data.entries;
1218     int ret, i, n;
1219
1220     n = 0;
1221     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1222     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1223     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1224     msrs[n++].index = MSR_PAT;
1225     if (has_msr_star) {
1226         msrs[n++].index = MSR_STAR;
1227     }
1228     if (has_msr_hsave_pa) {
1229         msrs[n++].index = MSR_VM_HSAVE_PA;
1230     }
1231     if (has_msr_tsc_deadline) {
1232         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1233     }
1234     if (has_msr_misc_enable) {
1235         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1236     }
1237
1238     if (!env->tsc_valid) {
1239         msrs[n++].index = MSR_IA32_TSC;
1240         env->tsc_valid = !runstate_is_running();
1241     }
1242
1243 #ifdef TARGET_X86_64
1244     if (lm_capable_kernel) {
1245         msrs[n++].index = MSR_CSTAR;
1246         msrs[n++].index = MSR_KERNELGSBASE;
1247         msrs[n++].index = MSR_FMASK;
1248         msrs[n++].index = MSR_LSTAR;
1249     }
1250 #endif
1251     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1252     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1253     if (has_msr_async_pf_en) {
1254         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1255     }
1256
1257     if (env->mcg_cap) {
1258         msrs[n++].index = MSR_MCG_STATUS;
1259         msrs[n++].index = MSR_MCG_CTL;
1260         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1261             msrs[n++].index = MSR_MC0_CTL + i;
1262         }
1263     }
1264
1265     msr_data.info.nmsrs = n;
1266     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1267     if (ret < 0) {
1268         return ret;
1269     }
1270
1271     for (i = 0; i < ret; i++) {
1272         switch (msrs[i].index) {
1273         case MSR_IA32_SYSENTER_CS:
1274             env->sysenter_cs = msrs[i].data;
1275             break;
1276         case MSR_IA32_SYSENTER_ESP:
1277             env->sysenter_esp = msrs[i].data;
1278             break;
1279         case MSR_IA32_SYSENTER_EIP:
1280             env->sysenter_eip = msrs[i].data;
1281             break;
1282         case MSR_PAT:
1283             env->pat = msrs[i].data;
1284             break;
1285         case MSR_STAR:
1286             env->star = msrs[i].data;
1287             break;
1288 #ifdef TARGET_X86_64
1289         case MSR_CSTAR:
1290             env->cstar = msrs[i].data;
1291             break;
1292         case MSR_KERNELGSBASE:
1293             env->kernelgsbase = msrs[i].data;
1294             break;
1295         case MSR_FMASK:
1296             env->fmask = msrs[i].data;
1297             break;
1298         case MSR_LSTAR:
1299             env->lstar = msrs[i].data;
1300             break;
1301 #endif
1302         case MSR_IA32_TSC:
1303             env->tsc = msrs[i].data;
1304             break;
1305         case MSR_IA32_TSCDEADLINE:
1306             env->tsc_deadline = msrs[i].data;
1307             break;
1308         case MSR_VM_HSAVE_PA:
1309             env->vm_hsave = msrs[i].data;
1310             break;
1311         case MSR_KVM_SYSTEM_TIME:
1312             env->system_time_msr = msrs[i].data;
1313             break;
1314         case MSR_KVM_WALL_CLOCK:
1315             env->wall_clock_msr = msrs[i].data;
1316             break;
1317         case MSR_MCG_STATUS:
1318             env->mcg_status = msrs[i].data;
1319             break;
1320         case MSR_MCG_CTL:
1321             env->mcg_ctl = msrs[i].data;
1322             break;
1323         case MSR_IA32_MISC_ENABLE:
1324             env->msr_ia32_misc_enable = msrs[i].data;
1325             break;
1326         default:
1327             if (msrs[i].index >= MSR_MC0_CTL &&
1328                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1329                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1330             }
1331             break;
1332         case MSR_KVM_ASYNC_PF_EN:
1333             env->async_pf_en_msr = msrs[i].data;
1334             break;
1335         }
1336     }
1337
1338     return 0;
1339 }
1340
1341 static int kvm_put_mp_state(CPUX86State *env)
1342 {
1343     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1344
1345     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1346 }
1347
1348 static int kvm_get_mp_state(CPUX86State *env)
1349 {
1350     struct kvm_mp_state mp_state;
1351     int ret;
1352
1353     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1354     if (ret < 0) {
1355         return ret;
1356     }
1357     env->mp_state = mp_state.mp_state;
1358     if (kvm_irqchip_in_kernel()) {
1359         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1360     }
1361     return 0;
1362 }
1363
1364 static int kvm_get_apic(CPUX86State *env)
1365 {
1366     DeviceState *apic = env->apic_state;
1367     struct kvm_lapic_state kapic;
1368     int ret;
1369
1370     if (apic && kvm_irqchip_in_kernel()) {
1371         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1372         if (ret < 0) {
1373             return ret;
1374         }
1375
1376         kvm_get_apic_state(apic, &kapic);
1377     }
1378     return 0;
1379 }
1380
1381 static int kvm_put_apic(CPUX86State *env)
1382 {
1383     DeviceState *apic = env->apic_state;
1384     struct kvm_lapic_state kapic;
1385
1386     if (apic && kvm_irqchip_in_kernel()) {
1387         kvm_put_apic_state(apic, &kapic);
1388
1389         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1390     }
1391     return 0;
1392 }
1393
1394 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1395 {
1396     struct kvm_vcpu_events events;
1397
1398     if (!kvm_has_vcpu_events()) {
1399         return 0;
1400     }
1401
1402     events.exception.injected = (env->exception_injected >= 0);
1403     events.exception.nr = env->exception_injected;
1404     events.exception.has_error_code = env->has_error_code;
1405     events.exception.error_code = env->error_code;
1406     events.exception.pad = 0;
1407
1408     events.interrupt.injected = (env->interrupt_injected >= 0);
1409     events.interrupt.nr = env->interrupt_injected;
1410     events.interrupt.soft = env->soft_interrupt;
1411
1412     events.nmi.injected = env->nmi_injected;
1413     events.nmi.pending = env->nmi_pending;
1414     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1415     events.nmi.pad = 0;
1416
1417     events.sipi_vector = env->sipi_vector;
1418
1419     events.flags = 0;
1420     if (level >= KVM_PUT_RESET_STATE) {
1421         events.flags |=
1422             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1423     }
1424
1425     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1426 }
1427
1428 static int kvm_get_vcpu_events(CPUX86State *env)
1429 {
1430     struct kvm_vcpu_events events;
1431     int ret;
1432
1433     if (!kvm_has_vcpu_events()) {
1434         return 0;
1435     }
1436
1437     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1438     if (ret < 0) {
1439        return ret;
1440     }
1441     env->exception_injected =
1442        events.exception.injected ? events.exception.nr : -1;
1443     env->has_error_code = events.exception.has_error_code;
1444     env->error_code = events.exception.error_code;
1445
1446     env->interrupt_injected =
1447         events.interrupt.injected ? events.interrupt.nr : -1;
1448     env->soft_interrupt = events.interrupt.soft;
1449
1450     env->nmi_injected = events.nmi.injected;
1451     env->nmi_pending = events.nmi.pending;
1452     if (events.nmi.masked) {
1453         env->hflags2 |= HF2_NMI_MASK;
1454     } else {
1455         env->hflags2 &= ~HF2_NMI_MASK;
1456     }
1457
1458     env->sipi_vector = events.sipi_vector;
1459
1460     return 0;
1461 }
1462
1463 static int kvm_guest_debug_workarounds(CPUX86State *env)
1464 {
1465     int ret = 0;
1466     unsigned long reinject_trap = 0;
1467
1468     if (!kvm_has_vcpu_events()) {
1469         if (env->exception_injected == 1) {
1470             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1471         } else if (env->exception_injected == 3) {
1472             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1473         }
1474         env->exception_injected = -1;
1475     }
1476
1477     /*
1478      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1479      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1480      * by updating the debug state once again if single-stepping is on.
1481      * Another reason to call kvm_update_guest_debug here is a pending debug
1482      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1483      * reinject them via SET_GUEST_DEBUG.
1484      */
1485     if (reinject_trap ||
1486         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1487         ret = kvm_update_guest_debug(env, reinject_trap);
1488     }
1489     return ret;
1490 }
1491
1492 static int kvm_put_debugregs(CPUX86State *env)
1493 {
1494     struct kvm_debugregs dbgregs;
1495     int i;
1496
1497     if (!kvm_has_debugregs()) {
1498         return 0;
1499     }
1500
1501     for (i = 0; i < 4; i++) {
1502         dbgregs.db[i] = env->dr[i];
1503     }
1504     dbgregs.dr6 = env->dr[6];
1505     dbgregs.dr7 = env->dr[7];
1506     dbgregs.flags = 0;
1507
1508     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1509 }
1510
1511 static int kvm_get_debugregs(CPUX86State *env)
1512 {
1513     struct kvm_debugregs dbgregs;
1514     int i, ret;
1515
1516     if (!kvm_has_debugregs()) {
1517         return 0;
1518     }
1519
1520     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1521     if (ret < 0) {
1522         return ret;
1523     }
1524     for (i = 0; i < 4; i++) {
1525         env->dr[i] = dbgregs.db[i];
1526     }
1527     env->dr[4] = env->dr[6] = dbgregs.dr6;
1528     env->dr[5] = env->dr[7] = dbgregs.dr7;
1529
1530     return 0;
1531 }
1532
1533 int kvm_arch_put_registers(CPUX86State *env, int level)
1534 {
1535     int ret;
1536
1537     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1538
1539     ret = kvm_getput_regs(env, 1);
1540     if (ret < 0) {
1541         return ret;
1542     }
1543     ret = kvm_put_xsave(env);
1544     if (ret < 0) {
1545         return ret;
1546     }
1547     ret = kvm_put_xcrs(env);
1548     if (ret < 0) {
1549         return ret;
1550     }
1551     ret = kvm_put_sregs(env);
1552     if (ret < 0) {
1553         return ret;
1554     }
1555     /* must be before kvm_put_msrs */
1556     ret = kvm_inject_mce_oldstyle(env);
1557     if (ret < 0) {
1558         return ret;
1559     }
1560     ret = kvm_put_msrs(env, level);
1561     if (ret < 0) {
1562         return ret;
1563     }
1564     if (level >= KVM_PUT_RESET_STATE) {
1565         ret = kvm_put_mp_state(env);
1566         if (ret < 0) {
1567             return ret;
1568         }
1569         ret = kvm_put_apic(env);
1570         if (ret < 0) {
1571             return ret;
1572         }
1573     }
1574     ret = kvm_put_vcpu_events(env, level);
1575     if (ret < 0) {
1576         return ret;
1577     }
1578     ret = kvm_put_debugregs(env);
1579     if (ret < 0) {
1580         return ret;
1581     }
1582     /* must be last */
1583     ret = kvm_guest_debug_workarounds(env);
1584     if (ret < 0) {
1585         return ret;
1586     }
1587     return 0;
1588 }
1589
1590 int kvm_arch_get_registers(CPUX86State *env)
1591 {
1592     int ret;
1593
1594     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1595
1596     ret = kvm_getput_regs(env, 0);
1597     if (ret < 0) {
1598         return ret;
1599     }
1600     ret = kvm_get_xsave(env);
1601     if (ret < 0) {
1602         return ret;
1603     }
1604     ret = kvm_get_xcrs(env);
1605     if (ret < 0) {
1606         return ret;
1607     }
1608     ret = kvm_get_sregs(env);
1609     if (ret < 0) {
1610         return ret;
1611     }
1612     ret = kvm_get_msrs(env);
1613     if (ret < 0) {
1614         return ret;
1615     }
1616     ret = kvm_get_mp_state(env);
1617     if (ret < 0) {
1618         return ret;
1619     }
1620     ret = kvm_get_apic(env);
1621     if (ret < 0) {
1622         return ret;
1623     }
1624     ret = kvm_get_vcpu_events(env);
1625     if (ret < 0) {
1626         return ret;
1627     }
1628     ret = kvm_get_debugregs(env);
1629     if (ret < 0) {
1630         return ret;
1631     }
1632     return 0;
1633 }
1634
1635 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1636 {
1637     int ret;
1638
1639     /* Inject NMI */
1640     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1641         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1642         DPRINTF("injected NMI\n");
1643         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1644         if (ret < 0) {
1645             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1646                     strerror(-ret));
1647         }
1648     }
1649
1650     if (!kvm_irqchip_in_kernel()) {
1651         /* Force the VCPU out of its inner loop to process any INIT requests
1652          * or pending TPR access reports. */
1653         if (env->interrupt_request &
1654             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1655             env->exit_request = 1;
1656         }
1657
1658         /* Try to inject an interrupt if the guest can accept it */
1659         if (run->ready_for_interrupt_injection &&
1660             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1661             (env->eflags & IF_MASK)) {
1662             int irq;
1663
1664             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1665             irq = cpu_get_pic_interrupt(env);
1666             if (irq >= 0) {
1667                 struct kvm_interrupt intr;
1668
1669                 intr.irq = irq;
1670                 DPRINTF("injected interrupt %d\n", irq);
1671                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1672                 if (ret < 0) {
1673                     fprintf(stderr,
1674                             "KVM: injection failed, interrupt lost (%s)\n",
1675                             strerror(-ret));
1676                 }
1677             }
1678         }
1679
1680         /* If we have an interrupt but the guest is not ready to receive an
1681          * interrupt, request an interrupt window exit.  This will
1682          * cause a return to userspace as soon as the guest is ready to
1683          * receive interrupts. */
1684         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1685             run->request_interrupt_window = 1;
1686         } else {
1687             run->request_interrupt_window = 0;
1688         }
1689
1690         DPRINTF("setting tpr\n");
1691         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1692     }
1693 }
1694
1695 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1696 {
1697     if (run->if_flag) {
1698         env->eflags |= IF_MASK;
1699     } else {
1700         env->eflags &= ~IF_MASK;
1701     }
1702     cpu_set_apic_tpr(env->apic_state, run->cr8);
1703     cpu_set_apic_base(env->apic_state, run->apic_base);
1704 }
1705
1706 int kvm_arch_process_async_events(CPUX86State *env)
1707 {
1708     X86CPU *cpu = x86_env_get_cpu(env);
1709
1710     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1711         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1712         assert(env->mcg_cap);
1713
1714         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1715
1716         kvm_cpu_synchronize_state(env);
1717
1718         if (env->exception_injected == EXCP08_DBLE) {
1719             /* this means triple fault */
1720             qemu_system_reset_request();
1721             env->exit_request = 1;
1722             return 0;
1723         }
1724         env->exception_injected = EXCP12_MCHK;
1725         env->has_error_code = 0;
1726
1727         env->halted = 0;
1728         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1729             env->mp_state = KVM_MP_STATE_RUNNABLE;
1730         }
1731     }
1732
1733     if (kvm_irqchip_in_kernel()) {
1734         return 0;
1735     }
1736
1737     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1738         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1739         apic_poll_irq(env->apic_state);
1740     }
1741     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1742          (env->eflags & IF_MASK)) ||
1743         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1744         env->halted = 0;
1745     }
1746     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1747         kvm_cpu_synchronize_state(env);
1748         do_cpu_init(cpu);
1749     }
1750     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1751         kvm_cpu_synchronize_state(env);
1752         do_cpu_sipi(cpu);
1753     }
1754     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1755         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1756         kvm_cpu_synchronize_state(env);
1757         apic_handle_tpr_access_report(env->apic_state, env->eip,
1758                                       env->tpr_access_type);
1759     }
1760
1761     return env->halted;
1762 }
1763
1764 static int kvm_handle_halt(CPUX86State *env)
1765 {
1766     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1767           (env->eflags & IF_MASK)) &&
1768         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1769         env->halted = 1;
1770         return EXCP_HLT;
1771     }
1772
1773     return 0;
1774 }
1775
1776 static int kvm_handle_tpr_access(CPUX86State *env)
1777 {
1778     struct kvm_run *run = env->kvm_run;
1779
1780     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1781                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1782                                                            : TPR_ACCESS_READ);
1783     return 1;
1784 }
1785
1786 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1787 {
1788     static const uint8_t int3 = 0xcc;
1789
1790     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1791         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1792         return -EINVAL;
1793     }
1794     return 0;
1795 }
1796
1797 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1798 {
1799     uint8_t int3;
1800
1801     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1802         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1803         return -EINVAL;
1804     }
1805     return 0;
1806 }
1807
1808 static struct {
1809     target_ulong addr;
1810     int len;
1811     int type;
1812 } hw_breakpoint[4];
1813
1814 static int nb_hw_breakpoint;
1815
1816 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1817 {
1818     int n;
1819
1820     for (n = 0; n < nb_hw_breakpoint; n++) {
1821         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1822             (hw_breakpoint[n].len == len || len == -1)) {
1823             return n;
1824         }
1825     }
1826     return -1;
1827 }
1828
1829 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1830                                   target_ulong len, int type)
1831 {
1832     switch (type) {
1833     case GDB_BREAKPOINT_HW:
1834         len = 1;
1835         break;
1836     case GDB_WATCHPOINT_WRITE:
1837     case GDB_WATCHPOINT_ACCESS:
1838         switch (len) {
1839         case 1:
1840             break;
1841         case 2:
1842         case 4:
1843         case 8:
1844             if (addr & (len - 1)) {
1845                 return -EINVAL;
1846             }
1847             break;
1848         default:
1849             return -EINVAL;
1850         }
1851         break;
1852     default:
1853         return -ENOSYS;
1854     }
1855
1856     if (nb_hw_breakpoint == 4) {
1857         return -ENOBUFS;
1858     }
1859     if (find_hw_breakpoint(addr, len, type) >= 0) {
1860         return -EEXIST;
1861     }
1862     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1863     hw_breakpoint[nb_hw_breakpoint].len = len;
1864     hw_breakpoint[nb_hw_breakpoint].type = type;
1865     nb_hw_breakpoint++;
1866
1867     return 0;
1868 }
1869
1870 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1871                                   target_ulong len, int type)
1872 {
1873     int n;
1874
1875     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1876     if (n < 0) {
1877         return -ENOENT;
1878     }
1879     nb_hw_breakpoint--;
1880     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1881
1882     return 0;
1883 }
1884
1885 void kvm_arch_remove_all_hw_breakpoints(void)
1886 {
1887     nb_hw_breakpoint = 0;
1888 }
1889
1890 static CPUWatchpoint hw_watchpoint;
1891
1892 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1893 {
1894     int ret = 0;
1895     int n;
1896
1897     if (arch_info->exception == 1) {
1898         if (arch_info->dr6 & (1 << 14)) {
1899             if (cpu_single_env->singlestep_enabled) {
1900                 ret = EXCP_DEBUG;
1901             }
1902         } else {
1903             for (n = 0; n < 4; n++) {
1904                 if (arch_info->dr6 & (1 << n)) {
1905                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1906                     case 0x0:
1907                         ret = EXCP_DEBUG;
1908                         break;
1909                     case 0x1:
1910                         ret = EXCP_DEBUG;
1911                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1912                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1913                         hw_watchpoint.flags = BP_MEM_WRITE;
1914                         break;
1915                     case 0x3:
1916                         ret = EXCP_DEBUG;
1917                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1918                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1919                         hw_watchpoint.flags = BP_MEM_ACCESS;
1920                         break;
1921                     }
1922                 }
1923             }
1924         }
1925     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1926         ret = EXCP_DEBUG;
1927     }
1928     if (ret == 0) {
1929         cpu_synchronize_state(cpu_single_env);
1930         assert(cpu_single_env->exception_injected == -1);
1931
1932         /* pass to guest */
1933         cpu_single_env->exception_injected = arch_info->exception;
1934         cpu_single_env->has_error_code = 0;
1935     }
1936
1937     return ret;
1938 }
1939
1940 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1941 {
1942     const uint8_t type_code[] = {
1943         [GDB_BREAKPOINT_HW] = 0x0,
1944         [GDB_WATCHPOINT_WRITE] = 0x1,
1945         [GDB_WATCHPOINT_ACCESS] = 0x3
1946     };
1947     const uint8_t len_code[] = {
1948         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1949     };
1950     int n;
1951
1952     if (kvm_sw_breakpoints_active(env)) {
1953         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1954     }
1955     if (nb_hw_breakpoint > 0) {
1956         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1957         dbg->arch.debugreg[7] = 0x0600;
1958         for (n = 0; n < nb_hw_breakpoint; n++) {
1959             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1960             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1961                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1962                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1963         }
1964     }
1965 }
1966
1967 static bool host_supports_vmx(void)
1968 {
1969     uint32_t ecx, unused;
1970
1971     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1972     return ecx & CPUID_EXT_VMX;
1973 }
1974
1975 #define VMX_INVALID_GUEST_STATE 0x80000021
1976
1977 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
1978 {
1979     uint64_t code;
1980     int ret;
1981
1982     switch (run->exit_reason) {
1983     case KVM_EXIT_HLT:
1984         DPRINTF("handle_hlt\n");
1985         ret = kvm_handle_halt(env);
1986         break;
1987     case KVM_EXIT_SET_TPR:
1988         ret = 0;
1989         break;
1990     case KVM_EXIT_TPR_ACCESS:
1991         ret = kvm_handle_tpr_access(env);
1992         break;
1993     case KVM_EXIT_FAIL_ENTRY:
1994         code = run->fail_entry.hardware_entry_failure_reason;
1995         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1996                 code);
1997         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1998             fprintf(stderr,
1999                     "\nIf you're running a guest on an Intel machine without "
2000                         "unrestricted mode\n"
2001                     "support, the failure can be most likely due to the guest "
2002                         "entering an invalid\n"
2003                     "state for Intel VT. For example, the guest maybe running "
2004                         "in big real mode\n"
2005                     "which is not supported on less recent Intel processors."
2006                         "\n\n");
2007         }
2008         ret = -1;
2009         break;
2010     case KVM_EXIT_EXCEPTION:
2011         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2012                 run->ex.exception, run->ex.error_code);
2013         ret = -1;
2014         break;
2015     case KVM_EXIT_DEBUG:
2016         DPRINTF("kvm_exit_debug\n");
2017         ret = kvm_handle_debug(&run->debug.arch);
2018         break;
2019     default:
2020         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2021         ret = -1;
2022         break;
2023     }
2024
2025     return ret;
2026 }
2027
2028 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2029 {
2030     kvm_cpu_synchronize_state(env);
2031     return !(env->cr[0] & CR0_PE_MASK) ||
2032            ((env->segs[R_CS].selector  & 3) != 3);
2033 }
2034
2035 void kvm_arch_init_irq_routing(KVMState *s)
2036 {
2037     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2038         /* If kernel can't do irq routing, interrupt source
2039          * override 0->2 cannot be set up as required by HPET.
2040          * So we have to disable it.
2041          */
2042         no_hpet = 1;
2043     }
2044 }