2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #ifdef HOST_WORDS_BIGENDIAN
33 #if TCG_TARGET_REG_BITS == 32
34 # define LO_OFF (MIPS_BE * 4)
35 # define HI_OFF (4 - LO_OFF)
37 /* To assert at compile-time that these values are never used
38 for TCG_TARGET_REG_BITS == 64. */
40 # define LO_OFF link_error()
41 # define HI_OFF link_error()
44 #ifdef CONFIG_DEBUG_TCG
45 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
81 #define TCG_TMP0 TCG_REG_AT
82 #define TCG_TMP1 TCG_REG_T9
83 #define TCG_TMP2 TCG_REG_T8
84 #define TCG_TMP3 TCG_REG_T7
86 #ifndef CONFIG_SOFTMMU
87 #define TCG_GUEST_BASE_REG TCG_REG_S1
90 /* check if we really need so many registers :P */
91 static const int tcg_target_reg_alloc_order
[] = {
92 /* Call saved registers. */
103 /* Call clobbered registers. */
113 /* Argument registers, opposite order of allocation. */
124 static const TCGReg tcg_target_call_iarg_regs
[] = {
129 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
137 static const TCGReg tcg_target_call_oarg_regs
[2] = {
142 static tcg_insn_unit
*tb_ret_addr
;
143 static tcg_insn_unit
*bswap32_addr
;
144 static tcg_insn_unit
*bswap32u_addr
;
145 static tcg_insn_unit
*bswap64_addr
;
147 static inline uint32_t reloc_pc16_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
149 /* Let the compiler perform the right-shift as part of the arithmetic. */
150 ptrdiff_t disp
= target
- (pc
+ 1);
151 tcg_debug_assert(disp
== (int16_t)disp
);
152 return disp
& 0xffff;
155 static inline void reloc_pc16(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
157 *pc
= deposit32(*pc
, 0, 16, reloc_pc16_val(pc
, target
));
160 static inline uint32_t reloc_26_val(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
162 tcg_debug_assert((((uintptr_t)pc
^ (uintptr_t)target
) & 0xf0000000) == 0);
163 return ((uintptr_t)target
>> 2) & 0x3ffffff;
166 static inline void reloc_26(tcg_insn_unit
*pc
, tcg_insn_unit
*target
)
168 *pc
= deposit32(*pc
, 0, 26, reloc_26_val(pc
, target
));
171 static bool patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
172 intptr_t value
, intptr_t addend
)
174 tcg_debug_assert(type
== R_MIPS_PC16
);
175 tcg_debug_assert(addend
== 0);
176 reloc_pc16(code_ptr
, (tcg_insn_unit
*)value
);
180 #define TCG_CT_CONST_ZERO 0x100
181 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
182 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
183 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
184 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
185 #define TCG_CT_CONST_WSZ 0x2000 /* word size */
187 static inline bool is_p2m1(tcg_target_long val
)
189 return val
&& ((val
+ 1) & val
) == 0;
192 /* parse target specific constraints */
193 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
194 const char *ct_str
, TCGType type
)
198 ct
->ct
|= TCG_CT_REG
;
199 ct
->u
.regs
= 0xffffffff;
201 case 'L': /* qemu_ld input arg constraint */
202 ct
->ct
|= TCG_CT_REG
;
203 ct
->u
.regs
= 0xffffffff;
204 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A0
);
205 #if defined(CONFIG_SOFTMMU)
206 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
207 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A2
);
211 case 'S': /* qemu_st constraint */
212 ct
->ct
|= TCG_CT_REG
;
213 ct
->u
.regs
= 0xffffffff;
214 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A0
);
215 #if defined(CONFIG_SOFTMMU)
216 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
217 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A2
);
218 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A3
);
220 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_A1
);
225 ct
->ct
|= TCG_CT_CONST_U16
;
228 ct
->ct
|= TCG_CT_CONST_S16
;
231 ct
->ct
|= TCG_CT_CONST_P2M1
;
234 ct
->ct
|= TCG_CT_CONST_N16
;
237 ct
->ct
|= TCG_CT_CONST_WSZ
;
240 /* We are cheating a bit here, using the fact that the register
241 ZERO is also the register number 0. Hence there is no need
242 to check for const_args in each instruction. */
243 ct
->ct
|= TCG_CT_CONST_ZERO
;
251 /* test if a constant matches the constraint */
252 static inline int tcg_target_const_match(tcg_target_long val
, TCGType type
,
253 const TCGArgConstraint
*arg_ct
)
257 if (ct
& TCG_CT_CONST
) {
259 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
261 } else if ((ct
& TCG_CT_CONST_U16
) && val
== (uint16_t)val
) {
263 } else if ((ct
& TCG_CT_CONST_S16
) && val
== (int16_t)val
) {
265 } else if ((ct
& TCG_CT_CONST_N16
) && val
>= -32767 && val
<= 32767) {
267 } else if ((ct
& TCG_CT_CONST_P2M1
)
268 && use_mips32r2_instructions
&& is_p2m1(val
)) {
270 } else if ((ct
& TCG_CT_CONST_WSZ
)
271 && val
== (type
== TCG_TYPE_I32
? 32 : 64)) {
277 /* instruction opcodes */
283 OPC_BLEZ
= 006 << 26,
284 OPC_BGTZ
= 007 << 26,
285 OPC_ADDIU
= 011 << 26,
286 OPC_SLTI
= 012 << 26,
287 OPC_SLTIU
= 013 << 26,
288 OPC_ANDI
= 014 << 26,
290 OPC_XORI
= 016 << 26,
292 OPC_DADDIU
= 031 << 26,
305 OPC_SPECIAL
= 000 << 26,
306 OPC_SLL
= OPC_SPECIAL
| 000,
307 OPC_SRL
= OPC_SPECIAL
| 002,
308 OPC_ROTR
= OPC_SPECIAL
| 002 | (1 << 21),
309 OPC_SRA
= OPC_SPECIAL
| 003,
310 OPC_SLLV
= OPC_SPECIAL
| 004,
311 OPC_SRLV
= OPC_SPECIAL
| 006,
312 OPC_ROTRV
= OPC_SPECIAL
| 006 | 0100,
313 OPC_SRAV
= OPC_SPECIAL
| 007,
314 OPC_JR_R5
= OPC_SPECIAL
| 010,
315 OPC_JALR
= OPC_SPECIAL
| 011,
316 OPC_MOVZ
= OPC_SPECIAL
| 012,
317 OPC_MOVN
= OPC_SPECIAL
| 013,
318 OPC_SYNC
= OPC_SPECIAL
| 017,
319 OPC_MFHI
= OPC_SPECIAL
| 020,
320 OPC_MFLO
= OPC_SPECIAL
| 022,
321 OPC_DSLLV
= OPC_SPECIAL
| 024,
322 OPC_DSRLV
= OPC_SPECIAL
| 026,
323 OPC_DROTRV
= OPC_SPECIAL
| 026 | 0100,
324 OPC_DSRAV
= OPC_SPECIAL
| 027,
325 OPC_MULT
= OPC_SPECIAL
| 030,
326 OPC_MUL_R6
= OPC_SPECIAL
| 030 | 0200,
327 OPC_MUH
= OPC_SPECIAL
| 030 | 0300,
328 OPC_MULTU
= OPC_SPECIAL
| 031,
329 OPC_MULU
= OPC_SPECIAL
| 031 | 0200,
330 OPC_MUHU
= OPC_SPECIAL
| 031 | 0300,
331 OPC_DIV
= OPC_SPECIAL
| 032,
332 OPC_DIV_R6
= OPC_SPECIAL
| 032 | 0200,
333 OPC_MOD
= OPC_SPECIAL
| 032 | 0300,
334 OPC_DIVU
= OPC_SPECIAL
| 033,
335 OPC_DIVU_R6
= OPC_SPECIAL
| 033 | 0200,
336 OPC_MODU
= OPC_SPECIAL
| 033 | 0300,
337 OPC_DMULT
= OPC_SPECIAL
| 034,
338 OPC_DMUL
= OPC_SPECIAL
| 034 | 0200,
339 OPC_DMUH
= OPC_SPECIAL
| 034 | 0300,
340 OPC_DMULTU
= OPC_SPECIAL
| 035,
341 OPC_DMULU
= OPC_SPECIAL
| 035 | 0200,
342 OPC_DMUHU
= OPC_SPECIAL
| 035 | 0300,
343 OPC_DDIV
= OPC_SPECIAL
| 036,
344 OPC_DDIV_R6
= OPC_SPECIAL
| 036 | 0200,
345 OPC_DMOD
= OPC_SPECIAL
| 036 | 0300,
346 OPC_DDIVU
= OPC_SPECIAL
| 037,
347 OPC_DDIVU_R6
= OPC_SPECIAL
| 037 | 0200,
348 OPC_DMODU
= OPC_SPECIAL
| 037 | 0300,
349 OPC_ADDU
= OPC_SPECIAL
| 041,
350 OPC_SUBU
= OPC_SPECIAL
| 043,
351 OPC_AND
= OPC_SPECIAL
| 044,
352 OPC_OR
= OPC_SPECIAL
| 045,
353 OPC_XOR
= OPC_SPECIAL
| 046,
354 OPC_NOR
= OPC_SPECIAL
| 047,
355 OPC_SLT
= OPC_SPECIAL
| 052,
356 OPC_SLTU
= OPC_SPECIAL
| 053,
357 OPC_DADDU
= OPC_SPECIAL
| 055,
358 OPC_DSUBU
= OPC_SPECIAL
| 057,
359 OPC_SELEQZ
= OPC_SPECIAL
| 065,
360 OPC_SELNEZ
= OPC_SPECIAL
| 067,
361 OPC_DSLL
= OPC_SPECIAL
| 070,
362 OPC_DSRL
= OPC_SPECIAL
| 072,
363 OPC_DROTR
= OPC_SPECIAL
| 072 | (1 << 21),
364 OPC_DSRA
= OPC_SPECIAL
| 073,
365 OPC_DSLL32
= OPC_SPECIAL
| 074,
366 OPC_DSRL32
= OPC_SPECIAL
| 076,
367 OPC_DROTR32
= OPC_SPECIAL
| 076 | (1 << 21),
368 OPC_DSRA32
= OPC_SPECIAL
| 077,
369 OPC_CLZ_R6
= OPC_SPECIAL
| 0120,
370 OPC_DCLZ_R6
= OPC_SPECIAL
| 0122,
372 OPC_REGIMM
= 001 << 26,
373 OPC_BLTZ
= OPC_REGIMM
| (000 << 16),
374 OPC_BGEZ
= OPC_REGIMM
| (001 << 16),
376 OPC_SPECIAL2
= 034 << 26,
377 OPC_MUL_R5
= OPC_SPECIAL2
| 002,
378 OPC_CLZ
= OPC_SPECIAL2
| 040,
379 OPC_DCLZ
= OPC_SPECIAL2
| 044,
381 OPC_SPECIAL3
= 037 << 26,
382 OPC_EXT
= OPC_SPECIAL3
| 000,
383 OPC_DEXTM
= OPC_SPECIAL3
| 001,
384 OPC_DEXTU
= OPC_SPECIAL3
| 002,
385 OPC_DEXT
= OPC_SPECIAL3
| 003,
386 OPC_INS
= OPC_SPECIAL3
| 004,
387 OPC_DINSM
= OPC_SPECIAL3
| 005,
388 OPC_DINSU
= OPC_SPECIAL3
| 006,
389 OPC_DINS
= OPC_SPECIAL3
| 007,
390 OPC_WSBH
= OPC_SPECIAL3
| 00240,
391 OPC_DSBH
= OPC_SPECIAL3
| 00244,
392 OPC_DSHD
= OPC_SPECIAL3
| 00544,
393 OPC_SEB
= OPC_SPECIAL3
| 02040,
394 OPC_SEH
= OPC_SPECIAL3
| 03040,
396 /* MIPS r6 doesn't have JR, JALR should be used instead */
397 OPC_JR
= use_mips32r6_instructions
? OPC_JALR
: OPC_JR_R5
,
400 * MIPS r6 replaces MUL with an alternative encoding which is
401 * backwards-compatible at the assembly level.
403 OPC_MUL
= use_mips32r6_instructions
? OPC_MUL_R6
: OPC_MUL_R5
,
405 /* MIPS r6 introduced names for weaker variants of SYNC. These are
406 backward compatible to previous architecture revisions. */
407 OPC_SYNC_WMB
= OPC_SYNC
| 0x04 << 5,
408 OPC_SYNC_MB
= OPC_SYNC
| 0x10 << 5,
409 OPC_SYNC_ACQUIRE
= OPC_SYNC
| 0x11 << 5,
410 OPC_SYNC_RELEASE
= OPC_SYNC
| 0x12 << 5,
411 OPC_SYNC_RMB
= OPC_SYNC
| 0x13 << 5,
413 /* Aliases for convenience. */
414 ALIAS_PADD
= sizeof(void *) == 4 ? OPC_ADDU
: OPC_DADDU
,
415 ALIAS_PADDI
= sizeof(void *) == 4 ? OPC_ADDIU
: OPC_DADDIU
,
416 ALIAS_TSRL
= TARGET_LONG_BITS
== 32 || TCG_TARGET_REG_BITS
== 32
417 ? OPC_SRL
: OPC_DSRL
,
423 static inline void tcg_out_opc_reg(TCGContext
*s
, MIPSInsn opc
,
424 TCGReg rd
, TCGReg rs
, TCGReg rt
)
429 inst
|= (rs
& 0x1F) << 21;
430 inst
|= (rt
& 0x1F) << 16;
431 inst
|= (rd
& 0x1F) << 11;
438 static inline void tcg_out_opc_imm(TCGContext
*s
, MIPSInsn opc
,
439 TCGReg rt
, TCGReg rs
, TCGArg imm
)
444 inst
|= (rs
& 0x1F) << 21;
445 inst
|= (rt
& 0x1F) << 16;
446 inst
|= (imm
& 0xffff);
453 static inline void tcg_out_opc_bf(TCGContext
*s
, MIPSInsn opc
, TCGReg rt
,
454 TCGReg rs
, int msb
, int lsb
)
459 inst
|= (rs
& 0x1F) << 21;
460 inst
|= (rt
& 0x1F) << 16;
461 inst
|= (msb
& 0x1F) << 11;
462 inst
|= (lsb
& 0x1F) << 6;
466 static inline void tcg_out_opc_bf64(TCGContext
*s
, MIPSInsn opc
, MIPSInsn opm
,
467 MIPSInsn oph
, TCGReg rt
, TCGReg rs
,
474 } else if (msb
>= 32) {
478 tcg_out_opc_bf(s
, opc
, rt
, rs
, msb
, lsb
);
484 static inline void tcg_out_opc_br(TCGContext
*s
, MIPSInsn opc
,
485 TCGReg rt
, TCGReg rs
)
487 tcg_out_opc_imm(s
, opc
, rt
, rs
, 0);
493 static inline void tcg_out_opc_sa(TCGContext
*s
, MIPSInsn opc
,
494 TCGReg rd
, TCGReg rt
, TCGArg sa
)
499 inst
|= (rt
& 0x1F) << 16;
500 inst
|= (rd
& 0x1F) << 11;
501 inst
|= (sa
& 0x1F) << 6;
506 static void tcg_out_opc_sa64(TCGContext
*s
, MIPSInsn opc1
, MIPSInsn opc2
,
507 TCGReg rd
, TCGReg rt
, TCGArg sa
)
511 inst
= (sa
& 32 ? opc2
: opc1
);
512 inst
|= (rt
& 0x1F) << 16;
513 inst
|= (rd
& 0x1F) << 11;
514 inst
|= (sa
& 0x1F) << 6;
520 * Returns true if the branch was in range and the insn was emitted.
522 static bool tcg_out_opc_jmp(TCGContext
*s
, MIPSInsn opc
, void *target
)
524 uintptr_t dest
= (uintptr_t)target
;
525 uintptr_t from
= (uintptr_t)s
->code_ptr
+ 4;
528 /* The pc-region branch happens within the 256MB region of
529 the delay slot (thus the +4). */
530 if ((from
^ dest
) & -(1 << 28)) {
533 tcg_debug_assert((dest
& 3) == 0);
536 inst
|= (dest
>> 2) & 0x3ffffff;
541 static inline void tcg_out_nop(TCGContext
*s
)
546 static inline void tcg_out_dsll(TCGContext
*s
, TCGReg rd
, TCGReg rt
, TCGArg sa
)
548 tcg_out_opc_sa64(s
, OPC_DSLL
, OPC_DSLL32
, rd
, rt
, sa
);
551 static inline void tcg_out_dsrl(TCGContext
*s
, TCGReg rd
, TCGReg rt
, TCGArg sa
)
553 tcg_out_opc_sa64(s
, OPC_DSRL
, OPC_DSRL32
, rd
, rt
, sa
);
556 static inline void tcg_out_dsra(TCGContext
*s
, TCGReg rd
, TCGReg rt
, TCGArg sa
)
558 tcg_out_opc_sa64(s
, OPC_DSRA
, OPC_DSRA32
, rd
, rt
, sa
);
561 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
562 TCGReg ret
, TCGReg arg
)
564 /* Simple reg-reg move, optimising out the 'do nothing' case */
566 tcg_out_opc_reg(s
, OPC_OR
, ret
, arg
, TCG_REG_ZERO
);
570 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
571 TCGReg ret
, tcg_target_long arg
)
573 if (TCG_TARGET_REG_BITS
== 64 && type
== TCG_TYPE_I32
) {
576 if (arg
== (int16_t)arg
) {
577 tcg_out_opc_imm(s
, OPC_ADDIU
, ret
, TCG_REG_ZERO
, arg
);
580 if (arg
== (uint16_t)arg
) {
581 tcg_out_opc_imm(s
, OPC_ORI
, ret
, TCG_REG_ZERO
, arg
);
584 if (TCG_TARGET_REG_BITS
== 32 || arg
== (int32_t)arg
) {
585 tcg_out_opc_imm(s
, OPC_LUI
, ret
, TCG_REG_ZERO
, arg
>> 16);
587 tcg_out_movi(s
, TCG_TYPE_I32
, ret
, arg
>> 31 >> 1);
588 if (arg
& 0xffff0000ull
) {
589 tcg_out_dsll(s
, ret
, ret
, 16);
590 tcg_out_opc_imm(s
, OPC_ORI
, ret
, ret
, arg
>> 16);
591 tcg_out_dsll(s
, ret
, ret
, 16);
593 tcg_out_dsll(s
, ret
, ret
, 32);
597 tcg_out_opc_imm(s
, OPC_ORI
, ret
, ret
, arg
& 0xffff);
601 static inline void tcg_out_bswap16(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
603 if (use_mips32r2_instructions
) {
604 tcg_out_opc_reg(s
, OPC_WSBH
, ret
, 0, arg
);
606 /* ret and arg can't be register at */
607 if (ret
== TCG_TMP0
|| arg
== TCG_TMP0
) {
611 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP0
, arg
, 8);
612 tcg_out_opc_sa(s
, OPC_SLL
, ret
, arg
, 8);
613 tcg_out_opc_imm(s
, OPC_ANDI
, ret
, ret
, 0xff00);
614 tcg_out_opc_reg(s
, OPC_OR
, ret
, ret
, TCG_TMP0
);
618 static inline void tcg_out_bswap16s(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
620 if (use_mips32r2_instructions
) {
621 tcg_out_opc_reg(s
, OPC_WSBH
, ret
, 0, arg
);
622 tcg_out_opc_reg(s
, OPC_SEH
, ret
, 0, ret
);
624 /* ret and arg can't be register at */
625 if (ret
== TCG_TMP0
|| arg
== TCG_TMP0
) {
629 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP0
, arg
, 8);
630 tcg_out_opc_sa(s
, OPC_SLL
, ret
, arg
, 24);
631 tcg_out_opc_sa(s
, OPC_SRA
, ret
, ret
, 16);
632 tcg_out_opc_reg(s
, OPC_OR
, ret
, ret
, TCG_TMP0
);
636 static void tcg_out_bswap_subr(TCGContext
*s
, tcg_insn_unit
*sub
)
638 bool ok
= tcg_out_opc_jmp(s
, OPC_JAL
, sub
);
639 tcg_debug_assert(ok
);
642 static void tcg_out_bswap32(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
644 if (use_mips32r2_instructions
) {
645 tcg_out_opc_reg(s
, OPC_WSBH
, ret
, 0, arg
);
646 tcg_out_opc_sa(s
, OPC_ROTR
, ret
, ret
, 16);
648 tcg_out_bswap_subr(s
, bswap32_addr
);
649 /* delay slot -- never omit the insn, like tcg_out_mov might. */
650 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP0
, arg
, TCG_REG_ZERO
);
651 tcg_out_mov(s
, TCG_TYPE_I32
, ret
, TCG_TMP3
);
655 static void tcg_out_bswap32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
657 if (use_mips32r2_instructions
) {
658 tcg_out_opc_reg(s
, OPC_DSBH
, ret
, 0, arg
);
659 tcg_out_opc_reg(s
, OPC_DSHD
, ret
, 0, ret
);
660 tcg_out_dsrl(s
, ret
, ret
, 32);
662 tcg_out_bswap_subr(s
, bswap32u_addr
);
663 /* delay slot -- never omit the insn, like tcg_out_mov might. */
664 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP0
, arg
, TCG_REG_ZERO
);
665 tcg_out_mov(s
, TCG_TYPE_I32
, ret
, TCG_TMP3
);
669 static void tcg_out_bswap64(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
671 if (use_mips32r2_instructions
) {
672 tcg_out_opc_reg(s
, OPC_DSBH
, ret
, 0, arg
);
673 tcg_out_opc_reg(s
, OPC_DSHD
, ret
, 0, ret
);
675 tcg_out_bswap_subr(s
, bswap64_addr
);
676 /* delay slot -- never omit the insn, like tcg_out_mov might. */
677 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP0
, arg
, TCG_REG_ZERO
);
678 tcg_out_mov(s
, TCG_TYPE_I32
, ret
, TCG_TMP3
);
682 static inline void tcg_out_ext8s(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
684 if (use_mips32r2_instructions
) {
685 tcg_out_opc_reg(s
, OPC_SEB
, ret
, 0, arg
);
687 tcg_out_opc_sa(s
, OPC_SLL
, ret
, arg
, 24);
688 tcg_out_opc_sa(s
, OPC_SRA
, ret
, ret
, 24);
692 static inline void tcg_out_ext16s(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
694 if (use_mips32r2_instructions
) {
695 tcg_out_opc_reg(s
, OPC_SEH
, ret
, 0, arg
);
697 tcg_out_opc_sa(s
, OPC_SLL
, ret
, arg
, 16);
698 tcg_out_opc_sa(s
, OPC_SRA
, ret
, ret
, 16);
702 static inline void tcg_out_ext32u(TCGContext
*s
, TCGReg ret
, TCGReg arg
)
704 if (use_mips32r2_instructions
) {
705 tcg_out_opc_bf(s
, OPC_DEXT
, ret
, arg
, 31, 0);
707 tcg_out_dsll(s
, ret
, arg
, 32);
708 tcg_out_dsrl(s
, ret
, ret
, 32);
712 static void tcg_out_ldst(TCGContext
*s
, MIPSInsn opc
, TCGReg data
,
713 TCGReg addr
, intptr_t ofs
)
717 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_TMP0
, ofs
- lo
);
718 if (addr
!= TCG_REG_ZERO
) {
719 tcg_out_opc_reg(s
, ALIAS_PADD
, TCG_TMP0
, TCG_TMP0
, addr
);
723 tcg_out_opc_imm(s
, opc
, data
, addr
, lo
);
726 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
727 TCGReg arg1
, intptr_t arg2
)
729 MIPSInsn opc
= OPC_LD
;
730 if (TCG_TARGET_REG_BITS
== 32 || type
== TCG_TYPE_I32
) {
733 tcg_out_ldst(s
, opc
, arg
, arg1
, arg2
);
736 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
737 TCGReg arg1
, intptr_t arg2
)
739 MIPSInsn opc
= OPC_SD
;
740 if (TCG_TARGET_REG_BITS
== 32 || type
== TCG_TYPE_I32
) {
743 tcg_out_ldst(s
, opc
, arg
, arg1
, arg2
);
746 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
747 TCGReg base
, intptr_t ofs
)
750 tcg_out_st(s
, type
, TCG_REG_ZERO
, base
, ofs
);
756 static void tcg_out_addsub2(TCGContext
*s
, TCGReg rl
, TCGReg rh
, TCGReg al
,
757 TCGReg ah
, TCGArg bl
, TCGArg bh
, bool cbl
,
758 bool cbh
, bool is_sub
)
760 TCGReg th
= TCG_TMP1
;
762 /* If we have a negative constant such that negating it would
763 make the high part zero, we can (usually) eliminate one insn. */
764 if (cbl
&& cbh
&& bh
== -1 && bl
!= 0) {
770 /* By operating on the high part first, we get to use the final
771 carry operation to move back from the temporary. */
773 tcg_out_opc_reg(s
, (is_sub
? OPC_SUBU
: OPC_ADDU
), th
, ah
, bh
);
774 } else if (bh
!= 0 || ah
== rl
) {
775 tcg_out_opc_imm(s
, OPC_ADDIU
, th
, ah
, (is_sub
? -bh
: bh
));
780 /* Note that tcg optimization should eliminate the bl == 0 case. */
783 tcg_out_opc_imm(s
, OPC_SLTIU
, TCG_TMP0
, al
, bl
);
784 tcg_out_opc_imm(s
, OPC_ADDIU
, rl
, al
, -bl
);
786 tcg_out_opc_reg(s
, OPC_SLTU
, TCG_TMP0
, al
, bl
);
787 tcg_out_opc_reg(s
, OPC_SUBU
, rl
, al
, bl
);
789 tcg_out_opc_reg(s
, OPC_SUBU
, rh
, th
, TCG_TMP0
);
792 tcg_out_opc_imm(s
, OPC_ADDIU
, rl
, al
, bl
);
793 tcg_out_opc_imm(s
, OPC_SLTIU
, TCG_TMP0
, rl
, bl
);
794 } else if (rl
== al
&& rl
== bl
) {
795 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP0
, al
, TCG_TARGET_REG_BITS
- 1);
796 tcg_out_opc_reg(s
, OPC_ADDU
, rl
, al
, bl
);
798 tcg_out_opc_reg(s
, OPC_ADDU
, rl
, al
, bl
);
799 tcg_out_opc_reg(s
, OPC_SLTU
, TCG_TMP0
, rl
, (rl
== bl
? al
: bl
));
801 tcg_out_opc_reg(s
, OPC_ADDU
, rh
, th
, TCG_TMP0
);
805 /* Bit 0 set if inversion required; bit 1 set if swapping required. */
806 #define MIPS_CMP_INV 1
807 #define MIPS_CMP_SWAP 2
809 static const uint8_t mips_cmp_map
[16] = {
812 [TCG_COND_GE
] = MIPS_CMP_INV
,
813 [TCG_COND_GEU
] = MIPS_CMP_INV
,
814 [TCG_COND_LE
] = MIPS_CMP_INV
| MIPS_CMP_SWAP
,
815 [TCG_COND_LEU
] = MIPS_CMP_INV
| MIPS_CMP_SWAP
,
816 [TCG_COND_GT
] = MIPS_CMP_SWAP
,
817 [TCG_COND_GTU
] = MIPS_CMP_SWAP
,
820 static void tcg_out_setcond(TCGContext
*s
, TCGCond cond
, TCGReg ret
,
821 TCGReg arg1
, TCGReg arg2
)
823 MIPSInsn s_opc
= OPC_SLTU
;
829 tcg_out_opc_reg(s
, OPC_XOR
, ret
, arg1
, arg2
);
832 tcg_out_opc_imm(s
, OPC_SLTIU
, ret
, arg1
, 1);
837 tcg_out_opc_reg(s
, OPC_XOR
, ret
, arg1
, arg2
);
840 tcg_out_opc_reg(s
, OPC_SLTU
, ret
, TCG_REG_ZERO
, arg1
);
854 cmp_map
= mips_cmp_map
[cond
];
855 if (cmp_map
& MIPS_CMP_SWAP
) {
860 tcg_out_opc_reg(s
, s_opc
, ret
, arg1
, arg2
);
861 if (cmp_map
& MIPS_CMP_INV
) {
862 tcg_out_opc_imm(s
, OPC_XORI
, ret
, ret
, 1);
872 static void tcg_out_brcond(TCGContext
*s
, TCGCond cond
, TCGReg arg1
,
873 TCGReg arg2
, TCGLabel
*l
)
875 static const MIPSInsn b_zero
[16] = {
876 [TCG_COND_LT
] = OPC_BLTZ
,
877 [TCG_COND_GT
] = OPC_BGTZ
,
878 [TCG_COND_LE
] = OPC_BLEZ
,
879 [TCG_COND_GE
] = OPC_BGEZ
,
882 MIPSInsn s_opc
= OPC_SLTU
;
899 b_opc
= b_zero
[cond
];
911 cmp_map
= mips_cmp_map
[cond
];
912 if (cmp_map
& MIPS_CMP_SWAP
) {
917 tcg_out_opc_reg(s
, s_opc
, TCG_TMP0
, arg1
, arg2
);
918 b_opc
= (cmp_map
& MIPS_CMP_INV
? OPC_BEQ
: OPC_BNE
);
928 tcg_out_opc_br(s
, b_opc
, arg1
, arg2
);
930 reloc_pc16(s
->code_ptr
- 1, l
->u
.value_ptr
);
932 tcg_out_reloc(s
, s
->code_ptr
- 1, R_MIPS_PC16
, l
, 0);
937 static TCGReg
tcg_out_reduce_eq2(TCGContext
*s
, TCGReg tmp0
, TCGReg tmp1
,
938 TCGReg al
, TCGReg ah
,
939 TCGReg bl
, TCGReg bh
)
941 /* Merge highpart comparison into AH. */
944 tcg_out_opc_reg(s
, OPC_XOR
, tmp0
, ah
, bh
);
950 /* Merge lowpart comparison into AL. */
953 tcg_out_opc_reg(s
, OPC_XOR
, tmp1
, al
, bl
);
959 /* Merge high and low part comparisons into AL. */
962 tcg_out_opc_reg(s
, OPC_OR
, tmp0
, ah
, al
);
971 static void tcg_out_setcond2(TCGContext
*s
, TCGCond cond
, TCGReg ret
,
972 TCGReg al
, TCGReg ah
, TCGReg bl
, TCGReg bh
)
974 TCGReg tmp0
= TCG_TMP0
;
977 tcg_debug_assert(ret
!= TCG_TMP0
);
978 if (ret
== ah
|| ret
== bh
) {
979 tcg_debug_assert(ret
!= TCG_TMP1
);
986 tmp1
= tcg_out_reduce_eq2(s
, tmp0
, tmp1
, al
, ah
, bl
, bh
);
987 tcg_out_setcond(s
, cond
, ret
, tmp1
, TCG_REG_ZERO
);
991 tcg_out_setcond(s
, TCG_COND_EQ
, tmp0
, ah
, bh
);
992 tcg_out_setcond(s
, tcg_unsigned_cond(cond
), tmp1
, al
, bl
);
993 tcg_out_opc_reg(s
, OPC_AND
, tmp1
, tmp1
, tmp0
);
994 tcg_out_setcond(s
, tcg_high_cond(cond
), tmp0
, ah
, bh
);
995 tcg_out_opc_reg(s
, OPC_OR
, ret
, tmp1
, tmp0
);
1000 static void tcg_out_brcond2(TCGContext
*s
, TCGCond cond
, TCGReg al
, TCGReg ah
,
1001 TCGReg bl
, TCGReg bh
, TCGLabel
*l
)
1003 TCGCond b_cond
= TCG_COND_NE
;
1004 TCGReg tmp
= TCG_TMP1
;
1006 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches.
1007 With setcond, we emit between 3 and 10 insns and only 1 branch,
1008 which ought to get better branch prediction. */
1013 tmp
= tcg_out_reduce_eq2(s
, TCG_TMP0
, TCG_TMP1
, al
, ah
, bl
, bh
);
1017 /* Minimize code size by preferring a compare not requiring INV. */
1018 if (mips_cmp_map
[cond
] & MIPS_CMP_INV
) {
1019 cond
= tcg_invert_cond(cond
);
1020 b_cond
= TCG_COND_EQ
;
1022 tcg_out_setcond2(s
, cond
, tmp
, al
, ah
, bl
, bh
);
1026 tcg_out_brcond(s
, b_cond
, tmp
, TCG_REG_ZERO
, l
);
1029 static void tcg_out_movcond(TCGContext
*s
, TCGCond cond
, TCGReg ret
,
1030 TCGReg c1
, TCGReg c2
, TCGReg v1
, TCGReg v2
)
1034 /* If one of the values is zero, put it last to match SEL*Z instructions */
1035 if (use_mips32r6_instructions
&& v1
== 0) {
1038 cond
= tcg_invert_cond(cond
);
1047 tcg_out_opc_reg(s
, OPC_XOR
, TCG_TMP0
, c1
, c2
);
1053 /* Minimize code size by preferring a compare not requiring INV. */
1054 if (mips_cmp_map
[cond
] & MIPS_CMP_INV
) {
1055 cond
= tcg_invert_cond(cond
);
1058 tcg_out_setcond(s
, cond
, TCG_TMP0
, c1
, c2
);
1063 if (use_mips32r6_instructions
) {
1064 MIPSInsn m_opc_t
= eqz
? OPC_SELEQZ
: OPC_SELNEZ
;
1065 MIPSInsn m_opc_f
= eqz
? OPC_SELNEZ
: OPC_SELEQZ
;
1068 tcg_out_opc_reg(s
, m_opc_f
, TCG_TMP1
, v2
, c1
);
1070 tcg_out_opc_reg(s
, m_opc_t
, ret
, v1
, c1
);
1072 tcg_out_opc_reg(s
, OPC_OR
, ret
, ret
, TCG_TMP1
);
1075 MIPSInsn m_opc
= eqz
? OPC_MOVZ
: OPC_MOVN
;
1077 tcg_out_opc_reg(s
, m_opc
, ret
, v1
, c1
);
1079 /* This should be guaranteed via constraints */
1080 tcg_debug_assert(v2
== ret
);
1084 static void tcg_out_call_int(TCGContext
*s
, tcg_insn_unit
*arg
, bool tail
)
1086 /* Note that the ABI requires the called function's address to be
1087 loaded into T9, even if a direct branch is in range. */
1088 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_T9
, (uintptr_t)arg
);
1090 /* But do try a direct branch, allowing the cpu better insn prefetch. */
1092 if (!tcg_out_opc_jmp(s
, OPC_J
, arg
)) {
1093 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_REG_T9
, 0);
1096 if (!tcg_out_opc_jmp(s
, OPC_JAL
, arg
)) {
1097 tcg_out_opc_reg(s
, OPC_JALR
, TCG_REG_RA
, TCG_REG_T9
, 0);
1102 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*arg
)
1104 tcg_out_call_int(s
, arg
, false);
1108 #if defined(CONFIG_SOFTMMU)
1109 #include "tcg-ldst.inc.c"
1111 static void * const qemu_ld_helpers
[16] = {
1112 [MO_UB
] = helper_ret_ldub_mmu
,
1113 [MO_SB
] = helper_ret_ldsb_mmu
,
1114 [MO_LEUW
] = helper_le_lduw_mmu
,
1115 [MO_LESW
] = helper_le_ldsw_mmu
,
1116 [MO_LEUL
] = helper_le_ldul_mmu
,
1117 [MO_LEQ
] = helper_le_ldq_mmu
,
1118 [MO_BEUW
] = helper_be_lduw_mmu
,
1119 [MO_BESW
] = helper_be_ldsw_mmu
,
1120 [MO_BEUL
] = helper_be_ldul_mmu
,
1121 [MO_BEQ
] = helper_be_ldq_mmu
,
1122 #if TCG_TARGET_REG_BITS == 64
1123 [MO_LESL
] = helper_le_ldsl_mmu
,
1124 [MO_BESL
] = helper_be_ldsl_mmu
,
1128 static void * const qemu_st_helpers
[16] = {
1129 [MO_UB
] = helper_ret_stb_mmu
,
1130 [MO_LEUW
] = helper_le_stw_mmu
,
1131 [MO_LEUL
] = helper_le_stl_mmu
,
1132 [MO_LEQ
] = helper_le_stq_mmu
,
1133 [MO_BEUW
] = helper_be_stw_mmu
,
1134 [MO_BEUL
] = helper_be_stl_mmu
,
1135 [MO_BEQ
] = helper_be_stq_mmu
,
1138 /* Helper routines for marshalling helper function arguments into
1139 * the correct registers and stack.
1140 * I is where we want to put this argument, and is updated and returned
1141 * for the next call. ARG is the argument itself.
1143 * We provide routines for arguments which are: immediate, 32 bit
1144 * value in register, 16 and 8 bit values in register (which must be zero
1145 * extended before use) and 64 bit value in a lo:hi register pair.
1148 static int tcg_out_call_iarg_reg(TCGContext
*s
, int i
, TCGReg arg
)
1150 if (i
< ARRAY_SIZE(tcg_target_call_iarg_regs
)) {
1151 tcg_out_mov(s
, TCG_TYPE_REG
, tcg_target_call_iarg_regs
[i
], arg
);
1153 /* For N32 and N64, the initial offset is different. But there
1154 we also have 8 argument register so we don't run out here. */
1155 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
1156 tcg_out_st(s
, TCG_TYPE_REG
, arg
, TCG_REG_SP
, 4 * i
);
1161 static int tcg_out_call_iarg_reg8(TCGContext
*s
, int i
, TCGReg arg
)
1163 TCGReg tmp
= TCG_TMP0
;
1164 if (i
< ARRAY_SIZE(tcg_target_call_iarg_regs
)) {
1165 tmp
= tcg_target_call_iarg_regs
[i
];
1167 tcg_out_opc_imm(s
, OPC_ANDI
, tmp
, arg
, 0xff);
1168 return tcg_out_call_iarg_reg(s
, i
, tmp
);
1171 static int tcg_out_call_iarg_reg16(TCGContext
*s
, int i
, TCGReg arg
)
1173 TCGReg tmp
= TCG_TMP0
;
1174 if (i
< ARRAY_SIZE(tcg_target_call_iarg_regs
)) {
1175 tmp
= tcg_target_call_iarg_regs
[i
];
1177 tcg_out_opc_imm(s
, OPC_ANDI
, tmp
, arg
, 0xffff);
1178 return tcg_out_call_iarg_reg(s
, i
, tmp
);
1181 static int tcg_out_call_iarg_imm(TCGContext
*s
, int i
, TCGArg arg
)
1183 TCGReg tmp
= TCG_TMP0
;
1187 if (i
< ARRAY_SIZE(tcg_target_call_iarg_regs
)) {
1188 tmp
= tcg_target_call_iarg_regs
[i
];
1190 tcg_out_movi(s
, TCG_TYPE_REG
, tmp
, arg
);
1192 return tcg_out_call_iarg_reg(s
, i
, tmp
);
1195 static int tcg_out_call_iarg_reg2(TCGContext
*s
, int i
, TCGReg al
, TCGReg ah
)
1197 tcg_debug_assert(TCG_TARGET_REG_BITS
== 32);
1199 i
= tcg_out_call_iarg_reg(s
, i
, (MIPS_BE
? ah
: al
));
1200 i
= tcg_out_call_iarg_reg(s
, i
, (MIPS_BE
? al
: ah
));
1204 /* We expect tlb_mask to be before tlb_table. */
1205 QEMU_BUILD_BUG_ON(offsetof(CPUArchState
, tlb_table
) <
1206 offsetof(CPUArchState
, tlb_mask
));
1208 /* We expect tlb_mask to be "near" tlb_table. */
1209 QEMU_BUILD_BUG_ON(offsetof(CPUArchState
, tlb_table
) -
1210 offsetof(CPUArchState
, tlb_mask
) >= 0x8000);
1213 * Perform the tlb comparison operation.
1214 * The complete host address is placed in BASE.
1215 * Clobbers TMP0, TMP1, TMP2, TMP3.
1217 static void tcg_out_tlb_load(TCGContext
*s
, TCGReg base
, TCGReg addrl
,
1218 TCGReg addrh
, TCGMemOpIdx oi
,
1219 tcg_insn_unit
*label_ptr
[2], bool is_load
)
1221 TCGMemOp opc
= get_memop(oi
);
1222 unsigned s_bits
= opc
& MO_SIZE
;
1223 unsigned a_bits
= get_alignment_bits(opc
);
1224 int mem_index
= get_mmuidx(oi
);
1225 int mask_off
= offsetof(CPUArchState
, tlb_mask
[mem_index
]);
1226 int table_off
= offsetof(CPUArchState
, tlb_table
[mem_index
]);
1227 int add_off
= offsetof(CPUTLBEntry
, addend
);
1228 int cmp_off
= (is_load
? offsetof(CPUTLBEntry
, addr_read
)
1229 : offsetof(CPUTLBEntry
, addr_write
));
1230 TCGReg mask_base
= TCG_AREG0
, table_base
= TCG_AREG0
;
1233 if (table_off
> 0x7fff) {
1234 int mask_hi
= mask_off
- (int16_t)mask_off
;
1235 int table_hi
= table_off
- (int16_t)table_off
;
1237 table_base
= TCG_TMP1
;
1238 if (likely(mask_hi
== table_hi
)) {
1239 mask_base
= table_base
;
1240 tcg_out_opc_imm(s
, OPC_LUI
, mask_base
, TCG_REG_ZERO
, mask_hi
>> 16);
1241 tcg_out_opc_reg(s
, ALIAS_PADD
, mask_base
, mask_base
, TCG_AREG0
);
1242 mask_off
-= mask_hi
;
1243 table_off
-= mask_hi
;
1246 mask_base
= TCG_TMP0
;
1247 tcg_out_opc_imm(s
, OPC_LUI
,
1248 mask_base
, TCG_REG_ZERO
, mask_hi
>> 16);
1249 tcg_out_opc_reg(s
, ALIAS_PADD
,
1250 mask_base
, mask_base
, TCG_AREG0
);
1252 table_off
-= mask_off
;
1253 mask_off
-= mask_hi
;
1254 tcg_out_opc_imm(s
, ALIAS_PADDI
, table_base
, mask_base
, mask_off
);
1258 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1259 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_TMP0
, mask_base
, mask_off
);
1260 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_TMP1
, table_base
, table_off
);
1262 /* Extract the TLB index from the address into TMP3. */
1263 tcg_out_opc_sa(s
, ALIAS_TSRL
, TCG_TMP3
, addrl
,
1264 TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
1265 tcg_out_opc_reg(s
, OPC_AND
, TCG_TMP3
, TCG_TMP3
, TCG_TMP0
);
1267 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */
1268 tcg_out_opc_reg(s
, ALIAS_PADD
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
1270 /* We don't currently support unaligned accesses.
1271 We could do so with mips32r6. */
1272 if (a_bits
< s_bits
) {
1276 /* Mask the page bits, keeping the alignment bits to compare against. */
1277 mask
= (target_ulong
)TARGET_PAGE_MASK
| ((1 << a_bits
) - 1);
1279 /* Load the (low-half) tlb comparator. */
1280 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1281 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_TMP0
, TCG_TMP3
, cmp_off
+ LO_OFF
);
1282 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_TMP1
, mask
);
1284 tcg_out_ldst(s
, (TARGET_LONG_BITS
== 64 ? OPC_LD
1285 : TCG_TARGET_REG_BITS
== 64 ? OPC_LWU
: OPC_LW
),
1286 TCG_TMP0
, TCG_TMP3
, cmp_off
);
1287 tcg_out_movi(s
, TCG_TYPE_TL
, TCG_TMP1
, mask
);
1288 /* No second compare is required here;
1289 load the tlb addend for the fast path. */
1290 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_TMP2
, TCG_TMP3
, add_off
);
1292 tcg_out_opc_reg(s
, OPC_AND
, TCG_TMP1
, TCG_TMP1
, addrl
);
1294 /* Zero extend a 32-bit guest address for a 64-bit host. */
1295 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1296 tcg_out_ext32u(s
, base
, addrl
);
1300 label_ptr
[0] = s
->code_ptr
;
1301 tcg_out_opc_br(s
, OPC_BNE
, TCG_TMP1
, TCG_TMP0
);
1303 /* Load and test the high half tlb comparator. */
1304 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1306 tcg_out_ld(s
, TCG_TYPE_I32
, TCG_TMP0
, TCG_TMP3
, cmp_off
+ HI_OFF
);
1308 /* Load the tlb addend for the fast path. */
1309 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_TMP2
, TCG_TMP3
, add_off
);
1311 label_ptr
[1] = s
->code_ptr
;
1312 tcg_out_opc_br(s
, OPC_BNE
, addrh
, TCG_TMP0
);
1316 tcg_out_opc_reg(s
, ALIAS_PADD
, base
, TCG_TMP2
, addrl
);
1319 static void add_qemu_ldst_label(TCGContext
*s
, int is_ld
, TCGMemOpIdx oi
,
1321 TCGReg datalo
, TCGReg datahi
,
1322 TCGReg addrlo
, TCGReg addrhi
,
1323 void *raddr
, tcg_insn_unit
*label_ptr
[2])
1325 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1327 label
->is_ld
= is_ld
;
1330 label
->datalo_reg
= datalo
;
1331 label
->datahi_reg
= datahi
;
1332 label
->addrlo_reg
= addrlo
;
1333 label
->addrhi_reg
= addrhi
;
1334 label
->raddr
= raddr
;
1335 label
->label_ptr
[0] = label_ptr
[0];
1336 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1337 label
->label_ptr
[1] = label_ptr
[1];
1341 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*l
)
1343 TCGMemOpIdx oi
= l
->oi
;
1344 TCGMemOp opc
= get_memop(oi
);
1348 /* resolve label address */
1349 reloc_pc16(l
->label_ptr
[0], s
->code_ptr
);
1350 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1351 reloc_pc16(l
->label_ptr
[1], s
->code_ptr
);
1355 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1356 i
= tcg_out_call_iarg_reg2(s
, i
, l
->addrlo_reg
, l
->addrhi_reg
);
1358 i
= tcg_out_call_iarg_reg(s
, i
, l
->addrlo_reg
);
1360 i
= tcg_out_call_iarg_imm(s
, i
, oi
);
1361 i
= tcg_out_call_iarg_imm(s
, i
, (intptr_t)l
->raddr
);
1362 tcg_out_call_int(s
, qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SSIZE
)], false);
1364 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[0], TCG_AREG0
);
1367 if (TCG_TARGET_REG_BITS
== 32 && (opc
& MO_SIZE
) == MO_64
) {
1368 /* We eliminated V0 from the possible output registers, so it
1369 cannot be clobbered here. So we must move V1 first. */
1371 tcg_out_mov(s
, TCG_TYPE_I32
, v0
, TCG_REG_V1
);
1374 tcg_out_mov(s
, TCG_TYPE_I32
, l
->datahi_reg
, TCG_REG_V1
);
1378 tcg_out_opc_br(s
, OPC_BEQ
, TCG_REG_ZERO
, TCG_REG_ZERO
);
1379 reloc_pc16(s
->code_ptr
- 1, l
->raddr
);
1382 if (TCG_TARGET_REG_BITS
== 64 && l
->type
== TCG_TYPE_I32
) {
1383 /* we always sign-extend 32-bit loads */
1384 tcg_out_opc_sa(s
, OPC_SLL
, v0
, TCG_REG_V0
, 0);
1386 tcg_out_opc_reg(s
, OPC_OR
, v0
, TCG_REG_V0
, TCG_REG_ZERO
);
1390 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*l
)
1392 TCGMemOpIdx oi
= l
->oi
;
1393 TCGMemOp opc
= get_memop(oi
);
1394 TCGMemOp s_bits
= opc
& MO_SIZE
;
1397 /* resolve label address */
1398 reloc_pc16(l
->label_ptr
[0], s
->code_ptr
);
1399 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1400 reloc_pc16(l
->label_ptr
[1], s
->code_ptr
);
1404 if (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
) {
1405 i
= tcg_out_call_iarg_reg2(s
, i
, l
->addrlo_reg
, l
->addrhi_reg
);
1407 i
= tcg_out_call_iarg_reg(s
, i
, l
->addrlo_reg
);
1411 i
= tcg_out_call_iarg_reg8(s
, i
, l
->datalo_reg
);
1414 i
= tcg_out_call_iarg_reg16(s
, i
, l
->datalo_reg
);
1417 i
= tcg_out_call_iarg_reg(s
, i
, l
->datalo_reg
);
1420 if (TCG_TARGET_REG_BITS
== 32) {
1421 i
= tcg_out_call_iarg_reg2(s
, i
, l
->datalo_reg
, l
->datahi_reg
);
1423 i
= tcg_out_call_iarg_reg(s
, i
, l
->datalo_reg
);
1429 i
= tcg_out_call_iarg_imm(s
, i
, oi
);
1431 /* Tail call to the store helper. Thus force the return address
1432 computation to take place in the return address register. */
1433 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_RA
, (intptr_t)l
->raddr
);
1434 i
= tcg_out_call_iarg_reg(s
, i
, TCG_REG_RA
);
1435 tcg_out_call_int(s
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)], true);
1437 tcg_out_mov(s
, TCG_TYPE_PTR
, tcg_target_call_iarg_regs
[0], TCG_AREG0
);
1441 static void tcg_out_qemu_ld_direct(TCGContext
*s
, TCGReg lo
, TCGReg hi
,
1442 TCGReg base
, TCGMemOp opc
, bool is_64
)
1444 switch (opc
& (MO_SSIZE
| MO_BSWAP
)) {
1446 tcg_out_opc_imm(s
, OPC_LBU
, lo
, base
, 0);
1449 tcg_out_opc_imm(s
, OPC_LB
, lo
, base
, 0);
1451 case MO_UW
| MO_BSWAP
:
1452 tcg_out_opc_imm(s
, OPC_LHU
, TCG_TMP1
, base
, 0);
1453 tcg_out_bswap16(s
, lo
, TCG_TMP1
);
1456 tcg_out_opc_imm(s
, OPC_LHU
, lo
, base
, 0);
1458 case MO_SW
| MO_BSWAP
:
1459 tcg_out_opc_imm(s
, OPC_LHU
, TCG_TMP1
, base
, 0);
1460 tcg_out_bswap16s(s
, lo
, TCG_TMP1
);
1463 tcg_out_opc_imm(s
, OPC_LH
, lo
, base
, 0);
1465 case MO_UL
| MO_BSWAP
:
1466 if (TCG_TARGET_REG_BITS
== 64 && is_64
) {
1467 if (use_mips32r2_instructions
) {
1468 tcg_out_opc_imm(s
, OPC_LWU
, lo
, base
, 0);
1469 tcg_out_bswap32u(s
, lo
, lo
);
1471 tcg_out_bswap_subr(s
, bswap32u_addr
);
1473 tcg_out_opc_imm(s
, OPC_LWU
, TCG_TMP0
, base
, 0);
1474 tcg_out_mov(s
, TCG_TYPE_I64
, lo
, TCG_TMP3
);
1479 case MO_SL
| MO_BSWAP
:
1480 if (use_mips32r2_instructions
) {
1481 tcg_out_opc_imm(s
, OPC_LW
, lo
, base
, 0);
1482 tcg_out_bswap32(s
, lo
, lo
);
1484 tcg_out_bswap_subr(s
, bswap32_addr
);
1486 tcg_out_opc_imm(s
, OPC_LW
, TCG_TMP0
, base
, 0);
1487 tcg_out_mov(s
, TCG_TYPE_I32
, lo
, TCG_TMP3
);
1491 if (TCG_TARGET_REG_BITS
== 64 && is_64
) {
1492 tcg_out_opc_imm(s
, OPC_LWU
, lo
, base
, 0);
1497 tcg_out_opc_imm(s
, OPC_LW
, lo
, base
, 0);
1499 case MO_Q
| MO_BSWAP
:
1500 if (TCG_TARGET_REG_BITS
== 64) {
1501 if (use_mips32r2_instructions
) {
1502 tcg_out_opc_imm(s
, OPC_LD
, lo
, base
, 0);
1503 tcg_out_bswap64(s
, lo
, lo
);
1505 tcg_out_bswap_subr(s
, bswap64_addr
);
1507 tcg_out_opc_imm(s
, OPC_LD
, TCG_TMP0
, base
, 0);
1508 tcg_out_mov(s
, TCG_TYPE_I64
, lo
, TCG_TMP3
);
1510 } else if (use_mips32r2_instructions
) {
1511 tcg_out_opc_imm(s
, OPC_LW
, TCG_TMP0
, base
, 0);
1512 tcg_out_opc_imm(s
, OPC_LW
, TCG_TMP1
, base
, 4);
1513 tcg_out_opc_reg(s
, OPC_WSBH
, TCG_TMP0
, 0, TCG_TMP0
);
1514 tcg_out_opc_reg(s
, OPC_WSBH
, TCG_TMP1
, 0, TCG_TMP1
);
1515 tcg_out_opc_sa(s
, OPC_ROTR
, MIPS_BE
? lo
: hi
, TCG_TMP0
, 16);
1516 tcg_out_opc_sa(s
, OPC_ROTR
, MIPS_BE
? hi
: lo
, TCG_TMP1
, 16);
1518 tcg_out_bswap_subr(s
, bswap32_addr
);
1520 tcg_out_opc_imm(s
, OPC_LW
, TCG_TMP0
, base
, 0);
1521 tcg_out_opc_imm(s
, OPC_LW
, TCG_TMP0
, base
, 4);
1522 tcg_out_bswap_subr(s
, bswap32_addr
);
1524 tcg_out_mov(s
, TCG_TYPE_I32
, MIPS_BE
? lo
: hi
, TCG_TMP3
);
1525 tcg_out_mov(s
, TCG_TYPE_I32
, MIPS_BE
? hi
: lo
, TCG_TMP3
);
1529 /* Prefer to load from offset 0 first, but allow for overlap. */
1530 if (TCG_TARGET_REG_BITS
== 64) {
1531 tcg_out_opc_imm(s
, OPC_LD
, lo
, base
, 0);
1532 } else if (MIPS_BE
? hi
!= base
: lo
== base
) {
1533 tcg_out_opc_imm(s
, OPC_LW
, hi
, base
, HI_OFF
);
1534 tcg_out_opc_imm(s
, OPC_LW
, lo
, base
, LO_OFF
);
1536 tcg_out_opc_imm(s
, OPC_LW
, lo
, base
, LO_OFF
);
1537 tcg_out_opc_imm(s
, OPC_LW
, hi
, base
, HI_OFF
);
1545 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1547 TCGReg addr_regl
, addr_regh
__attribute__((unused
));
1548 TCGReg data_regl
, data_regh
;
1551 #if defined(CONFIG_SOFTMMU)
1552 tcg_insn_unit
*label_ptr
[2];
1554 TCGReg base
= TCG_REG_A0
;
1556 data_regl
= *args
++;
1557 data_regh
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1558 addr_regl
= *args
++;
1559 addr_regh
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1561 opc
= get_memop(oi
);
1563 #if defined(CONFIG_SOFTMMU)
1564 tcg_out_tlb_load(s
, base
, addr_regl
, addr_regh
, oi
, label_ptr
, 1);
1565 tcg_out_qemu_ld_direct(s
, data_regl
, data_regh
, base
, opc
, is_64
);
1566 add_qemu_ldst_label(s
, 1, oi
,
1567 (is_64
? TCG_TYPE_I64
: TCG_TYPE_I32
),
1568 data_regl
, data_regh
, addr_regl
, addr_regh
,
1569 s
->code_ptr
, label_ptr
);
1571 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1572 tcg_out_ext32u(s
, base
, addr_regl
);
1575 if (guest_base
== 0 && data_regl
!= addr_regl
) {
1577 } else if (guest_base
== (int16_t)guest_base
) {
1578 tcg_out_opc_imm(s
, ALIAS_PADDI
, base
, addr_regl
, guest_base
);
1580 tcg_out_opc_reg(s
, ALIAS_PADD
, base
, TCG_GUEST_BASE_REG
, addr_regl
);
1582 tcg_out_qemu_ld_direct(s
, data_regl
, data_regh
, base
, opc
, is_64
);
1586 static void tcg_out_qemu_st_direct(TCGContext
*s
, TCGReg lo
, TCGReg hi
,
1587 TCGReg base
, TCGMemOp opc
)
1589 /* Don't clutter the code below with checks to avoid bswapping ZERO. */
1590 if ((lo
| hi
) == 0) {
1594 switch (opc
& (MO_SIZE
| MO_BSWAP
)) {
1596 tcg_out_opc_imm(s
, OPC_SB
, lo
, base
, 0);
1599 case MO_16
| MO_BSWAP
:
1600 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, lo
, 0xffff);
1601 tcg_out_bswap16(s
, TCG_TMP1
, TCG_TMP1
);
1605 tcg_out_opc_imm(s
, OPC_SH
, lo
, base
, 0);
1608 case MO_32
| MO_BSWAP
:
1609 tcg_out_bswap32(s
, TCG_TMP3
, lo
);
1613 tcg_out_opc_imm(s
, OPC_SW
, lo
, base
, 0);
1616 case MO_64
| MO_BSWAP
:
1617 if (TCG_TARGET_REG_BITS
== 64) {
1618 tcg_out_bswap64(s
, TCG_TMP3
, lo
);
1619 tcg_out_opc_imm(s
, OPC_SD
, TCG_TMP3
, base
, 0);
1620 } else if (use_mips32r2_instructions
) {
1621 tcg_out_opc_reg(s
, OPC_WSBH
, TCG_TMP0
, 0, MIPS_BE
? lo
: hi
);
1622 tcg_out_opc_reg(s
, OPC_WSBH
, TCG_TMP1
, 0, MIPS_BE
? hi
: lo
);
1623 tcg_out_opc_sa(s
, OPC_ROTR
, TCG_TMP0
, TCG_TMP0
, 16);
1624 tcg_out_opc_sa(s
, OPC_ROTR
, TCG_TMP1
, TCG_TMP1
, 16);
1625 tcg_out_opc_imm(s
, OPC_SW
, TCG_TMP0
, base
, 0);
1626 tcg_out_opc_imm(s
, OPC_SW
, TCG_TMP1
, base
, 4);
1628 tcg_out_bswap32(s
, TCG_TMP3
, MIPS_BE
? lo
: hi
);
1629 tcg_out_opc_imm(s
, OPC_SW
, TCG_TMP3
, base
, 0);
1630 tcg_out_bswap32(s
, TCG_TMP3
, MIPS_BE
? hi
: lo
);
1631 tcg_out_opc_imm(s
, OPC_SW
, TCG_TMP3
, base
, 4);
1635 if (TCG_TARGET_REG_BITS
== 64) {
1636 tcg_out_opc_imm(s
, OPC_SD
, lo
, base
, 0);
1638 tcg_out_opc_imm(s
, OPC_SW
, MIPS_BE
? hi
: lo
, base
, 0);
1639 tcg_out_opc_imm(s
, OPC_SW
, MIPS_BE
? lo
: hi
, base
, 4);
1648 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is_64
)
1650 TCGReg addr_regl
, addr_regh
__attribute__((unused
));
1651 TCGReg data_regl
, data_regh
;
1654 #if defined(CONFIG_SOFTMMU)
1655 tcg_insn_unit
*label_ptr
[2];
1657 TCGReg base
= TCG_REG_A0
;
1659 data_regl
= *args
++;
1660 data_regh
= (TCG_TARGET_REG_BITS
== 32 && is_64
? *args
++ : 0);
1661 addr_regl
= *args
++;
1662 addr_regh
= (TCG_TARGET_REG_BITS
< TARGET_LONG_BITS
? *args
++ : 0);
1664 opc
= get_memop(oi
);
1666 #if defined(CONFIG_SOFTMMU)
1667 tcg_out_tlb_load(s
, base
, addr_regl
, addr_regh
, oi
, label_ptr
, 0);
1668 tcg_out_qemu_st_direct(s
, data_regl
, data_regh
, base
, opc
);
1669 add_qemu_ldst_label(s
, 0, oi
,
1670 (is_64
? TCG_TYPE_I64
: TCG_TYPE_I32
),
1671 data_regl
, data_regh
, addr_regl
, addr_regh
,
1672 s
->code_ptr
, label_ptr
);
1675 if (TCG_TARGET_REG_BITS
> TARGET_LONG_BITS
) {
1676 tcg_out_ext32u(s
, base
, addr_regl
);
1679 if (guest_base
== 0) {
1681 } else if (guest_base
== (int16_t)guest_base
) {
1682 tcg_out_opc_imm(s
, ALIAS_PADDI
, base
, addr_regl
, guest_base
);
1684 tcg_out_opc_reg(s
, ALIAS_PADD
, base
, TCG_GUEST_BASE_REG
, addr_regl
);
1686 tcg_out_qemu_st_direct(s
, data_regl
, data_regh
, base
, opc
);
1690 static void tcg_out_mb(TCGContext
*s
, TCGArg a0
)
1692 static const MIPSInsn sync
[] = {
1693 /* Note that SYNC_MB is a slightly weaker than SYNC 0,
1694 as the former is an ordering barrier and the latter
1695 is a completion barrier. */
1696 [0 ... TCG_MO_ALL
] = OPC_SYNC_MB
,
1697 [TCG_MO_LD_LD
] = OPC_SYNC_RMB
,
1698 [TCG_MO_ST_ST
] = OPC_SYNC_WMB
,
1699 [TCG_MO_LD_ST
] = OPC_SYNC_RELEASE
,
1700 [TCG_MO_LD_ST
| TCG_MO_ST_ST
] = OPC_SYNC_RELEASE
,
1701 [TCG_MO_LD_ST
| TCG_MO_LD_LD
] = OPC_SYNC_ACQUIRE
,
1703 tcg_out32(s
, sync
[a0
& TCG_MO_ALL
]);
1706 static void tcg_out_clz(TCGContext
*s
, MIPSInsn opcv2
, MIPSInsn opcv6
,
1707 int width
, TCGReg a0
, TCGReg a1
, TCGArg a2
)
1709 if (use_mips32r6_instructions
) {
1711 tcg_out_opc_reg(s
, opcv6
, a0
, a1
, 0);
1713 tcg_out_opc_reg(s
, opcv6
, TCG_TMP0
, a1
, 0);
1714 tcg_out_movcond(s
, TCG_COND_EQ
, a0
, a1
, 0, a2
, TCG_TMP0
);
1718 tcg_out_opc_reg(s
, opcv2
, a0
, a1
, a1
);
1719 } else if (a0
== a2
) {
1720 tcg_out_opc_reg(s
, opcv2
, TCG_TMP0
, a1
, a1
);
1721 tcg_out_opc_reg(s
, OPC_MOVN
, a0
, TCG_TMP0
, a1
);
1722 } else if (a0
!= a1
) {
1723 tcg_out_opc_reg(s
, opcv2
, a0
, a1
, a1
);
1724 tcg_out_opc_reg(s
, OPC_MOVZ
, a0
, a2
, a1
);
1726 tcg_out_opc_reg(s
, opcv2
, TCG_TMP0
, a1
, a1
);
1727 tcg_out_opc_reg(s
, OPC_MOVZ
, TCG_TMP0
, a2
, a1
);
1728 tcg_out_mov(s
, TCG_TYPE_REG
, a0
, TCG_TMP0
);
1733 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1734 const TCGArg
*args
, const int *const_args
)
1746 case INDEX_op_exit_tb
:
1748 TCGReg b0
= TCG_REG_ZERO
;
1752 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_V0
, a0
& ~0xffff);
1755 if (!tcg_out_opc_jmp(s
, OPC_J
, tb_ret_addr
)) {
1756 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_TMP0
,
1757 (uintptr_t)tb_ret_addr
);
1758 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_TMP0
, 0);
1760 tcg_out_opc_imm(s
, OPC_ORI
, TCG_REG_V0
, b0
, a0
& 0xffff);
1763 case INDEX_op_goto_tb
:
1764 if (s
->tb_jmp_insn_offset
) {
1765 /* direct jump method */
1766 s
->tb_jmp_insn_offset
[a0
] = tcg_current_code_size(s
);
1767 /* Avoid clobbering the address during retranslation. */
1768 tcg_out32(s
, OPC_J
| (*(uint32_t *)s
->code_ptr
& 0x3ffffff));
1770 /* indirect jump method */
1771 tcg_out_ld(s
, TCG_TYPE_PTR
, TCG_TMP0
, TCG_REG_ZERO
,
1772 (uintptr_t)(s
->tb_jmp_target_addr
+ a0
));
1773 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_TMP0
, 0);
1776 set_jmp_reset_offset(s
, a0
);
1778 case INDEX_op_goto_ptr
:
1779 /* jmp to the given host address (could be epilogue) */
1780 tcg_out_opc_reg(s
, OPC_JR
, 0, a0
, 0);
1784 tcg_out_brcond(s
, TCG_COND_EQ
, TCG_REG_ZERO
, TCG_REG_ZERO
,
1788 case INDEX_op_ld8u_i32
:
1789 case INDEX_op_ld8u_i64
:
1792 case INDEX_op_ld8s_i32
:
1793 case INDEX_op_ld8s_i64
:
1796 case INDEX_op_ld16u_i32
:
1797 case INDEX_op_ld16u_i64
:
1800 case INDEX_op_ld16s_i32
:
1801 case INDEX_op_ld16s_i64
:
1804 case INDEX_op_ld_i32
:
1805 case INDEX_op_ld32s_i64
:
1808 case INDEX_op_ld32u_i64
:
1811 case INDEX_op_ld_i64
:
1814 case INDEX_op_st8_i32
:
1815 case INDEX_op_st8_i64
:
1818 case INDEX_op_st16_i32
:
1819 case INDEX_op_st16_i64
:
1822 case INDEX_op_st_i32
:
1823 case INDEX_op_st32_i64
:
1826 case INDEX_op_st_i64
:
1829 tcg_out_ldst(s
, i1
, a0
, a1
, a2
);
1832 case INDEX_op_add_i32
:
1833 i1
= OPC_ADDU
, i2
= OPC_ADDIU
;
1835 case INDEX_op_add_i64
:
1836 i1
= OPC_DADDU
, i2
= OPC_DADDIU
;
1838 case INDEX_op_or_i32
:
1839 case INDEX_op_or_i64
:
1840 i1
= OPC_OR
, i2
= OPC_ORI
;
1842 case INDEX_op_xor_i32
:
1843 case INDEX_op_xor_i64
:
1844 i1
= OPC_XOR
, i2
= OPC_XORI
;
1847 tcg_out_opc_imm(s
, i2
, a0
, a1
, a2
);
1851 tcg_out_opc_reg(s
, i1
, a0
, a1
, a2
);
1854 case INDEX_op_sub_i32
:
1855 i1
= OPC_SUBU
, i2
= OPC_ADDIU
;
1857 case INDEX_op_sub_i64
:
1858 i1
= OPC_DSUBU
, i2
= OPC_DADDIU
;
1861 tcg_out_opc_imm(s
, i2
, a0
, a1
, -a2
);
1865 case INDEX_op_and_i32
:
1866 if (c2
&& a2
!= (uint16_t)a2
) {
1867 int msb
= ctz32(~a2
) - 1;
1868 tcg_debug_assert(use_mips32r2_instructions
);
1869 tcg_debug_assert(is_p2m1(a2
));
1870 tcg_out_opc_bf(s
, OPC_EXT
, a0
, a1
, msb
, 0);
1873 i1
= OPC_AND
, i2
= OPC_ANDI
;
1875 case INDEX_op_and_i64
:
1876 if (c2
&& a2
!= (uint16_t)a2
) {
1877 int msb
= ctz64(~a2
) - 1;
1878 tcg_debug_assert(use_mips32r2_instructions
);
1879 tcg_debug_assert(is_p2m1(a2
));
1880 tcg_out_opc_bf64(s
, OPC_DEXT
, OPC_DEXTM
, OPC_DEXTU
, a0
, a1
, msb
, 0);
1883 i1
= OPC_AND
, i2
= OPC_ANDI
;
1885 case INDEX_op_nor_i32
:
1886 case INDEX_op_nor_i64
:
1890 case INDEX_op_mul_i32
:
1891 if (use_mips32_instructions
) {
1892 tcg_out_opc_reg(s
, OPC_MUL
, a0
, a1
, a2
);
1895 i1
= OPC_MULT
, i2
= OPC_MFLO
;
1897 case INDEX_op_mulsh_i32
:
1898 if (use_mips32r6_instructions
) {
1899 tcg_out_opc_reg(s
, OPC_MUH
, a0
, a1
, a2
);
1902 i1
= OPC_MULT
, i2
= OPC_MFHI
;
1904 case INDEX_op_muluh_i32
:
1905 if (use_mips32r6_instructions
) {
1906 tcg_out_opc_reg(s
, OPC_MUHU
, a0
, a1
, a2
);
1909 i1
= OPC_MULTU
, i2
= OPC_MFHI
;
1911 case INDEX_op_div_i32
:
1912 if (use_mips32r6_instructions
) {
1913 tcg_out_opc_reg(s
, OPC_DIV_R6
, a0
, a1
, a2
);
1916 i1
= OPC_DIV
, i2
= OPC_MFLO
;
1918 case INDEX_op_divu_i32
:
1919 if (use_mips32r6_instructions
) {
1920 tcg_out_opc_reg(s
, OPC_DIVU_R6
, a0
, a1
, a2
);
1923 i1
= OPC_DIVU
, i2
= OPC_MFLO
;
1925 case INDEX_op_rem_i32
:
1926 if (use_mips32r6_instructions
) {
1927 tcg_out_opc_reg(s
, OPC_MOD
, a0
, a1
, a2
);
1930 i1
= OPC_DIV
, i2
= OPC_MFHI
;
1932 case INDEX_op_remu_i32
:
1933 if (use_mips32r6_instructions
) {
1934 tcg_out_opc_reg(s
, OPC_MODU
, a0
, a1
, a2
);
1937 i1
= OPC_DIVU
, i2
= OPC_MFHI
;
1939 case INDEX_op_mul_i64
:
1940 if (use_mips32r6_instructions
) {
1941 tcg_out_opc_reg(s
, OPC_DMUL
, a0
, a1
, a2
);
1944 i1
= OPC_DMULT
, i2
= OPC_MFLO
;
1946 case INDEX_op_mulsh_i64
:
1947 if (use_mips32r6_instructions
) {
1948 tcg_out_opc_reg(s
, OPC_DMUH
, a0
, a1
, a2
);
1951 i1
= OPC_DMULT
, i2
= OPC_MFHI
;
1953 case INDEX_op_muluh_i64
:
1954 if (use_mips32r6_instructions
) {
1955 tcg_out_opc_reg(s
, OPC_DMUHU
, a0
, a1
, a2
);
1958 i1
= OPC_DMULTU
, i2
= OPC_MFHI
;
1960 case INDEX_op_div_i64
:
1961 if (use_mips32r6_instructions
) {
1962 tcg_out_opc_reg(s
, OPC_DDIV_R6
, a0
, a1
, a2
);
1965 i1
= OPC_DDIV
, i2
= OPC_MFLO
;
1967 case INDEX_op_divu_i64
:
1968 if (use_mips32r6_instructions
) {
1969 tcg_out_opc_reg(s
, OPC_DDIVU_R6
, a0
, a1
, a2
);
1972 i1
= OPC_DDIVU
, i2
= OPC_MFLO
;
1974 case INDEX_op_rem_i64
:
1975 if (use_mips32r6_instructions
) {
1976 tcg_out_opc_reg(s
, OPC_DMOD
, a0
, a1
, a2
);
1979 i1
= OPC_DDIV
, i2
= OPC_MFHI
;
1981 case INDEX_op_remu_i64
:
1982 if (use_mips32r6_instructions
) {
1983 tcg_out_opc_reg(s
, OPC_DMODU
, a0
, a1
, a2
);
1986 i1
= OPC_DDIVU
, i2
= OPC_MFHI
;
1988 tcg_out_opc_reg(s
, i1
, 0, a1
, a2
);
1989 tcg_out_opc_reg(s
, i2
, a0
, 0, 0);
1992 case INDEX_op_muls2_i32
:
1995 case INDEX_op_mulu2_i32
:
1998 case INDEX_op_muls2_i64
:
2001 case INDEX_op_mulu2_i64
:
2004 tcg_out_opc_reg(s
, i1
, 0, a2
, args
[3]);
2005 tcg_out_opc_reg(s
, OPC_MFLO
, a0
, 0, 0);
2006 tcg_out_opc_reg(s
, OPC_MFHI
, a1
, 0, 0);
2009 case INDEX_op_not_i32
:
2010 case INDEX_op_not_i64
:
2013 case INDEX_op_bswap16_i32
:
2014 case INDEX_op_bswap16_i64
:
2017 case INDEX_op_ext8s_i32
:
2018 case INDEX_op_ext8s_i64
:
2021 case INDEX_op_ext16s_i32
:
2022 case INDEX_op_ext16s_i64
:
2025 tcg_out_opc_reg(s
, i1
, a0
, TCG_REG_ZERO
, a1
);
2028 case INDEX_op_bswap32_i32
:
2029 tcg_out_bswap32(s
, a0
, a1
);
2031 case INDEX_op_bswap32_i64
:
2032 tcg_out_bswap32u(s
, a0
, a1
);
2034 case INDEX_op_bswap64_i64
:
2035 tcg_out_bswap64(s
, a0
, a1
);
2037 case INDEX_op_extrh_i64_i32
:
2038 tcg_out_dsra(s
, a0
, a1
, 32);
2040 case INDEX_op_ext32s_i64
:
2041 case INDEX_op_ext_i32_i64
:
2042 case INDEX_op_extrl_i64_i32
:
2043 tcg_out_opc_sa(s
, OPC_SLL
, a0
, a1
, 0);
2045 case INDEX_op_ext32u_i64
:
2046 case INDEX_op_extu_i32_i64
:
2047 tcg_out_ext32u(s
, a0
, a1
);
2050 case INDEX_op_sar_i32
:
2051 i1
= OPC_SRAV
, i2
= OPC_SRA
;
2053 case INDEX_op_shl_i32
:
2054 i1
= OPC_SLLV
, i2
= OPC_SLL
;
2056 case INDEX_op_shr_i32
:
2057 i1
= OPC_SRLV
, i2
= OPC_SRL
;
2059 case INDEX_op_rotr_i32
:
2060 i1
= OPC_ROTRV
, i2
= OPC_ROTR
;
2063 tcg_out_opc_sa(s
, i2
, a0
, a1
, a2
);
2067 tcg_out_opc_reg(s
, i1
, a0
, a2
, a1
);
2069 case INDEX_op_rotl_i32
:
2071 tcg_out_opc_sa(s
, OPC_ROTR
, a0
, a1
, 32 - a2
);
2073 tcg_out_opc_reg(s
, OPC_SUBU
, TCG_TMP0
, TCG_REG_ZERO
, a2
);
2074 tcg_out_opc_reg(s
, OPC_ROTRV
, a0
, TCG_TMP0
, a1
);
2077 case INDEX_op_sar_i64
:
2079 tcg_out_dsra(s
, a0
, a1
, a2
);
2084 case INDEX_op_shl_i64
:
2086 tcg_out_dsll(s
, a0
, a1
, a2
);
2091 case INDEX_op_shr_i64
:
2093 tcg_out_dsrl(s
, a0
, a1
, a2
);
2098 case INDEX_op_rotr_i64
:
2100 tcg_out_opc_sa64(s
, OPC_DROTR
, OPC_DROTR32
, a0
, a1
, a2
);
2105 case INDEX_op_rotl_i64
:
2107 tcg_out_opc_sa64(s
, OPC_DROTR
, OPC_DROTR32
, a0
, a1
, 64 - a2
);
2109 tcg_out_opc_reg(s
, OPC_DSUBU
, TCG_TMP0
, TCG_REG_ZERO
, a2
);
2110 tcg_out_opc_reg(s
, OPC_DROTRV
, a0
, TCG_TMP0
, a1
);
2114 case INDEX_op_clz_i32
:
2115 tcg_out_clz(s
, OPC_CLZ
, OPC_CLZ_R6
, 32, a0
, a1
, a2
);
2117 case INDEX_op_clz_i64
:
2118 tcg_out_clz(s
, OPC_DCLZ
, OPC_DCLZ_R6
, 64, a0
, a1
, a2
);
2121 case INDEX_op_deposit_i32
:
2122 tcg_out_opc_bf(s
, OPC_INS
, a0
, a2
, args
[3] + args
[4] - 1, args
[3]);
2124 case INDEX_op_deposit_i64
:
2125 tcg_out_opc_bf64(s
, OPC_DINS
, OPC_DINSM
, OPC_DINSU
, a0
, a2
,
2126 args
[3] + args
[4] - 1, args
[3]);
2128 case INDEX_op_extract_i32
:
2129 tcg_out_opc_bf(s
, OPC_EXT
, a0
, a1
, args
[3] - 1, a2
);
2131 case INDEX_op_extract_i64
:
2132 tcg_out_opc_bf64(s
, OPC_DEXT
, OPC_DEXTM
, OPC_DEXTU
, a0
, a1
,
2136 case INDEX_op_brcond_i32
:
2137 case INDEX_op_brcond_i64
:
2138 tcg_out_brcond(s
, a2
, a0
, a1
, arg_label(args
[3]));
2140 case INDEX_op_brcond2_i32
:
2141 tcg_out_brcond2(s
, args
[4], a0
, a1
, a2
, args
[3], arg_label(args
[5]));
2144 case INDEX_op_movcond_i32
:
2145 case INDEX_op_movcond_i64
:
2146 tcg_out_movcond(s
, args
[5], a0
, a1
, a2
, args
[3], args
[4]);
2149 case INDEX_op_setcond_i32
:
2150 case INDEX_op_setcond_i64
:
2151 tcg_out_setcond(s
, args
[3], a0
, a1
, a2
);
2153 case INDEX_op_setcond2_i32
:
2154 tcg_out_setcond2(s
, args
[5], a0
, a1
, a2
, args
[3], args
[4]);
2157 case INDEX_op_qemu_ld_i32
:
2158 tcg_out_qemu_ld(s
, args
, false);
2160 case INDEX_op_qemu_ld_i64
:
2161 tcg_out_qemu_ld(s
, args
, true);
2163 case INDEX_op_qemu_st_i32
:
2164 tcg_out_qemu_st(s
, args
, false);
2166 case INDEX_op_qemu_st_i64
:
2167 tcg_out_qemu_st(s
, args
, true);
2170 case INDEX_op_add2_i32
:
2171 tcg_out_addsub2(s
, a0
, a1
, a2
, args
[3], args
[4], args
[5],
2172 const_args
[4], const_args
[5], false);
2174 case INDEX_op_sub2_i32
:
2175 tcg_out_addsub2(s
, a0
, a1
, a2
, args
[3], args
[4], args
[5],
2176 const_args
[4], const_args
[5], true);
2182 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
2183 case INDEX_op_mov_i64
:
2184 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
2185 case INDEX_op_movi_i64
:
2186 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
2192 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op
)
2194 static const TCGTargetOpDef r
= { .args_ct_str
= { "r" } };
2195 static const TCGTargetOpDef r_r
= { .args_ct_str
= { "r", "r" } };
2196 static const TCGTargetOpDef r_L
= { .args_ct_str
= { "r", "L" } };
2197 static const TCGTargetOpDef rZ_r
= { .args_ct_str
= { "rZ", "r" } };
2198 static const TCGTargetOpDef SZ_S
= { .args_ct_str
= { "SZ", "S" } };
2199 static const TCGTargetOpDef rZ_rZ
= { .args_ct_str
= { "rZ", "rZ" } };
2200 static const TCGTargetOpDef r_r_L
= { .args_ct_str
= { "r", "r", "L" } };
2201 static const TCGTargetOpDef r_L_L
= { .args_ct_str
= { "r", "L", "L" } };
2202 static const TCGTargetOpDef r_r_ri
= { .args_ct_str
= { "r", "r", "ri" } };
2203 static const TCGTargetOpDef r_r_rI
= { .args_ct_str
= { "r", "r", "rI" } };
2204 static const TCGTargetOpDef r_r_rJ
= { .args_ct_str
= { "r", "r", "rJ" } };
2205 static const TCGTargetOpDef SZ_S_S
= { .args_ct_str
= { "SZ", "S", "S" } };
2206 static const TCGTargetOpDef SZ_SZ_S
2207 = { .args_ct_str
= { "SZ", "SZ", "S" } };
2208 static const TCGTargetOpDef SZ_SZ_S_S
2209 = { .args_ct_str
= { "SZ", "SZ", "S", "S" } };
2210 static const TCGTargetOpDef r_rZ_rN
2211 = { .args_ct_str
= { "r", "rZ", "rN" } };
2212 static const TCGTargetOpDef r_rZ_rZ
2213 = { .args_ct_str
= { "r", "rZ", "rZ" } };
2214 static const TCGTargetOpDef r_r_rIK
2215 = { .args_ct_str
= { "r", "r", "rIK" } };
2216 static const TCGTargetOpDef r_r_rWZ
2217 = { .args_ct_str
= { "r", "r", "rWZ" } };
2218 static const TCGTargetOpDef r_r_r_r
2219 = { .args_ct_str
= { "r", "r", "r", "r" } };
2220 static const TCGTargetOpDef r_r_L_L
2221 = { .args_ct_str
= { "r", "r", "L", "L" } };
2222 static const TCGTargetOpDef dep
2223 = { .args_ct_str
= { "r", "0", "rZ" } };
2224 static const TCGTargetOpDef movc
2225 = { .args_ct_str
= { "r", "rZ", "rZ", "rZ", "0" } };
2226 static const TCGTargetOpDef movc_r6
2227 = { .args_ct_str
= { "r", "rZ", "rZ", "rZ", "rZ" } };
2228 static const TCGTargetOpDef add2
2229 = { .args_ct_str
= { "r", "r", "rZ", "rZ", "rN", "rN" } };
2230 static const TCGTargetOpDef br2
2231 = { .args_ct_str
= { "rZ", "rZ", "rZ", "rZ" } };
2232 static const TCGTargetOpDef setc2
2233 = { .args_ct_str
= { "r", "rZ", "rZ", "rZ", "rZ" } };
2236 case INDEX_op_goto_ptr
:
2239 case INDEX_op_ld8u_i32
:
2240 case INDEX_op_ld8s_i32
:
2241 case INDEX_op_ld16u_i32
:
2242 case INDEX_op_ld16s_i32
:
2243 case INDEX_op_ld_i32
:
2244 case INDEX_op_not_i32
:
2245 case INDEX_op_bswap16_i32
:
2246 case INDEX_op_bswap32_i32
:
2247 case INDEX_op_ext8s_i32
:
2248 case INDEX_op_ext16s_i32
:
2249 case INDEX_op_extract_i32
:
2250 case INDEX_op_ld8u_i64
:
2251 case INDEX_op_ld8s_i64
:
2252 case INDEX_op_ld16u_i64
:
2253 case INDEX_op_ld16s_i64
:
2254 case INDEX_op_ld32s_i64
:
2255 case INDEX_op_ld32u_i64
:
2256 case INDEX_op_ld_i64
:
2257 case INDEX_op_not_i64
:
2258 case INDEX_op_bswap16_i64
:
2259 case INDEX_op_bswap32_i64
:
2260 case INDEX_op_bswap64_i64
:
2261 case INDEX_op_ext8s_i64
:
2262 case INDEX_op_ext16s_i64
:
2263 case INDEX_op_ext32s_i64
:
2264 case INDEX_op_ext32u_i64
:
2265 case INDEX_op_ext_i32_i64
:
2266 case INDEX_op_extu_i32_i64
:
2267 case INDEX_op_extrl_i64_i32
:
2268 case INDEX_op_extrh_i64_i32
:
2269 case INDEX_op_extract_i64
:
2272 case INDEX_op_st8_i32
:
2273 case INDEX_op_st16_i32
:
2274 case INDEX_op_st_i32
:
2275 case INDEX_op_st8_i64
:
2276 case INDEX_op_st16_i64
:
2277 case INDEX_op_st32_i64
:
2278 case INDEX_op_st_i64
:
2281 case INDEX_op_add_i32
:
2282 case INDEX_op_add_i64
:
2284 case INDEX_op_sub_i32
:
2285 case INDEX_op_sub_i64
:
2287 case INDEX_op_mul_i32
:
2288 case INDEX_op_mulsh_i32
:
2289 case INDEX_op_muluh_i32
:
2290 case INDEX_op_div_i32
:
2291 case INDEX_op_divu_i32
:
2292 case INDEX_op_rem_i32
:
2293 case INDEX_op_remu_i32
:
2294 case INDEX_op_nor_i32
:
2295 case INDEX_op_setcond_i32
:
2296 case INDEX_op_mul_i64
:
2297 case INDEX_op_mulsh_i64
:
2298 case INDEX_op_muluh_i64
:
2299 case INDEX_op_div_i64
:
2300 case INDEX_op_divu_i64
:
2301 case INDEX_op_rem_i64
:
2302 case INDEX_op_remu_i64
:
2303 case INDEX_op_nor_i64
:
2304 case INDEX_op_setcond_i64
:
2306 case INDEX_op_muls2_i32
:
2307 case INDEX_op_mulu2_i32
:
2308 case INDEX_op_muls2_i64
:
2309 case INDEX_op_mulu2_i64
:
2311 case INDEX_op_and_i32
:
2312 case INDEX_op_and_i64
:
2314 case INDEX_op_or_i32
:
2315 case INDEX_op_xor_i32
:
2316 case INDEX_op_or_i64
:
2317 case INDEX_op_xor_i64
:
2319 case INDEX_op_shl_i32
:
2320 case INDEX_op_shr_i32
:
2321 case INDEX_op_sar_i32
:
2322 case INDEX_op_rotr_i32
:
2323 case INDEX_op_rotl_i32
:
2324 case INDEX_op_shl_i64
:
2325 case INDEX_op_shr_i64
:
2326 case INDEX_op_sar_i64
:
2327 case INDEX_op_rotr_i64
:
2328 case INDEX_op_rotl_i64
:
2330 case INDEX_op_clz_i32
:
2331 case INDEX_op_clz_i64
:
2334 case INDEX_op_deposit_i32
:
2335 case INDEX_op_deposit_i64
:
2337 case INDEX_op_brcond_i32
:
2338 case INDEX_op_brcond_i64
:
2340 case INDEX_op_movcond_i32
:
2341 case INDEX_op_movcond_i64
:
2342 return use_mips32r6_instructions
? &movc_r6
: &movc
;
2344 case INDEX_op_add2_i32
:
2345 case INDEX_op_sub2_i32
:
2347 case INDEX_op_setcond2_i32
:
2349 case INDEX_op_brcond2_i32
:
2352 case INDEX_op_qemu_ld_i32
:
2353 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2355 case INDEX_op_qemu_st_i32
:
2356 return (TCG_TARGET_REG_BITS
== 64 || TARGET_LONG_BITS
== 32
2358 case INDEX_op_qemu_ld_i64
:
2359 return (TCG_TARGET_REG_BITS
== 64 ? &r_L
2360 : TARGET_LONG_BITS
== 32 ? &r_r_L
: &r_r_L_L
);
2361 case INDEX_op_qemu_st_i64
:
2362 return (TCG_TARGET_REG_BITS
== 64 ? &SZ_S
2363 : TARGET_LONG_BITS
== 32 ? &SZ_SZ_S
: &SZ_SZ_S_S
);
2370 static const int tcg_target_callee_save_regs
[] = {
2371 TCG_REG_S0
, /* used for the global env (TCG_AREG0) */
2380 TCG_REG_RA
, /* should be last for ABI compliance */
2383 /* The Linux kernel doesn't provide any information about the available
2384 instruction set. Probe it using a signal handler. */
2387 #ifndef use_movnz_instructions
2388 bool use_movnz_instructions
= false;
2391 #ifndef use_mips32_instructions
2392 bool use_mips32_instructions
= false;
2395 #ifndef use_mips32r2_instructions
2396 bool use_mips32r2_instructions
= false;
2399 static volatile sig_atomic_t got_sigill
;
2401 static void sigill_handler(int signo
, siginfo_t
*si
, void *data
)
2403 /* Skip the faulty instruction */
2404 ucontext_t
*uc
= (ucontext_t
*)data
;
2405 uc
->uc_mcontext
.pc
+= 4;
2410 static void tcg_target_detect_isa(void)
2412 struct sigaction sa_old
, sa_new
;
2414 memset(&sa_new
, 0, sizeof(sa_new
));
2415 sa_new
.sa_flags
= SA_SIGINFO
;
2416 sa_new
.sa_sigaction
= sigill_handler
;
2417 sigaction(SIGILL
, &sa_new
, &sa_old
);
2419 /* Probe for movn/movz, necessary to implement movcond. */
2420 #ifndef use_movnz_instructions
2422 asm volatile(".set push\n"
2424 "movn $zero, $zero, $zero\n"
2425 "movz $zero, $zero, $zero\n"
2428 use_movnz_instructions
= !got_sigill
;
2431 /* Probe for MIPS32 instructions. As no subsetting is allowed
2432 by the specification, it is only necessary to probe for one
2433 of the instructions. */
2434 #ifndef use_mips32_instructions
2436 asm volatile(".set push\n"
2438 "mul $zero, $zero\n"
2441 use_mips32_instructions
= !got_sigill
;
2444 /* Probe for MIPS32r2 instructions if MIPS32 instructions are
2445 available. As no subsetting is allowed by the specification,
2446 it is only necessary to probe for one of the instructions. */
2447 #ifndef use_mips32r2_instructions
2448 if (use_mips32_instructions
) {
2450 asm volatile(".set push\n"
2452 "seb $zero, $zero\n"
2455 use_mips32r2_instructions
= !got_sigill
;
2459 sigaction(SIGILL
, &sa_old
, NULL
);
2462 static tcg_insn_unit
*align_code_ptr(TCGContext
*s
)
2464 uintptr_t p
= (uintptr_t)s
->code_ptr
;
2467 s
->code_ptr
= (void *)p
;
2472 /* Stack frame parameters. */
2473 #define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2474 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2475 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2477 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2478 + TCG_TARGET_STACK_ALIGN - 1) \
2479 & -TCG_TARGET_STACK_ALIGN)
2480 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2482 /* We're expecting to be able to use an immediate for frame allocation. */
2483 QEMU_BUILD_BUG_ON(FRAME_SIZE
> 0x7fff);
2485 /* Generate global QEMU prologue and epilogue code */
2486 static void tcg_target_qemu_prologue(TCGContext
*s
)
2490 tcg_set_frame(s
, TCG_REG_SP
, TCG_STATIC_CALL_ARGS_SIZE
, TEMP_SIZE
);
2493 tcg_out_opc_imm(s
, ALIAS_PADDI
, TCG_REG_SP
, TCG_REG_SP
, -FRAME_SIZE
);
2494 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
2495 tcg_out_st(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
2496 TCG_REG_SP
, SAVE_OFS
+ i
* REG_SIZE
);
2499 #ifndef CONFIG_SOFTMMU
2501 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_GUEST_BASE_REG
, guest_base
);
2502 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
2506 /* Call generated code */
2507 tcg_out_opc_reg(s
, OPC_JR
, 0, tcg_target_call_iarg_regs
[1], 0);
2509 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
2512 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2513 * and fall through to the rest of the epilogue.
2515 s
->code_gen_epilogue
= s
->code_ptr
;
2516 tcg_out_mov(s
, TCG_TYPE_REG
, TCG_REG_V0
, TCG_REG_ZERO
);
2519 tb_ret_addr
= s
->code_ptr
;
2520 for (i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
2521 tcg_out_ld(s
, TCG_TYPE_REG
, tcg_target_callee_save_regs
[i
],
2522 TCG_REG_SP
, SAVE_OFS
+ i
* REG_SIZE
);
2525 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_REG_RA
, 0);
2527 tcg_out_opc_imm(s
, ALIAS_PADDI
, TCG_REG_SP
, TCG_REG_SP
, FRAME_SIZE
);
2529 if (use_mips32r2_instructions
) {
2533 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2534 clobbers TCG_TMP1, TCG_TMP2. */
2537 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2539 bswap32_addr
= align_code_ptr(s
);
2540 /* t3 = (ssss)d000 */
2541 tcg_out_opc_sa(s
, OPC_SLL
, TCG_TMP3
, TCG_TMP0
, 24);
2543 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP1
, TCG_TMP0
, 24);
2545 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP2
, TCG_TMP0
, 0xff00);
2547 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2549 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP1
, TCG_TMP0
, 8);
2551 tcg_out_opc_sa(s
, OPC_SLL
, TCG_TMP2
, TCG_TMP2
, 8);
2553 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP1
, 0xff00);
2555 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP2
);
2556 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_REG_RA
, 0);
2557 /* t3 = dcba -- delay slot */
2558 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2560 if (TCG_TARGET_REG_BITS
== 32) {
2565 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2567 bswap32u_addr
= align_code_ptr(s
);
2568 /* t1 = (0000)000d */
2569 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP0
, 0xff);
2571 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP3
, TCG_TMP0
, 24);
2572 /* t1 = (0000)d000 */
2573 tcg_out_dsll(s
, TCG_TMP1
, TCG_TMP1
, 24);
2575 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP2
, TCG_TMP0
, 0xff00);
2577 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2579 tcg_out_opc_sa(s
, OPC_SRL
, TCG_TMP1
, TCG_TMP0
, 8);
2581 tcg_out_opc_sa(s
, OPC_SLL
, TCG_TMP2
, TCG_TMP2
, 8);
2583 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP1
, 0xff00);
2585 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP2
);
2586 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_REG_RA
, 0);
2587 /* t3 = dcba -- delay slot */
2588 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2591 * bswap64 -- 64-bit swap. a0 = abcdefgh
2593 bswap64_addr
= align_code_ptr(s
);
2595 tcg_out_dsll(s
, TCG_TMP3
, TCG_TMP0
, 56);
2597 tcg_out_dsrl(s
, TCG_TMP1
, TCG_TMP0
, 56);
2600 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP2
, TCG_TMP0
, 0xff00);
2602 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2604 tcg_out_dsrl(s
, TCG_TMP1
, TCG_TMP0
, 40);
2606 tcg_out_dsll(s
, TCG_TMP2
, TCG_TMP2
, 40);
2608 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP1
, 0xff00);
2611 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP2
);
2613 tcg_out_dsrl(s
, TCG_TMP2
, TCG_TMP0
, 32);
2615 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2618 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP2
, 0xff00);
2620 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP2
, TCG_TMP2
, 0x00ff);
2622 tcg_out_dsll(s
, TCG_TMP1
, TCG_TMP1
, 8);
2624 tcg_out_dsll(s
, TCG_TMP2
, TCG_TMP2
, 24);
2627 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2629 tcg_out_dsrl(s
, TCG_TMP1
, TCG_TMP0
, 16);
2631 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP2
);
2634 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP2
, TCG_TMP1
, 0x00ff);
2636 tcg_out_opc_imm(s
, OPC_ANDI
, TCG_TMP1
, TCG_TMP1
, 0xff00);
2638 tcg_out_dsll(s
, TCG_TMP2
, TCG_TMP2
, 40);
2640 tcg_out_dsll(s
, TCG_TMP1
, TCG_TMP1
, 24);
2643 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP2
);
2644 tcg_out_opc_reg(s
, OPC_JR
, 0, TCG_REG_RA
, 0);
2645 /* t3 = hgfedcba -- delay slot */
2646 tcg_out_opc_reg(s
, OPC_OR
, TCG_TMP3
, TCG_TMP3
, TCG_TMP1
);
2649 static void tcg_target_init(TCGContext
*s
)
2651 tcg_target_detect_isa();
2652 tcg_target_available_regs
[TCG_TYPE_I32
] = 0xffffffff;
2653 if (TCG_TARGET_REG_BITS
== 64) {
2654 tcg_target_available_regs
[TCG_TYPE_I64
] = 0xffffffff;
2657 tcg_target_call_clobber_regs
= 0;
2658 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_V0
);
2659 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_V1
);
2660 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_A0
);
2661 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_A1
);
2662 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_A2
);
2663 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_A3
);
2664 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T0
);
2665 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T1
);
2666 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T2
);
2667 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T3
);
2668 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T4
);
2669 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T5
);
2670 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T6
);
2671 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T7
);
2672 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T8
);
2673 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_T9
);
2675 s
->reserved_regs
= 0;
2676 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_ZERO
); /* zero register */
2677 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_K0
); /* kernel use only */
2678 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_K1
); /* kernel use only */
2679 tcg_regset_set_reg(s
->reserved_regs
, TCG_TMP0
); /* internal use */
2680 tcg_regset_set_reg(s
->reserved_regs
, TCG_TMP1
); /* internal use */
2681 tcg_regset_set_reg(s
->reserved_regs
, TCG_TMP2
); /* internal use */
2682 tcg_regset_set_reg(s
->reserved_regs
, TCG_TMP3
); /* internal use */
2683 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_RA
); /* return address */
2684 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_SP
); /* stack pointer */
2685 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_GP
); /* global pointer */
2688 void tb_target_set_jmp_target(uintptr_t tc_ptr
, uintptr_t jmp_addr
,
2691 atomic_set((uint32_t *)jmp_addr
, deposit32(OPC_J
, 0, 26, addr
>> 2));
2692 flush_icache_range(jmp_addr
, jmp_addr
+ 4);
2697 uint8_t fde_def_cfa
[4];
2698 uint8_t fde_reg_ofs
[ARRAY_SIZE(tcg_target_callee_save_regs
) * 2];
2701 #define ELF_HOST_MACHINE EM_MIPS
2702 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2703 which is good because they're really quite complicated for MIPS. */
2705 static const DebugFrame debug_frame
= {
2706 .h
.cie
.len
= sizeof(DebugFrameCIE
) - 4, /* length after .len member */
2709 .h
.cie
.code_align
= 1,
2710 .h
.cie
.data_align
= -(TCG_TARGET_REG_BITS
/ 8) & 0x7f, /* sleb128 */
2711 .h
.cie
.return_column
= TCG_REG_RA
,
2713 /* Total FDE size does not include the "len" member. */
2714 .h
.fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, h
.fde
.cie_offset
),
2717 12, TCG_REG_SP
, /* DW_CFA_def_cfa sp, ... */
2718 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2722 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2723 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2724 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2725 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2726 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2727 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2728 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2729 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2730 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2734 void tcg_register_jit(void *buf
, size_t buf_size
)
2736 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));