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hw/i386/pc: Pass the boot_cpus value by argument
[qemu/ar7.git] / hw / i386 / pc.c
blobdc2ae6d5cf7fcb32e4b69ff4cb5279bafe130341
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/i386/apic.h"
31 #include "hw/i386/topology.h"
32 #include "hw/i386/fw_cfg.h"
33 #include "sysemu/cpus.h"
34 #include "hw/block/fdc.h"
35 #include "hw/ide.h"
36 #include "hw/pci/pci.h"
37 #include "hw/pci/pci_bus.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/timer/hpet.h"
40 #include "hw/firmware/smbios.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "migration/vmstate.h"
44 #include "multiboot.h"
45 #include "hw/timer/mc146818rtc.h"
46 #include "hw/dma/i8257.h"
47 #include "hw/timer/i8254.h"
48 #include "hw/input/i8042.h"
49 #include "hw/irq.h"
50 #include "hw/audio/pcspk.h"
51 #include "hw/pci/msi.h"
52 #include "hw/sysbus.h"
53 #include "sysemu/sysemu.h"
54 #include "sysemu/tcg.h"
55 #include "sysemu/numa.h"
56 #include "sysemu/kvm.h"
57 #include "sysemu/qtest.h"
58 #include "sysemu/reset.h"
59 #include "sysemu/runstate.h"
60 #include "kvm_i386.h"
61 #include "hw/xen/xen.h"
62 #include "hw/xen/start_info.h"
63 #include "ui/qemu-spice.h"
64 #include "exec/memory.h"
65 #include "exec/address-spaces.h"
66 #include "sysemu/arch_init.h"
67 #include "qemu/bitmap.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "qemu/option.h"
71 #include "hw/acpi/acpi.h"
72 #include "hw/acpi/cpu_hotplug.h"
73 #include "hw/boards.h"
74 #include "acpi-build.h"
75 #include "hw/mem/pc-dimm.h"
76 #include "qapi/error.h"
77 #include "qapi/qapi-visit-common.h"
78 #include "qapi/visitor.h"
79 #include "hw/core/cpu.h"
80 #include "hw/nmi.h"
81 #include "hw/usb.h"
82 #include "hw/i386/intel_iommu.h"
83 #include "hw/net/ne2000-isa.h"
84 #include "standard-headers/asm-x86/bootparam.h"
85 #include "hw/virtio/virtio-pmem-pci.h"
86 #include "hw/mem/memory-device.h"
87 #include "sysemu/replay.h"
88 #include "qapi/qmp/qerror.h"
89 #include "config-devices.h"
90 #include "e820_memory_layout.h"
91
92 /* debug PC/ISA interrupts */
93 //#define DEBUG_IRQ
94
95 #ifdef DEBUG_IRQ
96 #define DPRINTF(fmt, ...) \
97 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
98 #else
99 #define DPRINTF(fmt, ...)
100 #endif
101
102 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
103
104 /* Physical Address of PVH entry point read from kernel ELF NOTE */
105 static size_t pvh_start_addr;
106
107 GlobalProperty pc_compat_4_1[] = {};
108 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
109
110 GlobalProperty pc_compat_4_0[] = {};
111 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
112
113 GlobalProperty pc_compat_3_1[] = {
114 { "intel-iommu", "dma-drain", "off" },
115 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
117 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
118 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
119 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
120 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
121 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
123 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
125 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
126 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
133 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
134 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
135 };
136 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
137
138 GlobalProperty pc_compat_3_0[] = {
139 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
140 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
142 };
143 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
144
145 GlobalProperty pc_compat_2_12[] = {
146 { TYPE_X86_CPU, "legacy-cache", "on" },
147 { TYPE_X86_CPU, "topoext", "off" },
148 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
150 };
151 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
152
153 GlobalProperty pc_compat_2_11[] = {
154 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
155 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
156 };
157 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
158
159 GlobalProperty pc_compat_2_10[] = {
160 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
161 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
162 { "q35-pcihost", "x-pci-hole64-fix", "off" },
163 };
164 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
165
166 GlobalProperty pc_compat_2_9[] = {
167 { "mch", "extended-tseg-mbytes", "0" },
168 };
169 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
170
171 GlobalProperty pc_compat_2_8[] = {
172 { TYPE_X86_CPU, "tcg-cpuid", "off" },
173 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
174 { "ICH9-LPC", "x-smi-broadcast", "off" },
175 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
176 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
177 };
178 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
179
180 GlobalProperty pc_compat_2_7[] = {
181 { TYPE_X86_CPU, "l3-cache", "off" },
182 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
185 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
186 { "isa-pcspk", "migrate", "off" },
187 };
188 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
189
190 GlobalProperty pc_compat_2_6[] = {
191 { TYPE_X86_CPU, "cpuid-0xb", "off" },
192 { "vmxnet3", "romfile", "" },
193 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
194 { "apic-common", "legacy-instance-id", "on", }
195 };
196 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
197
198 GlobalProperty pc_compat_2_5[] = {};
199 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
200
201 GlobalProperty pc_compat_2_4[] = {
202 PC_CPU_MODEL_IDS("2.4.0")
203 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
204 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
206 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
207 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
208 { TYPE_X86_CPU, "check", "off" },
209 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
211 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
213 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
216 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
217 };
218 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
219
220 GlobalProperty pc_compat_2_3[] = {
221 PC_CPU_MODEL_IDS("2.3.0")
222 { TYPE_X86_CPU, "arat", "off" },
223 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
224 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
225 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
226 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
227 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
230 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
242 };
243 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
244
245 GlobalProperty pc_compat_2_2[] = {
246 PC_CPU_MODEL_IDS("2.2.0")
247 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
248 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
253 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
262 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
264 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
265 };
266 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
267
268 GlobalProperty pc_compat_2_1[] = {
269 PC_CPU_MODEL_IDS("2.1.0")
270 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
271 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
272 };
273 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
274
275 GlobalProperty pc_compat_2_0[] = {
276 PC_CPU_MODEL_IDS("2.0.0")
277 { "virtio-scsi-pci", "any_layout", "off" },
278 { "PIIX4_PM", "memory-hotplug-support", "off" },
279 { "apic", "version", "0x11" },
280 { "nec-usb-xhci", "superspeed-ports-first", "off" },
281 { "nec-usb-xhci", "force-pcie-endcap", "on" },
282 { "pci-serial", "prog_if", "0" },
283 { "pci-serial-2x", "prog_if", "0" },
284 { "pci-serial-4x", "prog_if", "0" },
285 { "virtio-net-pci", "guest_announce", "off" },
286 { "ICH9-LPC", "memory-hotplug-support", "off" },
287 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
288 { "ioh3420", COMPAT_PROP_PCP, "off" },
289 };
290 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
291
292 GlobalProperty pc_compat_1_7[] = {
293 PC_CPU_MODEL_IDS("1.7.0")
294 { TYPE_USB_DEVICE, "msos-desc", "no" },
295 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
296 { "hpet", HPET_INTCAP, "4" },
297 };
298 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
299
300 GlobalProperty pc_compat_1_6[] = {
301 PC_CPU_MODEL_IDS("1.6.0")
302 { "e1000", "mitigation", "off" },
303 { "qemu64-" TYPE_X86_CPU, "model", "2" },
304 { "qemu32-" TYPE_X86_CPU, "model", "3" },
305 { "i440FX-pcihost", "short_root_bus", "1" },
306 { "q35-pcihost", "short_root_bus", "1" },
307 };
308 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
309
310 GlobalProperty pc_compat_1_5[] = {
311 PC_CPU_MODEL_IDS("1.5.0")
312 { "Conroe-" TYPE_X86_CPU, "model", "2" },
313 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
314 { "Penryn-" TYPE_X86_CPU, "model", "2" },
315 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
317 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
318 { "virtio-net-pci", "any_layout", "off" },
319 { TYPE_X86_CPU, "pmu", "on" },
320 { "i440FX-pcihost", "short_root_bus", "0" },
321 { "q35-pcihost", "short_root_bus", "0" },
322 };
323 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
324
325 GlobalProperty pc_compat_1_4[] = {
326 PC_CPU_MODEL_IDS("1.4.0")
327 { "scsi-hd", "discard_granularity", "0" },
328 { "scsi-cd", "discard_granularity", "0" },
329 { "scsi-disk", "discard_granularity", "0" },
330 { "ide-hd", "discard_granularity", "0" },
331 { "ide-cd", "discard_granularity", "0" },
332 { "ide-drive", "discard_granularity", "0" },
333 { "virtio-blk-pci", "discard_granularity", "0" },
334 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
335 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
336 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
337 { "e1000", "romfile", "pxe-e1000.rom" },
338 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
339 { "pcnet", "romfile", "pxe-pcnet.rom" },
340 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
341 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
342 { "486-" TYPE_X86_CPU, "model", "0" },
343 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
344 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
345 };
346 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
347
348 void gsi_handler(void *opaque, int n, int level)
349 {
350 GSIState *s = opaque;
351
352 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
353 if (n < ISA_NUM_IRQS) {
354 qemu_set_irq(s->i8259_irq[n], level);
355 }
356 qemu_set_irq(s->ioapic_irq[n], level);
357 }
358
359 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
360 unsigned size)
361 {
362 }
363
364 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
365 {
366 return 0xffffffffffffffffULL;
367 }
368
369 /* MSDOS compatibility mode FPU exception support */
370 static qemu_irq ferr_irq;
371
372 void pc_register_ferr_irq(qemu_irq irq)
373 {
374 ferr_irq = irq;
375 }
376
377 /* XXX: add IGNNE support */
378 void cpu_set_ferr(CPUX86State *s)
379 {
380 qemu_irq_raise(ferr_irq);
381 }
382
383 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
384 unsigned size)
385 {
386 qemu_irq_lower(ferr_irq);
387 }
388
389 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
390 {
391 return 0xffffffffffffffffULL;
392 }
393
394 /* TSC handling */
395 uint64_t cpu_get_tsc(CPUX86State *env)
396 {
397 return cpu_get_ticks();
398 }
399
400 /* IRQ handling */
401 int cpu_get_pic_interrupt(CPUX86State *env)
402 {
403 X86CPU *cpu = env_archcpu(env);
404 int intno;
405
406 if (!kvm_irqchip_in_kernel()) {
407 intno = apic_get_interrupt(cpu->apic_state);
408 if (intno >= 0) {
409 return intno;
410 }
411 /* read the irq from the PIC */
412 if (!apic_accept_pic_intr(cpu->apic_state)) {
413 return -1;
414 }
415 }
416
417 intno = pic_read_irq(isa_pic);
418 return intno;
419 }
420
421 static void pic_irq_request(void *opaque, int irq, int level)
422 {
423 CPUState *cs = first_cpu;
424 X86CPU *cpu = X86_CPU(cs);
425
426 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
427 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
428 CPU_FOREACH(cs) {
429 cpu = X86_CPU(cs);
430 if (apic_accept_pic_intr(cpu->apic_state)) {
431 apic_deliver_pic_intr(cpu->apic_state, level);
432 }
433 }
434 } else {
435 if (level) {
436 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
437 } else {
438 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
439 }
440 }
441 }
442
443 /* PC cmos mappings */
444
445 #define REG_EQUIPMENT_BYTE 0x14
446
447 int cmos_get_fd_drive_type(FloppyDriveType fd0)
448 {
449 int val;
450
451 switch (fd0) {
452 case FLOPPY_DRIVE_TYPE_144:
453 /* 1.44 Mb 3"5 drive */
454 val = 4;
455 break;
456 case FLOPPY_DRIVE_TYPE_288:
457 /* 2.88 Mb 3"5 drive */
458 val = 5;
459 break;
460 case FLOPPY_DRIVE_TYPE_120:
461 /* 1.2 Mb 5"5 drive */
462 val = 2;
463 break;
464 case FLOPPY_DRIVE_TYPE_NONE:
465 default:
466 val = 0;
467 break;
468 }
469 return val;
470 }
471
472 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
473 int16_t cylinders, int8_t heads, int8_t sectors)
474 {
475 rtc_set_memory(s, type_ofs, 47);
476 rtc_set_memory(s, info_ofs, cylinders);
477 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
478 rtc_set_memory(s, info_ofs + 2, heads);
479 rtc_set_memory(s, info_ofs + 3, 0xff);
480 rtc_set_memory(s, info_ofs + 4, 0xff);
481 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
482 rtc_set_memory(s, info_ofs + 6, cylinders);
483 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
484 rtc_set_memory(s, info_ofs + 8, sectors);
485 }
486
487 /* convert boot_device letter to something recognizable by the bios */
488 static int boot_device2nibble(char boot_device)
489 {
490 switch(boot_device) {
491 case 'a':
492 case 'b':
493 return 0x01; /* floppy boot */
494 case 'c':
495 return 0x02; /* hard drive boot */
496 case 'd':
497 return 0x03; /* CD-ROM boot */
498 case 'n':
499 return 0x04; /* Network boot */
500 }
501 return 0;
502 }
503
504 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
505 {
506 #define PC_MAX_BOOT_DEVICES 3
507 int nbds, bds[3] = { 0, };
508 int i;
509
510 nbds = strlen(boot_device);
511 if (nbds > PC_MAX_BOOT_DEVICES) {
512 error_setg(errp, "Too many boot devices for PC");
513 return;
514 }
515 for (i = 0; i < nbds; i++) {
516 bds[i] = boot_device2nibble(boot_device[i]);
517 if (bds[i] == 0) {
518 error_setg(errp, "Invalid boot device for PC: '%c'",
519 boot_device[i]);
520 return;
521 }
522 }
523 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
524 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
525 }
526
527 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
528 {
529 set_boot_dev(opaque, boot_device, errp);
530 }
531
532 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
533 {
534 int val, nb, i;
535 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
536 FLOPPY_DRIVE_TYPE_NONE };
537
538 /* floppy type */
539 if (floppy) {
540 for (i = 0; i < 2; i++) {
541 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
542 }
543 }
544 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
545 cmos_get_fd_drive_type(fd_type[1]);
546 rtc_set_memory(rtc_state, 0x10, val);
547
548 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
549 nb = 0;
550 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
551 nb++;
552 }
553 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
554 nb++;
555 }
556 switch (nb) {
557 case 0:
558 break;
559 case 1:
560 val |= 0x01; /* 1 drive, ready for boot */
561 break;
562 case 2:
563 val |= 0x41; /* 2 drives, ready for boot */
564 break;
565 }
566 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
567 }
568
569 typedef struct pc_cmos_init_late_arg {
570 ISADevice *rtc_state;
571 BusState *idebus[2];
572 } pc_cmos_init_late_arg;
573
574 typedef struct check_fdc_state {
575 ISADevice *floppy;
576 bool multiple;
577 } CheckFdcState;
578
579 static int check_fdc(Object *obj, void *opaque)
580 {
581 CheckFdcState *state = opaque;
582 Object *fdc;
583 uint32_t iobase;
584 Error *local_err = NULL;
585
586 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
587 if (!fdc) {
588 return 0;
589 }
590
591 iobase = object_property_get_uint(obj, "iobase", &local_err);
592 if (local_err || iobase != 0x3f0) {
593 error_free(local_err);
594 return 0;
595 }
596
597 if (state->floppy) {
598 state->multiple = true;
599 } else {
600 state->floppy = ISA_DEVICE(obj);
601 }
602 return 0;
603 }
604
605 static const char * const fdc_container_path[] = {
606 "/unattached", "/peripheral", "/peripheral-anon"
607 };
608
609 /*
610 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
611 * and ACPI objects.
612 */
613 ISADevice *pc_find_fdc0(void)
614 {
615 int i;
616 Object *container;
617 CheckFdcState state = { 0 };
618
619 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
620 container = container_get(qdev_get_machine(), fdc_container_path[i]);
621 object_child_foreach(container, check_fdc, &state);
622 }
623
624 if (state.multiple) {
625 warn_report("multiple floppy disk controllers with "
626 "iobase=0x3f0 have been found");
627 error_printf("the one being picked for CMOS setup might not reflect "
628 "your intent");
629 }
630
631 return state.floppy;
632 }
633
634 static void pc_cmos_init_late(void *opaque)
635 {
636 pc_cmos_init_late_arg *arg = opaque;
637 ISADevice *s = arg->rtc_state;
638 int16_t cylinders;
639 int8_t heads, sectors;
640 int val;
641 int i, trans;
642
643 val = 0;
644 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
645 &cylinders, &heads, &sectors) >= 0) {
646 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
647 val |= 0xf0;
648 }
649 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
650 &cylinders, &heads, &sectors) >= 0) {
651 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
652 val |= 0x0f;
653 }
654 rtc_set_memory(s, 0x12, val);
655
656 val = 0;
657 for (i = 0; i < 4; i++) {
658 /* NOTE: ide_get_geometry() returns the physical
659 geometry. It is always such that: 1 <= sects <= 63, 1
660 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
661 geometry can be different if a translation is done. */
662 if (arg->idebus[i / 2] &&
663 ide_get_geometry(arg->idebus[i / 2], i % 2,
664 &cylinders, &heads, &sectors) >= 0) {
665 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
666 assert((trans & ~3) == 0);
667 val |= trans << (i * 2);
668 }
669 }
670 rtc_set_memory(s, 0x39, val);
671
672 pc_cmos_init_floppy(s, pc_find_fdc0());
673
674 qemu_unregister_reset(pc_cmos_init_late, opaque);
675 }
676
677 void pc_cmos_init(PCMachineState *pcms,
678 BusState *idebus0, BusState *idebus1,
679 ISADevice *s)
680 {
681 int val;
682 static pc_cmos_init_late_arg arg;
683
684 /* various important CMOS locations needed by PC/Bochs bios */
685
686 /* memory size */
687 /* base memory (first MiB) */
688 val = MIN(pcms->below_4g_mem_size / KiB, 640);
689 rtc_set_memory(s, 0x15, val);
690 rtc_set_memory(s, 0x16, val >> 8);
691 /* extended memory (next 64MiB) */
692 if (pcms->below_4g_mem_size > 1 * MiB) {
693 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
694 } else {
695 val = 0;
696 }
697 if (val > 65535)
698 val = 65535;
699 rtc_set_memory(s, 0x17, val);
700 rtc_set_memory(s, 0x18, val >> 8);
701 rtc_set_memory(s, 0x30, val);
702 rtc_set_memory(s, 0x31, val >> 8);
703 /* memory between 16MiB and 4GiB */
704 if (pcms->below_4g_mem_size > 16 * MiB) {
705 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
706 } else {
707 val = 0;
708 }
709 if (val > 65535)
710 val = 65535;
711 rtc_set_memory(s, 0x34, val);
712 rtc_set_memory(s, 0x35, val >> 8);
713 /* memory above 4GiB */
714 val = pcms->above_4g_mem_size / 65536;
715 rtc_set_memory(s, 0x5b, val);
716 rtc_set_memory(s, 0x5c, val >> 8);
717 rtc_set_memory(s, 0x5d, val >> 16);
718
719 object_property_add_link(OBJECT(pcms), "rtc_state",
720 TYPE_ISA_DEVICE,
721 (Object **)&pcms->rtc,
722 object_property_allow_set_link,
723 OBJ_PROP_LINK_STRONG, &error_abort);
724 object_property_set_link(OBJECT(pcms), OBJECT(s),
725 "rtc_state", &error_abort);
726
727 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
728
729 val = 0;
730 val |= 0x02; /* FPU is there */
731 val |= 0x04; /* PS/2 mouse installed */
732 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
733
734 /* hard drives and FDC */
735 arg.rtc_state = s;
736 arg.idebus[0] = idebus0;
737 arg.idebus[1] = idebus1;
738 qemu_register_reset(pc_cmos_init_late, &arg);
739 }
740
741 #define TYPE_PORT92 "port92"
742 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
743
744 /* port 92 stuff: could be split off */
745 typedef struct Port92State {
746 ISADevice parent_obj;
747
748 MemoryRegion io;
749 uint8_t outport;
750 qemu_irq a20_out;
751 } Port92State;
752
753 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
754 unsigned size)
755 {
756 Port92State *s = opaque;
757 int oldval = s->outport;
758
759 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
760 s->outport = val;
761 qemu_set_irq(s->a20_out, (val >> 1) & 1);
762 if ((val & 1) && !(oldval & 1)) {
763 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
764 }
765 }
766
767 static uint64_t port92_read(void *opaque, hwaddr addr,
768 unsigned size)
769 {
770 Port92State *s = opaque;
771 uint32_t ret;
772
773 ret = s->outport;
774 DPRINTF("port92: read 0x%02x\n", ret);
775 return ret;
776 }
777
778 static void port92_init(ISADevice *dev, qemu_irq a20_out)
779 {
780 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
781 }
782
783 static const VMStateDescription vmstate_port92_isa = {
784 .name = "port92",
785 .version_id = 1,
786 .minimum_version_id = 1,
787 .fields = (VMStateField[]) {
788 VMSTATE_UINT8(outport, Port92State),
789 VMSTATE_END_OF_LIST()
790 }
791 };
792
793 static void port92_reset(DeviceState *d)
794 {
795 Port92State *s = PORT92(d);
796
797 s->outport &= ~1;
798 }
799
800 static const MemoryRegionOps port92_ops = {
801 .read = port92_read,
802 .write = port92_write,
803 .impl = {
804 .min_access_size = 1,
805 .max_access_size = 1,
806 },
807 .endianness = DEVICE_LITTLE_ENDIAN,
808 };
809
810 static void port92_initfn(Object *obj)
811 {
812 Port92State *s = PORT92(obj);
813
814 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
815
816 s->outport = 0;
817
818 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
819 }
820
821 static void port92_realizefn(DeviceState *dev, Error **errp)
822 {
823 ISADevice *isadev = ISA_DEVICE(dev);
824 Port92State *s = PORT92(dev);
825
826 isa_register_ioport(isadev, &s->io, 0x92);
827 }
828
829 static void port92_class_initfn(ObjectClass *klass, void *data)
830 {
831 DeviceClass *dc = DEVICE_CLASS(klass);
832
833 dc->realize = port92_realizefn;
834 dc->reset = port92_reset;
835 dc->vmsd = &vmstate_port92_isa;
836 /*
837 * Reason: unlike ordinary ISA devices, this one needs additional
838 * wiring: its A20 output line needs to be wired up by
839 * port92_init().
840 */
841 dc->user_creatable = false;
842 }
843
844 static const TypeInfo port92_info = {
845 .name = TYPE_PORT92,
846 .parent = TYPE_ISA_DEVICE,
847 .instance_size = sizeof(Port92State),
848 .instance_init = port92_initfn,
849 .class_init = port92_class_initfn,
850 };
851
852 static void port92_register_types(void)
853 {
854 type_register_static(&port92_info);
855 }
856
857 type_init(port92_register_types)
858
859 static void handle_a20_line_change(void *opaque, int irq, int level)
860 {
861 X86CPU *cpu = opaque;
862
863 /* XXX: send to all CPUs ? */
864 /* XXX: add logic to handle multiple A20 line sources */
865 x86_cpu_set_a20(cpu, level);
866 }
867
868 /* Calculates initial APIC ID for a specific CPU index
869 *
870 * Currently we need to be able to calculate the APIC ID from the CPU index
871 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
872 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
873 * all CPUs up to max_cpus.
874 */
875 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
876 unsigned int cpu_index)
877 {
878 MachineState *ms = MACHINE(pcms);
879 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
880 uint32_t correct_id;
881 static bool warned;
882
883 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
884 ms->smp.threads, cpu_index);
885 if (pcmc->compat_apic_id_mode) {
886 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
887 error_report("APIC IDs set in compatibility mode, "
888 "CPU topology won't match the configuration");
889 warned = true;
890 }
891 return cpu_index;
892 } else {
893 return correct_id;
894 }
895 }
896
897 static void pc_build_smbios(PCMachineState *pcms)
898 {
899 uint8_t *smbios_tables, *smbios_anchor;
900 size_t smbios_tables_len, smbios_anchor_len;
901 struct smbios_phys_mem_area *mem_array;
902 unsigned i, array_count;
903 MachineState *ms = MACHINE(pcms);
904 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
905
906 /* tell smbios about cpuid version and features */
907 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
908
909 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
910 if (smbios_tables) {
911 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
912 smbios_tables, smbios_tables_len);
913 }
914
915 /* build the array of physical mem area from e820 table */
916 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
917 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
918 uint64_t addr, len;
919
920 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
921 mem_array[array_count].address = addr;
922 mem_array[array_count].length = len;
923 array_count++;
924 }
925 }
926 smbios_get_tables(ms, mem_array, array_count,
927 &smbios_tables, &smbios_tables_len,
928 &smbios_anchor, &smbios_anchor_len);
929 g_free(mem_array);
930
931 if (smbios_anchor) {
932 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
933 smbios_tables, smbios_tables_len);
934 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
935 smbios_anchor, smbios_anchor_len);
936 }
937 }
938
939 static FWCfgState *fw_cfg_arch_create(PCMachineState *pcms,
940 uint16_t boot_cpus)
941 {
942 FWCfgState *fw_cfg;
943 uint64_t *numa_fw_cfg;
944 int i;
945 const CPUArchIdList *cpus;
946 MachineClass *mc = MACHINE_GET_CLASS(pcms);
947 MachineState *ms = MACHINE(pcms);
948 int nb_numa_nodes = ms->numa_state->num_nodes;
949
950 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
951 &address_space_memory);
952 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
953
954 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
955 *
956 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
957 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
958 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
959 * for CPU hotplug also uses APIC ID and not "CPU index".
960 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
961 * but the "limit to the APIC ID values SeaBIOS may see".
962 *
963 * So for compatibility reasons with old BIOSes we are stuck with
964 * "etc/max-cpus" actually being apic_id_limit
965 */
966 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
967 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
968 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
969 acpi_tables, acpi_tables_len);
970 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
971
972 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
973 &e820_reserve, sizeof(e820_reserve));
974 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
975 sizeof(struct e820_entry) * e820_get_num_entries());
976
977 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
978 /* allocate memory for the NUMA channel: one (64bit) word for the number
979 * of nodes, one word for each VCPU->node and one word for each node to
980 * hold the amount of memory.
981 */
982 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
983 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
984 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
985 for (i = 0; i < cpus->len; i++) {
986 unsigned int apic_id = cpus->cpus[i].arch_id;
987 assert(apic_id < pcms->apic_id_limit);
988 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
989 }
990 for (i = 0; i < nb_numa_nodes; i++) {
991 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
992 cpu_to_le64(ms->numa_state->nodes[i].node_mem);
993 }
994 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
995 (1 + pcms->apic_id_limit + nb_numa_nodes) *
996 sizeof(*numa_fw_cfg));
997
998 return fw_cfg;
999 }
1000
1001 static long get_file_size(FILE *f)
1002 {
1003 long where, size;
1004
1005 /* XXX: on Unix systems, using fstat() probably makes more sense */
1006
1007 where = ftell(f);
1008 fseek(f, 0, SEEK_END);
1009 size = ftell(f);
1010 fseek(f, where, SEEK_SET);
1011
1012 return size;
1013 }
1014
1015 struct setup_data {
1016 uint64_t next;
1017 uint32_t type;
1018 uint32_t len;
1019 uint8_t data[0];
1020 } __attribute__((packed));
1021
1022
1023 /*
1024 * The entry point into the kernel for PVH boot is different from
1025 * the native entry point. The PVH entry is defined by the x86/HVM
1026 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1027 *
1028 * This function is passed to load_elf() when it is called from
1029 * load_elfboot() which then additionally checks for an ELF Note of
1030 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1031 * parse the PVH entry address from the ELF Note.
1032 *
1033 * Due to trickery in elf_opts.h, load_elf() is actually available as
1034 * load_elf32() or load_elf64() and this routine needs to be able
1035 * to deal with being called as 32 or 64 bit.
1036 *
1037 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1038 * global variable. (although the entry point is 32-bit, the kernel
1039 * binary can be either 32-bit or 64-bit).
1040 */
1041 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1042 {
1043 size_t *elf_note_data_addr;
1044
1045 /* Check if ELF Note header passed in is valid */
1046 if (arg1 == NULL) {
1047 return 0;
1048 }
1049
1050 if (is64) {
1051 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1052 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1053 uint64_t phdr_align = *(uint64_t *)arg2;
1054 uint64_t nhdr_namesz = nhdr64->n_namesz;
1055
1056 elf_note_data_addr =
1057 ((void *)nhdr64) + nhdr_size64 +
1058 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1059 } else {
1060 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1061 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1062 uint32_t phdr_align = *(uint32_t *)arg2;
1063 uint32_t nhdr_namesz = nhdr32->n_namesz;
1064
1065 elf_note_data_addr =
1066 ((void *)nhdr32) + nhdr_size32 +
1067 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1068 }
1069
1070 pvh_start_addr = *elf_note_data_addr;
1071
1072 return pvh_start_addr;
1073 }
1074
1075 static bool load_elfboot(const char *kernel_filename,
1076 int kernel_file_size,
1077 uint8_t *header,
1078 size_t pvh_xen_start_addr,
1079 FWCfgState *fw_cfg)
1080 {
1081 uint32_t flags = 0;
1082 uint32_t mh_load_addr = 0;
1083 uint32_t elf_kernel_size = 0;
1084 uint64_t elf_entry;
1085 uint64_t elf_low, elf_high;
1086 int kernel_size;
1087
1088 if (ldl_p(header) != 0x464c457f) {
1089 return false; /* no elfboot */
1090 }
1091
1092 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1093 flags = elf_is64 ?
1094 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1095
1096 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1097 error_report("elfboot unsupported flags = %x", flags);
1098 exit(1);
1099 }
1100
1101 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1102 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1103 NULL, &elf_note_type, &elf_entry,
1104 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1105 0, 0);
1106
1107 if (kernel_size < 0) {
1108 error_report("Error while loading elf kernel");
1109 exit(1);
1110 }
1111 mh_load_addr = elf_low;
1112 elf_kernel_size = elf_high - elf_low;
1113
1114 if (pvh_start_addr == 0) {
1115 error_report("Error loading uncompressed kernel without PVH ELF Note");
1116 exit(1);
1117 }
1118 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1119 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1120 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1121
1122 return true;
1123 }
1124
1125 static void load_linux(PCMachineState *pcms,
1126 FWCfgState *fw_cfg)
1127 {
1128 uint16_t protocol;
1129 int setup_size, kernel_size, cmdline_size;
1130 int dtb_size, setup_data_offset;
1131 uint32_t initrd_max;
1132 uint8_t header[8192], *setup, *kernel;
1133 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1134 FILE *f;
1135 char *vmode;
1136 MachineState *machine = MACHINE(pcms);
1137 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1138 struct setup_data *setup_data;
1139 const char *kernel_filename = machine->kernel_filename;
1140 const char *initrd_filename = machine->initrd_filename;
1141 const char *dtb_filename = machine->dtb;
1142 const char *kernel_cmdline = machine->kernel_cmdline;
1143
1144 /* Align to 16 bytes as a paranoia measure */
1145 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1146
1147 /* load the kernel header */
1148 f = fopen(kernel_filename, "rb");
1149 if (!f || !(kernel_size = get_file_size(f)) ||
1150 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1151 MIN(ARRAY_SIZE(header), kernel_size)) {
1152 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1153 kernel_filename, strerror(errno));
1154 exit(1);
1155 }
1156
1157 /* kernel protocol version */
1158 #if 0
1159 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
1160 #endif
1161 if (ldl_p(header+0x202) == 0x53726448) {
1162 protocol = lduw_p(header+0x206);
1163 } else {
1164 /*
1165 * This could be a multiboot kernel. If it is, let's stop treating it
1166 * like a Linux kernel.
1167 * Note: some multiboot images could be in the ELF format (the same of
1168 * PVH), so we try multiboot first since we check the multiboot magic
1169 * header before to load it.
1170 */
1171 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1172 kernel_cmdline, kernel_size, header)) {
1173 return;
1174 }
1175 /*
1176 * Check if the file is an uncompressed kernel file (ELF) and load it,
1177 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1178 * If load_elfboot() is successful, populate the fw_cfg info.
1179 */
1180 if (pcmc->pvh_enabled &&
1181 load_elfboot(kernel_filename, kernel_size,
1182 header, pvh_start_addr, fw_cfg)) {
1183 fclose(f);
1184
1185 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1186 strlen(kernel_cmdline) + 1);
1187 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1188
1189 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1190 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1191 header, sizeof(header));
1192
1193 /* load initrd */
1194 if (initrd_filename) {
1195 GMappedFile *mapped_file;
1196 gsize initrd_size;
1197 gchar *initrd_data;
1198 GError *gerr = NULL;
1199
1200 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1201 if (!mapped_file) {
1202 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1203 initrd_filename, gerr->message);
1204 exit(1);
1205 }
1206 pcms->initrd_mapped_file = mapped_file;
1207
1208 initrd_data = g_mapped_file_get_contents(mapped_file);
1209 initrd_size = g_mapped_file_get_length(mapped_file);
1210 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1211 if (initrd_size >= initrd_max) {
1212 fprintf(stderr, "qemu: initrd is too large, cannot support."
1213 "(max: %"PRIu32", need %"PRId64")\n",
1214 initrd_max, (uint64_t)initrd_size);
1215 exit(1);
1216 }
1217
1218 initrd_addr = (initrd_max - initrd_size) & ~4095;
1219
1220 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1221 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1222 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1223 initrd_size);
1224 }
1225
1226 option_rom[nb_option_roms].bootindex = 0;
1227 option_rom[nb_option_roms].name = "pvh.bin";
1228 nb_option_roms++;
1229
1230 return;
1231 }
1232 protocol = 0;
1233 }
1234
1235 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
1236 /* Low kernel */
1237 real_addr = 0x90000;
1238 cmdline_addr = 0x9a000 - cmdline_size;
1239 prot_addr = 0x10000;
1240 } else if (protocol < 0x202) {
1241 /* High but ancient kernel */
1242 real_addr = 0x90000;
1243 cmdline_addr = 0x9a000 - cmdline_size;
1244 prot_addr = 0x100000;
1245 } else {
1246 /* High and recent kernel */
1247 real_addr = 0x10000;
1248 cmdline_addr = 0x20000;
1249 prot_addr = 0x100000;
1250 }
1251
1252 #if 0
1253 fprintf(stderr,
1254 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1255 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1256 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1257 real_addr,
1258 cmdline_addr,
1259 prot_addr);
1260 #endif
1261
1262 /* highest address for loading the initrd */
1263 if (protocol >= 0x20c &&
1264 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1265 /*
1266 * Linux has supported initrd up to 4 GB for a very long time (2007,
1267 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1268 * though it only sets initrd_max to 2 GB to "work around bootloader
1269 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1270 * has supported this.
1271 *
1272 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1273 * be loaded into any address.
1274 *
1275 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1276 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1277 * field).
1278 *
1279 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1280 */
1281 initrd_max = UINT32_MAX;
1282 } else if (protocol >= 0x203) {
1283 initrd_max = ldl_p(header+0x22c);
1284 } else {
1285 initrd_max = 0x37ffffff;
1286 }
1287
1288 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1289 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1290 }
1291
1292 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1293 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
1294 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1295
1296 if (protocol >= 0x202) {
1297 stl_p(header+0x228, cmdline_addr);
1298 } else {
1299 stw_p(header+0x20, 0xA33F);
1300 stw_p(header+0x22, cmdline_addr-real_addr);
1301 }
1302
1303 /* handle vga= parameter */
1304 vmode = strstr(kernel_cmdline, "vga=");
1305 if (vmode) {
1306 unsigned int video_mode;
1307 /* skip "vga=" */
1308 vmode += 4;
1309 if (!strncmp(vmode, "normal", 6)) {
1310 video_mode = 0xffff;
1311 } else if (!strncmp(vmode, "ext", 3)) {
1312 video_mode = 0xfffe;
1313 } else if (!strncmp(vmode, "ask", 3)) {
1314 video_mode = 0xfffd;
1315 } else {
1316 video_mode = strtol(vmode, NULL, 0);
1317 }
1318 stw_p(header+0x1fa, video_mode);
1319 }
1320
1321 /* loader type */
1322 /* High nybble = B reserved for QEMU; low nybble is revision number.
1323 If this code is substantially changed, you may want to consider
1324 incrementing the revision. */
1325 if (protocol >= 0x200) {
1326 header[0x210] = 0xB0;
1327 }
1328 /* heap */
1329 if (protocol >= 0x201) {
1330 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1331 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
1332 }
1333
1334 /* load initrd */
1335 if (initrd_filename) {
1336 GMappedFile *mapped_file;
1337 gsize initrd_size;
1338 gchar *initrd_data;
1339 GError *gerr = NULL;
1340
1341 if (protocol < 0x200) {
1342 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1343 exit(1);
1344 }
1345
1346 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1347 if (!mapped_file) {
1348 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1349 initrd_filename, gerr->message);
1350 exit(1);
1351 }
1352 pcms->initrd_mapped_file = mapped_file;
1353
1354 initrd_data = g_mapped_file_get_contents(mapped_file);
1355 initrd_size = g_mapped_file_get_length(mapped_file);
1356 if (initrd_size >= initrd_max) {
1357 fprintf(stderr, "qemu: initrd is too large, cannot support."
1358 "(max: %"PRIu32", need %"PRId64")\n",
1359 initrd_max, (uint64_t)initrd_size);
1360 exit(1);
1361 }
1362
1363 initrd_addr = (initrd_max-initrd_size) & ~4095;
1364
1365 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1366 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1367 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1368
1369 stl_p(header+0x218, initrd_addr);
1370 stl_p(header+0x21c, initrd_size);
1371 }
1372
1373 /* load kernel and setup */
1374 setup_size = header[0x1f1];
1375 if (setup_size == 0) {
1376 setup_size = 4;
1377 }
1378 setup_size = (setup_size+1)*512;
1379 if (setup_size > kernel_size) {
1380 fprintf(stderr, "qemu: invalid kernel header\n");
1381 exit(1);
1382 }
1383 kernel_size -= setup_size;
1384
1385 setup = g_malloc(setup_size);
1386 kernel = g_malloc(kernel_size);
1387 fseek(f, 0, SEEK_SET);
1388 if (fread(setup, 1, setup_size, f) != setup_size) {
1389 fprintf(stderr, "fread() failed\n");
1390 exit(1);
1391 }
1392 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1393 fprintf(stderr, "fread() failed\n");
1394 exit(1);
1395 }
1396 fclose(f);
1397
1398 /* append dtb to kernel */
1399 if (dtb_filename) {
1400 if (protocol < 0x209) {
1401 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1402 exit(1);
1403 }
1404
1405 dtb_size = get_image_size(dtb_filename);
1406 if (dtb_size <= 0) {
1407 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1408 dtb_filename, strerror(errno));
1409 exit(1);
1410 }
1411
1412 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1413 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1414 kernel = g_realloc(kernel, kernel_size);
1415
1416 stq_p(header+0x250, prot_addr + setup_data_offset);
1417
1418 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1419 setup_data->next = 0;
1420 setup_data->type = cpu_to_le32(SETUP_DTB);
1421 setup_data->len = cpu_to_le32(dtb_size);
1422
1423 load_image_size(dtb_filename, setup_data->data, dtb_size);
1424 }
1425
1426 memcpy(setup, header, MIN(sizeof(header), setup_size));
1427
1428 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1429 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1430 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1431
1432 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1433 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1434 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1435
1436 option_rom[nb_option_roms].bootindex = 0;
1437 option_rom[nb_option_roms].name = "linuxboot.bin";
1438 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
1439 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
1440 }
1441 nb_option_roms++;
1442 }
1443
1444 #define NE2000_NB_MAX 6
1445
1446 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1447 0x280, 0x380 };
1448 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1449
1450 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1451 {
1452 static int nb_ne2k = 0;
1453
1454 if (nb_ne2k == NE2000_NB_MAX)
1455 return;
1456 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1457 ne2000_irq[nb_ne2k], nd);
1458 nb_ne2k++;
1459 }
1460
1461 DeviceState *cpu_get_current_apic(void)
1462 {
1463 if (current_cpu) {
1464 X86CPU *cpu = X86_CPU(current_cpu);
1465 return cpu->apic_state;
1466 } else {
1467 return NULL;
1468 }
1469 }
1470
1471 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
1472 {
1473 X86CPU *cpu = opaque;
1474
1475 if (level) {
1476 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
1477 }
1478 }
1479
1480 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
1481 {
1482 Object *cpu = NULL;
1483 Error *local_err = NULL;
1484 CPUX86State *env = NULL;
1485
1486 cpu = object_new(MACHINE(pcms)->cpu_type);
1487
1488 env = &X86_CPU(cpu)->env;
1489 env->nr_dies = pcms->smp_dies;
1490
1491 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
1492 object_property_set_bool(cpu, true, "realized", &local_err);
1493
1494 object_unref(cpu);
1495 error_propagate(errp, local_err);
1496 }
1497
1498 /*
1499 * This function is very similar to smp_parse()
1500 * in hw/core/machine.c but includes CPU die support.
1501 */
1502 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
1503 {
1504 PCMachineState *pcms = PC_MACHINE(ms);
1505
1506 if (opts) {
1507 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
1508 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
1509 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
1510 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
1511 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
1512
1513 /* compute missing values, prefer sockets over cores over threads */
1514 if (cpus == 0 || sockets == 0) {
1515 cores = cores > 0 ? cores : 1;
1516 threads = threads > 0 ? threads : 1;
1517 if (cpus == 0) {
1518 sockets = sockets > 0 ? sockets : 1;
1519 cpus = cores * threads * dies * sockets;
1520 } else {
1521 ms->smp.max_cpus =
1522 qemu_opt_get_number(opts, "maxcpus", cpus);
1523 sockets = ms->smp.max_cpus / (cores * threads * dies);
1524 }
1525 } else if (cores == 0) {
1526 threads = threads > 0 ? threads : 1;
1527 cores = cpus / (sockets * dies * threads);
1528 cores = cores > 0 ? cores : 1;
1529 } else if (threads == 0) {
1530 threads = cpus / (cores * dies * sockets);
1531 threads = threads > 0 ? threads : 1;
1532 } else if (sockets * dies * cores * threads < cpus) {
1533 error_report("cpu topology: "
1534 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
1535 "smp_cpus (%u)",
1536 sockets, dies, cores, threads, cpus);
1537 exit(1);
1538 }
1539
1540 ms->smp.max_cpus =
1541 qemu_opt_get_number(opts, "maxcpus", cpus);
1542
1543 if (ms->smp.max_cpus < cpus) {
1544 error_report("maxcpus must be equal to or greater than smp");
1545 exit(1);
1546 }
1547
1548 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
1549 error_report("cpu topology: "
1550 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
1551 "maxcpus (%u)",
1552 sockets, dies, cores, threads,
1553 ms->smp.max_cpus);
1554 exit(1);
1555 }
1556
1557 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
1558 warn_report("Invalid CPU topology deprecated: "
1559 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
1560 "!= maxcpus (%u)",
1561 sockets, dies, cores, threads,
1562 ms->smp.max_cpus);
1563 }
1564
1565 ms->smp.cpus = cpus;
1566 ms->smp.cores = cores;
1567 ms->smp.threads = threads;
1568 pcms->smp_dies = dies;
1569 }
1570
1571 if (ms->smp.cpus > 1) {
1572 Error *blocker = NULL;
1573 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
1574 replay_add_blocker(blocker);
1575 }
1576 }
1577
1578 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
1579 {
1580 PCMachineState *pcms = PC_MACHINE(ms);
1581 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
1582 Error *local_err = NULL;
1583
1584 if (id < 0) {
1585 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1586 return;
1587 }
1588
1589 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1590 error_setg(errp, "Unable to add CPU: %" PRIi64
1591 ", resulting APIC ID (%" PRIi64 ") is too large",
1592 id, apic_id);
1593 return;
1594 }
1595
1596 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
1597 if (local_err) {
1598 error_propagate(errp, local_err);
1599 return;
1600 }
1601 }
1602
1603 void pc_cpus_init(PCMachineState *pcms)
1604 {
1605 int i;
1606 const CPUArchIdList *possible_cpus;
1607 MachineState *ms = MACHINE(pcms);
1608 MachineClass *mc = MACHINE_GET_CLASS(pcms);
1609 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
1610
1611 x86_cpu_set_default_version(pcmc->default_cpu_version);
1612
1613 /* Calculates the limit to CPU APIC ID values
1614 *
1615 * Limit for the APIC ID value, so that all
1616 * CPU APIC IDs are < pcms->apic_id_limit.
1617 *
1618 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
1619 */
1620 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
1621 ms->smp.max_cpus - 1) + 1;
1622 possible_cpus = mc->possible_cpu_arch_ids(ms);
1623 for (i = 0; i < ms->smp.cpus; i++) {
1624 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
1625 }
1626 }
1627
1628 static void pc_build_feature_control_file(PCMachineState *pcms)
1629 {
1630 MachineState *ms = MACHINE(pcms);
1631 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
1632 CPUX86State *env = &cpu->env;
1633 uint32_t unused, ecx, edx;
1634 uint64_t feature_control_bits = 0;
1635 uint64_t *val;
1636
1637 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1638 if (ecx & CPUID_EXT_VMX) {
1639 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1640 }
1641
1642 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1643 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1644 (env->mcg_cap & MCG_LMCE_P)) {
1645 feature_control_bits |= FEATURE_CONTROL_LMCE;
1646 }
1647
1648 if (!feature_control_bits) {
1649 return;
1650 }
1651
1652 val = g_malloc(sizeof(*val));
1653 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1654 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1655 }
1656
1657 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1658 {
1659 if (cpus_count > 0xff) {
1660 /* If the number of CPUs can't be represented in 8 bits, the
1661 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1662 * to make old BIOSes fail more predictably.
1663 */
1664 rtc_set_memory(rtc, 0x5f, 0);
1665 } else {
1666 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1667 }
1668 }
1669
1670 static
1671 void pc_machine_done(Notifier *notifier, void *data)
1672 {
1673 PCMachineState *pcms = container_of(notifier,
1674 PCMachineState, machine_done);
1675 PCIBus *bus = pcms->bus;
1676
1677 /* set the number of CPUs */
1678 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
1679
1680 if (bus) {
1681 int extra_hosts = 0;
1682
1683 QLIST_FOREACH(bus, &bus->child, sibling) {
1684 /* look for expander root buses */
1685 if (pci_bus_is_root(bus)) {
1686 extra_hosts++;
1687 }
1688 }
1689 if (extra_hosts && pcms->fw_cfg) {
1690 uint64_t *val = g_malloc(sizeof(*val));
1691 *val = cpu_to_le64(extra_hosts);
1692 fw_cfg_add_file(pcms->fw_cfg,
1693 "etc/extra-pci-roots", val, sizeof(*val));
1694 }
1695 }
1696
1697 acpi_setup();
1698 if (pcms->fw_cfg) {
1699 pc_build_smbios(pcms);
1700 pc_build_feature_control_file(pcms);
1701 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1702 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1703 }
1704
1705 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
1706 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1707
1708 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
1709 iommu->intr_eim != ON_OFF_AUTO_ON) {
1710 error_report("current -smp configuration requires "
1711 "Extended Interrupt Mode enabled. "
1712 "You can add an IOMMU using: "
1713 "-device intel-iommu,intremap=on,eim=on");
1714 exit(EXIT_FAILURE);
1715 }
1716 }
1717 }
1718
1719 void pc_guest_info_init(PCMachineState *pcms)
1720 {
1721 int i;
1722 MachineState *ms = MACHINE(pcms);
1723
1724 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1725 pcms->numa_nodes = ms->numa_state->num_nodes;
1726 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1727 sizeof *pcms->node_mem);
1728 for (i = 0; i < ms->numa_state->num_nodes; i++) {
1729 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
1730 }
1731
1732 pcms->machine_done.notify = pc_machine_done;
1733 qemu_add_machine_init_done_notifier(&pcms->machine_done);
1734 }
1735
1736 /* setup pci memory address space mapping into system address space */
1737 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1738 MemoryRegion *pci_address_space)
1739 {
1740 /* Set to lower priority than RAM */
1741 memory_region_add_subregion_overlap(system_memory, 0x0,
1742 pci_address_space, -1);
1743 }
1744
1745 void xen_load_linux(PCMachineState *pcms)
1746 {
1747 int i;
1748 FWCfgState *fw_cfg;
1749
1750 assert(MACHINE(pcms)->kernel_filename != NULL);
1751
1752 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
1753 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
1754 rom_set_fw(fw_cfg);
1755
1756 load_linux(pcms, fw_cfg);
1757 for (i = 0; i < nb_option_roms; i++) {
1758 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
1759 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1760 !strcmp(option_rom[i].name, "pvh.bin") ||
1761 !strcmp(option_rom[i].name, "multiboot.bin"));
1762 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1763 }
1764 pcms->fw_cfg = fw_cfg;
1765 }
1766
1767 void pc_memory_init(PCMachineState *pcms,
1768 MemoryRegion *system_memory,
1769 MemoryRegion *rom_memory,
1770 MemoryRegion **ram_memory)
1771 {
1772 int linux_boot, i;
1773 MemoryRegion *ram, *option_rom_mr;
1774 MemoryRegion *ram_below_4g, *ram_above_4g;
1775 FWCfgState *fw_cfg;
1776 MachineState *machine = MACHINE(pcms);
1777 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1778
1779 assert(machine->ram_size == pcms->below_4g_mem_size +
1780 pcms->above_4g_mem_size);
1781
1782 linux_boot = (machine->kernel_filename != NULL);
1783
1784 /* Allocate RAM. We allocate it as a single memory region and use
1785 * aliases to address portions of it, mostly for backwards compatibility
1786 * with older qemus that used qemu_ram_alloc().
1787 */
1788 ram = g_malloc(sizeof(*ram));
1789 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1790 machine->ram_size);
1791 *ram_memory = ram;
1792 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1793 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1794 0, pcms->below_4g_mem_size);
1795 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1796 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1797 if (pcms->above_4g_mem_size > 0) {
1798 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1799 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1800 pcms->below_4g_mem_size,
1801 pcms->above_4g_mem_size);
1802 memory_region_add_subregion(system_memory, 0x100000000ULL,
1803 ram_above_4g);
1804 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
1805 }
1806
1807 if (!pcmc->has_reserved_memory &&
1808 (machine->ram_slots ||
1809 (machine->maxram_size > machine->ram_size))) {
1810 MachineClass *mc = MACHINE_GET_CLASS(machine);
1811
1812 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1813 mc->name);
1814 exit(EXIT_FAILURE);
1815 }
1816
1817 /* always allocate the device memory information */
1818 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1819
1820 /* initialize device memory address space */
1821 if (pcmc->has_reserved_memory &&
1822 (machine->ram_size < machine->maxram_size)) {
1823 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
1824
1825 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1826 error_report("unsupported amount of memory slots: %"PRIu64,
1827 machine->ram_slots);
1828 exit(EXIT_FAILURE);
1829 }
1830
1831 if (QEMU_ALIGN_UP(machine->maxram_size,
1832 TARGET_PAGE_SIZE) != machine->maxram_size) {
1833 error_report("maximum memory size must by aligned to multiple of "
1834 "%d bytes", TARGET_PAGE_SIZE);
1835 exit(EXIT_FAILURE);
1836 }
1837
1838 machine->device_memory->base =
1839 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
1840
1841 if (pcmc->enforce_aligned_dimm) {
1842 /* size device region assuming 1G page max alignment per slot */
1843 device_mem_size += (1 * GiB) * machine->ram_slots;
1844 }
1845
1846 if ((machine->device_memory->base + device_mem_size) <
1847 device_mem_size) {
1848 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1849 machine->maxram_size);
1850 exit(EXIT_FAILURE);
1851 }
1852
1853 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1854 "device-memory", device_mem_size);
1855 memory_region_add_subregion(system_memory, machine->device_memory->base,
1856 &machine->device_memory->mr);
1857 }
1858
1859 /* Initialize PC system firmware */
1860 pc_system_firmware_init(pcms, rom_memory);
1861
1862 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1863 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1864 &error_fatal);
1865 if (pcmc->pci_enabled) {
1866 memory_region_set_readonly(option_rom_mr, true);
1867 }
1868 memory_region_add_subregion_overlap(rom_memory,
1869 PC_ROM_MIN_VGA,
1870 option_rom_mr,
1871 1);
1872
1873 fw_cfg = fw_cfg_arch_create(pcms, pcms->boot_cpus);
1874
1875 rom_set_fw(fw_cfg);
1876
1877 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1878 uint64_t *val = g_malloc(sizeof(*val));
1879 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1880 uint64_t res_mem_end = machine->device_memory->base;
1881
1882 if (!pcmc->broken_reserved_end) {
1883 res_mem_end += memory_region_size(&machine->device_memory->mr);
1884 }
1885 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1886 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1887 }
1888
1889 if (linux_boot) {
1890 load_linux(pcms, fw_cfg);
1891 }
1892
1893 for (i = 0; i < nb_option_roms; i++) {
1894 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1895 }
1896 pcms->fw_cfg = fw_cfg;
1897
1898 /* Init default IOAPIC address space */
1899 pcms->ioapic_as = &address_space_memory;
1900 }
1901
1902 /*
1903 * The 64bit pci hole starts after "above 4G RAM" and
1904 * potentially the space reserved for memory hotplug.
1905 */
1906 uint64_t pc_pci_hole64_start(void)
1907 {
1908 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1909 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1910 MachineState *ms = MACHINE(pcms);
1911 uint64_t hole64_start = 0;
1912
1913 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1914 hole64_start = ms->device_memory->base;
1915 if (!pcmc->broken_reserved_end) {
1916 hole64_start += memory_region_size(&ms->device_memory->mr);
1917 }
1918 } else {
1919 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1920 }
1921
1922 return ROUND_UP(hole64_start, 1 * GiB);
1923 }
1924
1925 qemu_irq pc_allocate_cpu_irq(void)
1926 {
1927 return qemu_allocate_irq(pic_irq_request, NULL, 0);
1928 }
1929
1930 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1931 {
1932 DeviceState *dev = NULL;
1933
1934 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1935 if (pci_bus) {
1936 PCIDevice *pcidev = pci_vga_init(pci_bus);
1937 dev = pcidev ? &pcidev->qdev : NULL;
1938 } else if (isa_bus) {
1939 ISADevice *isadev = isa_vga_init(isa_bus);
1940 dev = isadev ? DEVICE(isadev) : NULL;
1941 }
1942 rom_reset_order_override();
1943 return dev;
1944 }
1945
1946 static const MemoryRegionOps ioport80_io_ops = {
1947 .write = ioport80_write,
1948 .read = ioport80_read,
1949 .endianness = DEVICE_NATIVE_ENDIAN,
1950 .impl = {
1951 .min_access_size = 1,
1952 .max_access_size = 1,
1953 },
1954 };
1955
1956 static const MemoryRegionOps ioportF0_io_ops = {
1957 .write = ioportF0_write,
1958 .read = ioportF0_read,
1959 .endianness = DEVICE_NATIVE_ENDIAN,
1960 .impl = {
1961 .min_access_size = 1,
1962 .max_access_size = 1,
1963 },
1964 };
1965
1966 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1967 {
1968 int i;
1969 DriveInfo *fd[MAX_FD];
1970 qemu_irq *a20_line;
1971 ISADevice *i8042, *port92, *vmmouse;
1972
1973 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1974 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1975
1976 for (i = 0; i < MAX_FD; i++) {
1977 fd[i] = drive_get(IF_FLOPPY, 0, i);
1978 create_fdctrl |= !!fd[i];
1979 }
1980 if (create_fdctrl) {
1981 fdctrl_init_isa(isa_bus, fd);
1982 }
1983
1984 i8042 = isa_create_simple(isa_bus, "i8042");
1985 if (!no_vmport) {
1986 vmport_init(isa_bus);
1987 vmmouse = isa_try_create(isa_bus, "vmmouse");
1988 } else {
1989 vmmouse = NULL;
1990 }
1991 if (vmmouse) {
1992 DeviceState *dev = DEVICE(vmmouse);
1993 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1994 qdev_init_nofail(dev);
1995 }
1996 port92 = isa_create_simple(isa_bus, "port92");
1997
1998 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1999 i8042_setup_a20_line(i8042, a20_line[0]);
2000 port92_init(port92, a20_line[1]);
2001 g_free(a20_line);
2002 }
2003
2004 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
2005 ISADevice **rtc_state,
2006 bool create_fdctrl,
2007 bool no_vmport,
2008 bool has_pit,
2009 uint32_t hpet_irqs)
2010 {
2011 int i;
2012 DeviceState *hpet = NULL;
2013 int pit_isa_irq = 0;
2014 qemu_irq pit_alt_irq = NULL;
2015 qemu_irq rtc_irq = NULL;
2016 ISADevice *pit = NULL;
2017 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2018 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
2019
2020 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
2021 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
2022
2023 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
2024 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
2025
2026 /*
2027 * Check if an HPET shall be created.
2028 *
2029 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2030 * when the HPET wants to take over. Thus we have to disable the latter.
2031 */
2032 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
2033 /* In order to set property, here not using sysbus_try_create_simple */
2034 hpet = qdev_try_create(NULL, TYPE_HPET);
2035 if (hpet) {
2036 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2037 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2038 * IRQ8 and IRQ2.
2039 */
2040 uint8_t compat = object_property_get_uint(OBJECT(hpet),
2041 HPET_INTCAP, NULL);
2042 if (!compat) {
2043 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2044 }
2045 qdev_init_nofail(hpet);
2046 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2047
2048 for (i = 0; i < GSI_NUM_PINS; i++) {
2049 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
2050 }
2051 pit_isa_irq = -1;
2052 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2053 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
2054 }
2055 }
2056 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
2057
2058 qemu_register_boot_set(pc_boot_set, *rtc_state);
2059
2060 if (!xen_enabled() && has_pit) {
2061 if (kvm_pit_in_kernel()) {
2062 pit = kvm_pit_init(isa_bus, 0x40);
2063 } else {
2064 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
2065 }
2066 if (hpet) {
2067 /* connect PIT to output control line of the HPET */
2068 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
2069 }
2070 pcspk_init(isa_bus, pit);
2071 }
2072
2073 i8257_dma_init(isa_bus, 0);
2074
2075 /* Super I/O */
2076 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
2077 }
2078
2079 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
2080 {
2081 int i;
2082
2083 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
2084 for (i = 0; i < nb_nics; i++) {
2085 NICInfo *nd = &nd_table[i];
2086 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
2087
2088 if (g_str_equal(model, "ne2k_isa")) {
2089 pc_init_ne2k_isa(isa_bus, nd);
2090 } else {
2091 pci_nic_init_nofail(nd, pci_bus, model, NULL);
2092 }
2093 }
2094 rom_reset_order_override();
2095 }
2096
2097 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2098 {
2099 DeviceState *dev;
2100 SysBusDevice *d;
2101 unsigned int i;
2102
2103 if (kvm_ioapic_in_kernel()) {
2104 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
2105 } else {
2106 dev = qdev_create(NULL, TYPE_IOAPIC);
2107 }
2108 if (parent_name) {
2109 object_property_add_child(object_resolve_path(parent_name, NULL),
2110 "ioapic", OBJECT(dev), NULL);
2111 }
2112 qdev_init_nofail(dev);
2113 d = SYS_BUS_DEVICE(dev);
2114 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
2115
2116 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2117 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2118 }
2119 }
2120
2121 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2122 Error **errp)
2123 {
2124 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2125 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2126 const MachineState *ms = MACHINE(hotplug_dev);
2127 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2128 const uint64_t legacy_align = TARGET_PAGE_SIZE;
2129 Error *local_err = NULL;
2130
2131 /*
2132 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2133 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2134 * addition to cover this case.
2135 */
2136 if (!pcms->acpi_dev || !acpi_enabled) {
2137 error_setg(errp,
2138 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2139 return;
2140 }
2141
2142 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2143 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2144 return;
2145 }
2146
2147 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
2148 if (local_err) {
2149 error_propagate(errp, local_err);
2150 return;
2151 }
2152
2153 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
2154 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
2155 }
2156
2157 static void pc_memory_plug(HotplugHandler *hotplug_dev,
2158 DeviceState *dev, Error **errp)
2159 {
2160 Error *local_err = NULL;
2161 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2162 MachineState *ms = MACHINE(hotplug_dev);
2163 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2164
2165 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
2166 if (local_err) {
2167 goto out;
2168 }
2169
2170 if (is_nvdimm) {
2171 nvdimm_plug(ms->nvdimms_state);
2172 }
2173
2174 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
2175 out:
2176 error_propagate(errp, local_err);
2177 }
2178
2179 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2180 DeviceState *dev, Error **errp)
2181 {
2182 Error *local_err = NULL;
2183 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2184
2185 /*
2186 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2187 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2188 * addition to cover this case.
2189 */
2190 if (!pcms->acpi_dev || !acpi_enabled) {
2191 error_setg(&local_err,
2192 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2193 goto out;
2194 }
2195
2196 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2197 error_setg(&local_err,
2198 "nvdimm device hot unplug is not supported yet.");
2199 goto out;
2200 }
2201
2202 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2203 &local_err);
2204 out:
2205 error_propagate(errp, local_err);
2206 }
2207
2208 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2209 DeviceState *dev, Error **errp)
2210 {
2211 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2212 Error *local_err = NULL;
2213
2214 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2215 if (local_err) {
2216 goto out;
2217 }
2218
2219 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
2220 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2221 out:
2222 error_propagate(errp, local_err);
2223 }
2224
2225 static int pc_apic_cmp(const void *a, const void *b)
2226 {
2227 CPUArchId *apic_a = (CPUArchId *)a;
2228 CPUArchId *apic_b = (CPUArchId *)b;
2229
2230 return apic_a->arch_id - apic_b->arch_id;
2231 }
2232
2233 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2234 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2235 * entry corresponding to CPU's apic_id returns NULL.
2236 */
2237 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2238 {
2239 CPUArchId apic_id, *found_cpu;
2240
2241 apic_id.arch_id = id;
2242 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2243 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
2244 pc_apic_cmp);
2245 if (found_cpu && idx) {
2246 *idx = found_cpu - ms->possible_cpus->cpus;
2247 }
2248 return found_cpu;
2249 }
2250
2251 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2252 DeviceState *dev, Error **errp)
2253 {
2254 CPUArchId *found_cpu;
2255 Error *local_err = NULL;
2256 X86CPU *cpu = X86_CPU(dev);
2257 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2258
2259 if (pcms->acpi_dev) {
2260 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2261 if (local_err) {
2262 goto out;
2263 }
2264 }
2265
2266 /* increment the number of CPUs */
2267 pcms->boot_cpus++;
2268 if (pcms->rtc) {
2269 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2270 }
2271 if (pcms->fw_cfg) {
2272 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2273 }
2274
2275 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2276 found_cpu->cpu = OBJECT(dev);
2277 out:
2278 error_propagate(errp, local_err);
2279 }
2280 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2281 DeviceState *dev, Error **errp)
2282 {
2283 int idx = -1;
2284 Error *local_err = NULL;
2285 X86CPU *cpu = X86_CPU(dev);
2286 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2287
2288 if (!pcms->acpi_dev) {
2289 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2290 goto out;
2291 }
2292
2293 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2294 assert(idx != -1);
2295 if (idx == 0) {
2296 error_setg(&local_err, "Boot CPU is unpluggable");
2297 goto out;
2298 }
2299
2300 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2301 &local_err);
2302 if (local_err) {
2303 goto out;
2304 }
2305
2306 out:
2307 error_propagate(errp, local_err);
2308
2309 }
2310
2311 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2312 DeviceState *dev, Error **errp)
2313 {
2314 CPUArchId *found_cpu;
2315 Error *local_err = NULL;
2316 X86CPU *cpu = X86_CPU(dev);
2317 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2318
2319 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2320 if (local_err) {
2321 goto out;
2322 }
2323
2324 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
2325 found_cpu->cpu = NULL;
2326 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
2327
2328 /* decrement the number of CPUs */
2329 pcms->boot_cpus--;
2330 /* Update the number of CPUs in CMOS */
2331 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2332 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2333 out:
2334 error_propagate(errp, local_err);
2335 }
2336
2337 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2338 DeviceState *dev, Error **errp)
2339 {
2340 int idx;
2341 CPUState *cs;
2342 CPUArchId *cpu_slot;
2343 X86CPUTopoInfo topo;
2344 X86CPU *cpu = X86_CPU(dev);
2345 CPUX86State *env = &cpu->env;
2346 MachineState *ms = MACHINE(hotplug_dev);
2347 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2348 unsigned int smp_cores = ms->smp.cores;
2349 unsigned int smp_threads = ms->smp.threads;
2350
2351 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2352 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2353 ms->cpu_type);
2354 return;
2355 }
2356
2357 env->nr_dies = pcms->smp_dies;
2358
2359 /*
2360 * If APIC ID is not set,
2361 * set it based on socket/die/core/thread properties.
2362 */
2363 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2364 int max_socket = (ms->smp.max_cpus - 1) /
2365 smp_threads / smp_cores / pcms->smp_dies;
2366
2367 /*
2368 * die-id was optional in QEMU 4.0 and older, so keep it optional
2369 * if there's only one die per socket.
2370 */
2371 if (cpu->die_id < 0 && pcms->smp_dies == 1) {
2372 cpu->die_id = 0;
2373 }
2374
2375 if (cpu->socket_id < 0) {
2376 error_setg(errp, "CPU socket-id is not set");
2377 return;
2378 } else if (cpu->socket_id > max_socket) {
2379 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2380 cpu->socket_id, max_socket);
2381 return;
2382 }
2383 if (cpu->die_id < 0) {
2384 error_setg(errp, "CPU die-id is not set");
2385 return;
2386 } else if (cpu->die_id > pcms->smp_dies - 1) {
2387 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
2388 cpu->die_id, pcms->smp_dies - 1);
2389 return;
2390 }
2391 if (cpu->core_id < 0) {
2392 error_setg(errp, "CPU core-id is not set");
2393 return;
2394 } else if (cpu->core_id > (smp_cores - 1)) {
2395 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2396 cpu->core_id, smp_cores - 1);
2397 return;
2398 }
2399 if (cpu->thread_id < 0) {
2400 error_setg(errp, "CPU thread-id is not set");
2401 return;
2402 } else if (cpu->thread_id > (smp_threads - 1)) {
2403 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2404 cpu->thread_id, smp_threads - 1);
2405 return;
2406 }
2407
2408 topo.pkg_id = cpu->socket_id;
2409 topo.die_id = cpu->die_id;
2410 topo.core_id = cpu->core_id;
2411 topo.smt_id = cpu->thread_id;
2412 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
2413 smp_threads, &topo);
2414 }
2415
2416 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
2417 if (!cpu_slot) {
2418 MachineState *ms = MACHINE(pcms);
2419
2420 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2421 smp_cores, smp_threads, &topo);
2422 error_setg(errp,
2423 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
2424 " APIC ID %" PRIu32 ", valid index range 0:%d",
2425 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
2426 cpu->apic_id, ms->possible_cpus->len - 1);
2427 return;
2428 }
2429
2430 if (cpu_slot->cpu) {
2431 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2432 idx, cpu->apic_id);
2433 return;
2434 }
2435
2436 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2437 * so that machine_query_hotpluggable_cpus would show correct values
2438 */
2439 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2440 * once -smp refactoring is complete and there will be CPU private
2441 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2442 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2443 smp_cores, smp_threads, &topo);
2444 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2445 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2446 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2447 return;
2448 }
2449 cpu->socket_id = topo.pkg_id;
2450
2451 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
2452 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
2453 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
2454 return;
2455 }
2456 cpu->die_id = topo.die_id;
2457
2458 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2459 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2460 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2461 return;
2462 }
2463 cpu->core_id = topo.core_id;
2464
2465 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2466 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2467 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2468 return;
2469 }
2470 cpu->thread_id = topo.smt_id;
2471
2472 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
2473 !kvm_hv_vpindex_settable()) {
2474 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2475 return;
2476 }
2477
2478 cs = CPU(cpu);
2479 cs->cpu_index = idx;
2480
2481 numa_cpu_pre_plug(cpu_slot, dev, errp);
2482 }
2483
2484 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
2485 DeviceState *dev, Error **errp)
2486 {
2487 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2488 Error *local_err = NULL;
2489
2490 if (!hotplug_dev2) {
2491 /*
2492 * Without a bus hotplug handler, we cannot control the plug/unplug
2493 * order. This should never be the case on x86, however better add
2494 * a safety net.
2495 */
2496 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
2497 return;
2498 }
2499 /*
2500 * First, see if we can plug this memory device at all. If that
2501 * succeeds, branch of to the actual hotplug handler.
2502 */
2503 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
2504 &local_err);
2505 if (!local_err) {
2506 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
2507 }
2508 error_propagate(errp, local_err);
2509 }
2510
2511 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
2512 DeviceState *dev, Error **errp)
2513 {
2514 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2515 Error *local_err = NULL;
2516
2517 /*
2518 * Plug the memory device first and then branch off to the actual
2519 * hotplug handler. If that one fails, we can easily undo the memory
2520 * device bits.
2521 */
2522 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2523 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
2524 if (local_err) {
2525 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2526 }
2527 error_propagate(errp, local_err);
2528 }
2529
2530 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
2531 DeviceState *dev, Error **errp)
2532 {
2533 /* We don't support virtio pmem hot unplug */
2534 error_setg(errp, "virtio pmem device unplug not supported.");
2535 }
2536
2537 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
2538 DeviceState *dev, Error **errp)
2539 {
2540 /* We don't support virtio pmem hot unplug */
2541 }
2542
2543 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2544 DeviceState *dev, Error **errp)
2545 {
2546 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2547 pc_memory_pre_plug(hotplug_dev, dev, errp);
2548 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2549 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2550 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2551 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
2552 }
2553 }
2554
2555 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2556 DeviceState *dev, Error **errp)
2557 {
2558 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2559 pc_memory_plug(hotplug_dev, dev, errp);
2560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2561 pc_cpu_plug(hotplug_dev, dev, errp);
2562 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2563 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
2564 }
2565 }
2566
2567 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2568 DeviceState *dev, Error **errp)
2569 {
2570 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2571 pc_memory_unplug_request(hotplug_dev, dev, errp);
2572 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2573 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
2574 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2575 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
2576 } else {
2577 error_setg(errp, "acpi: device unplug request for not supported device"
2578 " type: %s", object_get_typename(OBJECT(dev)));
2579 }
2580 }
2581
2582 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2583 DeviceState *dev, Error **errp)
2584 {
2585 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2586 pc_memory_unplug(hotplug_dev, dev, errp);
2587 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2588 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
2589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2590 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
2591 } else {
2592 error_setg(errp, "acpi: device unplug for not supported device"
2593 " type: %s", object_get_typename(OBJECT(dev)));
2594 }
2595 }
2596
2597 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
2598 DeviceState *dev)
2599 {
2600 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2601 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
2602 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2603 return HOTPLUG_HANDLER(machine);
2604 }
2605
2606 return NULL;
2607 }
2608
2609 static void
2610 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2611 const char *name, void *opaque,
2612 Error **errp)
2613 {
2614 MachineState *ms = MACHINE(obj);
2615 int64_t value = 0;
2616
2617 if (ms->device_memory) {
2618 value = memory_region_size(&ms->device_memory->mr);
2619 }
2620
2621 visit_type_int(v, name, &value, errp);
2622 }
2623
2624 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
2625 const char *name, void *opaque,
2626 Error **errp)
2627 {
2628 PCMachineState *pcms = PC_MACHINE(obj);
2629 uint64_t value = pcms->max_ram_below_4g;
2630
2631 visit_type_size(v, name, &value, errp);
2632 }
2633
2634 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
2635 const char *name, void *opaque,
2636 Error **errp)
2637 {
2638 PCMachineState *pcms = PC_MACHINE(obj);
2639 Error *error = NULL;
2640 uint64_t value;
2641
2642 visit_type_size(v, name, &value, &error);
2643 if (error) {
2644 error_propagate(errp, error);
2645 return;
2646 }
2647 if (value > 4 * GiB) {
2648 error_setg(&error,
2649 "Machine option 'max-ram-below-4g=%"PRIu64
2650 "' expects size less than or equal to 4G", value);
2651 error_propagate(errp, error);
2652 return;
2653 }
2654
2655 if (value < 1 * MiB) {
2656 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2657 "BIOS may not work with less than 1MiB", value);
2658 }
2659
2660 pcms->max_ram_below_4g = value;
2661 }
2662
2663 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2664 void *opaque, Error **errp)
2665 {
2666 PCMachineState *pcms = PC_MACHINE(obj);
2667 OnOffAuto vmport = pcms->vmport;
2668
2669 visit_type_OnOffAuto(v, name, &vmport, errp);
2670 }
2671
2672 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2673 void *opaque, Error **errp)
2674 {
2675 PCMachineState *pcms = PC_MACHINE(obj);
2676
2677 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
2678 }
2679
2680 bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2681 {
2682 bool smm_available = false;
2683
2684 if (pcms->smm == ON_OFF_AUTO_OFF) {
2685 return false;
2686 }
2687
2688 if (tcg_enabled() || qtest_enabled()) {
2689 smm_available = true;
2690 } else if (kvm_enabled()) {
2691 smm_available = kvm_has_smm();
2692 }
2693
2694 if (smm_available) {
2695 return true;
2696 }
2697
2698 if (pcms->smm == ON_OFF_AUTO_ON) {
2699 error_report("System Management Mode not supported by this hypervisor.");
2700 exit(1);
2701 }
2702 return false;
2703 }
2704
2705 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2706 void *opaque, Error **errp)
2707 {
2708 PCMachineState *pcms = PC_MACHINE(obj);
2709 OnOffAuto smm = pcms->smm;
2710
2711 visit_type_OnOffAuto(v, name, &smm, errp);
2712 }
2713
2714 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2715 void *opaque, Error **errp)
2716 {
2717 PCMachineState *pcms = PC_MACHINE(obj);
2718
2719 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
2720 }
2721
2722 static bool pc_machine_get_smbus(Object *obj, Error **errp)
2723 {
2724 PCMachineState *pcms = PC_MACHINE(obj);
2725
2726 return pcms->smbus_enabled;
2727 }
2728
2729 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2730 {
2731 PCMachineState *pcms = PC_MACHINE(obj);
2732
2733 pcms->smbus_enabled = value;
2734 }
2735
2736 static bool pc_machine_get_sata(Object *obj, Error **errp)
2737 {
2738 PCMachineState *pcms = PC_MACHINE(obj);
2739
2740 return pcms->sata_enabled;
2741 }
2742
2743 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2744 {
2745 PCMachineState *pcms = PC_MACHINE(obj);
2746
2747 pcms->sata_enabled = value;
2748 }
2749
2750 static bool pc_machine_get_pit(Object *obj, Error **errp)
2751 {
2752 PCMachineState *pcms = PC_MACHINE(obj);
2753
2754 return pcms->pit_enabled;
2755 }
2756
2757 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2758 {
2759 PCMachineState *pcms = PC_MACHINE(obj);
2760
2761 pcms->pit_enabled = value;
2762 }
2763
2764 static void pc_machine_initfn(Object *obj)
2765 {
2766 PCMachineState *pcms = PC_MACHINE(obj);
2767
2768 pcms->max_ram_below_4g = 0; /* use default */
2769 pcms->smm = ON_OFF_AUTO_AUTO;
2770 #ifdef CONFIG_VMPORT
2771 pcms->vmport = ON_OFF_AUTO_AUTO;
2772 #else
2773 pcms->vmport = ON_OFF_AUTO_OFF;
2774 #endif /* CONFIG_VMPORT */
2775 /* acpi build is enabled by default if machine supports it */
2776 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
2777 pcms->smbus_enabled = true;
2778 pcms->sata_enabled = true;
2779 pcms->pit_enabled = true;
2780 pcms->smp_dies = 1;
2781
2782 pc_system_flash_create(pcms);
2783 }
2784
2785 static void pc_machine_reset(MachineState *machine)
2786 {
2787 CPUState *cs;
2788 X86CPU *cpu;
2789
2790 qemu_devices_reset();
2791
2792 /* Reset APIC after devices have been reset to cancel
2793 * any changes that qemu_devices_reset() might have done.
2794 */
2795 CPU_FOREACH(cs) {
2796 cpu = X86_CPU(cs);
2797
2798 if (cpu->apic_state) {
2799 device_reset(cpu->apic_state);
2800 }
2801 }
2802 }
2803
2804 static void pc_machine_wakeup(MachineState *machine)
2805 {
2806 cpu_synchronize_all_states();
2807 pc_machine_reset(machine);
2808 cpu_synchronize_all_post_reset();
2809 }
2810
2811 static CpuInstanceProperties
2812 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2813 {
2814 MachineClass *mc = MACHINE_GET_CLASS(ms);
2815 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2816
2817 assert(cpu_index < possible_cpus->len);
2818 return possible_cpus->cpus[cpu_index].props;
2819 }
2820
2821 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2822 {
2823 X86CPUTopoInfo topo;
2824 PCMachineState *pcms = PC_MACHINE(ms);
2825
2826 assert(idx < ms->possible_cpus->len);
2827 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2828 pcms->smp_dies, ms->smp.cores,
2829 ms->smp.threads, &topo);
2830 return topo.pkg_id % ms->numa_state->num_nodes;
2831 }
2832
2833 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
2834 {
2835 PCMachineState *pcms = PC_MACHINE(ms);
2836 int i;
2837 unsigned int max_cpus = ms->smp.max_cpus;
2838
2839 if (ms->possible_cpus) {
2840 /*
2841 * make sure that max_cpus hasn't changed since the first use, i.e.
2842 * -smp hasn't been parsed after it
2843 */
2844 assert(ms->possible_cpus->len == max_cpus);
2845 return ms->possible_cpus;
2846 }
2847
2848 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2849 sizeof(CPUArchId) * max_cpus);
2850 ms->possible_cpus->len = max_cpus;
2851 for (i = 0; i < ms->possible_cpus->len; i++) {
2852 X86CPUTopoInfo topo;
2853
2854 ms->possible_cpus->cpus[i].type = ms->cpu_type;
2855 ms->possible_cpus->cpus[i].vcpus_count = 1;
2856 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
2857 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
2858 pcms->smp_dies, ms->smp.cores,
2859 ms->smp.threads, &topo);
2860 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2861 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
2862 if (pcms->smp_dies > 1) {
2863 ms->possible_cpus->cpus[i].props.has_die_id = true;
2864 ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
2865 }
2866 ms->possible_cpus->cpus[i].props.has_core_id = true;
2867 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2868 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2869 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
2870 }
2871 return ms->possible_cpus;
2872 }
2873
2874 static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2875 {
2876 /* cpu index isn't used */
2877 CPUState *cs;
2878
2879 CPU_FOREACH(cs) {
2880 X86CPU *cpu = X86_CPU(cs);
2881
2882 if (!cpu->apic_state) {
2883 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2884 } else {
2885 apic_deliver_nmi(cpu->apic_state);
2886 }
2887 }
2888 }
2889
2890 static void pc_machine_class_init(ObjectClass *oc, void *data)
2891 {
2892 MachineClass *mc = MACHINE_CLASS(oc);
2893 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2894 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2895 NMIClass *nc = NMI_CLASS(oc);
2896
2897 pcmc->pci_enabled = true;
2898 pcmc->has_acpi_build = true;
2899 pcmc->rsdp_in_ram = true;
2900 pcmc->smbios_defaults = true;
2901 pcmc->smbios_uuid_encoded = true;
2902 pcmc->gigabyte_align = true;
2903 pcmc->has_reserved_memory = true;
2904 pcmc->kvmclock_enabled = true;
2905 pcmc->enforce_aligned_dimm = true;
2906 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2907 * to be used at the moment, 32K should be enough for a while. */
2908 pcmc->acpi_data_size = 0x20000 + 0x8000;
2909 pcmc->save_tsc_khz = true;
2910 pcmc->linuxboot_dma_enabled = true;
2911 pcmc->pvh_enabled = true;
2912 assert(!mc->get_hotplug_handler);
2913 mc->get_hotplug_handler = pc_get_hotplug_handler;
2914 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
2915 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
2916 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
2917 mc->auto_enable_numa_with_memhp = true;
2918 mc->has_hotpluggable_cpus = true;
2919 mc->default_boot_order = "cad";
2920 mc->hot_add_cpu = pc_hot_add_cpu;
2921 mc->smp_parse = pc_smp_parse;
2922 mc->block_default_type = IF_IDE;
2923 mc->max_cpus = 255;
2924 mc->reset = pc_machine_reset;
2925 mc->wakeup = pc_machine_wakeup;
2926 hc->pre_plug = pc_machine_device_pre_plug_cb;
2927 hc->plug = pc_machine_device_plug_cb;
2928 hc->unplug_request = pc_machine_device_unplug_request_cb;
2929 hc->unplug = pc_machine_device_unplug_cb;
2930 nc->nmi_monitor_handler = x86_nmi;
2931 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
2932 mc->nvdimm_supported = true;
2933 mc->numa_mem_supported = true;
2934
2935 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2936 pc_machine_get_device_memory_region_size, NULL,
2937 NULL, NULL, &error_abort);
2938
2939 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2940 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2941 NULL, NULL, &error_abort);
2942
2943 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2944 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2945
2946 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2947 pc_machine_get_smm, pc_machine_set_smm,
2948 NULL, NULL, &error_abort);
2949 object_class_property_set_description(oc, PC_MACHINE_SMM,
2950 "Enable SMM (pc & q35)", &error_abort);
2951
2952 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2953 pc_machine_get_vmport, pc_machine_set_vmport,
2954 NULL, NULL, &error_abort);
2955 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2956 "Enable vmport (pc & q35)", &error_abort);
2957
2958 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2959 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
2960
2961 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2962 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
2963
2964 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2965 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
2966 }
2967
2968 static const TypeInfo pc_machine_info = {
2969 .name = TYPE_PC_MACHINE,
2970 .parent = TYPE_MACHINE,
2971 .abstract = true,
2972 .instance_size = sizeof(PCMachineState),
2973 .instance_init = pc_machine_initfn,
2974 .class_size = sizeof(PCMachineClass),
2975 .class_init = pc_machine_class_init,
2976 .interfaces = (InterfaceInfo[]) {
2977 { TYPE_HOTPLUG_HANDLER },
2978 { TYPE_NMI },
2979 { }
2980 },
2981 };
2982
2983 static void pc_machine_register_types(void)
2984 {
2985 type_register_static(&pc_machine_info);
2986 }
2987
2988 type_init(pc_machine_register_types)
AR7 emulation for QEMU