target-microblaze/helper.c

   1 /*
   2  *  MicroBlaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "qemu/host-utils.h"
  24
  25 #define D(x)
  26
  27 #if defined(CONFIG_USER_ONLY)
  28
  29 void mb_cpu_do_interrupt(CPUState *cs)
  30 {
  31     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  32     CPUMBState *env = &cpu->env;
  33
  34     cs->exception_index = -1;
  35     env->res_addr = RES_ADDR_NONE;
  36     env->regs[14] = env->sregs[SR_PC];
  37 }
  38
  39 int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  40                             int mmu_idx)
  41 {
  42     cs->exception_index = 0xaa;
  43     cpu_dump_state(cs, stderr, fprintf, 0);
  44     return 1;
  45 }
  46
  47 #else /* !CONFIG_USER_ONLY */
  48
  49 int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  50                             int mmu_idx)
  51 {
  52     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  53     CPUMBState *env = &cpu->env;
  54     unsigned int hit;
  55     unsigned int mmu_available;
  56     int r = 1;
  57     int prot;
  58
  59     mmu_available = 0;
  60     if (cpu->cfg.use_mmu) {
  61         mmu_available = 1;
  62         if ((cpu->cfg.pvr == C_PVR_FULL) &&
  63             (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  64             mmu_available = 0;
  65         }
  66     }
  67
  68     /* Translate if the MMU is available and enabled.  */
  69     if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  70         target_ulong vaddr, paddr;
  71         struct microblaze_mmu_lookup lu;
  72
  73         hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  74         if (hit) {
  75             vaddr = address & TARGET_PAGE_MASK;
  76             paddr = lu.paddr + vaddr - lu.vaddr;
  77
  78             qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
  79                     mmu_idx, vaddr, paddr, lu.prot);
  80             tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  81             r = 0;
  82         } else {
  83             env->sregs[SR_EAR] = address;
  84             qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
  85                                         mmu_idx, address);
  86
  87             switch (lu.err) {
  88                 case ERR_PROT:
  89                     env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  90                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  91                     break;
  92                 case ERR_MISS:
  93                     env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  94                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  95                     break;
  96                 default:
  97                     abort();
  98                     break;
  99             }
 100
 101             if (cs->exception_index == EXCP_MMU) {
 102                 cpu_abort(cs, "recursive faults\n");
 103             }
 104
 105             /* TLB miss.  */
 106             cs->exception_index = EXCP_MMU;
 107         }
 108     } else {
 109         /* MMU disabled or not available.  */
 110         address &= TARGET_PAGE_MASK;
 111         prot = PAGE_BITS;
 112         tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 113         r = 0;
 114     }
 115     return r;
 116 }
 117
 118 void mb_cpu_do_interrupt(CPUState *cs)
 119 {
 120     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 121     CPUMBState *env = &cpu->env;
 122     uint32_t t;
 123
 124     /* IMM flag cannot propagate across a branch and into the dslot.  */
 125     assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 126     assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 127 /*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 128     env->res_addr = RES_ADDR_NONE;
 129     switch (cs->exception_index) {
 130         case EXCP_HW_EXCP:
 131             if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 132                 qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
 133                 return;
 134             }
 135
 136             env->regs[17] = env->sregs[SR_PC] + 4;
 137             env->sregs[SR_ESR] &= ~(1 << 12);
 138
 139             /* Exception breaks branch + dslot sequence?  */
 140             if (env->iflags & D_FLAG) {
 141                 env->sregs[SR_ESR] |= 1 << 12 ;
 142                 env->sregs[SR_BTR] = env->btarget;
 143             }
 144
 145             /* Disable the MMU.  */
 146             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 147             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 148             env->sregs[SR_MSR] |= t;
 149             /* Exception in progress.  */
 150             env->sregs[SR_MSR] |= MSR_EIP;
 151
 152             qemu_log_mask(CPU_LOG_INT,
 153                           "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 154                           env->sregs[SR_PC], env->sregs[SR_EAR],
 155                           env->sregs[SR_ESR], env->iflags);
 156             log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 157             env->iflags &= ~(IMM_FLAG | D_FLAG);
 158             env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 159             break;
 160
 161         case EXCP_MMU:
 162             env->regs[17] = env->sregs[SR_PC];
 163
 164             env->sregs[SR_ESR] &= ~(1 << 12);
 165             /* Exception breaks branch + dslot sequence?  */
 166             if (env->iflags & D_FLAG) {
 167                 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 168                 env->sregs[SR_ESR] |= 1 << 12 ;
 169                 env->sregs[SR_BTR] = env->btarget;
 170
 171                 /* Reexecute the branch.  */
 172                 env->regs[17] -= 4;
 173                 /* was the branch immprefixed?.  */
 174                 if (env->bimm) {
 175                     qemu_log_mask(CPU_LOG_INT,
 176                                   "bimm exception at pc=%x iflags=%x\n",
 177                                   env->sregs[SR_PC], env->iflags);
 178                     env->regs[17] -= 4;
 179                     log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 180                 }
 181             } else if (env->iflags & IMM_FLAG) {
 182                 D(qemu_log("IMM_FLAG set at exception\n"));
 183                 env->regs[17] -= 4;
 184             }
 185
 186             /* Disable the MMU.  */
 187             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 188             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 189             env->sregs[SR_MSR] |= t;
 190             /* Exception in progress.  */
 191             env->sregs[SR_MSR] |= MSR_EIP;
 192
 193             qemu_log_mask(CPU_LOG_INT,
 194                           "exception at pc=%x ear=%x iflags=%x\n",
 195                           env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 196             log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 197             env->iflags &= ~(IMM_FLAG | D_FLAG);
 198             env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 199             break;
 200
 201         case EXCP_IRQ:
 202             assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 203             assert(env->sregs[SR_MSR] & MSR_IE);
 204             assert(!(env->iflags & D_FLAG));
 205
 206             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 207
 208 #if 0
 209 #include "disas/disas.h"
 210
 211 /* Useful instrumentation when debugging interrupt issues in either
 212    the models or in sw.  */
 213             {
 214                 const char *sym;
 215
 216                 sym = lookup_symbol(env->sregs[SR_PC]);
 217                 if (sym
 218                     && (!strcmp("netif_rx", sym)
 219                         || !strcmp("process_backlog", sym))) {
 220
 221                     qemu_log(
 222                          "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 223                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 224                          sym);
 225
 226                     log_cpu_state(cs, 0);
 227                 }
 228             }
 229 #endif
 230             qemu_log_mask(CPU_LOG_INT,
 231                          "interrupt at pc=%x msr=%x %x iflags=%x\n",
 232                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 233
 234             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 235                                     | MSR_UM | MSR_IE);
 236             env->sregs[SR_MSR] |= t;
 237
 238             env->regs[14] = env->sregs[SR_PC];
 239             env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
 240             //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 241             break;
 242
 243         case EXCP_BREAK:
 244         case EXCP_HW_BREAK:
 245             assert(!(env->iflags & IMM_FLAG));
 246             assert(!(env->iflags & D_FLAG));
 247             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 248             qemu_log_mask(CPU_LOG_INT,
 249                         "break at pc=%x msr=%x %x iflags=%x\n",
 250                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 251             log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 252             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 253             env->sregs[SR_MSR] |= t;
 254             env->sregs[SR_MSR] |= MSR_BIP;
 255             if (cs->exception_index == EXCP_HW_BREAK) {
 256                 env->regs[16] = env->sregs[SR_PC];
 257                 env->sregs[SR_MSR] |= MSR_BIP;
 258                 env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
 259             } else
 260                 env->sregs[SR_PC] = env->btarget;
 261             break;
 262         default:
 263             cpu_abort(cs, "unhandled exception type=%d\n",
 264                       cs->exception_index);
 265             break;
 266     }
 267 }
 268
 269 hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 270 {
 271     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 272     CPUMBState *env = &cpu->env;
 273     target_ulong vaddr, paddr = 0;
 274     struct microblaze_mmu_lookup lu;
 275     unsigned int hit;
 276
 277     if (env->sregs[SR_MSR] & MSR_VM) {
 278         hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 279         if (hit) {
 280             vaddr = addr & TARGET_PAGE_MASK;
 281             paddr = lu.paddr + vaddr - lu.vaddr;
 282         } else
 283             paddr = 0; /* ???.  */
 284     } else
 285         paddr = addr & TARGET_PAGE_MASK;
 286
 287     return paddr;
 288 }
 289 #endif
 290
 291 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 292 {
 293     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 294     CPUMBState *env = &cpu->env;
 295
 296     if ((interrupt_request & CPU_INTERRUPT_HARD)
 297         && (env->sregs[SR_MSR] & MSR_IE)
 298         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 299         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 300         cs->exception_index = EXCP_IRQ;
 301         mb_cpu_do_interrupt(cs);
 302         return true;
 303     }
 304     return false;
 305 }