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trace: fix documentation
[qemu/ar7.git] / target-cris / translate.c
blob295005f1413d7e62c0cb11e2e34a4cba18be968d
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "qemu/osdep.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "tcg-op.h"
30 #include "exec/helper-proto.h"
31 #include "mmu.h"
32 #include "exec/cpu_ldst.h"
33 #include "crisv32-decode.h"
34
35 #include "exec/helper-gen.h"
36
37 #include "trace-tcg.h"
38
39
40 #define DISAS_CRIS 0
41 #if DISAS_CRIS
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
49 #define BUG_ON(x) ({if (x) BUG();})
50
51 #define DISAS_SWI 5
52
53 /* Used by the decoder. */
54 #define EXTRACT_FIELD(src, start, end) \
55 (((src) >> start) & ((1 << (end - start + 1)) - 1))
56
57 #define CC_MASK_NZ 0xc
58 #define CC_MASK_NZV 0xe
59 #define CC_MASK_NZVC 0xf
60 #define CC_MASK_RNZV 0x10e
61
62 static TCGv_ptr cpu_env;
63 static TCGv cpu_R[16];
64 static TCGv cpu_PR[16];
65 static TCGv cc_x;
66 static TCGv cc_src;
67 static TCGv cc_dest;
68 static TCGv cc_result;
69 static TCGv cc_op;
70 static TCGv cc_size;
71 static TCGv cc_mask;
72
73 static TCGv env_btaken;
74 static TCGv env_btarget;
75 static TCGv env_pc;
76
77 #include "exec/gen-icount.h"
78
79 /* This is the state at translation time. */
80 typedef struct DisasContext {
81 CRISCPU *cpu;
82 target_ulong pc, ppc;
83
84 /* Decoder. */
85 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
86 uint32_t ir;
87 uint32_t opcode;
88 unsigned int op1;
89 unsigned int op2;
90 unsigned int zsize, zzsize;
91 unsigned int mode;
92 unsigned int postinc;
93
94 unsigned int size;
95 unsigned int src;
96 unsigned int dst;
97 unsigned int cond;
98
99 int update_cc;
100 int cc_op;
101 int cc_size;
102 uint32_t cc_mask;
103
104 int cc_size_uptodate; /* -1 invalid or last written value. */
105
106 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
107 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
108 int flagx_known; /* Whether or not flags_x has the x flag known at
109 translation time. */
110 int flags_x;
111
112 int clear_x; /* Clear x after this insn? */
113 int clear_prefix; /* Clear prefix after this insn? */
114 int clear_locked_irq; /* Clear the irq lockout. */
115 int cpustate_changed;
116 unsigned int tb_flags; /* tb dependent flags. */
117 int is_jmp;
118
119 #define JMP_NOJMP 0
120 #define JMP_DIRECT 1
121 #define JMP_DIRECT_CC 2
122 #define JMP_INDIRECT 3
123 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
124 uint32_t jmp_pc;
125
126 int delayed_branch;
127
128 struct TranslationBlock *tb;
129 int singlestep_enabled;
130 } DisasContext;
131
132 static void gen_BUG(DisasContext *dc, const char *file, int line)
133 {
134 fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line);
135 if (qemu_log_separate()) {
136 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
137 }
138 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
139 }
140
141 static const char *regnames[] =
142 {
143 "$r0", "$r1", "$r2", "$r3",
144 "$r4", "$r5", "$r6", "$r7",
145 "$r8", "$r9", "$r10", "$r11",
146 "$r12", "$r13", "$sp", "$acr",
147 };
148 static const char *pregnames[] =
149 {
150 "$bz", "$vr", "$pid", "$srs",
151 "$wz", "$exs", "$eda", "$mof",
152 "$dz", "$ebp", "$erp", "$srp",
153 "$nrp", "$ccs", "$usp", "$spc",
154 };
155
156 /* We need this table to handle preg-moves with implicit width. */
157 static int preg_sizes[] = {
158 1, /* bz. */
159 1, /* vr. */
160 4, /* pid. */
161 1, /* srs. */
162 2, /* wz. */
163 4, 4, 4,
164 4, 4, 4, 4,
165 4, 4, 4, 4,
166 };
167
168 #define t_gen_mov_TN_env(tn, member) \
169 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
170 #define t_gen_mov_env_TN(member, tn) \
171 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
172
173 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
174 {
175 assert(r >= 0 && r <= 15);
176 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
177 tcg_gen_mov_tl(tn, tcg_const_tl(0));
178 } else if (r == PR_VR) {
179 tcg_gen_mov_tl(tn, tcg_const_tl(32));
180 } else {
181 tcg_gen_mov_tl(tn, cpu_PR[r]);
182 }
183 }
184 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
185 {
186 assert(r >= 0 && r <= 15);
187 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
188 return;
189 } else if (r == PR_SRS) {
190 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
191 } else {
192 if (r == PR_PID) {
193 gen_helper_tlb_flush_pid(cpu_env, tn);
194 }
195 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
196 gen_helper_spc_write(cpu_env, tn);
197 } else if (r == PR_CCS) {
198 dc->cpustate_changed = 1;
199 }
200 tcg_gen_mov_tl(cpu_PR[r], tn);
201 }
202 }
203
204 /* Sign extend at translation time. */
205 static int sign_extend(unsigned int val, unsigned int width)
206 {
207 int sval;
208
209 /* LSL. */
210 val <<= 31 - width;
211 sval = val;
212 /* ASR. */
213 sval >>= 31 - width;
214 return sval;
215 }
216
217 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
218 unsigned int size, unsigned int sign)
219 {
220 int r;
221
222 switch (size) {
223 case 4:
224 {
225 r = cpu_ldl_code(env, addr);
226 break;
227 }
228 case 2:
229 {
230 if (sign) {
231 r = cpu_ldsw_code(env, addr);
232 } else {
233 r = cpu_lduw_code(env, addr);
234 }
235 break;
236 }
237 case 1:
238 {
239 if (sign) {
240 r = cpu_ldsb_code(env, addr);
241 } else {
242 r = cpu_ldub_code(env, addr);
243 }
244 break;
245 }
246 default:
247 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
248 break;
249 }
250 return r;
251 }
252
253 static void cris_lock_irq(DisasContext *dc)
254 {
255 dc->clear_locked_irq = 0;
256 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
257 }
258
259 static inline void t_gen_raise_exception(uint32_t index)
260 {
261 TCGv_i32 tmp = tcg_const_i32(index);
262 gen_helper_raise_exception(cpu_env, tmp);
263 tcg_temp_free_i32(tmp);
264 }
265
266 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
267 {
268 TCGv t0, t_31;
269
270 t0 = tcg_temp_new();
271 t_31 = tcg_const_tl(31);
272 tcg_gen_shl_tl(d, a, b);
273
274 tcg_gen_sub_tl(t0, t_31, b);
275 tcg_gen_sar_tl(t0, t0, t_31);
276 tcg_gen_and_tl(t0, t0, d);
277 tcg_gen_xor_tl(d, d, t0);
278 tcg_temp_free(t0);
279 tcg_temp_free(t_31);
280 }
281
282 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
283 {
284 TCGv t0, t_31;
285
286 t0 = tcg_temp_new();
287 t_31 = tcg_temp_new();
288 tcg_gen_shr_tl(d, a, b);
289
290 tcg_gen_movi_tl(t_31, 31);
291 tcg_gen_sub_tl(t0, t_31, b);
292 tcg_gen_sar_tl(t0, t0, t_31);
293 tcg_gen_and_tl(t0, t0, d);
294 tcg_gen_xor_tl(d, d, t0);
295 tcg_temp_free(t0);
296 tcg_temp_free(t_31);
297 }
298
299 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
300 {
301 TCGv t0, t_31;
302
303 t0 = tcg_temp_new();
304 t_31 = tcg_temp_new();
305 tcg_gen_sar_tl(d, a, b);
306
307 tcg_gen_movi_tl(t_31, 31);
308 tcg_gen_sub_tl(t0, t_31, b);
309 tcg_gen_sar_tl(t0, t0, t_31);
310 tcg_gen_or_tl(d, d, t0);
311 tcg_temp_free(t0);
312 tcg_temp_free(t_31);
313 }
314
315 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
316 {
317 TCGv t = tcg_temp_new();
318
319 /*
320 * d <<= 1
321 * if (d >= s)
322 * d -= s;
323 */
324 tcg_gen_shli_tl(d, a, 1);
325 tcg_gen_sub_tl(t, d, b);
326 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
327 tcg_temp_free(t);
328 }
329
330 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
331 {
332 TCGv t;
333
334 /*
335 * d <<= 1
336 * if (n)
337 * d += s;
338 */
339 t = tcg_temp_new();
340 tcg_gen_shli_tl(d, a, 1);
341 tcg_gen_shli_tl(t, ccs, 31 - 3);
342 tcg_gen_sari_tl(t, t, 31);
343 tcg_gen_and_tl(t, t, b);
344 tcg_gen_add_tl(d, d, t);
345 tcg_temp_free(t);
346 }
347
348 /* Extended arithmetics on CRIS. */
349 static inline void t_gen_add_flag(TCGv d, int flag)
350 {
351 TCGv c;
352
353 c = tcg_temp_new();
354 t_gen_mov_TN_preg(c, PR_CCS);
355 /* Propagate carry into d. */
356 tcg_gen_andi_tl(c, c, 1 << flag);
357 if (flag) {
358 tcg_gen_shri_tl(c, c, flag);
359 }
360 tcg_gen_add_tl(d, d, c);
361 tcg_temp_free(c);
362 }
363
364 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
365 {
366 if (dc->flagx_known) {
367 if (dc->flags_x) {
368 TCGv c;
369
370 c = tcg_temp_new();
371 t_gen_mov_TN_preg(c, PR_CCS);
372 /* C flag is already at bit 0. */
373 tcg_gen_andi_tl(c, c, C_FLAG);
374 tcg_gen_add_tl(d, d, c);
375 tcg_temp_free(c);
376 }
377 } else {
378 TCGv x, c;
379
380 x = tcg_temp_new();
381 c = tcg_temp_new();
382 t_gen_mov_TN_preg(x, PR_CCS);
383 tcg_gen_mov_tl(c, x);
384
385 /* Propagate carry into d if X is set. Branch free. */
386 tcg_gen_andi_tl(c, c, C_FLAG);
387 tcg_gen_andi_tl(x, x, X_FLAG);
388 tcg_gen_shri_tl(x, x, 4);
389
390 tcg_gen_and_tl(x, x, c);
391 tcg_gen_add_tl(d, d, x);
392 tcg_temp_free(x);
393 tcg_temp_free(c);
394 }
395 }
396
397 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
398 {
399 if (dc->flagx_known) {
400 if (dc->flags_x) {
401 TCGv c;
402
403 c = tcg_temp_new();
404 t_gen_mov_TN_preg(c, PR_CCS);
405 /* C flag is already at bit 0. */
406 tcg_gen_andi_tl(c, c, C_FLAG);
407 tcg_gen_sub_tl(d, d, c);
408 tcg_temp_free(c);
409 }
410 } else {
411 TCGv x, c;
412
413 x = tcg_temp_new();
414 c = tcg_temp_new();
415 t_gen_mov_TN_preg(x, PR_CCS);
416 tcg_gen_mov_tl(c, x);
417
418 /* Propagate carry into d if X is set. Branch free. */
419 tcg_gen_andi_tl(c, c, C_FLAG);
420 tcg_gen_andi_tl(x, x, X_FLAG);
421 tcg_gen_shri_tl(x, x, 4);
422
423 tcg_gen_and_tl(x, x, c);
424 tcg_gen_sub_tl(d, d, x);
425 tcg_temp_free(x);
426 tcg_temp_free(c);
427 }
428 }
429
430 /* Swap the two bytes within each half word of the s operand.
431 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
432 static inline void t_gen_swapb(TCGv d, TCGv s)
433 {
434 TCGv t, org_s;
435
436 t = tcg_temp_new();
437 org_s = tcg_temp_new();
438
439 /* d and s may refer to the same object. */
440 tcg_gen_mov_tl(org_s, s);
441 tcg_gen_shli_tl(t, org_s, 8);
442 tcg_gen_andi_tl(d, t, 0xff00ff00);
443 tcg_gen_shri_tl(t, org_s, 8);
444 tcg_gen_andi_tl(t, t, 0x00ff00ff);
445 tcg_gen_or_tl(d, d, t);
446 tcg_temp_free(t);
447 tcg_temp_free(org_s);
448 }
449
450 /* Swap the halfwords of the s operand. */
451 static inline void t_gen_swapw(TCGv d, TCGv s)
452 {
453 TCGv t;
454 /* d and s refer the same object. */
455 t = tcg_temp_new();
456 tcg_gen_mov_tl(t, s);
457 tcg_gen_shli_tl(d, t, 16);
458 tcg_gen_shri_tl(t, t, 16);
459 tcg_gen_or_tl(d, d, t);
460 tcg_temp_free(t);
461 }
462
463 /* Reverse the within each byte.
464 T0 = (((T0 << 7) & 0x80808080) |
465 ((T0 << 5) & 0x40404040) |
466 ((T0 << 3) & 0x20202020) |
467 ((T0 << 1) & 0x10101010) |
468 ((T0 >> 1) & 0x08080808) |
469 ((T0 >> 3) & 0x04040404) |
470 ((T0 >> 5) & 0x02020202) |
471 ((T0 >> 7) & 0x01010101));
472 */
473 static inline void t_gen_swapr(TCGv d, TCGv s)
474 {
475 struct {
476 int shift; /* LSL when positive, LSR when negative. */
477 uint32_t mask;
478 } bitrev[] = {
479 {7, 0x80808080},
480 {5, 0x40404040},
481 {3, 0x20202020},
482 {1, 0x10101010},
483 {-1, 0x08080808},
484 {-3, 0x04040404},
485 {-5, 0x02020202},
486 {-7, 0x01010101}
487 };
488 int i;
489 TCGv t, org_s;
490
491 /* d and s refer the same object. */
492 t = tcg_temp_new();
493 org_s = tcg_temp_new();
494 tcg_gen_mov_tl(org_s, s);
495
496 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
497 tcg_gen_andi_tl(d, t, bitrev[0].mask);
498 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
499 if (bitrev[i].shift >= 0) {
500 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
501 } else {
502 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
503 }
504 tcg_gen_andi_tl(t, t, bitrev[i].mask);
505 tcg_gen_or_tl(d, d, t);
506 }
507 tcg_temp_free(t);
508 tcg_temp_free(org_s);
509 }
510
511 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
512 {
513 TCGLabel *l1 = gen_new_label();
514
515 /* Conditional jmp. */
516 tcg_gen_mov_tl(env_pc, pc_false);
517 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
518 tcg_gen_mov_tl(env_pc, pc_true);
519 gen_set_label(l1);
520 }
521
522 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
523 {
524 TranslationBlock *tb;
525 tb = dc->tb;
526 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
527 tcg_gen_goto_tb(n);
528 tcg_gen_movi_tl(env_pc, dest);
529 tcg_gen_exit_tb((uintptr_t)tb + n);
530 } else {
531 tcg_gen_movi_tl(env_pc, dest);
532 tcg_gen_exit_tb(0);
533 }
534 }
535
536 static inline void cris_clear_x_flag(DisasContext *dc)
537 {
538 if (dc->flagx_known && dc->flags_x) {
539 dc->flags_uptodate = 0;
540 }
541
542 dc->flagx_known = 1;
543 dc->flags_x = 0;
544 }
545
546 static void cris_flush_cc_state(DisasContext *dc)
547 {
548 if (dc->cc_size_uptodate != dc->cc_size) {
549 tcg_gen_movi_tl(cc_size, dc->cc_size);
550 dc->cc_size_uptodate = dc->cc_size;
551 }
552 tcg_gen_movi_tl(cc_op, dc->cc_op);
553 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
554 }
555
556 static void cris_evaluate_flags(DisasContext *dc)
557 {
558 if (dc->flags_uptodate) {
559 return;
560 }
561
562 cris_flush_cc_state(dc);
563
564 switch (dc->cc_op) {
565 case CC_OP_MCP:
566 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
567 cpu_PR[PR_CCS], cc_src,
568 cc_dest, cc_result);
569 break;
570 case CC_OP_MULS:
571 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
572 cpu_PR[PR_CCS], cc_result,
573 cpu_PR[PR_MOF]);
574 break;
575 case CC_OP_MULU:
576 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
577 cpu_PR[PR_CCS], cc_result,
578 cpu_PR[PR_MOF]);
579 break;
580 case CC_OP_MOVE:
581 case CC_OP_AND:
582 case CC_OP_OR:
583 case CC_OP_XOR:
584 case CC_OP_ASR:
585 case CC_OP_LSR:
586 case CC_OP_LSL:
587 switch (dc->cc_size) {
588 case 4:
589 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
590 cpu_env, cpu_PR[PR_CCS], cc_result);
591 break;
592 case 2:
593 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
594 cpu_env, cpu_PR[PR_CCS], cc_result);
595 break;
596 default:
597 gen_helper_evaluate_flags(cpu_env);
598 break;
599 }
600 break;
601 case CC_OP_FLAGS:
602 /* live. */
603 break;
604 case CC_OP_SUB:
605 case CC_OP_CMP:
606 if (dc->cc_size == 4) {
607 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
608 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
609 } else {
610 gen_helper_evaluate_flags(cpu_env);
611 }
612
613 break;
614 default:
615 switch (dc->cc_size) {
616 case 4:
617 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
618 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
619 break;
620 default:
621 gen_helper_evaluate_flags(cpu_env);
622 break;
623 }
624 break;
625 }
626
627 if (dc->flagx_known) {
628 if (dc->flags_x) {
629 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
630 } else if (dc->cc_op == CC_OP_FLAGS) {
631 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
632 }
633 }
634 dc->flags_uptodate = 1;
635 }
636
637 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
638 {
639 uint32_t ovl;
640
641 if (!mask) {
642 dc->update_cc = 0;
643 return;
644 }
645
646 /* Check if we need to evaluate the condition codes due to
647 CC overlaying. */
648 ovl = (dc->cc_mask ^ mask) & ~mask;
649 if (ovl) {
650 /* TODO: optimize this case. It trigs all the time. */
651 cris_evaluate_flags(dc);
652 }
653 dc->cc_mask = mask;
654 dc->update_cc = 1;
655 }
656
657 static void cris_update_cc_op(DisasContext *dc, int op, int size)
658 {
659 dc->cc_op = op;
660 dc->cc_size = size;
661 dc->flags_uptodate = 0;
662 }
663
664 static inline void cris_update_cc_x(DisasContext *dc)
665 {
666 /* Save the x flag state at the time of the cc snapshot. */
667 if (dc->flagx_known) {
668 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
669 return;
670 }
671 tcg_gen_movi_tl(cc_x, dc->flags_x);
672 dc->cc_x_uptodate = 2 | dc->flags_x;
673 } else {
674 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
675 dc->cc_x_uptodate = 1;
676 }
677 }
678
679 /* Update cc prior to executing ALU op. Needs source operands untouched. */
680 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
681 TCGv dst, TCGv src, int size)
682 {
683 if (dc->update_cc) {
684 cris_update_cc_op(dc, op, size);
685 tcg_gen_mov_tl(cc_src, src);
686
687 if (op != CC_OP_MOVE
688 && op != CC_OP_AND
689 && op != CC_OP_OR
690 && op != CC_OP_XOR
691 && op != CC_OP_ASR
692 && op != CC_OP_LSR
693 && op != CC_OP_LSL) {
694 tcg_gen_mov_tl(cc_dest, dst);
695 }
696
697 cris_update_cc_x(dc);
698 }
699 }
700
701 /* Update cc after executing ALU op. needs the result. */
702 static inline void cris_update_result(DisasContext *dc, TCGv res)
703 {
704 if (dc->update_cc) {
705 tcg_gen_mov_tl(cc_result, res);
706 }
707 }
708
709 /* Returns one if the write back stage should execute. */
710 static void cris_alu_op_exec(DisasContext *dc, int op,
711 TCGv dst, TCGv a, TCGv b, int size)
712 {
713 /* Emit the ALU insns. */
714 switch (op) {
715 case CC_OP_ADD:
716 tcg_gen_add_tl(dst, a, b);
717 /* Extended arithmetics. */
718 t_gen_addx_carry(dc, dst);
719 break;
720 case CC_OP_ADDC:
721 tcg_gen_add_tl(dst, a, b);
722 t_gen_add_flag(dst, 0); /* C_FLAG. */
723 break;
724 case CC_OP_MCP:
725 tcg_gen_add_tl(dst, a, b);
726 t_gen_add_flag(dst, 8); /* R_FLAG. */
727 break;
728 case CC_OP_SUB:
729 tcg_gen_sub_tl(dst, a, b);
730 /* Extended arithmetics. */
731 t_gen_subx_carry(dc, dst);
732 break;
733 case CC_OP_MOVE:
734 tcg_gen_mov_tl(dst, b);
735 break;
736 case CC_OP_OR:
737 tcg_gen_or_tl(dst, a, b);
738 break;
739 case CC_OP_AND:
740 tcg_gen_and_tl(dst, a, b);
741 break;
742 case CC_OP_XOR:
743 tcg_gen_xor_tl(dst, a, b);
744 break;
745 case CC_OP_LSL:
746 t_gen_lsl(dst, a, b);
747 break;
748 case CC_OP_LSR:
749 t_gen_lsr(dst, a, b);
750 break;
751 case CC_OP_ASR:
752 t_gen_asr(dst, a, b);
753 break;
754 case CC_OP_NEG:
755 tcg_gen_neg_tl(dst, b);
756 /* Extended arithmetics. */
757 t_gen_subx_carry(dc, dst);
758 break;
759 case CC_OP_LZ:
760 gen_helper_lz(dst, b);
761 break;
762 case CC_OP_MULS:
763 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
764 break;
765 case CC_OP_MULU:
766 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
767 break;
768 case CC_OP_DSTEP:
769 t_gen_cris_dstep(dst, a, b);
770 break;
771 case CC_OP_MSTEP:
772 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
773 break;
774 case CC_OP_BOUND:
775 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
776 break;
777 case CC_OP_CMP:
778 tcg_gen_sub_tl(dst, a, b);
779 /* Extended arithmetics. */
780 t_gen_subx_carry(dc, dst);
781 break;
782 default:
783 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
784 BUG();
785 break;
786 }
787
788 if (size == 1) {
789 tcg_gen_andi_tl(dst, dst, 0xff);
790 } else if (size == 2) {
791 tcg_gen_andi_tl(dst, dst, 0xffff);
792 }
793 }
794
795 static void cris_alu(DisasContext *dc, int op,
796 TCGv d, TCGv op_a, TCGv op_b, int size)
797 {
798 TCGv tmp;
799 int writeback;
800
801 writeback = 1;
802
803 if (op == CC_OP_CMP) {
804 tmp = tcg_temp_new();
805 writeback = 0;
806 } else if (size == 4) {
807 tmp = d;
808 writeback = 0;
809 } else {
810 tmp = tcg_temp_new();
811 }
812
813
814 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
815 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
816 cris_update_result(dc, tmp);
817
818 /* Writeback. */
819 if (writeback) {
820 if (size == 1) {
821 tcg_gen_andi_tl(d, d, ~0xff);
822 } else {
823 tcg_gen_andi_tl(d, d, ~0xffff);
824 }
825 tcg_gen_or_tl(d, d, tmp);
826 }
827 if (!TCGV_EQUAL(tmp, d)) {
828 tcg_temp_free(tmp);
829 }
830 }
831
832 static int arith_cc(DisasContext *dc)
833 {
834 if (dc->update_cc) {
835 switch (dc->cc_op) {
836 case CC_OP_ADDC: return 1;
837 case CC_OP_ADD: return 1;
838 case CC_OP_SUB: return 1;
839 case CC_OP_DSTEP: return 1;
840 case CC_OP_LSL: return 1;
841 case CC_OP_LSR: return 1;
842 case CC_OP_ASR: return 1;
843 case CC_OP_CMP: return 1;
844 case CC_OP_NEG: return 1;
845 case CC_OP_OR: return 1;
846 case CC_OP_AND: return 1;
847 case CC_OP_XOR: return 1;
848 case CC_OP_MULU: return 1;
849 case CC_OP_MULS: return 1;
850 default:
851 return 0;
852 }
853 }
854 return 0;
855 }
856
857 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
858 {
859 int arith_opt, move_opt;
860
861 /* TODO: optimize more condition codes. */
862
863 /*
864 * If the flags are live, we've gotta look into the bits of CCS.
865 * Otherwise, if we just did an arithmetic operation we try to
866 * evaluate the condition code faster.
867 *
868 * When this function is done, T0 should be non-zero if the condition
869 * code is true.
870 */
871 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
872 move_opt = (dc->cc_op == CC_OP_MOVE);
873 switch (cond) {
874 case CC_EQ:
875 if ((arith_opt || move_opt)
876 && dc->cc_x_uptodate != (2 | X_FLAG)) {
877 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
878 cc_result, tcg_const_tl(0));
879 } else {
880 cris_evaluate_flags(dc);
881 tcg_gen_andi_tl(cc,
882 cpu_PR[PR_CCS], Z_FLAG);
883 }
884 break;
885 case CC_NE:
886 if ((arith_opt || move_opt)
887 && dc->cc_x_uptodate != (2 | X_FLAG)) {
888 tcg_gen_mov_tl(cc, cc_result);
889 } else {
890 cris_evaluate_flags(dc);
891 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
892 Z_FLAG);
893 tcg_gen_andi_tl(cc, cc, Z_FLAG);
894 }
895 break;
896 case CC_CS:
897 cris_evaluate_flags(dc);
898 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
899 break;
900 case CC_CC:
901 cris_evaluate_flags(dc);
902 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
903 tcg_gen_andi_tl(cc, cc, C_FLAG);
904 break;
905 case CC_VS:
906 cris_evaluate_flags(dc);
907 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
908 break;
909 case CC_VC:
910 cris_evaluate_flags(dc);
911 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
912 V_FLAG);
913 tcg_gen_andi_tl(cc, cc, V_FLAG);
914 break;
915 case CC_PL:
916 if (arith_opt || move_opt) {
917 int bits = 31;
918
919 if (dc->cc_size == 1) {
920 bits = 7;
921 } else if (dc->cc_size == 2) {
922 bits = 15;
923 }
924
925 tcg_gen_shri_tl(cc, cc_result, bits);
926 tcg_gen_xori_tl(cc, cc, 1);
927 } else {
928 cris_evaluate_flags(dc);
929 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
930 N_FLAG);
931 tcg_gen_andi_tl(cc, cc, N_FLAG);
932 }
933 break;
934 case CC_MI:
935 if (arith_opt || move_opt) {
936 int bits = 31;
937
938 if (dc->cc_size == 1) {
939 bits = 7;
940 } else if (dc->cc_size == 2) {
941 bits = 15;
942 }
943
944 tcg_gen_shri_tl(cc, cc_result, bits);
945 tcg_gen_andi_tl(cc, cc, 1);
946 } else {
947 cris_evaluate_flags(dc);
948 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
949 N_FLAG);
950 }
951 break;
952 case CC_LS:
953 cris_evaluate_flags(dc);
954 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
955 C_FLAG | Z_FLAG);
956 break;
957 case CC_HI:
958 cris_evaluate_flags(dc);
959 {
960 TCGv tmp;
961
962 tmp = tcg_temp_new();
963 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
964 C_FLAG | Z_FLAG);
965 /* Overlay the C flag on top of the Z. */
966 tcg_gen_shli_tl(cc, tmp, 2);
967 tcg_gen_and_tl(cc, tmp, cc);
968 tcg_gen_andi_tl(cc, cc, Z_FLAG);
969
970 tcg_temp_free(tmp);
971 }
972 break;
973 case CC_GE:
974 cris_evaluate_flags(dc);
975 /* Overlay the V flag on top of the N. */
976 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
977 tcg_gen_xor_tl(cc,
978 cpu_PR[PR_CCS], cc);
979 tcg_gen_andi_tl(cc, cc, N_FLAG);
980 tcg_gen_xori_tl(cc, cc, N_FLAG);
981 break;
982 case CC_LT:
983 cris_evaluate_flags(dc);
984 /* Overlay the V flag on top of the N. */
985 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
986 tcg_gen_xor_tl(cc,
987 cpu_PR[PR_CCS], cc);
988 tcg_gen_andi_tl(cc, cc, N_FLAG);
989 break;
990 case CC_GT:
991 cris_evaluate_flags(dc);
992 {
993 TCGv n, z;
994
995 n = tcg_temp_new();
996 z = tcg_temp_new();
997
998 /* To avoid a shift we overlay everything on
999 the V flag. */
1000 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1001 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1002 /* invert Z. */
1003 tcg_gen_xori_tl(z, z, 2);
1004
1005 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1006 tcg_gen_xori_tl(n, n, 2);
1007 tcg_gen_and_tl(cc, z, n);
1008 tcg_gen_andi_tl(cc, cc, 2);
1009
1010 tcg_temp_free(n);
1011 tcg_temp_free(z);
1012 }
1013 break;
1014 case CC_LE:
1015 cris_evaluate_flags(dc);
1016 {
1017 TCGv n, z;
1018
1019 n = tcg_temp_new();
1020 z = tcg_temp_new();
1021
1022 /* To avoid a shift we overlay everything on
1023 the V flag. */
1024 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1025 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1026
1027 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1028 tcg_gen_or_tl(cc, z, n);
1029 tcg_gen_andi_tl(cc, cc, 2);
1030
1031 tcg_temp_free(n);
1032 tcg_temp_free(z);
1033 }
1034 break;
1035 case CC_P:
1036 cris_evaluate_flags(dc);
1037 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1038 break;
1039 case CC_A:
1040 tcg_gen_movi_tl(cc, 1);
1041 break;
1042 default:
1043 BUG();
1044 break;
1045 };
1046 }
1047
1048 static void cris_store_direct_jmp(DisasContext *dc)
1049 {
1050 /* Store the direct jmp state into the cpu-state. */
1051 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1052 if (dc->jmp == JMP_DIRECT) {
1053 tcg_gen_movi_tl(env_btaken, 1);
1054 }
1055 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1056 dc->jmp = JMP_INDIRECT;
1057 }
1058 }
1059
1060 static void cris_prepare_cc_branch (DisasContext *dc,
1061 int offset, int cond)
1062 {
1063 /* This helps us re-schedule the micro-code to insns in delay-slots
1064 before the actual jump. */
1065 dc->delayed_branch = 2;
1066 dc->jmp = JMP_DIRECT_CC;
1067 dc->jmp_pc = dc->pc + offset;
1068
1069 gen_tst_cc(dc, env_btaken, cond);
1070 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1071 }
1072
1073
1074 /* jumps, when the dest is in a live reg for example. Direct should be set
1075 when the dest addr is constant to allow tb chaining. */
1076 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1077 {
1078 /* This helps us re-schedule the micro-code to insns in delay-slots
1079 before the actual jump. */
1080 dc->delayed_branch = 2;
1081 dc->jmp = type;
1082 if (type == JMP_INDIRECT) {
1083 tcg_gen_movi_tl(env_btaken, 1);
1084 }
1085 }
1086
1087 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1088 {
1089 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1090
1091 /* If we get a fault on a delayslot we must keep the jmp state in
1092 the cpu-state to be able to re-execute the jmp. */
1093 if (dc->delayed_branch == 1) {
1094 cris_store_direct_jmp(dc);
1095 }
1096
1097 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1098 }
1099
1100 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1101 unsigned int size, int sign)
1102 {
1103 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1104
1105 /* If we get a fault on a delayslot we must keep the jmp state in
1106 the cpu-state to be able to re-execute the jmp. */
1107 if (dc->delayed_branch == 1) {
1108 cris_store_direct_jmp(dc);
1109 }
1110
1111 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1112 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1113 }
1114
1115 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1116 unsigned int size)
1117 {
1118 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1119
1120 /* If we get a fault on a delayslot we must keep the jmp state in
1121 the cpu-state to be able to re-execute the jmp. */
1122 if (dc->delayed_branch == 1) {
1123 cris_store_direct_jmp(dc);
1124 }
1125
1126
1127 /* Conditional writes. We only support the kind were X and P are known
1128 at translation time. */
1129 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1130 dc->postinc = 0;
1131 cris_evaluate_flags(dc);
1132 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1133 return;
1134 }
1135
1136 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1137
1138 if (dc->flagx_known && dc->flags_x) {
1139 cris_evaluate_flags(dc);
1140 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1141 }
1142 }
1143
1144 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1145 {
1146 if (size == 1) {
1147 tcg_gen_ext8s_i32(d, s);
1148 } else if (size == 2) {
1149 tcg_gen_ext16s_i32(d, s);
1150 } else if (!TCGV_EQUAL(d, s)) {
1151 tcg_gen_mov_tl(d, s);
1152 }
1153 }
1154
1155 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1156 {
1157 if (size == 1) {
1158 tcg_gen_ext8u_i32(d, s);
1159 } else if (size == 2) {
1160 tcg_gen_ext16u_i32(d, s);
1161 } else if (!TCGV_EQUAL(d, s)) {
1162 tcg_gen_mov_tl(d, s);
1163 }
1164 }
1165
1166 #if DISAS_CRIS
1167 static char memsize_char(int size)
1168 {
1169 switch (size) {
1170 case 1: return 'b'; break;
1171 case 2: return 'w'; break;
1172 case 4: return 'd'; break;
1173 default:
1174 return 'x';
1175 break;
1176 }
1177 }
1178 #endif
1179
1180 static inline unsigned int memsize_z(DisasContext *dc)
1181 {
1182 return dc->zsize + 1;
1183 }
1184
1185 static inline unsigned int memsize_zz(DisasContext *dc)
1186 {
1187 switch (dc->zzsize) {
1188 case 0: return 1;
1189 case 1: return 2;
1190 default:
1191 return 4;
1192 }
1193 }
1194
1195 static inline void do_postinc (DisasContext *dc, int size)
1196 {
1197 if (dc->postinc) {
1198 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1199 }
1200 }
1201
1202 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1203 int size, int s_ext, TCGv dst)
1204 {
1205 if (s_ext) {
1206 t_gen_sext(dst, cpu_R[rs], size);
1207 } else {
1208 t_gen_zext(dst, cpu_R[rs], size);
1209 }
1210 }
1211
1212 /* Prepare T0 and T1 for a register alu operation.
1213 s_ext decides if the operand1 should be sign-extended or zero-extended when
1214 needed. */
1215 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1216 int size, int s_ext, TCGv dst, TCGv src)
1217 {
1218 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1219
1220 if (s_ext) {
1221 t_gen_sext(dst, cpu_R[rd], size);
1222 } else {
1223 t_gen_zext(dst, cpu_R[rd], size);
1224 }
1225 }
1226
1227 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1228 int s_ext, int memsize, TCGv dst)
1229 {
1230 unsigned int rs;
1231 uint32_t imm;
1232 int is_imm;
1233 int insn_len = 2;
1234
1235 rs = dc->op1;
1236 is_imm = rs == 15 && dc->postinc;
1237
1238 /* Load [$rs] onto T1. */
1239 if (is_imm) {
1240 insn_len = 2 + memsize;
1241 if (memsize == 1) {
1242 insn_len++;
1243 }
1244
1245 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1246 tcg_gen_movi_tl(dst, imm);
1247 dc->postinc = 0;
1248 } else {
1249 cris_flush_cc_state(dc);
1250 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1251 if (s_ext) {
1252 t_gen_sext(dst, dst, memsize);
1253 } else {
1254 t_gen_zext(dst, dst, memsize);
1255 }
1256 }
1257 return insn_len;
1258 }
1259
1260 /* Prepare T0 and T1 for a memory + alu operation.
1261 s_ext decides if the operand1 should be sign-extended or zero-extended when
1262 needed. */
1263 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1264 int s_ext, int memsize, TCGv dst, TCGv src)
1265 {
1266 int insn_len;
1267
1268 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1269 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1270 return insn_len;
1271 }
1272
1273 #if DISAS_CRIS
1274 static const char *cc_name(int cc)
1275 {
1276 static const char *cc_names[16] = {
1277 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1278 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1279 };
1280 assert(cc < 16);
1281 return cc_names[cc];
1282 }
1283 #endif
1284
1285 /* Start of insn decoders. */
1286
1287 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1288 {
1289 int32_t offset;
1290 int sign;
1291 uint32_t cond = dc->op2;
1292
1293 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1294 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1295
1296 offset *= 2;
1297 offset |= sign << 8;
1298 offset = sign_extend(offset, 8);
1299
1300 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1301
1302 /* op2 holds the condition-code. */
1303 cris_cc_mask(dc, 0);
1304 cris_prepare_cc_branch(dc, offset, cond);
1305 return 2;
1306 }
1307 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1308 {
1309 int32_t imm;
1310
1311 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1312 imm = sign_extend(dc->op1, 7);
1313
1314 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1315 cris_cc_mask(dc, 0);
1316 /* Fetch register operand, */
1317 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1318
1319 return 2;
1320 }
1321 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1322 {
1323 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1324
1325 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1326
1327 cris_cc_mask(dc, CC_MASK_NZVC);
1328
1329 cris_alu(dc, CC_OP_ADD,
1330 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1331 return 2;
1332 }
1333 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1334 {
1335 uint32_t imm;
1336
1337 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1338 imm = sign_extend(dc->op1, 5);
1339 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1340
1341 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1342 return 2;
1343 }
1344 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1345 {
1346 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1347
1348 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1349
1350 cris_cc_mask(dc, CC_MASK_NZVC);
1351 cris_alu(dc, CC_OP_SUB,
1352 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1353 return 2;
1354 }
1355 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1356 {
1357 uint32_t imm;
1358 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1359 imm = sign_extend(dc->op1, 5);
1360
1361 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1362 cris_cc_mask(dc, CC_MASK_NZVC);
1363
1364 cris_alu(dc, CC_OP_CMP,
1365 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1366 return 2;
1367 }
1368 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1369 {
1370 uint32_t imm;
1371 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1372 imm = sign_extend(dc->op1, 5);
1373
1374 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1375 cris_cc_mask(dc, CC_MASK_NZ);
1376
1377 cris_alu(dc, CC_OP_AND,
1378 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1379 return 2;
1380 }
1381 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1382 {
1383 uint32_t imm;
1384 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1385 imm = sign_extend(dc->op1, 5);
1386 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1387 cris_cc_mask(dc, CC_MASK_NZ);
1388
1389 cris_alu(dc, CC_OP_OR,
1390 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1391 return 2;
1392 }
1393 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1394 {
1395 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1396 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1397
1398 cris_cc_mask(dc, CC_MASK_NZ);
1399 cris_evaluate_flags(dc);
1400 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1401 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1402 cris_alu(dc, CC_OP_MOVE,
1403 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1404 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1405 dc->flags_uptodate = 1;
1406 return 2;
1407 }
1408 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1409 {
1410 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1411 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1412 cris_cc_mask(dc, CC_MASK_NZ);
1413
1414 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1415 cris_alu(dc, CC_OP_MOVE,
1416 cpu_R[dc->op2],
1417 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1418 return 2;
1419 }
1420 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1421 {
1422 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1423 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1424
1425 cris_cc_mask(dc, CC_MASK_NZ);
1426
1427 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1428
1429 cris_alu(dc, CC_OP_MOVE,
1430 cpu_R[dc->op2],
1431 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1432 return 2;
1433 }
1434 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1435 {
1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1437 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1438
1439 cris_cc_mask(dc, CC_MASK_NZ);
1440
1441 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1442 cris_alu(dc, CC_OP_MOVE,
1443 cpu_R[dc->op2],
1444 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1445 return 2;
1446 }
1447
1448 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1449 {
1450 int size = memsize_zz(dc);
1451
1452 LOG_DIS("move.%c $r%u, $r%u\n",
1453 memsize_char(size), dc->op1, dc->op2);
1454
1455 cris_cc_mask(dc, CC_MASK_NZ);
1456 if (size == 4) {
1457 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1458 cris_cc_mask(dc, CC_MASK_NZ);
1459 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1460 cris_update_cc_x(dc);
1461 cris_update_result(dc, cpu_R[dc->op2]);
1462 } else {
1463 TCGv t0;
1464
1465 t0 = tcg_temp_new();
1466 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1467 cris_alu(dc, CC_OP_MOVE,
1468 cpu_R[dc->op2],
1469 cpu_R[dc->op2], t0, size);
1470 tcg_temp_free(t0);
1471 }
1472 return 2;
1473 }
1474
1475 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1476 {
1477 int cond = dc->op2;
1478
1479 LOG_DIS("s%s $r%u\n",
1480 cc_name(cond), dc->op1);
1481
1482 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1483 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
1484
1485 cris_cc_mask(dc, 0);
1486 return 2;
1487 }
1488
1489 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1490 {
1491 if (size == 4) {
1492 t[0] = cpu_R[dc->op2];
1493 t[1] = cpu_R[dc->op1];
1494 } else {
1495 t[0] = tcg_temp_new();
1496 t[1] = tcg_temp_new();
1497 }
1498 }
1499
1500 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1501 {
1502 if (size != 4) {
1503 tcg_temp_free(t[0]);
1504 tcg_temp_free(t[1]);
1505 }
1506 }
1507
1508 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1509 {
1510 TCGv t[2];
1511 int size = memsize_zz(dc);
1512
1513 LOG_DIS("and.%c $r%u, $r%u\n",
1514 memsize_char(size), dc->op1, dc->op2);
1515
1516 cris_cc_mask(dc, CC_MASK_NZ);
1517
1518 cris_alu_alloc_temps(dc, size, t);
1519 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1520 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1521 cris_alu_free_temps(dc, size, t);
1522 return 2;
1523 }
1524
1525 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1526 {
1527 TCGv t0;
1528 LOG_DIS("lz $r%u, $r%u\n",
1529 dc->op1, dc->op2);
1530 cris_cc_mask(dc, CC_MASK_NZ);
1531 t0 = tcg_temp_new();
1532 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1533 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1534 tcg_temp_free(t0);
1535 return 2;
1536 }
1537
1538 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1539 {
1540 TCGv t[2];
1541 int size = memsize_zz(dc);
1542
1543 LOG_DIS("lsl.%c $r%u, $r%u\n",
1544 memsize_char(size), dc->op1, dc->op2);
1545
1546 cris_cc_mask(dc, CC_MASK_NZ);
1547 cris_alu_alloc_temps(dc, size, t);
1548 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1549 tcg_gen_andi_tl(t[1], t[1], 63);
1550 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1551 cris_alu_alloc_temps(dc, size, t);
1552 return 2;
1553 }
1554
1555 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1556 {
1557 TCGv t[2];
1558 int size = memsize_zz(dc);
1559
1560 LOG_DIS("lsr.%c $r%u, $r%u\n",
1561 memsize_char(size), dc->op1, dc->op2);
1562
1563 cris_cc_mask(dc, CC_MASK_NZ);
1564 cris_alu_alloc_temps(dc, size, t);
1565 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1566 tcg_gen_andi_tl(t[1], t[1], 63);
1567 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1568 cris_alu_free_temps(dc, size, t);
1569 return 2;
1570 }
1571
1572 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1573 {
1574 TCGv t[2];
1575 int size = memsize_zz(dc);
1576
1577 LOG_DIS("asr.%c $r%u, $r%u\n",
1578 memsize_char(size), dc->op1, dc->op2);
1579
1580 cris_cc_mask(dc, CC_MASK_NZ);
1581 cris_alu_alloc_temps(dc, size, t);
1582 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1583 tcg_gen_andi_tl(t[1], t[1], 63);
1584 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1585 cris_alu_free_temps(dc, size, t);
1586 return 2;
1587 }
1588
1589 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1590 {
1591 TCGv t[2];
1592 int size = memsize_zz(dc);
1593
1594 LOG_DIS("muls.%c $r%u, $r%u\n",
1595 memsize_char(size), dc->op1, dc->op2);
1596 cris_cc_mask(dc, CC_MASK_NZV);
1597 cris_alu_alloc_temps(dc, size, t);
1598 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1599
1600 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1601 cris_alu_free_temps(dc, size, t);
1602 return 2;
1603 }
1604
1605 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1606 {
1607 TCGv t[2];
1608 int size = memsize_zz(dc);
1609
1610 LOG_DIS("mulu.%c $r%u, $r%u\n",
1611 memsize_char(size), dc->op1, dc->op2);
1612 cris_cc_mask(dc, CC_MASK_NZV);
1613 cris_alu_alloc_temps(dc, size, t);
1614 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1615
1616 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1617 cris_alu_alloc_temps(dc, size, t);
1618 return 2;
1619 }
1620
1621
1622 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1623 {
1624 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1625 cris_cc_mask(dc, CC_MASK_NZ);
1626 cris_alu(dc, CC_OP_DSTEP,
1627 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1628 return 2;
1629 }
1630
1631 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1632 {
1633 TCGv t[2];
1634 int size = memsize_zz(dc);
1635 LOG_DIS("xor.%c $r%u, $r%u\n",
1636 memsize_char(size), dc->op1, dc->op2);
1637 BUG_ON(size != 4); /* xor is dword. */
1638 cris_cc_mask(dc, CC_MASK_NZ);
1639 cris_alu_alloc_temps(dc, size, t);
1640 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1641
1642 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1643 cris_alu_free_temps(dc, size, t);
1644 return 2;
1645 }
1646
1647 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1648 {
1649 TCGv l0;
1650 int size = memsize_zz(dc);
1651 LOG_DIS("bound.%c $r%u, $r%u\n",
1652 memsize_char(size), dc->op1, dc->op2);
1653 cris_cc_mask(dc, CC_MASK_NZ);
1654 l0 = tcg_temp_local_new();
1655 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1656 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1657 tcg_temp_free(l0);
1658 return 2;
1659 }
1660
1661 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1662 {
1663 TCGv t[2];
1664 int size = memsize_zz(dc);
1665 LOG_DIS("cmp.%c $r%u, $r%u\n",
1666 memsize_char(size), dc->op1, dc->op2);
1667 cris_cc_mask(dc, CC_MASK_NZVC);
1668 cris_alu_alloc_temps(dc, size, t);
1669 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1670
1671 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1672 cris_alu_free_temps(dc, size, t);
1673 return 2;
1674 }
1675
1676 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1677 {
1678 TCGv t0;
1679
1680 LOG_DIS("abs $r%u, $r%u\n",
1681 dc->op1, dc->op2);
1682 cris_cc_mask(dc, CC_MASK_NZ);
1683
1684 t0 = tcg_temp_new();
1685 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1686 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1687 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1688 tcg_temp_free(t0);
1689
1690 cris_alu(dc, CC_OP_MOVE,
1691 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1692 return 2;
1693 }
1694
1695 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1696 {
1697 TCGv t[2];
1698 int size = memsize_zz(dc);
1699 LOG_DIS("add.%c $r%u, $r%u\n",
1700 memsize_char(size), dc->op1, dc->op2);
1701 cris_cc_mask(dc, CC_MASK_NZVC);
1702 cris_alu_alloc_temps(dc, size, t);
1703 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1704
1705 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1706 cris_alu_free_temps(dc, size, t);
1707 return 2;
1708 }
1709
1710 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1711 {
1712 LOG_DIS("addc $r%u, $r%u\n",
1713 dc->op1, dc->op2);
1714 cris_evaluate_flags(dc);
1715 /* Set for this insn. */
1716 dc->flagx_known = 1;
1717 dc->flags_x = X_FLAG;
1718
1719 cris_cc_mask(dc, CC_MASK_NZVC);
1720 cris_alu(dc, CC_OP_ADDC,
1721 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1722 return 2;
1723 }
1724
1725 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1726 {
1727 LOG_DIS("mcp $p%u, $r%u\n",
1728 dc->op2, dc->op1);
1729 cris_evaluate_flags(dc);
1730 cris_cc_mask(dc, CC_MASK_RNZV);
1731 cris_alu(dc, CC_OP_MCP,
1732 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1733 return 2;
1734 }
1735
1736 #if DISAS_CRIS
1737 static char * swapmode_name(int mode, char *modename) {
1738 int i = 0;
1739 if (mode & 8) {
1740 modename[i++] = 'n';
1741 }
1742 if (mode & 4) {
1743 modename[i++] = 'w';
1744 }
1745 if (mode & 2) {
1746 modename[i++] = 'b';
1747 }
1748 if (mode & 1) {
1749 modename[i++] = 'r';
1750 }
1751 modename[i++] = 0;
1752 return modename;
1753 }
1754 #endif
1755
1756 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1757 {
1758 TCGv t0;
1759 #if DISAS_CRIS
1760 char modename[4];
1761 #endif
1762 LOG_DIS("swap%s $r%u\n",
1763 swapmode_name(dc->op2, modename), dc->op1);
1764
1765 cris_cc_mask(dc, CC_MASK_NZ);
1766 t0 = tcg_temp_new();
1767 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1768 if (dc->op2 & 8) {
1769 tcg_gen_not_tl(t0, t0);
1770 }
1771 if (dc->op2 & 4) {
1772 t_gen_swapw(t0, t0);
1773 }
1774 if (dc->op2 & 2) {
1775 t_gen_swapb(t0, t0);
1776 }
1777 if (dc->op2 & 1) {
1778 t_gen_swapr(t0, t0);
1779 }
1780 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1781 tcg_temp_free(t0);
1782 return 2;
1783 }
1784
1785 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1786 {
1787 TCGv t[2];
1788 int size = memsize_zz(dc);
1789 LOG_DIS("or.%c $r%u, $r%u\n",
1790 memsize_char(size), dc->op1, dc->op2);
1791 cris_cc_mask(dc, CC_MASK_NZ);
1792 cris_alu_alloc_temps(dc, size, t);
1793 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1794 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1795 cris_alu_free_temps(dc, size, t);
1796 return 2;
1797 }
1798
1799 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1800 {
1801 TCGv t0;
1802 LOG_DIS("addi.%c $r%u, $r%u\n",
1803 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1804 cris_cc_mask(dc, 0);
1805 t0 = tcg_temp_new();
1806 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1807 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1808 tcg_temp_free(t0);
1809 return 2;
1810 }
1811
1812 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1813 {
1814 TCGv t0;
1815 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1816 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1817 cris_cc_mask(dc, 0);
1818 t0 = tcg_temp_new();
1819 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1820 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1821 tcg_temp_free(t0);
1822 return 2;
1823 }
1824
1825 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1826 {
1827 TCGv t[2];
1828 int size = memsize_zz(dc);
1829 LOG_DIS("neg.%c $r%u, $r%u\n",
1830 memsize_char(size), dc->op1, dc->op2);
1831 cris_cc_mask(dc, CC_MASK_NZVC);
1832 cris_alu_alloc_temps(dc, size, t);
1833 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1834
1835 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1836 cris_alu_free_temps(dc, size, t);
1837 return 2;
1838 }
1839
1840 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1841 {
1842 LOG_DIS("btst $r%u, $r%u\n",
1843 dc->op1, dc->op2);
1844 cris_cc_mask(dc, CC_MASK_NZ);
1845 cris_evaluate_flags(dc);
1846 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1847 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1848 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1849 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1850 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1851 dc->flags_uptodate = 1;
1852 return 2;
1853 }
1854
1855 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1856 {
1857 TCGv t[2];
1858 int size = memsize_zz(dc);
1859 LOG_DIS("sub.%c $r%u, $r%u\n",
1860 memsize_char(size), dc->op1, dc->op2);
1861 cris_cc_mask(dc, CC_MASK_NZVC);
1862 cris_alu_alloc_temps(dc, size, t);
1863 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1864 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1865 cris_alu_free_temps(dc, size, t);
1866 return 2;
1867 }
1868
1869 /* Zero extension. From size to dword. */
1870 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1871 {
1872 TCGv t0;
1873 int size = memsize_z(dc);
1874 LOG_DIS("movu.%c $r%u, $r%u\n",
1875 memsize_char(size),
1876 dc->op1, dc->op2);
1877
1878 cris_cc_mask(dc, CC_MASK_NZ);
1879 t0 = tcg_temp_new();
1880 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1881 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1882 tcg_temp_free(t0);
1883 return 2;
1884 }
1885
1886 /* Sign extension. From size to dword. */
1887 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1888 {
1889 TCGv t0;
1890 int size = memsize_z(dc);
1891 LOG_DIS("movs.%c $r%u, $r%u\n",
1892 memsize_char(size),
1893 dc->op1, dc->op2);
1894
1895 cris_cc_mask(dc, CC_MASK_NZ);
1896 t0 = tcg_temp_new();
1897 /* Size can only be qi or hi. */
1898 t_gen_sext(t0, cpu_R[dc->op1], size);
1899 cris_alu(dc, CC_OP_MOVE,
1900 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1901 tcg_temp_free(t0);
1902 return 2;
1903 }
1904
1905 /* zero extension. From size to dword. */
1906 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1907 {
1908 TCGv t0;
1909 int size = memsize_z(dc);
1910 LOG_DIS("addu.%c $r%u, $r%u\n",
1911 memsize_char(size),
1912 dc->op1, dc->op2);
1913
1914 cris_cc_mask(dc, CC_MASK_NZVC);
1915 t0 = tcg_temp_new();
1916 /* Size can only be qi or hi. */
1917 t_gen_zext(t0, cpu_R[dc->op1], size);
1918 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1919 tcg_temp_free(t0);
1920 return 2;
1921 }
1922
1923 /* Sign extension. From size to dword. */
1924 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1925 {
1926 TCGv t0;
1927 int size = memsize_z(dc);
1928 LOG_DIS("adds.%c $r%u, $r%u\n",
1929 memsize_char(size),
1930 dc->op1, dc->op2);
1931
1932 cris_cc_mask(dc, CC_MASK_NZVC);
1933 t0 = tcg_temp_new();
1934 /* Size can only be qi or hi. */
1935 t_gen_sext(t0, cpu_R[dc->op1], size);
1936 cris_alu(dc, CC_OP_ADD,
1937 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1938 tcg_temp_free(t0);
1939 return 2;
1940 }
1941
1942 /* Zero extension. From size to dword. */
1943 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1944 {
1945 TCGv t0;
1946 int size = memsize_z(dc);
1947 LOG_DIS("subu.%c $r%u, $r%u\n",
1948 memsize_char(size),
1949 dc->op1, dc->op2);
1950
1951 cris_cc_mask(dc, CC_MASK_NZVC);
1952 t0 = tcg_temp_new();
1953 /* Size can only be qi or hi. */
1954 t_gen_zext(t0, cpu_R[dc->op1], size);
1955 cris_alu(dc, CC_OP_SUB,
1956 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1957 tcg_temp_free(t0);
1958 return 2;
1959 }
1960
1961 /* Sign extension. From size to dword. */
1962 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1963 {
1964 TCGv t0;
1965 int size = memsize_z(dc);
1966 LOG_DIS("subs.%c $r%u, $r%u\n",
1967 memsize_char(size),
1968 dc->op1, dc->op2);
1969
1970 cris_cc_mask(dc, CC_MASK_NZVC);
1971 t0 = tcg_temp_new();
1972 /* Size can only be qi or hi. */
1973 t_gen_sext(t0, cpu_R[dc->op1], size);
1974 cris_alu(dc, CC_OP_SUB,
1975 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1976 tcg_temp_free(t0);
1977 return 2;
1978 }
1979
1980 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1981 {
1982 uint32_t flags;
1983 int set = (~dc->opcode >> 2) & 1;
1984
1985
1986 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1987 | EXTRACT_FIELD(dc->ir, 0, 3);
1988 if (set && flags == 0) {
1989 LOG_DIS("nop\n");
1990 return 2;
1991 } else if (!set && (flags & 0x20)) {
1992 LOG_DIS("di\n");
1993 } else {
1994 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
1995 }
1996
1997 /* User space is not allowed to touch these. Silently ignore. */
1998 if (dc->tb_flags & U_FLAG) {
1999 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2000 }
2001
2002 if (flags & X_FLAG) {
2003 dc->flagx_known = 1;
2004 if (set) {
2005 dc->flags_x = X_FLAG;
2006 } else {
2007 dc->flags_x = 0;
2008 }
2009 }
2010
2011 /* Break the TB if any of the SPI flag changes. */
2012 if (flags & (P_FLAG | S_FLAG)) {
2013 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2014 dc->is_jmp = DISAS_UPDATE;
2015 dc->cpustate_changed = 1;
2016 }
2017
2018 /* For the I flag, only act on posedge. */
2019 if ((flags & I_FLAG)) {
2020 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2021 dc->is_jmp = DISAS_UPDATE;
2022 dc->cpustate_changed = 1;
2023 }
2024
2025
2026 /* Simply decode the flags. */
2027 cris_evaluate_flags(dc);
2028 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2029 cris_update_cc_x(dc);
2030 tcg_gen_movi_tl(cc_op, dc->cc_op);
2031
2032 if (set) {
2033 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2034 /* Enter user mode. */
2035 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2036 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2037 dc->cpustate_changed = 1;
2038 }
2039 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2040 } else {
2041 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2042 }
2043
2044 dc->flags_uptodate = 1;
2045 dc->clear_x = 0;
2046 return 2;
2047 }
2048
2049 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2050 {
2051 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2052 cris_cc_mask(dc, 0);
2053 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2054 tcg_const_tl(dc->op1));
2055 return 2;
2056 }
2057 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2058 {
2059 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2060 cris_cc_mask(dc, 0);
2061 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2062 tcg_const_tl(dc->op2));
2063 return 2;
2064 }
2065
2066 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2067 {
2068 TCGv t[2];
2069 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2070 cris_cc_mask(dc, 0);
2071
2072 t[0] = tcg_temp_new();
2073 if (dc->op2 == PR_CCS) {
2074 cris_evaluate_flags(dc);
2075 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2076 if (dc->tb_flags & U_FLAG) {
2077 t[1] = tcg_temp_new();
2078 /* User space is not allowed to touch all flags. */
2079 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2080 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2081 tcg_gen_or_tl(t[0], t[1], t[0]);
2082 tcg_temp_free(t[1]);
2083 }
2084 } else {
2085 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2086 }
2087
2088 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2089 if (dc->op2 == PR_CCS) {
2090 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2091 dc->flags_uptodate = 1;
2092 }
2093 tcg_temp_free(t[0]);
2094 return 2;
2095 }
2096 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2097 {
2098 TCGv t0;
2099 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2100 cris_cc_mask(dc, 0);
2101
2102 if (dc->op2 == PR_CCS) {
2103 cris_evaluate_flags(dc);
2104 }
2105
2106 if (dc->op2 == PR_DZ) {
2107 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2108 } else {
2109 t0 = tcg_temp_new();
2110 t_gen_mov_TN_preg(t0, dc->op2);
2111 cris_alu(dc, CC_OP_MOVE,
2112 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2113 preg_sizes[dc->op2]);
2114 tcg_temp_free(t0);
2115 }
2116 return 2;
2117 }
2118
2119 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2120 {
2121 int memsize = memsize_zz(dc);
2122 int insn_len;
2123 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2124 memsize_char(memsize),
2125 dc->op1, dc->postinc ? "+]" : "]",
2126 dc->op2);
2127
2128 if (memsize == 4) {
2129 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2130 cris_cc_mask(dc, CC_MASK_NZ);
2131 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2132 cris_update_cc_x(dc);
2133 cris_update_result(dc, cpu_R[dc->op2]);
2134 } else {
2135 TCGv t0;
2136
2137 t0 = tcg_temp_new();
2138 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2139 cris_cc_mask(dc, CC_MASK_NZ);
2140 cris_alu(dc, CC_OP_MOVE,
2141 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2142 tcg_temp_free(t0);
2143 }
2144 do_postinc(dc, memsize);
2145 return insn_len;
2146 }
2147
2148 static inline void cris_alu_m_alloc_temps(TCGv *t)
2149 {
2150 t[0] = tcg_temp_new();
2151 t[1] = tcg_temp_new();
2152 }
2153
2154 static inline void cris_alu_m_free_temps(TCGv *t)
2155 {
2156 tcg_temp_free(t[0]);
2157 tcg_temp_free(t[1]);
2158 }
2159
2160 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2161 {
2162 TCGv t[2];
2163 int memsize = memsize_z(dc);
2164 int insn_len;
2165 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2166 memsize_char(memsize),
2167 dc->op1, dc->postinc ? "+]" : "]",
2168 dc->op2);
2169
2170 cris_alu_m_alloc_temps(t);
2171 /* sign extend. */
2172 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2173 cris_cc_mask(dc, CC_MASK_NZ);
2174 cris_alu(dc, CC_OP_MOVE,
2175 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2176 do_postinc(dc, memsize);
2177 cris_alu_m_free_temps(t);
2178 return insn_len;
2179 }
2180
2181 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2182 {
2183 TCGv t[2];
2184 int memsize = memsize_z(dc);
2185 int insn_len;
2186 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2187 memsize_char(memsize),
2188 dc->op1, dc->postinc ? "+]" : "]",
2189 dc->op2);
2190
2191 cris_alu_m_alloc_temps(t);
2192 /* sign extend. */
2193 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2194 cris_cc_mask(dc, CC_MASK_NZVC);
2195 cris_alu(dc, CC_OP_ADD,
2196 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2197 do_postinc(dc, memsize);
2198 cris_alu_m_free_temps(t);
2199 return insn_len;
2200 }
2201
2202 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2203 {
2204 TCGv t[2];
2205 int memsize = memsize_z(dc);
2206 int insn_len;
2207 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2208 memsize_char(memsize),
2209 dc->op1, dc->postinc ? "+]" : "]",
2210 dc->op2);
2211
2212 cris_alu_m_alloc_temps(t);
2213 /* sign extend. */
2214 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2215 cris_cc_mask(dc, CC_MASK_NZVC);
2216 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2217 do_postinc(dc, memsize);
2218 cris_alu_m_free_temps(t);
2219 return insn_len;
2220 }
2221
2222 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2223 {
2224 TCGv t[2];
2225 int memsize = memsize_z(dc);
2226 int insn_len;
2227 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2228 memsize_char(memsize),
2229 dc->op1, dc->postinc ? "+]" : "]",
2230 dc->op2);
2231
2232 cris_alu_m_alloc_temps(t);
2233 /* sign extend. */
2234 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2235 cris_cc_mask(dc, CC_MASK_NZVC);
2236 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2237 do_postinc(dc, memsize);
2238 cris_alu_m_free_temps(t);
2239 return insn_len;
2240 }
2241
2242 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2243 {
2244 TCGv t[2];
2245 int memsize = memsize_z(dc);
2246 int insn_len;
2247 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2248 memsize_char(memsize),
2249 dc->op1, dc->postinc ? "+]" : "]",
2250 dc->op2);
2251
2252 cris_alu_m_alloc_temps(t);
2253 /* sign extend. */
2254 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2255 cris_cc_mask(dc, CC_MASK_NZVC);
2256 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2257 do_postinc(dc, memsize);
2258 cris_alu_m_free_temps(t);
2259 return insn_len;
2260 }
2261
2262 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2263 {
2264 TCGv t[2];
2265 int memsize = memsize_z(dc);
2266 int insn_len;
2267
2268 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2269 memsize_char(memsize),
2270 dc->op1, dc->postinc ? "+]" : "]",
2271 dc->op2);
2272
2273 cris_alu_m_alloc_temps(t);
2274 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2275 cris_cc_mask(dc, CC_MASK_NZ);
2276 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2277 do_postinc(dc, memsize);
2278 cris_alu_m_free_temps(t);
2279 return insn_len;
2280 }
2281
2282 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2283 {
2284 TCGv t[2];
2285 int memsize = memsize_z(dc);
2286 int insn_len;
2287 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2288 memsize_char(memsize),
2289 dc->op1, dc->postinc ? "+]" : "]",
2290 dc->op2);
2291
2292 cris_alu_m_alloc_temps(t);
2293 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2294 cris_cc_mask(dc, CC_MASK_NZVC);
2295 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2296 do_postinc(dc, memsize);
2297 cris_alu_m_free_temps(t);
2298 return insn_len;
2299 }
2300
2301 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2302 {
2303 TCGv t[2];
2304 int memsize = memsize_z(dc);
2305 int insn_len;
2306 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2307 memsize_char(memsize),
2308 dc->op1, dc->postinc ? "+]" : "]",
2309 dc->op2);
2310
2311 cris_alu_m_alloc_temps(t);
2312 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2313 cris_cc_mask(dc, CC_MASK_NZVC);
2314 cris_alu(dc, CC_OP_CMP,
2315 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2316 memsize_zz(dc));
2317 do_postinc(dc, memsize);
2318 cris_alu_m_free_temps(t);
2319 return insn_len;
2320 }
2321
2322 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2323 {
2324 TCGv t[2];
2325 int memsize = memsize_zz(dc);
2326 int insn_len;
2327 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2328 memsize_char(memsize),
2329 dc->op1, dc->postinc ? "+]" : "]",
2330 dc->op2);
2331
2332 cris_alu_m_alloc_temps(t);
2333 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2334 cris_cc_mask(dc, CC_MASK_NZVC);
2335 cris_alu(dc, CC_OP_CMP,
2336 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2337 memsize_zz(dc));
2338 do_postinc(dc, memsize);
2339 cris_alu_m_free_temps(t);
2340 return insn_len;
2341 }
2342
2343 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2344 {
2345 TCGv t[2];
2346 int memsize = memsize_zz(dc);
2347 int insn_len;
2348 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2349 memsize_char(memsize),
2350 dc->op1, dc->postinc ? "+]" : "]",
2351 dc->op2);
2352
2353 cris_evaluate_flags(dc);
2354
2355 cris_alu_m_alloc_temps(t);
2356 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2357 cris_cc_mask(dc, CC_MASK_NZ);
2358 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2359
2360 cris_alu(dc, CC_OP_CMP,
2361 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2362 do_postinc(dc, memsize);
2363 cris_alu_m_free_temps(t);
2364 return insn_len;
2365 }
2366
2367 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2368 {
2369 TCGv t[2];
2370 int memsize = memsize_zz(dc);
2371 int insn_len;
2372 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2373 memsize_char(memsize),
2374 dc->op1, dc->postinc ? "+]" : "]",
2375 dc->op2);
2376
2377 cris_alu_m_alloc_temps(t);
2378 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2379 cris_cc_mask(dc, CC_MASK_NZ);
2380 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2381 do_postinc(dc, memsize);
2382 cris_alu_m_free_temps(t);
2383 return insn_len;
2384 }
2385
2386 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2387 {
2388 TCGv t[2];
2389 int memsize = memsize_zz(dc);
2390 int insn_len;
2391 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2392 memsize_char(memsize),
2393 dc->op1, dc->postinc ? "+]" : "]",
2394 dc->op2);
2395
2396 cris_alu_m_alloc_temps(t);
2397 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2398 cris_cc_mask(dc, CC_MASK_NZVC);
2399 cris_alu(dc, CC_OP_ADD,
2400 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2401 do_postinc(dc, memsize);
2402 cris_alu_m_free_temps(t);
2403 return insn_len;
2404 }
2405
2406 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2407 {
2408 TCGv t[2];
2409 int memsize = memsize_zz(dc);
2410 int insn_len;
2411 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2412 memsize_char(memsize),
2413 dc->op1, dc->postinc ? "+]" : "]",
2414 dc->op2);
2415
2416 cris_alu_m_alloc_temps(t);
2417 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2418 cris_cc_mask(dc, 0);
2419 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2420 do_postinc(dc, memsize);
2421 cris_alu_m_free_temps(t);
2422 return insn_len;
2423 }
2424
2425 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2426 {
2427 TCGv l[2];
2428 int memsize = memsize_zz(dc);
2429 int insn_len;
2430 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2431 memsize_char(memsize),
2432 dc->op1, dc->postinc ? "+]" : "]",
2433 dc->op2);
2434
2435 l[0] = tcg_temp_local_new();
2436 l[1] = tcg_temp_local_new();
2437 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2438 cris_cc_mask(dc, CC_MASK_NZ);
2439 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2440 do_postinc(dc, memsize);
2441 tcg_temp_free(l[0]);
2442 tcg_temp_free(l[1]);
2443 return insn_len;
2444 }
2445
2446 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2447 {
2448 TCGv t[2];
2449 int insn_len = 2;
2450 LOG_DIS("addc [$r%u%s, $r%u\n",
2451 dc->op1, dc->postinc ? "+]" : "]",
2452 dc->op2);
2453
2454 cris_evaluate_flags(dc);
2455
2456 /* Set for this insn. */
2457 dc->flagx_known = 1;
2458 dc->flags_x = X_FLAG;
2459
2460 cris_alu_m_alloc_temps(t);
2461 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2462 cris_cc_mask(dc, CC_MASK_NZVC);
2463 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2464 do_postinc(dc, 4);
2465 cris_alu_m_free_temps(t);
2466 return insn_len;
2467 }
2468
2469 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2470 {
2471 TCGv t[2];
2472 int memsize = memsize_zz(dc);
2473 int insn_len;
2474 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2475 memsize_char(memsize),
2476 dc->op1, dc->postinc ? "+]" : "]",
2477 dc->op2, dc->ir, dc->zzsize);
2478
2479 cris_alu_m_alloc_temps(t);
2480 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2481 cris_cc_mask(dc, CC_MASK_NZVC);
2482 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2483 do_postinc(dc, memsize);
2484 cris_alu_m_free_temps(t);
2485 return insn_len;
2486 }
2487
2488 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2489 {
2490 TCGv t[2];
2491 int memsize = memsize_zz(dc);
2492 int insn_len;
2493 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2494 memsize_char(memsize),
2495 dc->op1, dc->postinc ? "+]" : "]",
2496 dc->op2, dc->pc);
2497
2498 cris_alu_m_alloc_temps(t);
2499 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2500 cris_cc_mask(dc, CC_MASK_NZ);
2501 cris_alu(dc, CC_OP_OR,
2502 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2503 do_postinc(dc, memsize);
2504 cris_alu_m_free_temps(t);
2505 return insn_len;
2506 }
2507
2508 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2509 {
2510 TCGv t[2];
2511 int memsize = memsize_zz(dc);
2512 int insn_len = 2;
2513
2514 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2515 memsize_char(memsize),
2516 dc->op1,
2517 dc->postinc ? "+]" : "]",
2518 dc->op2);
2519
2520 cris_alu_m_alloc_temps(t);
2521 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2522 cris_cc_mask(dc, 0);
2523 if (dc->op2 == PR_CCS) {
2524 cris_evaluate_flags(dc);
2525 if (dc->tb_flags & U_FLAG) {
2526 /* User space is not allowed to touch all flags. */
2527 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2528 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2529 tcg_gen_or_tl(t[1], t[0], t[1]);
2530 }
2531 }
2532
2533 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2534
2535 do_postinc(dc, memsize);
2536 cris_alu_m_free_temps(t);
2537 return insn_len;
2538 }
2539
2540 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2541 {
2542 TCGv t0;
2543 int memsize;
2544
2545 memsize = preg_sizes[dc->op2];
2546
2547 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2548 memsize_char(memsize),
2549 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2550
2551 /* prepare store. Address in T0, value in T1. */
2552 if (dc->op2 == PR_CCS) {
2553 cris_evaluate_flags(dc);
2554 }
2555 t0 = tcg_temp_new();
2556 t_gen_mov_TN_preg(t0, dc->op2);
2557 cris_flush_cc_state(dc);
2558 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2559 tcg_temp_free(t0);
2560
2561 cris_cc_mask(dc, 0);
2562 if (dc->postinc) {
2563 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2564 }
2565 return 2;
2566 }
2567
2568 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2569 {
2570 TCGv_i64 tmp[16];
2571 TCGv tmp32;
2572 TCGv addr;
2573 int i;
2574 int nr = dc->op2 + 1;
2575
2576 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2577 dc->postinc ? "+]" : "]", dc->op2);
2578
2579 addr = tcg_temp_new();
2580 /* There are probably better ways of doing this. */
2581 cris_flush_cc_state(dc);
2582 for (i = 0; i < (nr >> 1); i++) {
2583 tmp[i] = tcg_temp_new_i64();
2584 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2585 gen_load64(dc, tmp[i], addr);
2586 }
2587 if (nr & 1) {
2588 tmp32 = tcg_temp_new_i32();
2589 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2590 gen_load(dc, tmp32, addr, 4, 0);
2591 } else {
2592 TCGV_UNUSED(tmp32);
2593 }
2594 tcg_temp_free(addr);
2595
2596 for (i = 0; i < (nr >> 1); i++) {
2597 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
2598 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2599 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2600 tcg_temp_free_i64(tmp[i]);
2601 }
2602 if (nr & 1) {
2603 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2604 tcg_temp_free(tmp32);
2605 }
2606
2607 /* writeback the updated pointer value. */
2608 if (dc->postinc) {
2609 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2610 }
2611
2612 /* gen_load might want to evaluate the previous insns flags. */
2613 cris_cc_mask(dc, 0);
2614 return 2;
2615 }
2616
2617 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2618 {
2619 TCGv tmp;
2620 TCGv addr;
2621 int i;
2622
2623 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2624 dc->postinc ? "+]" : "]");
2625
2626 cris_flush_cc_state(dc);
2627
2628 tmp = tcg_temp_new();
2629 addr = tcg_temp_new();
2630 tcg_gen_movi_tl(tmp, 4);
2631 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2632 for (i = 0; i <= dc->op2; i++) {
2633 /* Displace addr. */
2634 /* Perform the store. */
2635 gen_store(dc, addr, cpu_R[i], 4);
2636 tcg_gen_add_tl(addr, addr, tmp);
2637 }
2638 if (dc->postinc) {
2639 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2640 }
2641 cris_cc_mask(dc, 0);
2642 tcg_temp_free(tmp);
2643 tcg_temp_free(addr);
2644 return 2;
2645 }
2646
2647 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2648 {
2649 int memsize;
2650
2651 memsize = memsize_zz(dc);
2652
2653 LOG_DIS("move.%c $r%u, [$r%u]\n",
2654 memsize_char(memsize), dc->op2, dc->op1);
2655
2656 /* prepare store. */
2657 cris_flush_cc_state(dc);
2658 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2659
2660 if (dc->postinc) {
2661 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2662 }
2663 cris_cc_mask(dc, 0);
2664 return 2;
2665 }
2666
2667 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2668 {
2669 LOG_DIS("lapcq %x, $r%u\n",
2670 dc->pc + dc->op1*2, dc->op2);
2671 cris_cc_mask(dc, 0);
2672 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2673 return 2;
2674 }
2675
2676 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2677 {
2678 unsigned int rd;
2679 int32_t imm;
2680 int32_t pc;
2681
2682 rd = dc->op2;
2683
2684 cris_cc_mask(dc, 0);
2685 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2686 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2687
2688 pc = dc->pc;
2689 pc += imm;
2690 tcg_gen_movi_tl(cpu_R[rd], pc);
2691 return 6;
2692 }
2693
2694 /* Jump to special reg. */
2695 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2696 {
2697 LOG_DIS("jump $p%u\n", dc->op2);
2698
2699 if (dc->op2 == PR_CCS) {
2700 cris_evaluate_flags(dc);
2701 }
2702 t_gen_mov_TN_preg(env_btarget, dc->op2);
2703 /* rete will often have low bit set to indicate delayslot. */
2704 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2705 cris_cc_mask(dc, 0);
2706 cris_prepare_jmp(dc, JMP_INDIRECT);
2707 return 2;
2708 }
2709
2710 /* Jump and save. */
2711 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2712 {
2713 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2714 cris_cc_mask(dc, 0);
2715 /* Store the return address in Pd. */
2716 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2717 if (dc->op2 > 15) {
2718 abort();
2719 }
2720 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2721
2722 cris_prepare_jmp(dc, JMP_INDIRECT);
2723 return 2;
2724 }
2725
2726 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2727 {
2728 uint32_t imm;
2729
2730 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2731
2732 LOG_DIS("jas 0x%x\n", imm);
2733 cris_cc_mask(dc, 0);
2734 /* Store the return address in Pd. */
2735 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2736
2737 dc->jmp_pc = imm;
2738 cris_prepare_jmp(dc, JMP_DIRECT);
2739 return 6;
2740 }
2741
2742 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2743 {
2744 uint32_t imm;
2745
2746 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2747
2748 LOG_DIS("jasc 0x%x\n", imm);
2749 cris_cc_mask(dc, 0);
2750 /* Store the return address in Pd. */
2751 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2752
2753 dc->jmp_pc = imm;
2754 cris_prepare_jmp(dc, JMP_DIRECT);
2755 return 6;
2756 }
2757
2758 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2759 {
2760 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2761 cris_cc_mask(dc, 0);
2762 /* Store the return address in Pd. */
2763 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2764 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2765 cris_prepare_jmp(dc, JMP_INDIRECT);
2766 return 2;
2767 }
2768
2769 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2770 {
2771 int32_t offset;
2772 uint32_t cond = dc->op2;
2773
2774 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2775
2776 LOG_DIS("b%s %d pc=%x dst=%x\n",
2777 cc_name(cond), offset,
2778 dc->pc, dc->pc + offset);
2779
2780 cris_cc_mask(dc, 0);
2781 /* op2 holds the condition-code. */
2782 cris_prepare_cc_branch(dc, offset, cond);
2783 return 4;
2784 }
2785
2786 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2787 {
2788 int32_t simm;
2789
2790 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2791
2792 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2793 cris_cc_mask(dc, 0);
2794 /* Store the return address in Pd. */
2795 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2796
2797 dc->jmp_pc = dc->pc + simm;
2798 cris_prepare_jmp(dc, JMP_DIRECT);
2799 return 6;
2800 }
2801
2802 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2803 {
2804 int32_t simm;
2805 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2806
2807 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2808 cris_cc_mask(dc, 0);
2809 /* Store the return address in Pd. */
2810 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2811
2812 dc->jmp_pc = dc->pc + simm;
2813 cris_prepare_jmp(dc, JMP_DIRECT);
2814 return 6;
2815 }
2816
2817 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2818 {
2819 cris_cc_mask(dc, 0);
2820
2821 if (dc->op2 == 15) {
2822 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2823 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2824 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2825 t_gen_raise_exception(EXCP_HLT);
2826 return 2;
2827 }
2828
2829 switch (dc->op2 & 7) {
2830 case 2:
2831 /* rfe. */
2832 LOG_DIS("rfe\n");
2833 cris_evaluate_flags(dc);
2834 gen_helper_rfe(cpu_env);
2835 dc->is_jmp = DISAS_UPDATE;
2836 break;
2837 case 5:
2838 /* rfn. */
2839 LOG_DIS("rfn\n");
2840 cris_evaluate_flags(dc);
2841 gen_helper_rfn(cpu_env);
2842 dc->is_jmp = DISAS_UPDATE;
2843 break;
2844 case 6:
2845 LOG_DIS("break %d\n", dc->op1);
2846 cris_evaluate_flags(dc);
2847 /* break. */
2848 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2849
2850 /* Breaks start at 16 in the exception vector. */
2851 t_gen_mov_env_TN(trap_vector,
2852 tcg_const_tl(dc->op1 + 16));
2853 t_gen_raise_exception(EXCP_BREAK);
2854 dc->is_jmp = DISAS_UPDATE;
2855 break;
2856 default:
2857 printf("op2=%x\n", dc->op2);
2858 BUG();
2859 break;
2860
2861 }
2862 return 2;
2863 }
2864
2865 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2866 {
2867 return 2;
2868 }
2869
2870 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2871 {
2872 return 2;
2873 }
2874
2875 static int dec_null(CPUCRISState *env, DisasContext *dc)
2876 {
2877 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2878 dc->pc, dc->opcode, dc->op1, dc->op2);
2879 fflush(NULL);
2880 BUG();
2881 return 2;
2882 }
2883
2884 static struct decoder_info {
2885 struct {
2886 uint32_t bits;
2887 uint32_t mask;
2888 };
2889 int (*dec)(CPUCRISState *env, DisasContext *dc);
2890 } decinfo[] = {
2891 /* Order matters here. */
2892 {DEC_MOVEQ, dec_moveq},
2893 {DEC_BTSTQ, dec_btstq},
2894 {DEC_CMPQ, dec_cmpq},
2895 {DEC_ADDOQ, dec_addoq},
2896 {DEC_ADDQ, dec_addq},
2897 {DEC_SUBQ, dec_subq},
2898 {DEC_ANDQ, dec_andq},
2899 {DEC_ORQ, dec_orq},
2900 {DEC_ASRQ, dec_asrq},
2901 {DEC_LSLQ, dec_lslq},
2902 {DEC_LSRQ, dec_lsrq},
2903 {DEC_BCCQ, dec_bccq},
2904
2905 {DEC_BCC_IM, dec_bcc_im},
2906 {DEC_JAS_IM, dec_jas_im},
2907 {DEC_JAS_R, dec_jas_r},
2908 {DEC_JASC_IM, dec_jasc_im},
2909 {DEC_JASC_R, dec_jasc_r},
2910 {DEC_BAS_IM, dec_bas_im},
2911 {DEC_BASC_IM, dec_basc_im},
2912 {DEC_JUMP_P, dec_jump_p},
2913 {DEC_LAPC_IM, dec_lapc_im},
2914 {DEC_LAPCQ, dec_lapcq},
2915
2916 {DEC_RFE_ETC, dec_rfe_etc},
2917 {DEC_ADDC_MR, dec_addc_mr},
2918
2919 {DEC_MOVE_MP, dec_move_mp},
2920 {DEC_MOVE_PM, dec_move_pm},
2921 {DEC_MOVEM_MR, dec_movem_mr},
2922 {DEC_MOVEM_RM, dec_movem_rm},
2923 {DEC_MOVE_PR, dec_move_pr},
2924 {DEC_SCC_R, dec_scc_r},
2925 {DEC_SETF, dec_setclrf},
2926 {DEC_CLEARF, dec_setclrf},
2927
2928 {DEC_MOVE_SR, dec_move_sr},
2929 {DEC_MOVE_RP, dec_move_rp},
2930 {DEC_SWAP_R, dec_swap_r},
2931 {DEC_ABS_R, dec_abs_r},
2932 {DEC_LZ_R, dec_lz_r},
2933 {DEC_MOVE_RS, dec_move_rs},
2934 {DEC_BTST_R, dec_btst_r},
2935 {DEC_ADDC_R, dec_addc_r},
2936
2937 {DEC_DSTEP_R, dec_dstep_r},
2938 {DEC_XOR_R, dec_xor_r},
2939 {DEC_MCP_R, dec_mcp_r},
2940 {DEC_CMP_R, dec_cmp_r},
2941
2942 {DEC_ADDI_R, dec_addi_r},
2943 {DEC_ADDI_ACR, dec_addi_acr},
2944
2945 {DEC_ADD_R, dec_add_r},
2946 {DEC_SUB_R, dec_sub_r},
2947
2948 {DEC_ADDU_R, dec_addu_r},
2949 {DEC_ADDS_R, dec_adds_r},
2950 {DEC_SUBU_R, dec_subu_r},
2951 {DEC_SUBS_R, dec_subs_r},
2952 {DEC_LSL_R, dec_lsl_r},
2953
2954 {DEC_AND_R, dec_and_r},
2955 {DEC_OR_R, dec_or_r},
2956 {DEC_BOUND_R, dec_bound_r},
2957 {DEC_ASR_R, dec_asr_r},
2958 {DEC_LSR_R, dec_lsr_r},
2959
2960 {DEC_MOVU_R, dec_movu_r},
2961 {DEC_MOVS_R, dec_movs_r},
2962 {DEC_NEG_R, dec_neg_r},
2963 {DEC_MOVE_R, dec_move_r},
2964
2965 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2966 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2967
2968 {DEC_MULS_R, dec_muls_r},
2969 {DEC_MULU_R, dec_mulu_r},
2970
2971 {DEC_ADDU_M, dec_addu_m},
2972 {DEC_ADDS_M, dec_adds_m},
2973 {DEC_SUBU_M, dec_subu_m},
2974 {DEC_SUBS_M, dec_subs_m},
2975
2976 {DEC_CMPU_M, dec_cmpu_m},
2977 {DEC_CMPS_M, dec_cmps_m},
2978 {DEC_MOVU_M, dec_movu_m},
2979 {DEC_MOVS_M, dec_movs_m},
2980
2981 {DEC_CMP_M, dec_cmp_m},
2982 {DEC_ADDO_M, dec_addo_m},
2983 {DEC_BOUND_M, dec_bound_m},
2984 {DEC_ADD_M, dec_add_m},
2985 {DEC_SUB_M, dec_sub_m},
2986 {DEC_AND_M, dec_and_m},
2987 {DEC_OR_M, dec_or_m},
2988 {DEC_MOVE_RM, dec_move_rm},
2989 {DEC_TEST_M, dec_test_m},
2990 {DEC_MOVE_MR, dec_move_mr},
2991
2992 {{0, 0}, dec_null}
2993 };
2994
2995 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
2996 {
2997 int insn_len = 2;
2998 int i;
2999
3000 /* Load a halfword onto the instruction register. */
3001 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3002
3003 /* Now decode it. */
3004 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3005 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3006 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3007 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3008 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3009 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3010
3011 /* Large switch for all insns. */
3012 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3013 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3014 insn_len = decinfo[i].dec(env, dc);
3015 break;
3016 }
3017 }
3018
3019 #if !defined(CONFIG_USER_ONLY)
3020 /* Single-stepping ? */
3021 if (dc->tb_flags & S_FLAG) {
3022 TCGLabel *l1 = gen_new_label();
3023 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3024 /* We treat SPC as a break with an odd trap vector. */
3025 cris_evaluate_flags(dc);
3026 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3027 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3028 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3029 t_gen_raise_exception(EXCP_BREAK);
3030 gen_set_label(l1);
3031 }
3032 #endif
3033 return insn_len;
3034 }
3035
3036 #include "translate_v10.c"
3037
3038 /*
3039 * Delay slots on QEMU/CRIS.
3040 *
3041 * If an exception hits on a delayslot, the core will let ERP (the Exception
3042 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3043 * to give SW a hint that the exception actually hit on the dslot.
3044 *
3045 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3046 * the core and any jmp to an odd addresses will mask off that lsb. It is
3047 * simply there to let sw know there was an exception on a dslot.
3048 *
3049 * When the software returns from an exception, the branch will re-execute.
3050 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3051 * and the branch and delayslot dont share pages.
3052 *
3053 * The TB contaning the branch insn will set up env->btarget and evaluate
3054 * env->btaken. When the translation loop exits we will note that the branch
3055 * sequence is broken and let env->dslot be the size of the branch insn (those
3056 * vary in length).
3057 *
3058 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3059 * set). It will also expect to have env->dslot setup with the size of the
3060 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3061 * will execute the dslot and take the branch, either to btarget or just one
3062 * insn ahead.
3063 *
3064 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3065 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3066 * branch and set lsb). Then env->dslot gets cleared so that the exception
3067 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3068 * masked off and we will reexecute the branch insn.
3069 *
3070 */
3071
3072 /* generate intermediate code for basic block 'tb'. */
3073 void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
3074 {
3075 CRISCPU *cpu = cris_env_get_cpu(env);
3076 CPUState *cs = CPU(cpu);
3077 uint32_t pc_start;
3078 unsigned int insn_len;
3079 struct DisasContext ctx;
3080 struct DisasContext *dc = &ctx;
3081 uint32_t next_page_start;
3082 target_ulong npc;
3083 int num_insns;
3084 int max_insns;
3085
3086 if (env->pregs[PR_VR] == 32) {
3087 dc->decoder = crisv32_decoder;
3088 dc->clear_locked_irq = 0;
3089 } else {
3090 dc->decoder = crisv10_decoder;
3091 dc->clear_locked_irq = 1;
3092 }
3093
3094 /* Odd PC indicates that branch is rexecuting due to exception in the
3095 * delayslot, like in real hw.
3096 */
3097 pc_start = tb->pc & ~1;
3098 dc->cpu = cpu;
3099 dc->tb = tb;
3100
3101 dc->is_jmp = DISAS_NEXT;
3102 dc->ppc = pc_start;
3103 dc->pc = pc_start;
3104 dc->singlestep_enabled = cs->singlestep_enabled;
3105 dc->flags_uptodate = 1;
3106 dc->flagx_known = 1;
3107 dc->flags_x = tb->flags & X_FLAG;
3108 dc->cc_x_uptodate = 0;
3109 dc->cc_mask = 0;
3110 dc->update_cc = 0;
3111 dc->clear_prefix = 0;
3112
3113 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3114 dc->cc_size_uptodate = -1;
3115
3116 /* Decode TB flags. */
3117 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3118 | X_FLAG | PFIX_FLAG);
3119 dc->delayed_branch = !!(tb->flags & 7);
3120 if (dc->delayed_branch) {
3121 dc->jmp = JMP_INDIRECT;
3122 } else {
3123 dc->jmp = JMP_NOJMP;
3124 }
3125
3126 dc->cpustate_changed = 0;
3127
3128 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3129 qemu_log(
3130 "pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3131 "pid=%x usp=%x\n"
3132 "%x.%x.%x.%x\n"
3133 "%x.%x.%x.%x\n"
3134 "%x.%x.%x.%x\n"
3135 "%x.%x.%x.%x\n",
3136 dc->pc, dc->ppc,
3137 (uint64_t)tb->flags,
3138 env->btarget, (unsigned)tb->flags & 7,
3139 env->pregs[PR_CCS],
3140 env->pregs[PR_PID], env->pregs[PR_USP],
3141 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3142 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3143 env->regs[8], env->regs[9],
3144 env->regs[10], env->regs[11],
3145 env->regs[12], env->regs[13],
3146 env->regs[14], env->regs[15]);
3147 qemu_log("--------------\n");
3148 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3149 }
3150
3151 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3152 num_insns = 0;
3153 max_insns = tb->cflags & CF_COUNT_MASK;
3154 if (max_insns == 0) {
3155 max_insns = CF_COUNT_MASK;
3156 }
3157 if (max_insns > TCG_MAX_INSNS) {
3158 max_insns = TCG_MAX_INSNS;
3159 }
3160
3161 gen_tb_start(tb);
3162 do {
3163 tcg_gen_insn_start(dc->delayed_branch == 1
3164 ? dc->ppc | 1 : dc->pc);
3165 num_insns++;
3166
3167 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3168 cris_evaluate_flags(dc);
3169 tcg_gen_movi_tl(env_pc, dc->pc);
3170 t_gen_raise_exception(EXCP_DEBUG);
3171 dc->is_jmp = DISAS_UPDATE;
3172 /* The address covered by the breakpoint must be included in
3173 [tb->pc, tb->pc + tb->size) in order to for it to be
3174 properly cleared -- thus we increment the PC here so that
3175 the logic setting tb->size below does the right thing. */
3176 dc->pc += 2;
3177 break;
3178 }
3179
3180 /* Pretty disas. */
3181 LOG_DIS("%8.8x:\t", dc->pc);
3182
3183 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3184 gen_io_start();
3185 }
3186 dc->clear_x = 1;
3187
3188 insn_len = dc->decoder(env, dc);
3189 dc->ppc = dc->pc;
3190 dc->pc += insn_len;
3191 if (dc->clear_x) {
3192 cris_clear_x_flag(dc);
3193 }
3194
3195 /* Check for delayed branches here. If we do it before
3196 actually generating any host code, the simulator will just
3197 loop doing nothing for on this program location. */
3198 if (dc->delayed_branch) {
3199 dc->delayed_branch--;
3200 if (dc->delayed_branch == 0) {
3201 if (tb->flags & 7) {
3202 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3203 }
3204 if (dc->cpustate_changed || !dc->flagx_known
3205 || (dc->flags_x != (tb->flags & X_FLAG))) {
3206 cris_store_direct_jmp(dc);
3207 }
3208
3209 if (dc->clear_locked_irq) {
3210 dc->clear_locked_irq = 0;
3211 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3212 }
3213
3214 if (dc->jmp == JMP_DIRECT_CC) {
3215 TCGLabel *l1 = gen_new_label();
3216 cris_evaluate_flags(dc);
3217
3218 /* Conditional jmp. */
3219 tcg_gen_brcondi_tl(TCG_COND_EQ,
3220 env_btaken, 0, l1);
3221 gen_goto_tb(dc, 1, dc->jmp_pc);
3222 gen_set_label(l1);
3223 gen_goto_tb(dc, 0, dc->pc);
3224 dc->is_jmp = DISAS_TB_JUMP;
3225 dc->jmp = JMP_NOJMP;
3226 } else if (dc->jmp == JMP_DIRECT) {
3227 cris_evaluate_flags(dc);
3228 gen_goto_tb(dc, 0, dc->jmp_pc);
3229 dc->is_jmp = DISAS_TB_JUMP;
3230 dc->jmp = JMP_NOJMP;
3231 } else {
3232 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3233 dc->is_jmp = DISAS_JUMP;
3234 }
3235 break;
3236 }
3237 }
3238
3239 /* If we are rexecuting a branch due to exceptions on
3240 delay slots dont break. */
3241 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3242 break;
3243 }
3244 } while (!dc->is_jmp && !dc->cpustate_changed
3245 && !tcg_op_buf_full()
3246 && !singlestep
3247 && (dc->pc < next_page_start)
3248 && num_insns < max_insns);
3249
3250 if (dc->clear_locked_irq) {
3251 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3252 }
3253
3254 npc = dc->pc;
3255
3256 if (tb->cflags & CF_LAST_IO)
3257 gen_io_end();
3258 /* Force an update if the per-tb cpu state has changed. */
3259 if (dc->is_jmp == DISAS_NEXT
3260 && (dc->cpustate_changed || !dc->flagx_known
3261 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3262 dc->is_jmp = DISAS_UPDATE;
3263 tcg_gen_movi_tl(env_pc, npc);
3264 }
3265 /* Broken branch+delayslot sequence. */
3266 if (dc->delayed_branch == 1) {
3267 /* Set env->dslot to the size of the branch insn. */
3268 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3269 cris_store_direct_jmp(dc);
3270 }
3271
3272 cris_evaluate_flags(dc);
3273
3274 if (unlikely(cs->singlestep_enabled)) {
3275 if (dc->is_jmp == DISAS_NEXT) {
3276 tcg_gen_movi_tl(env_pc, npc);
3277 }
3278 t_gen_raise_exception(EXCP_DEBUG);
3279 } else {
3280 switch (dc->is_jmp) {
3281 case DISAS_NEXT:
3282 gen_goto_tb(dc, 1, npc);
3283 break;
3284 default:
3285 case DISAS_JUMP:
3286 case DISAS_UPDATE:
3287 /* indicate that the hash table must be used
3288 to find the next TB */
3289 tcg_gen_exit_tb(0);
3290 break;
3291 case DISAS_SWI:
3292 case DISAS_TB_JUMP:
3293 /* nothing more to generate */
3294 break;
3295 }
3296 }
3297 gen_tb_end(tb, num_insns);
3298
3299 tb->size = dc->pc - pc_start;
3300 tb->icount = num_insns;
3301
3302 #ifdef DEBUG_DISAS
3303 #if !DISAS_CRIS
3304 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3305 log_target_disas(cs, pc_start, dc->pc - pc_start,
3306 env->pregs[PR_VR]);
3307 qemu_log("\nisize=%d osize=%d\n",
3308 dc->pc - pc_start, tcg_op_buf_count());
3309 }
3310 #endif
3311 #endif
3312 }
3313
3314 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3315 int flags)
3316 {
3317 CRISCPU *cpu = CRIS_CPU(cs);
3318 CPUCRISState *env = &cpu->env;
3319 int i;
3320 uint32_t srs;
3321
3322 if (!env || !f) {
3323 return;
3324 }
3325
3326 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3327 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3328 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3329 env->cc_op,
3330 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3331
3332
3333 for (i = 0; i < 16; i++) {
3334 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3335 if ((i + 1) % 4 == 0) {
3336 cpu_fprintf(f, "\n");
3337 }
3338 }
3339 cpu_fprintf(f, "\nspecial regs:\n");
3340 for (i = 0; i < 16; i++) {
3341 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3342 if ((i + 1) % 4 == 0) {
3343 cpu_fprintf(f, "\n");
3344 }
3345 }
3346 srs = env->pregs[PR_SRS];
3347 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3348 if (srs < ARRAY_SIZE(env->sregs)) {
3349 for (i = 0; i < 16; i++) {
3350 cpu_fprintf(f, "s%2.2d=%8.8x ",
3351 i, env->sregs[srs][i]);
3352 if ((i + 1) % 4 == 0) {
3353 cpu_fprintf(f, "\n");
3354 }
3355 }
3356 }
3357 cpu_fprintf(f, "\n\n");
3358
3359 }
3360
3361 void cris_initialize_tcg(void)
3362 {
3363 int i;
3364
3365 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3366 cc_x = tcg_global_mem_new(TCG_AREG0,
3367 offsetof(CPUCRISState, cc_x), "cc_x");
3368 cc_src = tcg_global_mem_new(TCG_AREG0,
3369 offsetof(CPUCRISState, cc_src), "cc_src");
3370 cc_dest = tcg_global_mem_new(TCG_AREG0,
3371 offsetof(CPUCRISState, cc_dest),
3372 "cc_dest");
3373 cc_result = tcg_global_mem_new(TCG_AREG0,
3374 offsetof(CPUCRISState, cc_result),
3375 "cc_result");
3376 cc_op = tcg_global_mem_new(TCG_AREG0,
3377 offsetof(CPUCRISState, cc_op), "cc_op");
3378 cc_size = tcg_global_mem_new(TCG_AREG0,
3379 offsetof(CPUCRISState, cc_size),
3380 "cc_size");
3381 cc_mask = tcg_global_mem_new(TCG_AREG0,
3382 offsetof(CPUCRISState, cc_mask),
3383 "cc_mask");
3384
3385 env_pc = tcg_global_mem_new(TCG_AREG0,
3386 offsetof(CPUCRISState, pc),
3387 "pc");
3388 env_btarget = tcg_global_mem_new(TCG_AREG0,
3389 offsetof(CPUCRISState, btarget),
3390 "btarget");
3391 env_btaken = tcg_global_mem_new(TCG_AREG0,
3392 offsetof(CPUCRISState, btaken),
3393 "btaken");
3394 for (i = 0; i < 16; i++) {
3395 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3396 offsetof(CPUCRISState, regs[i]),
3397 regnames[i]);
3398 }
3399 for (i = 0; i < 16; i++) {
3400 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3401 offsetof(CPUCRISState, pregs[i]),
3402 pregnames[i]);
3403 }
3404 }
3405
3406 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3407 target_ulong *data)
3408 {
3409 env->pc = data[0];
3410 }
AR7 emulation for QEMU