pc-bios/s390-ccw/s390-arch.h

   1 /*
   2  * S390 Basic Architecture
   3  *
   4  * Copyright (c) 2019 Jason J. Herne <jjherne@us.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   7  * your option) any later version. See the COPYING file in the top-level
   8  * directory.
   9  */
  10
  11 #ifndef S390_ARCH_H
  12 #define S390_ARCH_H
  13
  14 typedef struct PSW {
  15     uint64_t mask;
  16     uint64_t addr;
  17 } __attribute__ ((aligned(8))) PSW;
  18 _Static_assert(sizeof(struct PSW) == 16, "PSW size incorrect");
  19
  20 /* Older PSW format used by LPSW instruction */
  21 typedef struct PSWLegacy {
  22     uint32_t mask;
  23     uint32_t addr;
  24 } __attribute__ ((aligned(8))) PSWLegacy;
  25 _Static_assert(sizeof(struct PSWLegacy) == 8, "PSWLegacy size incorrect");
  26
  27 /* s390 psw bit masks */
  28 #define PSW_MASK_IOINT      0x0200000000000000ULL
  29 #define PSW_MASK_WAIT       0x0002000000000000ULL
  30 #define PSW_MASK_EAMODE     0x0000000100000000ULL
  31 #define PSW_MASK_BAMODE     0x0000000080000000ULL
  32 #define PSW_MASK_ZMODE      (PSW_MASK_EAMODE | PSW_MASK_BAMODE)
  33
  34 /* Low core mapping */
  35 typedef struct LowCore {
  36     /* prefix area: defined by architecture */
  37     PSWLegacy       ipl_psw;                  /* 0x000 */
  38     uint32_t        ccw1[2];                  /* 0x008 */
  39     union {
  40         uint32_t        ccw2[2];                  /* 0x010 */
  41         struct {
  42             uint32_t reserved10;
  43             uint32_t ptr_iplb;
  44         };
  45     };
  46     uint8_t         pad1[0x80 - 0x18];        /* 0x018 */
  47     uint32_t        ext_params;               /* 0x080 */
  48     uint16_t        cpu_addr;                 /* 0x084 */
  49     uint16_t        ext_int_code;             /* 0x086 */
  50     uint16_t        svc_ilen;                 /* 0x088 */
  51     uint16_t        svc_code;                 /* 0x08a */
  52     uint16_t        pgm_ilen;                 /* 0x08c */
  53     uint16_t        pgm_code;                 /* 0x08e */
  54     uint32_t        data_exc_code;            /* 0x090 */
  55     uint16_t        mon_class_num;            /* 0x094 */
  56     uint16_t        per_perc_atmid;           /* 0x096 */
  57     uint64_t        per_address;              /* 0x098 */
  58     uint8_t         exc_access_id;            /* 0x0a0 */
  59     uint8_t         per_access_id;            /* 0x0a1 */
  60     uint8_t         op_access_id;             /* 0x0a2 */
  61     uint8_t         ar_access_id;             /* 0x0a3 */
  62     uint8_t         pad2[0xA8 - 0xA4];        /* 0x0a4 */
  63     uint64_t        trans_exc_code;           /* 0x0a8 */
  64     uint64_t        monitor_code;             /* 0x0b0 */
  65     uint16_t        subchannel_id;            /* 0x0b8 */
  66     uint16_t        subchannel_nr;            /* 0x0ba */
  67     uint32_t        io_int_parm;              /* 0x0bc */
  68     uint32_t        io_int_word;              /* 0x0c0 */
  69     uint8_t         pad3[0xc8 - 0xc4];        /* 0x0c4 */
  70     uint32_t        stfl_fac_list;            /* 0x0c8 */
  71     uint8_t         pad4[0xe8 - 0xcc];        /* 0x0cc */
  72     uint64_t        mcic;                     /* 0x0e8 */
  73     uint8_t         pad5[0xf4 - 0xf0];        /* 0x0f0 */
  74     uint32_t        external_damage_code;     /* 0x0f4 */
  75     uint64_t        failing_storage_address;  /* 0x0f8 */
  76     uint8_t         pad6[0x110 - 0x100];      /* 0x100 */
  77     uint64_t        per_breaking_event_addr;  /* 0x110 */
  78     uint8_t         pad7[0x120 - 0x118];      /* 0x118 */
  79     PSW             restart_old_psw;          /* 0x120 */
  80     PSW             external_old_psw;         /* 0x130 */
  81     PSW             svc_old_psw;              /* 0x140 */
  82     PSW             program_old_psw;          /* 0x150 */
  83     PSW             mcck_old_psw;             /* 0x160 */
  84     PSW             io_old_psw;               /* 0x170 */
  85     uint8_t         pad8[0x1a0 - 0x180];      /* 0x180 */
  86     PSW             restart_new_psw;          /* 0x1a0 */
  87     PSW             external_new_psw;         /* 0x1b0 */
  88     PSW             svc_new_psw;              /* 0x1c0 */
  89     PSW             program_new_psw;          /* 0x1d0 */
  90     PSW             mcck_new_psw;             /* 0x1e0 */
  91     PSW             io_new_psw;               /* 0x1f0 */
  92 } __attribute__((packed, aligned(8192))) LowCore;
  93
  94 extern LowCore *lowcore;
  95
  96 static inline void set_prefix(uint32_t address)
  97 {
  98     asm volatile("spx %0" : : "m" (address) : "memory");
  99 }
 100
 101 static inline uint32_t store_prefix(void)
 102 {
 103     uint32_t address;
 104
 105     asm volatile("stpx %0" : "=m" (address));
 106     return address;
 107 }
 108
 109 #endif