hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129 };
 130
 131 #define TYPE_PCI_DEVICE "pci-device"
 132 #define PCI_DEVICE(obj) \
 133      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 134 #define PCI_DEVICE_CLASS(klass) \
 135      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 136 #define PCI_DEVICE_GET_CLASS(obj) \
 137      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 138
 139 typedef struct PCIDeviceClass {
 140     DeviceClass parent_class;
 141
 142     int (*init)(PCIDevice *dev);
 143     PCIUnregisterFunc *exit;
 144     PCIConfigReadFunc *config_read;
 145     PCIConfigWriteFunc *config_write;
 146
 147     uint16_t vendor_id;
 148     uint16_t device_id;
 149     uint8_t revision;
 150     uint16_t class_id;
 151     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 152     uint16_t subsystem_id;              /* only for header type = 0 */
 153
 154     /*
 155      * pci-to-pci bridge or normal device.
 156      * This doesn't mean pci host switch.
 157      * When card bus bridge is supported, this would be enhanced.
 158      */
 159     int is_bridge;
 160
 161     /* pcie stuff */
 162     int is_express;   /* is this device pci express? */
 163
 164     /* device isn't hot-pluggable */
 165     int no_hotplug;
 166
 167     /* rom bar */
 168     const char *romfile;
 169 } PCIDeviceClass;
 170
 171 struct PCIDevice {
 172     DeviceState qdev;
 173     /* PCI config space */
 174     uint8_t *config;
 175
 176     /* Used to enable config checks on load. Note that writable bits are
 177      * never checked even if set in cmask. */
 178     uint8_t *cmask;
 179
 180     /* Used to implement R/W bytes */
 181     uint8_t *wmask;
 182
 183     /* Used to implement RW1C(Write 1 to Clear) bytes */
 184     uint8_t *w1cmask;
 185
 186     /* Used to allocate config space for capabilities. */
 187     uint8_t *used;
 188
 189     /* the following fields are read only */
 190     PCIBus *bus;
 191     uint32_t devfn;
 192     char name[64];
 193     PCIIORegion io_regions[PCI_NUM_REGIONS];
 194
 195     /* do not access the following fields */
 196     PCIConfigReadFunc *config_read;
 197     PCIConfigWriteFunc *config_write;
 198
 199     /* IRQ objects for the INTA-INTD pins.  */
 200     qemu_irq *irq;
 201
 202     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 203     uint8_t irq_state;
 204
 205     /* Capability bits */
 206     uint32_t cap_present;
 207
 208     /* Offset of MSI-X capability in config space */
 209     uint8_t msix_cap;
 210
 211     /* MSI-X entries */
 212     int msix_entries_nr;
 213
 214     /* Space to store MSIX table */
 215     uint8_t *msix_table_page;
 216     /* MMIO index used to map MSIX table and pending bit entries. */
 217     MemoryRegion msix_mmio;
 218     /* Reference-count for entries actually in use by driver. */
 219     unsigned *msix_entry_used;
 220     /* Region including the MSI-X table */
 221     uint32_t msix_bar_size;
 222     /* MSIX function mask set or MSIX disabled */
 223     bool msix_function_masked;
 224     /* Version id needed for VMState */
 225     int32_t version_id;
 226
 227     /* Offset of MSI capability in config space */
 228     uint8_t msi_cap;
 229
 230     /* PCI Express */
 231     PCIExpressDevice exp;
 232
 233     /* Location of option rom */
 234     char *romfile;
 235     bool has_rom;
 236     MemoryRegion rom;
 237     uint32_t rom_bar;
 238 };
 239
 240 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 241                       uint8_t attr, MemoryRegion *memory);
 242 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 243
 244 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 245                        uint8_t offset, uint8_t size);
 246
 247 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 248
 249 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 250
 251
 252 uint32_t pci_default_read_config(PCIDevice *d,
 253                                  uint32_t address, int len);
 254 void pci_default_write_config(PCIDevice *d,
 255                               uint32_t address, uint32_t val, int len);
 256 void pci_device_save(PCIDevice *s, QEMUFile *f);
 257 int pci_device_load(PCIDevice *s, QEMUFile *f);
 258 MemoryRegion *pci_address_space(PCIDevice *dev);
 259 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 260
 261 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 262 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 263
 264 typedef enum {
 265     PCI_HOTPLUG_DISABLED,
 266     PCI_HOTPLUG_ENABLED,
 267     PCI_COLDPLUG_ENABLED,
 268 } PCIHotplugState;
 269
 270 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 271                               PCIHotplugState state);
 272 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 273                          const char *name,
 274                          MemoryRegion *address_space_mem,
 275                          MemoryRegion *address_space_io,
 276                          uint8_t devfn_min);
 277 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 278                     MemoryRegion *address_space_mem,
 279                     MemoryRegion *address_space_io,
 280                     uint8_t devfn_min);
 281 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 282                   void *irq_opaque, int nirq);
 283 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 284 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 285 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 286                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 287                          void *irq_opaque,
 288                          MemoryRegion *address_space_mem,
 289                          MemoryRegion *address_space_io,
 290                          uint8_t devfn_min, int nirq);
 291 void pci_device_reset(PCIDevice *dev);
 292 void pci_bus_reset(PCIBus *bus);
 293
 294 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 295                         const char *default_devaddr);
 296 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 297                                const char *default_devaddr);
 298 int pci_bus_num(PCIBus *s);
 299 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 300 PCIBus *pci_find_root_bus(int domain);
 301 int pci_find_domain(const PCIBus *bus);
 302 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 303 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 304 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 305 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 306
 307 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 308                       unsigned int *slotp, unsigned int *funcp);
 309 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 310                      unsigned *slotp);
 311
 312 void pci_device_deassert_intx(PCIDevice *dev);
 313
 314 static inline void
 315 pci_set_byte(uint8_t *config, uint8_t val)
 316 {
 317     *config = val;
 318 }
 319
 320 static inline uint8_t
 321 pci_get_byte(const uint8_t *config)
 322 {
 323     return *config;
 324 }
 325
 326 static inline void
 327 pci_set_word(uint8_t *config, uint16_t val)
 328 {
 329     cpu_to_le16wu((uint16_t *)config, val);
 330 }
 331
 332 static inline uint16_t
 333 pci_get_word(const uint8_t *config)
 334 {
 335     return le16_to_cpupu((const uint16_t *)config);
 336 }
 337
 338 static inline void
 339 pci_set_long(uint8_t *config, uint32_t val)
 340 {
 341     cpu_to_le32wu((uint32_t *)config, val);
 342 }
 343
 344 static inline uint32_t
 345 pci_get_long(const uint8_t *config)
 346 {
 347     return le32_to_cpupu((const uint32_t *)config);
 348 }
 349
 350 static inline void
 351 pci_set_quad(uint8_t *config, uint64_t val)
 352 {
 353     cpu_to_le64w((uint64_t *)config, val);
 354 }
 355
 356 static inline uint64_t
 357 pci_get_quad(const uint8_t *config)
 358 {
 359     return le64_to_cpup((const uint64_t *)config);
 360 }
 361
 362 static inline void
 363 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 364 {
 365     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 366 }
 367
 368 static inline void
 369 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 370 {
 371     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 372 }
 373
 374 static inline void
 375 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 376 {
 377     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 378 }
 379
 380 static inline void
 381 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 382 {
 383     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 384 }
 385
 386 static inline void
 387 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 388 {
 389     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 390 }
 391
 392 static inline void
 393 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 394 {
 395     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 396 }
 397
 398 /*
 399  * helper functions to do bit mask operation on configuration space.
 400  * Just to set bit, use test-and-set and discard returned value.
 401  * Just to clear bit, use test-and-clear and discard returned value.
 402  * NOTE: They aren't atomic.
 403  */
 404 static inline uint8_t
 405 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 406 {
 407     uint8_t val = pci_get_byte(config);
 408     pci_set_byte(config, val & ~mask);
 409     return val & mask;
 410 }
 411
 412 static inline uint8_t
 413 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 414 {
 415     uint8_t val = pci_get_byte(config);
 416     pci_set_byte(config, val | mask);
 417     return val & mask;
 418 }
 419
 420 static inline uint16_t
 421 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 422 {
 423     uint16_t val = pci_get_word(config);
 424     pci_set_word(config, val & ~mask);
 425     return val & mask;
 426 }
 427
 428 static inline uint16_t
 429 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 430 {
 431     uint16_t val = pci_get_word(config);
 432     pci_set_word(config, val | mask);
 433     return val & mask;
 434 }
 435
 436 static inline uint32_t
 437 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 438 {
 439     uint32_t val = pci_get_long(config);
 440     pci_set_long(config, val & ~mask);
 441     return val & mask;
 442 }
 443
 444 static inline uint32_t
 445 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 446 {
 447     uint32_t val = pci_get_long(config);
 448     pci_set_long(config, val | mask);
 449     return val & mask;
 450 }
 451
 452 static inline uint64_t
 453 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 454 {
 455     uint64_t val = pci_get_quad(config);
 456     pci_set_quad(config, val & ~mask);
 457     return val & mask;
 458 }
 459
 460 static inline uint64_t
 461 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 462 {
 463     uint64_t val = pci_get_quad(config);
 464     pci_set_quad(config, val | mask);
 465     return val & mask;
 466 }
 467
 468 /* Access a register specified by a mask */
 469 static inline void
 470 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 471 {
 472     uint8_t val = pci_get_byte(config);
 473     uint8_t rval = reg << (ffs(mask) - 1);
 474     pci_set_byte(config, (~mask & val) | (mask & rval));
 475 }
 476
 477 static inline uint8_t
 478 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 479 {
 480     uint8_t val = pci_get_byte(config);
 481     return (val & mask) >> (ffs(mask) - 1);
 482 }
 483
 484 static inline void
 485 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 486 {
 487     uint16_t val = pci_get_word(config);
 488     uint16_t rval = reg << (ffs(mask) - 1);
 489     pci_set_word(config, (~mask & val) | (mask & rval));
 490 }
 491
 492 static inline uint16_t
 493 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 494 {
 495     uint16_t val = pci_get_word(config);
 496     return (val & mask) >> (ffs(mask) - 1);
 497 }
 498
 499 static inline void
 500 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 501 {
 502     uint32_t val = pci_get_long(config);
 503     uint32_t rval = reg << (ffs(mask) - 1);
 504     pci_set_long(config, (~mask & val) | (mask & rval));
 505 }
 506
 507 static inline uint32_t
 508 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 509 {
 510     uint32_t val = pci_get_long(config);
 511     return (val & mask) >> (ffs(mask) - 1);
 512 }
 513
 514 static inline void
 515 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 516 {
 517     uint64_t val = pci_get_quad(config);
 518     uint64_t rval = reg << (ffs(mask) - 1);
 519     pci_set_quad(config, (~mask & val) | (mask & rval));
 520 }
 521
 522 static inline uint64_t
 523 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 524 {
 525     uint64_t val = pci_get_quad(config);
 526     return (val & mask) >> (ffs(mask) - 1);
 527 }
 528
 529 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 530                                     const char *name);
 531 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 532                                            bool multifunction,
 533                                            const char *name);
 534 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 535 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 536
 537 static inline int pci_is_express(const PCIDevice *d)
 538 {
 539     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 540 }
 541
 542 static inline uint32_t pci_config_size(const PCIDevice *d)
 543 {
 544     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 545 }
 546
 547 /* DMA access functions */
 548 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 549                              void *buf, dma_addr_t len, DMADirection dir)
 550 {
 551     cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
 552     return 0;
 553 }
 554
 555 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 556                                void *buf, dma_addr_t len)
 557 {
 558     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 559 }
 560
 561 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 562                                 const void *buf, dma_addr_t len)
 563 {
 564     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 565 }
 566
 567 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 568     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 569                                                    dma_addr_t addr)     \
 570     {                                                                   \
 571         return ld##_l##_phys(addr);                                     \
 572     }                                                                   \
 573     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 574                           dma_addr_t addr, uint##_bits##_t val)         \
 575     {                                                                   \
 576         st##_s##_phys(addr, val);                                       \
 577     }
 578
 579 PCI_DMA_DEFINE_LDST(ub, b, 8);
 580 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 581 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 582 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 583 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 584 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 585 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 586
 587 #undef PCI_DMA_DEFINE_LDST
 588
 589 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 590                                 dma_addr_t *plen, DMADirection dir)
 591 {
 592     target_phys_addr_t len = *plen;
 593     void *buf;
 594
 595     buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
 596     *plen = len;
 597     return buf;
 598 }
 599
 600 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 601                                  DMADirection dir, dma_addr_t access_len)
 602 {
 603     cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
 604                               access_len);
 605 }
 606
 607 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 608                                        int alloc_hint)
 609 {
 610     qemu_sglist_init(qsg, alloc_hint);
 611 }
 612
 613 extern const VMStateDescription vmstate_pci_device;
 614
 615 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 616     .name       = (stringify(_field)),                               \
 617     .size       = sizeof(PCIDevice),                                 \
 618     .vmsd       = &vmstate_pci_device,                               \
 619     .flags      = VMS_STRUCT,                                        \
 620     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 621 }
 622
 623 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 624     .name       = (stringify(_field)),                               \
 625     .size       = sizeof(PCIDevice),                                 \
 626     .vmsd       = &vmstate_pci_device,                               \
 627     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 628     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 629 }
 630
 631 #endif