target/arm: NS BusFault on vector table fetch escalates to NS HardFault
[qemu/ar7.git] / hw / misc / macio / macio.c
blob82492096f81ae22244ac38f1eb925aa41e67a592
1 /*
2 * PowerMac MacIO device emulation
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "qemu/module.h"
29 #include "hw/hw.h"
30 #include "hw/ppc/mac.h"
31 #include "hw/misc/macio/cuda.h"
32 #include "hw/pci/pci.h"
33 #include "hw/ppc/mac_dbdma.h"
34 #include "hw/char/escc.h"
35 #include "hw/misc/macio/macio.h"
36 #include "hw/intc/heathrow_pic.h"
37 #include "trace.h"
39 /* Note: this code is strongly inspirated from the corresponding code
40 * in PearPC */
43 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
44 * while the other one is the normal, current ESCC interface.
46 * The magic below creates memory aliases to spawn the escc-legacy device
47 * purely by rerouting the respective registers to our escc region. This
48 * works because the only difference between the two memory regions is the
49 * register layout, not their semantics.
51 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
53 static void macio_escc_legacy_setup(MacIOState *s)
55 ESCCState *escc = ESCC(&s->escc);
56 SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
57 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
58 MemoryRegion *bar = &s->bar;
59 int i;
60 static const int maps[] = {
61 0x00, 0x00, /* Command B */
62 0x02, 0x20, /* Command A */
63 0x04, 0x10, /* Data B */
64 0x06, 0x30, /* Data A */
65 0x08, 0x40, /* Enhancement B */
66 0x0A, 0x50, /* Enhancement A */
67 0x80, 0x80, /* Recovery count */
68 0x90, 0x90, /* Start A */
69 0xa0, 0xa0, /* Start B */
70 0xb0, 0xb0, /* Detect AB */
73 memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256);
74 for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
75 MemoryRegion *port = g_new(MemoryRegion, 1);
76 memory_region_init_alias(port, OBJECT(s), "escc-legacy-port",
77 sysbus_mmio_get_region(sbd, 0),
78 maps[i + 1], 0x2);
79 memory_region_add_subregion(escc_legacy, maps[i], port);
82 memory_region_add_subregion(bar, 0x12000, escc_legacy);
85 static void macio_bar_setup(MacIOState *s)
87 ESCCState *escc = ESCC(&s->escc);
88 SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
89 MemoryRegion *bar = &s->bar;
91 memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0));
92 macio_escc_legacy_setup(s);
95 static void macio_init_child_obj(MacIOState *s, const char *childname,
96 void *child, size_t childsize,
97 const char *childtype)
99 object_initialize_child(OBJECT(s), childname, child, childsize, childtype,
100 &error_abort, NULL);
101 qdev_set_parent_bus(DEVICE(child), BUS(&s->macio_bus));
104 static void macio_common_realize(PCIDevice *d, Error **errp)
106 MacIOState *s = MACIO(d);
107 SysBusDevice *sysbus_dev;
108 Error *err = NULL;
110 object_property_set_bool(OBJECT(&s->dbdma), true, "realized", &err);
111 if (err) {
112 error_propagate(errp, err);
113 return;
115 sysbus_dev = SYS_BUS_DEVICE(&s->dbdma);
116 memory_region_add_subregion(&s->bar, 0x08000,
117 sysbus_mmio_get_region(sysbus_dev, 0));
119 qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
120 qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
121 qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4);
122 qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hd(0));
123 qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1));
124 qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
125 qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
126 object_property_set_bool(OBJECT(&s->escc), true, "realized", &err);
127 if (err) {
128 error_propagate(errp, err);
129 return;
132 macio_bar_setup(s);
133 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
136 static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
137 qemu_irq irq0, qemu_irq irq1, int dmaid,
138 Error **errp)
140 SysBusDevice *sysbus_dev;
142 sysbus_dev = SYS_BUS_DEVICE(ide);
143 sysbus_connect_irq(sysbus_dev, 0, irq0);
144 sysbus_connect_irq(sysbus_dev, 1, irq1);
145 qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
146 object_property_set_link(OBJECT(ide), OBJECT(&s->dbdma), "dbdma", errp);
147 macio_ide_register_dma(ide);
149 object_property_set_bool(OBJECT(ide), true, "realized", errp);
152 static void macio_oldworld_realize(PCIDevice *d, Error **errp)
154 MacIOState *s = MACIO(d);
155 OldWorldMacIOState *os = OLDWORLD_MACIO(d);
156 DeviceState *pic_dev = DEVICE(os->pic);
157 Error *err = NULL;
158 SysBusDevice *sysbus_dev;
160 macio_common_realize(d, &err);
161 if (err) {
162 error_propagate(errp, err);
163 return;
166 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
167 s->frequency);
168 object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
169 if (err) {
170 error_propagate(errp, err);
171 return;
173 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
174 memory_region_add_subregion(&s->bar, 0x16000,
175 sysbus_mmio_get_region(sysbus_dev, 0));
176 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
177 OLDWORLD_CUDA_IRQ));
179 sysbus_dev = SYS_BUS_DEVICE(&s->escc);
180 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
181 OLDWORLD_ESCCB_IRQ));
182 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
183 OLDWORLD_ESCCA_IRQ));
185 object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
186 if (err) {
187 error_propagate(errp, err);
188 return;
190 sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
191 memory_region_add_subregion(&s->bar, 0x60000,
192 sysbus_mmio_get_region(sysbus_dev, 0));
193 pmac_format_nvram_partition(&os->nvram, os->nvram.size);
195 /* Heathrow PIC */
196 sysbus_dev = SYS_BUS_DEVICE(os->pic);
197 memory_region_add_subregion(&s->bar, 0x0,
198 sysbus_mmio_get_region(sysbus_dev, 0));
200 /* IDE buses */
201 macio_realize_ide(s, &os->ide[0],
202 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
203 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),
204 0x16, &err);
205 if (err) {
206 error_propagate(errp, err);
207 return;
210 macio_realize_ide(s, &os->ide[1],
211 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),
212 qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),
213 0x1a, &err);
214 if (err) {
215 error_propagate(errp, err);
216 return;
220 static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size,
221 int index)
223 gchar *name = g_strdup_printf("ide[%i]", index);
224 uint32_t addr = 0x1f000 + ((index + 1) * 0x1000);
226 macio_init_child_obj(s, name, ide, ide_size, TYPE_MACIO_IDE);
227 qdev_prop_set_uint32(DEVICE(ide), "addr", addr);
228 memory_region_add_subregion(&s->bar, addr, &ide->mem);
229 g_free(name);
232 static void macio_oldworld_init(Object *obj)
234 MacIOState *s = MACIO(obj);
235 OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
236 DeviceState *dev;
237 int i;
239 object_property_add_link(obj, "pic", TYPE_HEATHROW,
240 (Object **) &os->pic,
241 qdev_prop_allow_set_link_before_realize,
242 0, NULL);
244 macio_init_child_obj(s, "cuda", &s->cuda, sizeof(s->cuda), TYPE_CUDA);
246 object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
247 dev = DEVICE(&os->nvram);
248 qdev_prop_set_uint32(dev, "size", 0x2000);
249 qdev_prop_set_uint32(dev, "it_shift", 4);
251 for (i = 0; i < 2; i++) {
252 macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
256 static void timer_write(void *opaque, hwaddr addr, uint64_t value,
257 unsigned size)
259 trace_macio_timer_write(addr, size, value);
262 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
264 uint32_t value = 0;
265 uint64_t systime = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
266 uint64_t kltime;
268 kltime = muldiv64(systime, 4194300, NANOSECONDS_PER_SECOND * 4);
269 kltime = muldiv64(kltime, 18432000, 1048575);
271 switch (addr) {
272 case 0x38:
273 value = kltime;
274 break;
275 case 0x3c:
276 value = kltime >> 32;
277 break;
280 trace_macio_timer_read(addr, size, value);
281 return value;
284 static const MemoryRegionOps timer_ops = {
285 .read = timer_read,
286 .write = timer_write,
287 .endianness = DEVICE_LITTLE_ENDIAN,
290 static void macio_newworld_realize(PCIDevice *d, Error **errp)
292 MacIOState *s = MACIO(d);
293 NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
294 DeviceState *pic_dev = DEVICE(ns->pic);
295 Error *err = NULL;
296 SysBusDevice *sysbus_dev;
297 MemoryRegion *timer_memory = NULL;
299 macio_common_realize(d, &err);
300 if (err) {
301 error_propagate(errp, err);
302 return;
305 sysbus_dev = SYS_BUS_DEVICE(&s->escc);
306 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
307 NEWWORLD_ESCCB_IRQ));
308 sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
309 NEWWORLD_ESCCA_IRQ));
311 /* OpenPIC */
312 sysbus_dev = SYS_BUS_DEVICE(ns->pic);
313 memory_region_add_subregion(&s->bar, 0x40000,
314 sysbus_mmio_get_region(sysbus_dev, 0));
316 /* IDE buses */
317 macio_realize_ide(s, &ns->ide[0],
318 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ),
319 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ),
320 0x16, &err);
321 if (err) {
322 error_propagate(errp, err);
323 return;
326 macio_realize_ide(s, &ns->ide[1],
327 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ),
328 qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ),
329 0x1a, &err);
330 if (err) {
331 error_propagate(errp, err);
332 return;
335 /* Timer */
336 timer_memory = g_new(MemoryRegion, 1);
337 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
338 0x1000);
339 memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
341 if (ns->has_pmu) {
342 /* GPIOs */
343 sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
344 object_property_set_link(OBJECT(&ns->gpio), OBJECT(pic_dev), "pic",
345 &error_abort);
346 memory_region_add_subregion(&s->bar, 0x50,
347 sysbus_mmio_get_region(sysbus_dev, 0));
348 object_property_set_bool(OBJECT(&ns->gpio), true, "realized", &err);
350 /* PMU */
351 object_initialize_child(OBJECT(s), "pmu", &s->pmu, sizeof(s->pmu),
352 TYPE_VIA_PMU, &error_abort, NULL);
353 object_property_set_link(OBJECT(&s->pmu), OBJECT(sysbus_dev), "gpio",
354 &error_abort);
355 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
356 qdev_set_parent_bus(DEVICE(&s->pmu), BUS(&s->macio_bus));
358 object_property_set_bool(OBJECT(&s->pmu), true, "realized", &err);
359 if (err) {
360 error_propagate(errp, err);
361 return;
363 sysbus_dev = SYS_BUS_DEVICE(&s->pmu);
364 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
365 NEWWORLD_PMU_IRQ));
366 memory_region_add_subregion(&s->bar, 0x16000,
367 sysbus_mmio_get_region(sysbus_dev, 0));
368 } else {
369 /* CUDA */
370 object_initialize_child(OBJECT(s), "cuda", &s->cuda, sizeof(s->cuda),
371 TYPE_CUDA, &error_abort, NULL);
372 qdev_set_parent_bus(DEVICE(&s->cuda), BUS(&s->macio_bus));
373 qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
374 s->frequency);
376 object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err);
377 if (err) {
378 error_propagate(errp, err);
379 return;
381 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
382 sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
383 NEWWORLD_CUDA_IRQ));
384 memory_region_add_subregion(&s->bar, 0x16000,
385 sysbus_mmio_get_region(sysbus_dev, 0));
389 static void macio_newworld_init(Object *obj)
391 MacIOState *s = MACIO(obj);
392 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
393 int i;
395 object_property_add_link(obj, "pic", TYPE_OPENPIC,
396 (Object **) &ns->pic,
397 qdev_prop_allow_set_link_before_realize,
398 0, NULL);
400 macio_init_child_obj(s, "gpio", &ns->gpio, sizeof(ns->gpio),
401 TYPE_MACIO_GPIO);
403 for (i = 0; i < 2; i++) {
404 macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
408 static void macio_instance_init(Object *obj)
410 MacIOState *s = MACIO(obj);
412 memory_region_init(&s->bar, obj, "macio", 0x80000);
414 qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
415 DEVICE(obj), "macio.0");
417 macio_init_child_obj(s, "dbdma", &s->dbdma, sizeof(s->dbdma),
418 TYPE_MAC_DBDMA);
420 macio_init_child_obj(s, "escc", &s->escc, sizeof(s->escc), TYPE_ESCC);
423 static const VMStateDescription vmstate_macio_oldworld = {
424 .name = "macio-oldworld",
425 .version_id = 0,
426 .minimum_version_id = 0,
427 .fields = (VMStateField[]) {
428 VMSTATE_PCI_DEVICE(parent_obj.parent, OldWorldMacIOState),
429 VMSTATE_END_OF_LIST()
433 static void macio_oldworld_class_init(ObjectClass *oc, void *data)
435 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
436 DeviceClass *dc = DEVICE_CLASS(oc);
438 pdc->realize = macio_oldworld_realize;
439 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
440 dc->vmsd = &vmstate_macio_oldworld;
443 static const VMStateDescription vmstate_macio_newworld = {
444 .name = "macio-newworld",
445 .version_id = 0,
446 .minimum_version_id = 0,
447 .fields = (VMStateField[]) {
448 VMSTATE_PCI_DEVICE(parent_obj.parent, NewWorldMacIOState),
449 VMSTATE_END_OF_LIST()
453 static Property macio_newworld_properties[] = {
454 DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false),
455 DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false),
456 DEFINE_PROP_END_OF_LIST()
459 static void macio_newworld_class_init(ObjectClass *oc, void *data)
461 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
462 DeviceClass *dc = DEVICE_CLASS(oc);
464 pdc->realize = macio_newworld_realize;
465 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
466 dc->vmsd = &vmstate_macio_newworld;
467 dc->props = macio_newworld_properties;
470 static Property macio_properties[] = {
471 DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0),
472 DEFINE_PROP_END_OF_LIST()
475 static void macio_class_init(ObjectClass *klass, void *data)
477 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
478 DeviceClass *dc = DEVICE_CLASS(klass);
480 k->vendor_id = PCI_VENDOR_ID_APPLE;
481 k->class_id = PCI_CLASS_OTHERS << 8;
482 dc->props = macio_properties;
483 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
484 /* Reason: Uses serial_hds in macio_instance_init */
485 dc->user_creatable = false;
488 static const TypeInfo macio_bus_info = {
489 .name = TYPE_MACIO_BUS,
490 .parent = TYPE_BUS,
491 .instance_size = sizeof(MacIOBusState),
494 static const TypeInfo macio_oldworld_type_info = {
495 .name = TYPE_OLDWORLD_MACIO,
496 .parent = TYPE_MACIO,
497 .instance_size = sizeof(OldWorldMacIOState),
498 .instance_init = macio_oldworld_init,
499 .class_init = macio_oldworld_class_init,
502 static const TypeInfo macio_newworld_type_info = {
503 .name = TYPE_NEWWORLD_MACIO,
504 .parent = TYPE_MACIO,
505 .instance_size = sizeof(NewWorldMacIOState),
506 .instance_init = macio_newworld_init,
507 .class_init = macio_newworld_class_init,
510 static const TypeInfo macio_type_info = {
511 .name = TYPE_MACIO,
512 .parent = TYPE_PCI_DEVICE,
513 .instance_size = sizeof(MacIOState),
514 .instance_init = macio_instance_init,
515 .abstract = true,
516 .class_init = macio_class_init,
517 .interfaces = (InterfaceInfo[]) {
518 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
519 { },
523 static void macio_register_types(void)
525 type_register_static(&macio_bus_info);
526 type_register_static(&macio_type_info);
527 type_register_static(&macio_oldworld_type_info);
528 type_register_static(&macio_newworld_type_info);
531 type_init(macio_register_types)