2 * ARM SSE-200 Message Handling Unit (MHU)
4 * Copyright (c) 2019 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * This is a model of the Message Handling Unit (MHU) which is part of the
14 * Arm SSE-200 and documented in
15 * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
18 #include "qemu/osdep.h"
20 #include "qemu/module.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "hw/sysbus.h"
25 #include "hw/registerfields.h"
26 #include "hw/misc/armsse-mhu.h"
28 REG32(CPU0INTR_STAT
, 0x0)
29 REG32(CPU0INTR_SET
, 0x4)
30 REG32(CPU0INTR_CLR
, 0x8)
31 REG32(CPU1INTR_STAT
, 0x10)
32 REG32(CPU1INTR_SET
, 0x14)
33 REG32(CPU1INTR_CLR
, 0x18)
47 /* Valid bits in the interrupt registers. If any are set the IRQ is raised */
51 static const int armsse_mhu_id
[] = {
52 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
53 0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
54 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
57 static void armsse_mhu_update(ARMSSEMHU
*s
)
59 qemu_set_irq(s
->cpu0irq
, s
->cpu0intr
!= 0);
60 qemu_set_irq(s
->cpu1irq
, s
->cpu1intr
!= 0);
63 static uint64_t armsse_mhu_read(void *opaque
, hwaddr offset
, unsigned size
)
65 ARMSSEMHU
*s
= ARMSSE_MHU(opaque
);
77 case A_PID4
... A_CID3
:
78 r
= armsse_mhu_id
[(offset
- A_PID4
) / 4];
85 qemu_log_mask(LOG_GUEST_ERROR
,
86 "SSE MHU: read of write-only register at offset 0x%x\n",
92 qemu_log_mask(LOG_GUEST_ERROR
,
93 "SSE MHU read: bad offset 0x%x\n", (int)offset
);
97 trace_armsse_mhu_read(offset
, r
, size
);
101 static void armsse_mhu_write(void *opaque
, hwaddr offset
,
102 uint64_t value
, unsigned size
)
104 ARMSSEMHU
*s
= ARMSSE_MHU(opaque
);
106 trace_armsse_mhu_write(offset
, value
, size
);
110 s
->cpu0intr
|= (value
& INTR_MASK
);
113 s
->cpu0intr
&= ~(value
& INTR_MASK
);
116 s
->cpu1intr
|= (value
& INTR_MASK
);
119 s
->cpu1intr
&= ~(value
& INTR_MASK
);
122 case A_CPU0INTR_STAT
:
123 case A_CPU1INTR_STAT
:
124 case A_PID4
... A_CID3
:
125 qemu_log_mask(LOG_GUEST_ERROR
,
126 "SSE MHU: write to read-only register at offset 0x%x\n",
131 qemu_log_mask(LOG_GUEST_ERROR
,
132 "SSE MHU write: bad offset 0x%x\n", (int)offset
);
136 armsse_mhu_update(s
);
139 static const MemoryRegionOps armsse_mhu_ops
= {
140 .read
= armsse_mhu_read
,
141 .write
= armsse_mhu_write
,
142 .endianness
= DEVICE_LITTLE_ENDIAN
,
143 .valid
.min_access_size
= 4,
144 .valid
.max_access_size
= 4,
147 static void armsse_mhu_reset(DeviceState
*dev
)
149 ARMSSEMHU
*s
= ARMSSE_MHU(dev
);
155 static const VMStateDescription armsse_mhu_vmstate
= {
156 .name
= "armsse-mhu",
158 .minimum_version_id
= 1,
159 .fields
= (VMStateField
[]) {
160 VMSTATE_UINT32(cpu0intr
, ARMSSEMHU
),
161 VMSTATE_UINT32(cpu1intr
, ARMSSEMHU
),
162 VMSTATE_END_OF_LIST()
166 static void armsse_mhu_init(Object
*obj
)
168 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
169 ARMSSEMHU
*s
= ARMSSE_MHU(obj
);
171 memory_region_init_io(&s
->iomem
, obj
, &armsse_mhu_ops
,
172 s
, "armsse-mhu", 0x1000);
173 sysbus_init_mmio(sbd
, &s
->iomem
);
174 sysbus_init_irq(sbd
, &s
->cpu0irq
);
175 sysbus_init_irq(sbd
, &s
->cpu1irq
);
178 static void armsse_mhu_class_init(ObjectClass
*klass
, void *data
)
180 DeviceClass
*dc
= DEVICE_CLASS(klass
);
182 dc
->reset
= armsse_mhu_reset
;
183 dc
->vmsd
= &armsse_mhu_vmstate
;
186 static const TypeInfo armsse_mhu_info
= {
187 .name
= TYPE_ARMSSE_MHU
,
188 .parent
= TYPE_SYS_BUS_DEVICE
,
189 .instance_size
= sizeof(ARMSSEMHU
),
190 .instance_init
= armsse_mhu_init
,
191 .class_init
= armsse_mhu_class_init
,
194 static void armsse_mhu_register_types(void)
196 type_register_static(&armsse_mhu_info
);
199 type_init(armsse_mhu_register_types
);