2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "sysemu/cpus.h"
35 #include "hw/block/fdc.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/pci_bus.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/timer/hpet.h"
41 #include "hw/firmware/smbios.h"
42 #include "hw/loader.h"
44 #include "multiboot.h"
45 #include "hw/timer/mc146818rtc.h"
46 #include "hw/dma/i8257.h"
47 #include "hw/timer/i8254.h"
48 #include "hw/input/i8042.h"
49 #include "hw/audio/pcspk.h"
50 #include "hw/pci/msi.h"
51 #include "hw/sysbus.h"
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "sysemu/numa.h"
55 #include "sysemu/kvm.h"
56 #include "sysemu/qtest.h"
58 #include "hw/xen/xen.h"
59 #include "hw/xen/start_info.h"
60 #include "ui/qemu-spice.h"
61 #include "exec/memory.h"
62 #include "exec/address-spaces.h"
63 #include "sysemu/arch_init.h"
64 #include "qemu/bitmap.h"
65 #include "qemu/config-file.h"
66 #include "qemu/error-report.h"
67 #include "qemu/option.h"
68 #include "hw/acpi/acpi.h"
69 #include "hw/acpi/cpu_hotplug.h"
70 #include "hw/boards.h"
71 #include "acpi-build.h"
72 #include "hw/mem/pc-dimm.h"
73 #include "qapi/error.h"
74 #include "qapi/qapi-visit-common.h"
75 #include "qapi/visitor.h"
79 #include "hw/i386/intel_iommu.h"
80 #include "hw/net/ne2000-isa.h"
81 #include "standard-headers/asm-x86/bootparam.h"
82 #include "hw/virtio/virtio-pmem-pci.h"
83 #include "hw/mem/memory-device.h"
84 #include "sysemu/replay.h"
85 #include "qapi/qmp/qerror.h"
87 /* debug PC/ISA interrupts */
91 #define DPRINTF(fmt, ...) \
92 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
94 #define DPRINTF(fmt, ...)
97 #define E820_NR_ENTRIES 16
103 } QEMU_PACKED
__attribute((__aligned__(4)));
107 struct e820_entry entry
[E820_NR_ENTRIES
];
108 } QEMU_PACKED
__attribute((__aligned__(4)));
110 static struct e820_table e820_reserve
;
111 static struct e820_entry
*e820_table
;
112 static unsigned e820_entries
;
113 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
115 /* Physical Address of PVH entry point read from kernel ELF NOTE */
116 static size_t pvh_start_addr
;
118 GlobalProperty pc_compat_4_0
[] = {};
119 const size_t pc_compat_4_0_len
= G_N_ELEMENTS(pc_compat_4_0
);
121 GlobalProperty pc_compat_3_1
[] = {
122 { "intel-iommu", "dma-drain", "off" },
123 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "off" },
124 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "off" },
125 { "Opteron_G4" "-" TYPE_X86_CPU
, "npt", "off" },
126 { "Opteron_G4" "-" TYPE_X86_CPU
, "nrip-save", "off" },
127 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "off" },
128 { "Opteron_G5" "-" TYPE_X86_CPU
, "npt", "off" },
129 { "Opteron_G5" "-" TYPE_X86_CPU
, "nrip-save", "off" },
130 { "EPYC" "-" TYPE_X86_CPU
, "npt", "off" },
131 { "EPYC" "-" TYPE_X86_CPU
, "nrip-save", "off" },
132 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "npt", "off" },
133 { "EPYC-IBPB" "-" TYPE_X86_CPU
, "nrip-save", "off" },
134 { "Skylake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
135 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
136 { "Skylake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
137 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "mpx", "on" },
138 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
139 { "Icelake-Client" "-" TYPE_X86_CPU
, "mpx", "on" },
140 { "Icelake-Server" "-" TYPE_X86_CPU
, "mpx", "on" },
141 { "Cascadelake-Server" "-" TYPE_X86_CPU
, "stepping", "5" },
142 { TYPE_X86_CPU
, "x-intel-pt-auto-level", "off" },
144 const size_t pc_compat_3_1_len
= G_N_ELEMENTS(pc_compat_3_1
);
146 GlobalProperty pc_compat_3_0
[] = {
147 { TYPE_X86_CPU
, "x-hv-synic-kvm-only", "on" },
148 { "Skylake-Server" "-" TYPE_X86_CPU
, "pku", "off" },
149 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU
, "pku", "off" },
151 const size_t pc_compat_3_0_len
= G_N_ELEMENTS(pc_compat_3_0
);
153 GlobalProperty pc_compat_2_12
[] = {
154 { TYPE_X86_CPU
, "legacy-cache", "on" },
155 { TYPE_X86_CPU
, "topoext", "off" },
156 { "EPYC-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
157 { "EPYC-IBPB-" TYPE_X86_CPU
, "xlevel", "0x8000000a" },
159 const size_t pc_compat_2_12_len
= G_N_ELEMENTS(pc_compat_2_12
);
161 GlobalProperty pc_compat_2_11
[] = {
162 { TYPE_X86_CPU
, "x-migrate-smi-count", "off" },
163 { "Skylake-Server" "-" TYPE_X86_CPU
, "clflushopt", "off" },
165 const size_t pc_compat_2_11_len
= G_N_ELEMENTS(pc_compat_2_11
);
167 GlobalProperty pc_compat_2_10
[] = {
168 { TYPE_X86_CPU
, "x-hv-max-vps", "0x40" },
169 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
170 { "q35-pcihost", "x-pci-hole64-fix", "off" },
172 const size_t pc_compat_2_10_len
= G_N_ELEMENTS(pc_compat_2_10
);
174 GlobalProperty pc_compat_2_9
[] = {
175 { "mch", "extended-tseg-mbytes", "0" },
177 const size_t pc_compat_2_9_len
= G_N_ELEMENTS(pc_compat_2_9
);
179 GlobalProperty pc_compat_2_8
[] = {
180 { TYPE_X86_CPU
, "tcg-cpuid", "off" },
181 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
182 { "ICH9-LPC", "x-smi-broadcast", "off" },
183 { TYPE_X86_CPU
, "vmware-cpuid-freq", "off" },
184 { "Haswell-" TYPE_X86_CPU
, "stepping", "1" },
186 const size_t pc_compat_2_8_len
= G_N_ELEMENTS(pc_compat_2_8
);
188 GlobalProperty pc_compat_2_7
[] = {
189 { TYPE_X86_CPU
, "l3-cache", "off" },
190 { TYPE_X86_CPU
, "full-cpuid-auto-level", "off" },
191 { "Opteron_G3" "-" TYPE_X86_CPU
, "family", "15" },
192 { "Opteron_G3" "-" TYPE_X86_CPU
, "model", "6" },
193 { "Opteron_G3" "-" TYPE_X86_CPU
, "stepping", "1" },
194 { "isa-pcspk", "migrate", "off" },
196 const size_t pc_compat_2_7_len
= G_N_ELEMENTS(pc_compat_2_7
);
198 GlobalProperty pc_compat_2_6
[] = {
199 { TYPE_X86_CPU
, "cpuid-0xb", "off" },
200 { "vmxnet3", "romfile", "" },
201 { TYPE_X86_CPU
, "fill-mtrr-mask", "off" },
202 { "apic-common", "legacy-instance-id", "on", }
204 const size_t pc_compat_2_6_len
= G_N_ELEMENTS(pc_compat_2_6
);
206 GlobalProperty pc_compat_2_5
[] = {};
207 const size_t pc_compat_2_5_len
= G_N_ELEMENTS(pc_compat_2_5
);
209 GlobalProperty pc_compat_2_4
[] = {
210 PC_CPU_MODEL_IDS("2.4.0")
211 { "Haswell-" TYPE_X86_CPU
, "abm", "off" },
212 { "Haswell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
213 { "Broadwell-" TYPE_X86_CPU
, "abm", "off" },
214 { "Broadwell-noTSX-" TYPE_X86_CPU
, "abm", "off" },
215 { "host" "-" TYPE_X86_CPU
, "host-cache-info", "on" },
216 { TYPE_X86_CPU
, "check", "off" },
217 { "qemu64" "-" TYPE_X86_CPU
, "sse4a", "on" },
218 { "qemu64" "-" TYPE_X86_CPU
, "abm", "on" },
219 { "qemu64" "-" TYPE_X86_CPU
, "popcnt", "on" },
220 { "qemu32" "-" TYPE_X86_CPU
, "popcnt", "on" },
221 { "Opteron_G2" "-" TYPE_X86_CPU
, "rdtscp", "on" },
222 { "Opteron_G3" "-" TYPE_X86_CPU
, "rdtscp", "on" },
223 { "Opteron_G4" "-" TYPE_X86_CPU
, "rdtscp", "on" },
224 { "Opteron_G5" "-" TYPE_X86_CPU
, "rdtscp", "on", }
226 const size_t pc_compat_2_4_len
= G_N_ELEMENTS(pc_compat_2_4
);
228 GlobalProperty pc_compat_2_3
[] = {
229 PC_CPU_MODEL_IDS("2.3.0")
230 { TYPE_X86_CPU
, "arat", "off" },
231 { "qemu64" "-" TYPE_X86_CPU
, "min-level", "4" },
232 { "kvm64" "-" TYPE_X86_CPU
, "min-level", "5" },
233 { "pentium3" "-" TYPE_X86_CPU
, "min-level", "2" },
234 { "n270" "-" TYPE_X86_CPU
, "min-level", "5" },
235 { "Conroe" "-" TYPE_X86_CPU
, "min-level", "4" },
236 { "Penryn" "-" TYPE_X86_CPU
, "min-level", "4" },
237 { "Nehalem" "-" TYPE_X86_CPU
, "min-level", "4" },
238 { "n270" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
239 { "Penryn" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
240 { "Conroe" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
241 { "Nehalem" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
242 { "Westmere" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
243 { "SandyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
244 { "IvyBridge" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
245 { "Haswell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
246 { "Haswell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
247 { "Broadwell" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
248 { "Broadwell-noTSX" "-" TYPE_X86_CPU
, "min-xlevel", "0x8000000a" },
249 { TYPE_X86_CPU
, "kvm-no-smi-migration", "on" },
251 const size_t pc_compat_2_3_len
= G_N_ELEMENTS(pc_compat_2_3
);
253 GlobalProperty pc_compat_2_2
[] = {
254 PC_CPU_MODEL_IDS("2.2.0")
255 { "kvm64" "-" TYPE_X86_CPU
, "vme", "off" },
256 { "kvm32" "-" TYPE_X86_CPU
, "vme", "off" },
257 { "Conroe" "-" TYPE_X86_CPU
, "vme", "off" },
258 { "Penryn" "-" TYPE_X86_CPU
, "vme", "off" },
259 { "Nehalem" "-" TYPE_X86_CPU
, "vme", "off" },
260 { "Westmere" "-" TYPE_X86_CPU
, "vme", "off" },
261 { "SandyBridge" "-" TYPE_X86_CPU
, "vme", "off" },
262 { "Haswell" "-" TYPE_X86_CPU
, "vme", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU
, "vme", "off" },
264 { "Opteron_G1" "-" TYPE_X86_CPU
, "vme", "off" },
265 { "Opteron_G2" "-" TYPE_X86_CPU
, "vme", "off" },
266 { "Opteron_G3" "-" TYPE_X86_CPU
, "vme", "off" },
267 { "Opteron_G4" "-" TYPE_X86_CPU
, "vme", "off" },
268 { "Opteron_G5" "-" TYPE_X86_CPU
, "vme", "off" },
269 { "Haswell" "-" TYPE_X86_CPU
, "f16c", "off" },
270 { "Haswell" "-" TYPE_X86_CPU
, "rdrand", "off" },
271 { "Broadwell" "-" TYPE_X86_CPU
, "f16c", "off" },
272 { "Broadwell" "-" TYPE_X86_CPU
, "rdrand", "off" },
274 const size_t pc_compat_2_2_len
= G_N_ELEMENTS(pc_compat_2_2
);
276 GlobalProperty pc_compat_2_1
[] = {
277 PC_CPU_MODEL_IDS("2.1.0")
278 { "coreduo" "-" TYPE_X86_CPU
, "vmx", "on" },
279 { "core2duo" "-" TYPE_X86_CPU
, "vmx", "on" },
281 const size_t pc_compat_2_1_len
= G_N_ELEMENTS(pc_compat_2_1
);
283 GlobalProperty pc_compat_2_0
[] = {
284 PC_CPU_MODEL_IDS("2.0.0")
285 { "virtio-scsi-pci", "any_layout", "off" },
286 { "PIIX4_PM", "memory-hotplug-support", "off" },
287 { "apic", "version", "0x11" },
288 { "nec-usb-xhci", "superspeed-ports-first", "off" },
289 { "nec-usb-xhci", "force-pcie-endcap", "on" },
290 { "pci-serial", "prog_if", "0" },
291 { "pci-serial-2x", "prog_if", "0" },
292 { "pci-serial-4x", "prog_if", "0" },
293 { "virtio-net-pci", "guest_announce", "off" },
294 { "ICH9-LPC", "memory-hotplug-support", "off" },
295 { "xio3130-downstream", COMPAT_PROP_PCP
, "off" },
296 { "ioh3420", COMPAT_PROP_PCP
, "off" },
298 const size_t pc_compat_2_0_len
= G_N_ELEMENTS(pc_compat_2_0
);
300 GlobalProperty pc_compat_1_7
[] = {
301 PC_CPU_MODEL_IDS("1.7.0")
302 { TYPE_USB_DEVICE
, "msos-desc", "no" },
303 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
304 { "hpet", HPET_INTCAP
, "4" },
306 const size_t pc_compat_1_7_len
= G_N_ELEMENTS(pc_compat_1_7
);
308 GlobalProperty pc_compat_1_6
[] = {
309 PC_CPU_MODEL_IDS("1.6.0")
310 { "e1000", "mitigation", "off" },
311 { "qemu64-" TYPE_X86_CPU
, "model", "2" },
312 { "qemu32-" TYPE_X86_CPU
, "model", "3" },
313 { "i440FX-pcihost", "short_root_bus", "1" },
314 { "q35-pcihost", "short_root_bus", "1" },
316 const size_t pc_compat_1_6_len
= G_N_ELEMENTS(pc_compat_1_6
);
318 GlobalProperty pc_compat_1_5
[] = {
319 PC_CPU_MODEL_IDS("1.5.0")
320 { "Conroe-" TYPE_X86_CPU
, "model", "2" },
321 { "Conroe-" TYPE_X86_CPU
, "min-level", "2" },
322 { "Penryn-" TYPE_X86_CPU
, "model", "2" },
323 { "Penryn-" TYPE_X86_CPU
, "min-level", "2" },
324 { "Nehalem-" TYPE_X86_CPU
, "model", "2" },
325 { "Nehalem-" TYPE_X86_CPU
, "min-level", "2" },
326 { "virtio-net-pci", "any_layout", "off" },
327 { TYPE_X86_CPU
, "pmu", "on" },
328 { "i440FX-pcihost", "short_root_bus", "0" },
329 { "q35-pcihost", "short_root_bus", "0" },
331 const size_t pc_compat_1_5_len
= G_N_ELEMENTS(pc_compat_1_5
);
333 GlobalProperty pc_compat_1_4
[] = {
334 PC_CPU_MODEL_IDS("1.4.0")
335 { "scsi-hd", "discard_granularity", "0" },
336 { "scsi-cd", "discard_granularity", "0" },
337 { "scsi-disk", "discard_granularity", "0" },
338 { "ide-hd", "discard_granularity", "0" },
339 { "ide-cd", "discard_granularity", "0" },
340 { "ide-drive", "discard_granularity", "0" },
341 { "virtio-blk-pci", "discard_granularity", "0" },
342 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
343 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
344 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
345 { "e1000", "romfile", "pxe-e1000.rom" },
346 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
347 { "pcnet", "romfile", "pxe-pcnet.rom" },
348 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
349 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
350 { "486-" TYPE_X86_CPU
, "model", "0" },
351 { "n270" "-" TYPE_X86_CPU
, "movbe", "off" },
352 { "Westmere" "-" TYPE_X86_CPU
, "pclmulqdq", "off" },
354 const size_t pc_compat_1_4_len
= G_N_ELEMENTS(pc_compat_1_4
);
356 void gsi_handler(void *opaque
, int n
, int level
)
358 GSIState
*s
= opaque
;
360 DPRINTF("pc: %s GSI %d\n", level
? "raising" : "lowering", n
);
361 if (n
< ISA_NUM_IRQS
) {
362 qemu_set_irq(s
->i8259_irq
[n
], level
);
364 qemu_set_irq(s
->ioapic_irq
[n
], level
);
367 static void ioport80_write(void *opaque
, hwaddr addr
, uint64_t data
,
372 static uint64_t ioport80_read(void *opaque
, hwaddr addr
, unsigned size
)
374 return 0xffffffffffffffffULL
;
377 /* MSDOS compatibility mode FPU exception support */
378 static qemu_irq ferr_irq
;
380 void pc_register_ferr_irq(qemu_irq irq
)
385 /* XXX: add IGNNE support */
386 void cpu_set_ferr(CPUX86State
*s
)
388 qemu_irq_raise(ferr_irq
);
391 static void ioportF0_write(void *opaque
, hwaddr addr
, uint64_t data
,
394 qemu_irq_lower(ferr_irq
);
397 static uint64_t ioportF0_read(void *opaque
, hwaddr addr
, unsigned size
)
399 return 0xffffffffffffffffULL
;
403 uint64_t cpu_get_tsc(CPUX86State
*env
)
405 return cpu_get_ticks();
409 int cpu_get_pic_interrupt(CPUX86State
*env
)
411 X86CPU
*cpu
= env_archcpu(env
);
414 if (!kvm_irqchip_in_kernel()) {
415 intno
= apic_get_interrupt(cpu
->apic_state
);
419 /* read the irq from the PIC */
420 if (!apic_accept_pic_intr(cpu
->apic_state
)) {
425 intno
= pic_read_irq(isa_pic
);
429 static void pic_irq_request(void *opaque
, int irq
, int level
)
431 CPUState
*cs
= first_cpu
;
432 X86CPU
*cpu
= X86_CPU(cs
);
434 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
435 if (cpu
->apic_state
&& !kvm_irqchip_in_kernel()) {
438 if (apic_accept_pic_intr(cpu
->apic_state
)) {
439 apic_deliver_pic_intr(cpu
->apic_state
, level
);
444 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
446 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
451 /* PC cmos mappings */
453 #define REG_EQUIPMENT_BYTE 0x14
455 int cmos_get_fd_drive_type(FloppyDriveType fd0
)
460 case FLOPPY_DRIVE_TYPE_144
:
461 /* 1.44 Mb 3"5 drive */
464 case FLOPPY_DRIVE_TYPE_288
:
465 /* 2.88 Mb 3"5 drive */
468 case FLOPPY_DRIVE_TYPE_120
:
469 /* 1.2 Mb 5"5 drive */
472 case FLOPPY_DRIVE_TYPE_NONE
:
480 static void cmos_init_hd(ISADevice
*s
, int type_ofs
, int info_ofs
,
481 int16_t cylinders
, int8_t heads
, int8_t sectors
)
483 rtc_set_memory(s
, type_ofs
, 47);
484 rtc_set_memory(s
, info_ofs
, cylinders
);
485 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
486 rtc_set_memory(s
, info_ofs
+ 2, heads
);
487 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
488 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
489 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
490 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
491 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
492 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
495 /* convert boot_device letter to something recognizable by the bios */
496 static int boot_device2nibble(char boot_device
)
498 switch(boot_device
) {
501 return 0x01; /* floppy boot */
503 return 0x02; /* hard drive boot */
505 return 0x03; /* CD-ROM boot */
507 return 0x04; /* Network boot */
512 static void set_boot_dev(ISADevice
*s
, const char *boot_device
, Error
**errp
)
514 #define PC_MAX_BOOT_DEVICES 3
515 int nbds
, bds
[3] = { 0, };
518 nbds
= strlen(boot_device
);
519 if (nbds
> PC_MAX_BOOT_DEVICES
) {
520 error_setg(errp
, "Too many boot devices for PC");
523 for (i
= 0; i
< nbds
; i
++) {
524 bds
[i
] = boot_device2nibble(boot_device
[i
]);
526 error_setg(errp
, "Invalid boot device for PC: '%c'",
531 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
532 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
535 static void pc_boot_set(void *opaque
, const char *boot_device
, Error
**errp
)
537 set_boot_dev(opaque
, boot_device
, errp
);
540 static void pc_cmos_init_floppy(ISADevice
*rtc_state
, ISADevice
*floppy
)
543 FloppyDriveType fd_type
[2] = { FLOPPY_DRIVE_TYPE_NONE
,
544 FLOPPY_DRIVE_TYPE_NONE
};
548 for (i
= 0; i
< 2; i
++) {
549 fd_type
[i
] = isa_fdc_get_drive_type(floppy
, i
);
552 val
= (cmos_get_fd_drive_type(fd_type
[0]) << 4) |
553 cmos_get_fd_drive_type(fd_type
[1]);
554 rtc_set_memory(rtc_state
, 0x10, val
);
556 val
= rtc_get_memory(rtc_state
, REG_EQUIPMENT_BYTE
);
558 if (fd_type
[0] != FLOPPY_DRIVE_TYPE_NONE
) {
561 if (fd_type
[1] != FLOPPY_DRIVE_TYPE_NONE
) {
568 val
|= 0x01; /* 1 drive, ready for boot */
571 val
|= 0x41; /* 2 drives, ready for boot */
574 rtc_set_memory(rtc_state
, REG_EQUIPMENT_BYTE
, val
);
577 typedef struct pc_cmos_init_late_arg
{
578 ISADevice
*rtc_state
;
580 } pc_cmos_init_late_arg
;
582 typedef struct check_fdc_state
{
587 static int check_fdc(Object
*obj
, void *opaque
)
589 CheckFdcState
*state
= opaque
;
592 Error
*local_err
= NULL
;
594 fdc
= object_dynamic_cast(obj
, TYPE_ISA_FDC
);
599 iobase
= object_property_get_uint(obj
, "iobase", &local_err
);
600 if (local_err
|| iobase
!= 0x3f0) {
601 error_free(local_err
);
606 state
->multiple
= true;
608 state
->floppy
= ISA_DEVICE(obj
);
613 static const char * const fdc_container_path
[] = {
614 "/unattached", "/peripheral", "/peripheral-anon"
618 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
621 ISADevice
*pc_find_fdc0(void)
625 CheckFdcState state
= { 0 };
627 for (i
= 0; i
< ARRAY_SIZE(fdc_container_path
); i
++) {
628 container
= container_get(qdev_get_machine(), fdc_container_path
[i
]);
629 object_child_foreach(container
, check_fdc
, &state
);
632 if (state
.multiple
) {
633 warn_report("multiple floppy disk controllers with "
634 "iobase=0x3f0 have been found");
635 error_printf("the one being picked for CMOS setup might not reflect "
642 static void pc_cmos_init_late(void *opaque
)
644 pc_cmos_init_late_arg
*arg
= opaque
;
645 ISADevice
*s
= arg
->rtc_state
;
647 int8_t heads
, sectors
;
652 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 0,
653 &cylinders
, &heads
, §ors
) >= 0) {
654 cmos_init_hd(s
, 0x19, 0x1b, cylinders
, heads
, sectors
);
657 if (arg
->idebus
[0] && ide_get_geometry(arg
->idebus
[0], 1,
658 &cylinders
, &heads
, §ors
) >= 0) {
659 cmos_init_hd(s
, 0x1a, 0x24, cylinders
, heads
, sectors
);
662 rtc_set_memory(s
, 0x12, val
);
665 for (i
= 0; i
< 4; i
++) {
666 /* NOTE: ide_get_geometry() returns the physical
667 geometry. It is always such that: 1 <= sects <= 63, 1
668 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
669 geometry can be different if a translation is done. */
670 if (arg
->idebus
[i
/ 2] &&
671 ide_get_geometry(arg
->idebus
[i
/ 2], i
% 2,
672 &cylinders
, &heads
, §ors
) >= 0) {
673 trans
= ide_get_bios_chs_trans(arg
->idebus
[i
/ 2], i
% 2) - 1;
674 assert((trans
& ~3) == 0);
675 val
|= trans
<< (i
* 2);
678 rtc_set_memory(s
, 0x39, val
);
680 pc_cmos_init_floppy(s
, pc_find_fdc0());
682 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
685 void pc_cmos_init(PCMachineState
*pcms
,
686 BusState
*idebus0
, BusState
*idebus1
,
690 static pc_cmos_init_late_arg arg
;
692 /* various important CMOS locations needed by PC/Bochs bios */
695 /* base memory (first MiB) */
696 val
= MIN(pcms
->below_4g_mem_size
/ KiB
, 640);
697 rtc_set_memory(s
, 0x15, val
);
698 rtc_set_memory(s
, 0x16, val
>> 8);
699 /* extended memory (next 64MiB) */
700 if (pcms
->below_4g_mem_size
> 1 * MiB
) {
701 val
= (pcms
->below_4g_mem_size
- 1 * MiB
) / KiB
;
707 rtc_set_memory(s
, 0x17, val
);
708 rtc_set_memory(s
, 0x18, val
>> 8);
709 rtc_set_memory(s
, 0x30, val
);
710 rtc_set_memory(s
, 0x31, val
>> 8);
711 /* memory between 16MiB and 4GiB */
712 if (pcms
->below_4g_mem_size
> 16 * MiB
) {
713 val
= (pcms
->below_4g_mem_size
- 16 * MiB
) / (64 * KiB
);
719 rtc_set_memory(s
, 0x34, val
);
720 rtc_set_memory(s
, 0x35, val
>> 8);
721 /* memory above 4GiB */
722 val
= pcms
->above_4g_mem_size
/ 65536;
723 rtc_set_memory(s
, 0x5b, val
);
724 rtc_set_memory(s
, 0x5c, val
>> 8);
725 rtc_set_memory(s
, 0x5d, val
>> 16);
727 object_property_add_link(OBJECT(pcms
), "rtc_state",
729 (Object
**)&pcms
->rtc
,
730 object_property_allow_set_link
,
731 OBJ_PROP_LINK_STRONG
, &error_abort
);
732 object_property_set_link(OBJECT(pcms
), OBJECT(s
),
733 "rtc_state", &error_abort
);
735 set_boot_dev(s
, MACHINE(pcms
)->boot_order
, &error_fatal
);
738 val
|= 0x02; /* FPU is there */
739 val
|= 0x04; /* PS/2 mouse installed */
740 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
742 /* hard drives and FDC */
744 arg
.idebus
[0] = idebus0
;
745 arg
.idebus
[1] = idebus1
;
746 qemu_register_reset(pc_cmos_init_late
, &arg
);
749 #define TYPE_PORT92 "port92"
750 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
752 /* port 92 stuff: could be split off */
753 typedef struct Port92State
{
754 ISADevice parent_obj
;
761 static void port92_write(void *opaque
, hwaddr addr
, uint64_t val
,
764 Port92State
*s
= opaque
;
765 int oldval
= s
->outport
;
767 DPRINTF("port92: write 0x%02" PRIx64
"\n", val
);
769 qemu_set_irq(s
->a20_out
, (val
>> 1) & 1);
770 if ((val
& 1) && !(oldval
& 1)) {
771 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
775 static uint64_t port92_read(void *opaque
, hwaddr addr
,
778 Port92State
*s
= opaque
;
782 DPRINTF("port92: read 0x%02x\n", ret
);
786 static void port92_init(ISADevice
*dev
, qemu_irq a20_out
)
788 qdev_connect_gpio_out_named(DEVICE(dev
), PORT92_A20_LINE
, 0, a20_out
);
791 static const VMStateDescription vmstate_port92_isa
= {
794 .minimum_version_id
= 1,
795 .fields
= (VMStateField
[]) {
796 VMSTATE_UINT8(outport
, Port92State
),
797 VMSTATE_END_OF_LIST()
801 static void port92_reset(DeviceState
*d
)
803 Port92State
*s
= PORT92(d
);
808 static const MemoryRegionOps port92_ops
= {
810 .write
= port92_write
,
812 .min_access_size
= 1,
813 .max_access_size
= 1,
815 .endianness
= DEVICE_LITTLE_ENDIAN
,
818 static void port92_initfn(Object
*obj
)
820 Port92State
*s
= PORT92(obj
);
822 memory_region_init_io(&s
->io
, OBJECT(s
), &port92_ops
, s
, "port92", 1);
826 qdev_init_gpio_out_named(DEVICE(obj
), &s
->a20_out
, PORT92_A20_LINE
, 1);
829 static void port92_realizefn(DeviceState
*dev
, Error
**errp
)
831 ISADevice
*isadev
= ISA_DEVICE(dev
);
832 Port92State
*s
= PORT92(dev
);
834 isa_register_ioport(isadev
, &s
->io
, 0x92);
837 static void port92_class_initfn(ObjectClass
*klass
, void *data
)
839 DeviceClass
*dc
= DEVICE_CLASS(klass
);
841 dc
->realize
= port92_realizefn
;
842 dc
->reset
= port92_reset
;
843 dc
->vmsd
= &vmstate_port92_isa
;
845 * Reason: unlike ordinary ISA devices, this one needs additional
846 * wiring: its A20 output line needs to be wired up by
849 dc
->user_creatable
= false;
852 static const TypeInfo port92_info
= {
854 .parent
= TYPE_ISA_DEVICE
,
855 .instance_size
= sizeof(Port92State
),
856 .instance_init
= port92_initfn
,
857 .class_init
= port92_class_initfn
,
860 static void port92_register_types(void)
862 type_register_static(&port92_info
);
865 type_init(port92_register_types
)
867 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
869 X86CPU
*cpu
= opaque
;
871 /* XXX: send to all CPUs ? */
872 /* XXX: add logic to handle multiple A20 line sources */
873 x86_cpu_set_a20(cpu
, level
);
876 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
878 int index
= le32_to_cpu(e820_reserve
.count
);
879 struct e820_entry
*entry
;
881 if (type
!= E820_RAM
) {
882 /* old FW_CFG_E820_TABLE entry -- reservations only */
883 if (index
>= E820_NR_ENTRIES
) {
886 entry
= &e820_reserve
.entry
[index
++];
888 entry
->address
= cpu_to_le64(address
);
889 entry
->length
= cpu_to_le64(length
);
890 entry
->type
= cpu_to_le32(type
);
892 e820_reserve
.count
= cpu_to_le32(index
);
895 /* new "etc/e820" file -- include ram too */
896 e820_table
= g_renew(struct e820_entry
, e820_table
, e820_entries
+ 1);
897 e820_table
[e820_entries
].address
= cpu_to_le64(address
);
898 e820_table
[e820_entries
].length
= cpu_to_le64(length
);
899 e820_table
[e820_entries
].type
= cpu_to_le32(type
);
905 int e820_get_num_entries(void)
910 bool e820_get_entry(int idx
, uint32_t type
, uint64_t *address
, uint64_t *length
)
912 if (idx
< e820_entries
&& e820_table
[idx
].type
== cpu_to_le32(type
)) {
913 *address
= le64_to_cpu(e820_table
[idx
].address
);
914 *length
= le64_to_cpu(e820_table
[idx
].length
);
920 /* Calculates initial APIC ID for a specific CPU index
922 * Currently we need to be able to calculate the APIC ID from the CPU index
923 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
924 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
925 * all CPUs up to max_cpus.
927 static uint32_t x86_cpu_apic_id_from_index(PCMachineState
*pcms
,
928 unsigned int cpu_index
)
930 MachineState
*ms
= MACHINE(pcms
);
931 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
935 correct_id
= x86_apicid_from_cpu_idx(pcms
->smp_dies
, ms
->smp
.cores
,
936 ms
->smp
.threads
, cpu_index
);
937 if (pcmc
->compat_apic_id_mode
) {
938 if (cpu_index
!= correct_id
&& !warned
&& !qtest_enabled()) {
939 error_report("APIC IDs set in compatibility mode, "
940 "CPU topology won't match the configuration");
949 static void pc_build_smbios(PCMachineState
*pcms
)
951 uint8_t *smbios_tables
, *smbios_anchor
;
952 size_t smbios_tables_len
, smbios_anchor_len
;
953 struct smbios_phys_mem_area
*mem_array
;
954 unsigned i
, array_count
;
955 MachineState
*ms
= MACHINE(pcms
);
956 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
958 /* tell smbios about cpuid version and features */
959 smbios_set_cpuid(cpu
->env
.cpuid_version
, cpu
->env
.features
[FEAT_1_EDX
]);
961 smbios_tables
= smbios_get_table_legacy(ms
, &smbios_tables_len
);
963 fw_cfg_add_bytes(pcms
->fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
964 smbios_tables
, smbios_tables_len
);
967 /* build the array of physical mem area from e820 table */
968 mem_array
= g_malloc0(sizeof(*mem_array
) * e820_get_num_entries());
969 for (i
= 0, array_count
= 0; i
< e820_get_num_entries(); i
++) {
972 if (e820_get_entry(i
, E820_RAM
, &addr
, &len
)) {
973 mem_array
[array_count
].address
= addr
;
974 mem_array
[array_count
].length
= len
;
978 smbios_get_tables(ms
, mem_array
, array_count
,
979 &smbios_tables
, &smbios_tables_len
,
980 &smbios_anchor
, &smbios_anchor_len
);
984 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-tables",
985 smbios_tables
, smbios_tables_len
);
986 fw_cfg_add_file(pcms
->fw_cfg
, "etc/smbios/smbios-anchor",
987 smbios_anchor
, smbios_anchor_len
);
991 static FWCfgState
*bochs_bios_init(AddressSpace
*as
, PCMachineState
*pcms
)
994 uint64_t *numa_fw_cfg
;
996 const CPUArchIdList
*cpus
;
997 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
999 fw_cfg
= fw_cfg_init_io_dma(FW_CFG_IO_BASE
, FW_CFG_IO_BASE
+ 4, as
);
1000 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1002 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1004 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1005 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1006 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1007 * for CPU hotplug also uses APIC ID and not "CPU index".
1008 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1009 * but the "limit to the APIC ID values SeaBIOS may see".
1011 * So for compatibility reasons with old BIOSes we are stuck with
1012 * "etc/max-cpus" actually being apic_id_limit
1014 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)pcms
->apic_id_limit
);
1015 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1016 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
,
1017 acpi_tables
, acpi_tables_len
);
1018 fw_cfg_add_i32(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, kvm_allows_irq0_override());
1020 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
,
1021 &e820_reserve
, sizeof(e820_reserve
));
1022 fw_cfg_add_file(fw_cfg
, "etc/e820", e820_table
,
1023 sizeof(struct e820_entry
) * e820_entries
);
1025 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, &hpet_cfg
, sizeof(hpet_cfg
));
1026 /* allocate memory for the NUMA channel: one (64bit) word for the number
1027 * of nodes, one word for each VCPU->node and one word for each node to
1028 * hold the amount of memory.
1030 numa_fw_cfg
= g_new0(uint64_t, 1 + pcms
->apic_id_limit
+ nb_numa_nodes
);
1031 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
1032 cpus
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
1033 for (i
= 0; i
< cpus
->len
; i
++) {
1034 unsigned int apic_id
= cpus
->cpus
[i
].arch_id
;
1035 assert(apic_id
< pcms
->apic_id_limit
);
1036 numa_fw_cfg
[apic_id
+ 1] = cpu_to_le64(cpus
->cpus
[i
].props
.node_id
);
1038 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1039 numa_fw_cfg
[pcms
->apic_id_limit
+ 1 + i
] =
1040 cpu_to_le64(numa_info
[i
].node_mem
);
1042 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, numa_fw_cfg
,
1043 (1 + pcms
->apic_id_limit
+ nb_numa_nodes
) *
1044 sizeof(*numa_fw_cfg
));
1049 static long get_file_size(FILE *f
)
1053 /* XXX: on Unix systems, using fstat() probably makes more sense */
1056 fseek(f
, 0, SEEK_END
);
1058 fseek(f
, where
, SEEK_SET
);
1068 } __attribute__((packed
));
1072 * The entry point into the kernel for PVH boot is different from
1073 * the native entry point. The PVH entry is defined by the x86/HVM
1074 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1076 * This function is passed to load_elf() when it is called from
1077 * load_elfboot() which then additionally checks for an ELF Note of
1078 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1079 * parse the PVH entry address from the ELF Note.
1081 * Due to trickery in elf_opts.h, load_elf() is actually available as
1082 * load_elf32() or load_elf64() and this routine needs to be able
1083 * to deal with being called as 32 or 64 bit.
1085 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1086 * global variable. (although the entry point is 32-bit, the kernel
1087 * binary can be either 32-bit or 64-bit).
1089 static uint64_t read_pvh_start_addr(void *arg1
, void *arg2
, bool is64
)
1091 size_t *elf_note_data_addr
;
1093 /* Check if ELF Note header passed in is valid */
1099 struct elf64_note
*nhdr64
= (struct elf64_note
*)arg1
;
1100 uint64_t nhdr_size64
= sizeof(struct elf64_note
);
1101 uint64_t phdr_align
= *(uint64_t *)arg2
;
1102 uint64_t nhdr_namesz
= nhdr64
->n_namesz
;
1104 elf_note_data_addr
=
1105 ((void *)nhdr64
) + nhdr_size64
+
1106 QEMU_ALIGN_UP(nhdr_namesz
, phdr_align
);
1108 struct elf32_note
*nhdr32
= (struct elf32_note
*)arg1
;
1109 uint32_t nhdr_size32
= sizeof(struct elf32_note
);
1110 uint32_t phdr_align
= *(uint32_t *)arg2
;
1111 uint32_t nhdr_namesz
= nhdr32
->n_namesz
;
1113 elf_note_data_addr
=
1114 ((void *)nhdr32
) + nhdr_size32
+
1115 QEMU_ALIGN_UP(nhdr_namesz
, phdr_align
);
1118 pvh_start_addr
= *elf_note_data_addr
;
1120 return pvh_start_addr
;
1123 static bool load_elfboot(const char *kernel_filename
,
1124 int kernel_file_size
,
1126 size_t pvh_xen_start_addr
,
1130 uint32_t mh_load_addr
= 0;
1131 uint32_t elf_kernel_size
= 0;
1133 uint64_t elf_low
, elf_high
;
1136 if (ldl_p(header
) != 0x464c457f) {
1137 return false; /* no elfboot */
1140 bool elf_is64
= header
[EI_CLASS
] == ELFCLASS64
;
1142 ((Elf64_Ehdr
*)header
)->e_flags
: ((Elf32_Ehdr
*)header
)->e_flags
;
1144 if (flags
& 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1145 error_report("elfboot unsupported flags = %x", flags
);
1149 uint64_t elf_note_type
= XEN_ELFNOTE_PHYS32_ENTRY
;
1150 kernel_size
= load_elf(kernel_filename
, read_pvh_start_addr
,
1151 NULL
, &elf_note_type
, &elf_entry
,
1152 &elf_low
, &elf_high
, 0, I386_ELF_MACHINE
,
1155 if (kernel_size
< 0) {
1156 error_report("Error while loading elf kernel");
1159 mh_load_addr
= elf_low
;
1160 elf_kernel_size
= elf_high
- elf_low
;
1162 if (pvh_start_addr
== 0) {
1163 error_report("Error loading uncompressed kernel without PVH ELF Note");
1166 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ENTRY
, pvh_start_addr
);
1167 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, mh_load_addr
);
1168 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, elf_kernel_size
);
1173 static void load_linux(PCMachineState
*pcms
,
1177 int setup_size
, kernel_size
, cmdline_size
;
1178 int dtb_size
, setup_data_offset
;
1179 uint32_t initrd_max
;
1180 uint8_t header
[8192], *setup
, *kernel
;
1181 hwaddr real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
1184 MachineState
*machine
= MACHINE(pcms
);
1185 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1186 struct setup_data
*setup_data
;
1187 const char *kernel_filename
= machine
->kernel_filename
;
1188 const char *initrd_filename
= machine
->initrd_filename
;
1189 const char *dtb_filename
= machine
->dtb
;
1190 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1192 /* Align to 16 bytes as a paranoia measure */
1193 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
1195 /* load the kernel header */
1196 f
= fopen(kernel_filename
, "rb");
1197 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
1198 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
1199 MIN(ARRAY_SIZE(header
), kernel_size
)) {
1200 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
1201 kernel_filename
, strerror(errno
));
1205 /* kernel protocol version */
1207 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
1209 if (ldl_p(header
+0x202) == 0x53726448) {
1210 protocol
= lduw_p(header
+0x206);
1213 * This could be a multiboot kernel. If it is, let's stop treating it
1214 * like a Linux kernel.
1215 * Note: some multiboot images could be in the ELF format (the same of
1216 * PVH), so we try multiboot first since we check the multiboot magic
1217 * header before to load it.
1219 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
1220 kernel_cmdline
, kernel_size
, header
)) {
1224 * Check if the file is an uncompressed kernel file (ELF) and load it,
1225 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1226 * If load_elfboot() is successful, populate the fw_cfg info.
1228 if (pcmc
->pvh_enabled
&&
1229 load_elfboot(kernel_filename
, kernel_size
,
1230 header
, pvh_start_addr
, fw_cfg
)) {
1233 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1234 strlen(kernel_cmdline
) + 1);
1235 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1237 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, sizeof(header
));
1238 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
,
1239 header
, sizeof(header
));
1242 if (initrd_filename
) {
1245 GError
*gerr
= NULL
;
1247 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1248 &initrd_size
, &gerr
)) {
1249 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1250 initrd_filename
, gerr
->message
);
1254 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1255 if (initrd_size
>= initrd_max
) {
1256 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1257 "(max: %"PRIu32
", need %"PRId64
")\n",
1258 initrd_max
, (uint64_t)initrd_size
);
1262 initrd_addr
= (initrd_max
- initrd_size
) & ~4095;
1264 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1265 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1266 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
,
1270 option_rom
[nb_option_roms
].bootindex
= 0;
1271 option_rom
[nb_option_roms
].name
= "pvh.bin";
1279 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
1281 real_addr
= 0x90000;
1282 cmdline_addr
= 0x9a000 - cmdline_size
;
1283 prot_addr
= 0x10000;
1284 } else if (protocol
< 0x202) {
1285 /* High but ancient kernel */
1286 real_addr
= 0x90000;
1287 cmdline_addr
= 0x9a000 - cmdline_size
;
1288 prot_addr
= 0x100000;
1290 /* High and recent kernel */
1291 real_addr
= 0x10000;
1292 cmdline_addr
= 0x20000;
1293 prot_addr
= 0x100000;
1298 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
1299 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
1300 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
1306 /* highest address for loading the initrd */
1307 if (protocol
>= 0x20c &&
1308 lduw_p(header
+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G
) {
1310 * Linux has supported initrd up to 4 GB for a very long time (2007,
1311 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1312 * though it only sets initrd_max to 2 GB to "work around bootloader
1313 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1314 * has supported this.
1316 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1317 * be loaded into any address.
1319 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1320 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1323 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1325 initrd_max
= UINT32_MAX
;
1326 } else if (protocol
>= 0x203) {
1327 initrd_max
= ldl_p(header
+0x22c);
1329 initrd_max
= 0x37ffffff;
1332 if (initrd_max
>= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
) {
1333 initrd_max
= pcms
->below_4g_mem_size
- pcmc
->acpi_data_size
- 1;
1336 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
1337 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
1338 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1340 if (protocol
>= 0x202) {
1341 stl_p(header
+0x228, cmdline_addr
);
1343 stw_p(header
+0x20, 0xA33F);
1344 stw_p(header
+0x22, cmdline_addr
-real_addr
);
1347 /* handle vga= parameter */
1348 vmode
= strstr(kernel_cmdline
, "vga=");
1350 unsigned int video_mode
;
1353 if (!strncmp(vmode
, "normal", 6)) {
1354 video_mode
= 0xffff;
1355 } else if (!strncmp(vmode
, "ext", 3)) {
1356 video_mode
= 0xfffe;
1357 } else if (!strncmp(vmode
, "ask", 3)) {
1358 video_mode
= 0xfffd;
1360 video_mode
= strtol(vmode
, NULL
, 0);
1362 stw_p(header
+0x1fa, video_mode
);
1366 /* High nybble = B reserved for QEMU; low nybble is revision number.
1367 If this code is substantially changed, you may want to consider
1368 incrementing the revision. */
1369 if (protocol
>= 0x200) {
1370 header
[0x210] = 0xB0;
1373 if (protocol
>= 0x201) {
1374 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
1375 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
1379 if (initrd_filename
) {
1382 GError
*gerr
= NULL
;
1384 if (protocol
< 0x200) {
1385 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
1389 if (!g_file_get_contents(initrd_filename
, &initrd_data
,
1390 &initrd_size
, &gerr
)) {
1391 fprintf(stderr
, "qemu: error reading initrd %s: %s\n",
1392 initrd_filename
, gerr
->message
);
1395 if (initrd_size
>= initrd_max
) {
1396 fprintf(stderr
, "qemu: initrd is too large, cannot support."
1397 "(max: %"PRIu32
", need %"PRId64
")\n",
1398 initrd_max
, (uint64_t)initrd_size
);
1402 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
1404 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
1405 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
1406 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
1408 stl_p(header
+0x218, initrd_addr
);
1409 stl_p(header
+0x21c, initrd_size
);
1412 /* load kernel and setup */
1413 setup_size
= header
[0x1f1];
1414 if (setup_size
== 0) {
1417 setup_size
= (setup_size
+1)*512;
1418 if (setup_size
> kernel_size
) {
1419 fprintf(stderr
, "qemu: invalid kernel header\n");
1422 kernel_size
-= setup_size
;
1424 setup
= g_malloc(setup_size
);
1425 kernel
= g_malloc(kernel_size
);
1426 fseek(f
, 0, SEEK_SET
);
1427 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
1428 fprintf(stderr
, "fread() failed\n");
1431 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
1432 fprintf(stderr
, "fread() failed\n");
1437 /* append dtb to kernel */
1439 if (protocol
< 0x209) {
1440 fprintf(stderr
, "qemu: Linux kernel too old to load a dtb\n");
1444 dtb_size
= get_image_size(dtb_filename
);
1445 if (dtb_size
<= 0) {
1446 fprintf(stderr
, "qemu: error reading dtb %s: %s\n",
1447 dtb_filename
, strerror(errno
));
1451 setup_data_offset
= QEMU_ALIGN_UP(kernel_size
, 16);
1452 kernel_size
= setup_data_offset
+ sizeof(struct setup_data
) + dtb_size
;
1453 kernel
= g_realloc(kernel
, kernel_size
);
1455 stq_p(header
+0x250, prot_addr
+ setup_data_offset
);
1457 setup_data
= (struct setup_data
*)(kernel
+ setup_data_offset
);
1458 setup_data
->next
= 0;
1459 setup_data
->type
= cpu_to_le32(SETUP_DTB
);
1460 setup_data
->len
= cpu_to_le32(dtb_size
);
1462 load_image_size(dtb_filename
, setup_data
->data
, dtb_size
);
1465 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
1467 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
1468 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1469 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
1471 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
1472 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
1473 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
1475 option_rom
[nb_option_roms
].bootindex
= 0;
1476 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
1477 if (pcmc
->linuxboot_dma_enabled
&& fw_cfg_dma_enabled(fw_cfg
)) {
1478 option_rom
[nb_option_roms
].name
= "linuxboot_dma.bin";
1483 #define NE2000_NB_MAX 6
1485 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
1487 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
1489 void pc_init_ne2k_isa(ISABus
*bus
, NICInfo
*nd
)
1491 static int nb_ne2k
= 0;
1493 if (nb_ne2k
== NE2000_NB_MAX
)
1495 isa_ne2000_init(bus
, ne2000_io
[nb_ne2k
],
1496 ne2000_irq
[nb_ne2k
], nd
);
1500 DeviceState
*cpu_get_current_apic(void)
1503 X86CPU
*cpu
= X86_CPU(current_cpu
);
1504 return cpu
->apic_state
;
1510 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
1512 X86CPU
*cpu
= opaque
;
1515 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_SMI
);
1519 static void pc_new_cpu(PCMachineState
*pcms
, int64_t apic_id
, Error
**errp
)
1522 Error
*local_err
= NULL
;
1523 CPUX86State
*env
= NULL
;
1525 cpu
= object_new(MACHINE(pcms
)->cpu_type
);
1527 env
= &X86_CPU(cpu
)->env
;
1528 env
->nr_dies
= pcms
->smp_dies
;
1530 object_property_set_uint(cpu
, apic_id
, "apic-id", &local_err
);
1531 object_property_set_bool(cpu
, true, "realized", &local_err
);
1534 error_propagate(errp
, local_err
);
1538 * This function is very similar to smp_parse()
1539 * in hw/core/machine.c but includes CPU die support.
1541 void pc_smp_parse(MachineState
*ms
, QemuOpts
*opts
)
1543 PCMachineState
*pcms
= PC_MACHINE(ms
);
1546 unsigned cpus
= qemu_opt_get_number(opts
, "cpus", 0);
1547 unsigned sockets
= qemu_opt_get_number(opts
, "sockets", 0);
1548 unsigned dies
= qemu_opt_get_number(opts
, "dies", 1);
1549 unsigned cores
= qemu_opt_get_number(opts
, "cores", 0);
1550 unsigned threads
= qemu_opt_get_number(opts
, "threads", 0);
1552 /* compute missing values, prefer sockets over cores over threads */
1553 if (cpus
== 0 || sockets
== 0) {
1554 cores
= cores
> 0 ? cores
: 1;
1555 threads
= threads
> 0 ? threads
: 1;
1557 sockets
= sockets
> 0 ? sockets
: 1;
1558 cpus
= cores
* threads
* dies
* sockets
;
1561 qemu_opt_get_number(opts
, "maxcpus", cpus
);
1562 sockets
= ms
->smp
.max_cpus
/ (cores
* threads
* dies
);
1564 } else if (cores
== 0) {
1565 threads
= threads
> 0 ? threads
: 1;
1566 cores
= cpus
/ (sockets
* dies
* threads
);
1567 cores
= cores
> 0 ? cores
: 1;
1568 } else if (threads
== 0) {
1569 threads
= cpus
/ (cores
* dies
* sockets
);
1570 threads
= threads
> 0 ? threads
: 1;
1571 } else if (sockets
* dies
* cores
* threads
< cpus
) {
1572 error_report("cpu topology: "
1573 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
1575 sockets
, dies
, cores
, threads
, cpus
);
1580 qemu_opt_get_number(opts
, "maxcpus", cpus
);
1582 if (ms
->smp
.max_cpus
< cpus
) {
1583 error_report("maxcpus must be equal to or greater than smp");
1587 if (sockets
* dies
* cores
* threads
> ms
->smp
.max_cpus
) {
1588 error_report("cpu topology: "
1589 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
1591 sockets
, dies
, cores
, threads
,
1596 if (sockets
* dies
* cores
* threads
!= ms
->smp
.max_cpus
) {
1597 warn_report("Invalid CPU topology deprecated: "
1598 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
1600 sockets
, dies
, cores
, threads
,
1604 ms
->smp
.cpus
= cpus
;
1605 ms
->smp
.cores
= cores
;
1606 ms
->smp
.threads
= threads
;
1607 pcms
->smp_dies
= dies
;
1610 if (ms
->smp
.cpus
> 1) {
1611 Error
*blocker
= NULL
;
1612 error_setg(&blocker
, QERR_REPLAY_NOT_SUPPORTED
, "smp");
1613 replay_add_blocker(blocker
);
1617 void pc_hot_add_cpu(MachineState
*ms
, const int64_t id
, Error
**errp
)
1619 PCMachineState
*pcms
= PC_MACHINE(ms
);
1620 int64_t apic_id
= x86_cpu_apic_id_from_index(pcms
, id
);
1621 Error
*local_err
= NULL
;
1624 error_setg(errp
, "Invalid CPU id: %" PRIi64
, id
);
1628 if (apic_id
>= ACPI_CPU_HOTPLUG_ID_LIMIT
) {
1629 error_setg(errp
, "Unable to add CPU: %" PRIi64
1630 ", resulting APIC ID (%" PRIi64
") is too large",
1635 pc_new_cpu(PC_MACHINE(ms
), apic_id
, &local_err
);
1637 error_propagate(errp
, local_err
);
1642 void pc_cpus_init(PCMachineState
*pcms
)
1645 const CPUArchIdList
*possible_cpus
;
1646 MachineState
*ms
= MACHINE(pcms
);
1647 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
1648 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(mc
);
1650 x86_cpu_set_default_version(pcmc
->default_cpu_version
);
1652 /* Calculates the limit to CPU APIC ID values
1654 * Limit for the APIC ID value, so that all
1655 * CPU APIC IDs are < pcms->apic_id_limit.
1657 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1659 pcms
->apic_id_limit
= x86_cpu_apic_id_from_index(pcms
,
1660 ms
->smp
.max_cpus
- 1) + 1;
1661 possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
1662 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
1663 pc_new_cpu(pcms
, possible_cpus
->cpus
[i
].arch_id
, &error_fatal
);
1667 static void pc_build_feature_control_file(PCMachineState
*pcms
)
1669 MachineState
*ms
= MACHINE(pcms
);
1670 X86CPU
*cpu
= X86_CPU(ms
->possible_cpus
->cpus
[0].cpu
);
1671 CPUX86State
*env
= &cpu
->env
;
1672 uint32_t unused
, ecx
, edx
;
1673 uint64_t feature_control_bits
= 0;
1676 cpu_x86_cpuid(env
, 1, 0, &unused
, &unused
, &ecx
, &edx
);
1677 if (ecx
& CPUID_EXT_VMX
) {
1678 feature_control_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1681 if ((edx
& (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
)) ==
1682 (CPUID_EXT2_MCE
| CPUID_EXT2_MCA
) &&
1683 (env
->mcg_cap
& MCG_LMCE_P
)) {
1684 feature_control_bits
|= FEATURE_CONTROL_LMCE
;
1687 if (!feature_control_bits
) {
1691 val
= g_malloc(sizeof(*val
));
1692 *val
= cpu_to_le64(feature_control_bits
| FEATURE_CONTROL_LOCKED
);
1693 fw_cfg_add_file(pcms
->fw_cfg
, "etc/msr_feature_control", val
, sizeof(*val
));
1696 static void rtc_set_cpus_count(ISADevice
*rtc
, uint16_t cpus_count
)
1698 if (cpus_count
> 0xff) {
1699 /* If the number of CPUs can't be represented in 8 bits, the
1700 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1701 * to make old BIOSes fail more predictably.
1703 rtc_set_memory(rtc
, 0x5f, 0);
1705 rtc_set_memory(rtc
, 0x5f, cpus_count
- 1);
1710 void pc_machine_done(Notifier
*notifier
, void *data
)
1712 PCMachineState
*pcms
= container_of(notifier
,
1713 PCMachineState
, machine_done
);
1714 PCIBus
*bus
= pcms
->bus
;
1716 /* set the number of CPUs */
1717 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
1720 int extra_hosts
= 0;
1722 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1723 /* look for expander root buses */
1724 if (pci_bus_is_root(bus
)) {
1728 if (extra_hosts
&& pcms
->fw_cfg
) {
1729 uint64_t *val
= g_malloc(sizeof(*val
));
1730 *val
= cpu_to_le64(extra_hosts
);
1731 fw_cfg_add_file(pcms
->fw_cfg
,
1732 "etc/extra-pci-roots", val
, sizeof(*val
));
1738 pc_build_smbios(pcms
);
1739 pc_build_feature_control_file(pcms
);
1740 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1741 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1744 if (pcms
->apic_id_limit
> 255 && !xen_enabled()) {
1745 IntelIOMMUState
*iommu
= INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1747 if (!iommu
|| !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu
)) ||
1748 iommu
->intr_eim
!= ON_OFF_AUTO_ON
) {
1749 error_report("current -smp configuration requires "
1750 "Extended Interrupt Mode enabled. "
1751 "You can add an IOMMU using: "
1752 "-device intel-iommu,intremap=on,eim=on");
1758 void pc_guest_info_init(PCMachineState
*pcms
)
1762 pcms
->apic_xrupt_override
= kvm_allows_irq0_override();
1763 pcms
->numa_nodes
= nb_numa_nodes
;
1764 pcms
->node_mem
= g_malloc0(pcms
->numa_nodes
*
1765 sizeof *pcms
->node_mem
);
1766 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1767 pcms
->node_mem
[i
] = numa_info
[i
].node_mem
;
1770 pcms
->machine_done
.notify
= pc_machine_done
;
1771 qemu_add_machine_init_done_notifier(&pcms
->machine_done
);
1774 /* setup pci memory address space mapping into system address space */
1775 void pc_pci_as_mapping_init(Object
*owner
, MemoryRegion
*system_memory
,
1776 MemoryRegion
*pci_address_space
)
1778 /* Set to lower priority than RAM */
1779 memory_region_add_subregion_overlap(system_memory
, 0x0,
1780 pci_address_space
, -1);
1783 void xen_load_linux(PCMachineState
*pcms
)
1788 assert(MACHINE(pcms
)->kernel_filename
!= NULL
);
1790 fw_cfg
= fw_cfg_init_io(FW_CFG_IO_BASE
);
1791 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
1794 load_linux(pcms
, fw_cfg
);
1795 for (i
= 0; i
< nb_option_roms
; i
++) {
1796 assert(!strcmp(option_rom
[i
].name
, "linuxboot.bin") ||
1797 !strcmp(option_rom
[i
].name
, "linuxboot_dma.bin") ||
1798 !strcmp(option_rom
[i
].name
, "pvh.bin") ||
1799 !strcmp(option_rom
[i
].name
, "multiboot.bin"));
1800 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1802 pcms
->fw_cfg
= fw_cfg
;
1805 void pc_memory_init(PCMachineState
*pcms
,
1806 MemoryRegion
*system_memory
,
1807 MemoryRegion
*rom_memory
,
1808 MemoryRegion
**ram_memory
)
1811 MemoryRegion
*ram
, *option_rom_mr
;
1812 MemoryRegion
*ram_below_4g
, *ram_above_4g
;
1814 MachineState
*machine
= MACHINE(pcms
);
1815 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1817 assert(machine
->ram_size
== pcms
->below_4g_mem_size
+
1818 pcms
->above_4g_mem_size
);
1820 linux_boot
= (machine
->kernel_filename
!= NULL
);
1822 /* Allocate RAM. We allocate it as a single memory region and use
1823 * aliases to address portions of it, mostly for backwards compatibility
1824 * with older qemus that used qemu_ram_alloc().
1826 ram
= g_malloc(sizeof(*ram
));
1827 memory_region_allocate_system_memory(ram
, NULL
, "pc.ram",
1830 ram_below_4g
= g_malloc(sizeof(*ram_below_4g
));
1831 memory_region_init_alias(ram_below_4g
, NULL
, "ram-below-4g", ram
,
1832 0, pcms
->below_4g_mem_size
);
1833 memory_region_add_subregion(system_memory
, 0, ram_below_4g
);
1834 e820_add_entry(0, pcms
->below_4g_mem_size
, E820_RAM
);
1835 if (pcms
->above_4g_mem_size
> 0) {
1836 ram_above_4g
= g_malloc(sizeof(*ram_above_4g
));
1837 memory_region_init_alias(ram_above_4g
, NULL
, "ram-above-4g", ram
,
1838 pcms
->below_4g_mem_size
,
1839 pcms
->above_4g_mem_size
);
1840 memory_region_add_subregion(system_memory
, 0x100000000ULL
,
1842 e820_add_entry(0x100000000ULL
, pcms
->above_4g_mem_size
, E820_RAM
);
1845 if (!pcmc
->has_reserved_memory
&&
1846 (machine
->ram_slots
||
1847 (machine
->maxram_size
> machine
->ram_size
))) {
1848 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1850 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1855 /* always allocate the device memory information */
1856 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
1858 /* initialize device memory address space */
1859 if (pcmc
->has_reserved_memory
&&
1860 (machine
->ram_size
< machine
->maxram_size
)) {
1861 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1863 if (machine
->ram_slots
> ACPI_MAX_RAM_SLOTS
) {
1864 error_report("unsupported amount of memory slots: %"PRIu64
,
1865 machine
->ram_slots
);
1869 if (QEMU_ALIGN_UP(machine
->maxram_size
,
1870 TARGET_PAGE_SIZE
) != machine
->maxram_size
) {
1871 error_report("maximum memory size must by aligned to multiple of "
1872 "%d bytes", TARGET_PAGE_SIZE
);
1876 machine
->device_memory
->base
=
1877 ROUND_UP(0x100000000ULL
+ pcms
->above_4g_mem_size
, 1 * GiB
);
1879 if (pcmc
->enforce_aligned_dimm
) {
1880 /* size device region assuming 1G page max alignment per slot */
1881 device_mem_size
+= (1 * GiB
) * machine
->ram_slots
;
1884 if ((machine
->device_memory
->base
+ device_mem_size
) <
1886 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT
,
1887 machine
->maxram_size
);
1891 memory_region_init(&machine
->device_memory
->mr
, OBJECT(pcms
),
1892 "device-memory", device_mem_size
);
1893 memory_region_add_subregion(system_memory
, machine
->device_memory
->base
,
1894 &machine
->device_memory
->mr
);
1897 /* Initialize PC system firmware */
1898 pc_system_firmware_init(pcms
, rom_memory
);
1900 option_rom_mr
= g_malloc(sizeof(*option_rom_mr
));
1901 memory_region_init_ram(option_rom_mr
, NULL
, "pc.rom", PC_ROM_SIZE
,
1903 if (pcmc
->pci_enabled
) {
1904 memory_region_set_readonly(option_rom_mr
, true);
1906 memory_region_add_subregion_overlap(rom_memory
,
1911 fw_cfg
= bochs_bios_init(&address_space_memory
, pcms
);
1915 if (pcmc
->has_reserved_memory
&& machine
->device_memory
->base
) {
1916 uint64_t *val
= g_malloc(sizeof(*val
));
1917 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1918 uint64_t res_mem_end
= machine
->device_memory
->base
;
1920 if (!pcmc
->broken_reserved_end
) {
1921 res_mem_end
+= memory_region_size(&machine
->device_memory
->mr
);
1923 *val
= cpu_to_le64(ROUND_UP(res_mem_end
, 1 * GiB
));
1924 fw_cfg_add_file(fw_cfg
, "etc/reserved-memory-end", val
, sizeof(*val
));
1928 load_linux(pcms
, fw_cfg
);
1931 for (i
= 0; i
< nb_option_roms
; i
++) {
1932 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1934 pcms
->fw_cfg
= fw_cfg
;
1936 /* Init default IOAPIC address space */
1937 pcms
->ioapic_as
= &address_space_memory
;
1941 * The 64bit pci hole starts after "above 4G RAM" and
1942 * potentially the space reserved for memory hotplug.
1944 uint64_t pc_pci_hole64_start(void)
1946 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
1947 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
1948 MachineState
*ms
= MACHINE(pcms
);
1949 uint64_t hole64_start
= 0;
1951 if (pcmc
->has_reserved_memory
&& ms
->device_memory
->base
) {
1952 hole64_start
= ms
->device_memory
->base
;
1953 if (!pcmc
->broken_reserved_end
) {
1954 hole64_start
+= memory_region_size(&ms
->device_memory
->mr
);
1957 hole64_start
= 0x100000000ULL
+ pcms
->above_4g_mem_size
;
1960 return ROUND_UP(hole64_start
, 1 * GiB
);
1963 qemu_irq
pc_allocate_cpu_irq(void)
1965 return qemu_allocate_irq(pic_irq_request
, NULL
, 0);
1968 DeviceState
*pc_vga_init(ISABus
*isa_bus
, PCIBus
*pci_bus
)
1970 DeviceState
*dev
= NULL
;
1972 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA
);
1974 PCIDevice
*pcidev
= pci_vga_init(pci_bus
);
1975 dev
= pcidev
? &pcidev
->qdev
: NULL
;
1976 } else if (isa_bus
) {
1977 ISADevice
*isadev
= isa_vga_init(isa_bus
);
1978 dev
= isadev
? DEVICE(isadev
) : NULL
;
1980 rom_reset_order_override();
1984 static const MemoryRegionOps ioport80_io_ops
= {
1985 .write
= ioport80_write
,
1986 .read
= ioport80_read
,
1987 .endianness
= DEVICE_NATIVE_ENDIAN
,
1989 .min_access_size
= 1,
1990 .max_access_size
= 1,
1994 static const MemoryRegionOps ioportF0_io_ops
= {
1995 .write
= ioportF0_write
,
1996 .read
= ioportF0_read
,
1997 .endianness
= DEVICE_NATIVE_ENDIAN
,
1999 .min_access_size
= 1,
2000 .max_access_size
= 1,
2004 static void pc_superio_init(ISABus
*isa_bus
, bool create_fdctrl
, bool no_vmport
)
2007 DriveInfo
*fd
[MAX_FD
];
2009 ISADevice
*i8042
, *port92
, *vmmouse
;
2011 serial_hds_isa_init(isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
2012 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
2014 for (i
= 0; i
< MAX_FD
; i
++) {
2015 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
2016 create_fdctrl
|= !!fd
[i
];
2018 if (create_fdctrl
) {
2019 fdctrl_init_isa(isa_bus
, fd
);
2022 i8042
= isa_create_simple(isa_bus
, "i8042");
2024 vmport_init(isa_bus
);
2025 vmmouse
= isa_try_create(isa_bus
, "vmmouse");
2030 DeviceState
*dev
= DEVICE(vmmouse
);
2031 qdev_prop_set_ptr(dev
, "ps2_mouse", i8042
);
2032 qdev_init_nofail(dev
);
2034 port92
= isa_create_simple(isa_bus
, "port92");
2036 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
2037 i8042_setup_a20_line(i8042
, a20_line
[0]);
2038 port92_init(port92
, a20_line
[1]);
2042 void pc_basic_device_init(ISABus
*isa_bus
, qemu_irq
*gsi
,
2043 ISADevice
**rtc_state
,
2050 DeviceState
*hpet
= NULL
;
2051 int pit_isa_irq
= 0;
2052 qemu_irq pit_alt_irq
= NULL
;
2053 qemu_irq rtc_irq
= NULL
;
2054 ISADevice
*pit
= NULL
;
2055 MemoryRegion
*ioport80_io
= g_new(MemoryRegion
, 1);
2056 MemoryRegion
*ioportF0_io
= g_new(MemoryRegion
, 1);
2058 memory_region_init_io(ioport80_io
, NULL
, &ioport80_io_ops
, NULL
, "ioport80", 1);
2059 memory_region_add_subregion(isa_bus
->address_space_io
, 0x80, ioport80_io
);
2061 memory_region_init_io(ioportF0_io
, NULL
, &ioportF0_io_ops
, NULL
, "ioportF0", 1);
2062 memory_region_add_subregion(isa_bus
->address_space_io
, 0xf0, ioportF0_io
);
2065 * Check if an HPET shall be created.
2067 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2068 * when the HPET wants to take over. Thus we have to disable the latter.
2070 if (!no_hpet
&& (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
2071 /* In order to set property, here not using sysbus_try_create_simple */
2072 hpet
= qdev_try_create(NULL
, TYPE_HPET
);
2074 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2075 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2078 uint8_t compat
= object_property_get_uint(OBJECT(hpet
),
2081 qdev_prop_set_uint32(hpet
, HPET_INTCAP
, hpet_irqs
);
2083 qdev_init_nofail(hpet
);
2084 sysbus_mmio_map(SYS_BUS_DEVICE(hpet
), 0, HPET_BASE
);
2086 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
2087 sysbus_connect_irq(SYS_BUS_DEVICE(hpet
), i
, gsi
[i
]);
2090 pit_alt_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_PIT_INT
);
2091 rtc_irq
= qdev_get_gpio_in(hpet
, HPET_LEGACY_RTC_INT
);
2094 *rtc_state
= mc146818_rtc_init(isa_bus
, 2000, rtc_irq
);
2096 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
2098 if (!xen_enabled() && has_pit
) {
2099 if (kvm_pit_in_kernel()) {
2100 pit
= kvm_pit_init(isa_bus
, 0x40);
2102 pit
= i8254_pit_init(isa_bus
, 0x40, pit_isa_irq
, pit_alt_irq
);
2105 /* connect PIT to output control line of the HPET */
2106 qdev_connect_gpio_out(hpet
, 0, qdev_get_gpio_in(DEVICE(pit
), 0));
2108 pcspk_init(isa_bus
, pit
);
2111 i8257_dma_init(isa_bus
, 0);
2114 pc_superio_init(isa_bus
, create_fdctrl
, no_vmport
);
2117 void pc_nic_init(PCMachineClass
*pcmc
, ISABus
*isa_bus
, PCIBus
*pci_bus
)
2121 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC
);
2122 for (i
= 0; i
< nb_nics
; i
++) {
2123 NICInfo
*nd
= &nd_table
[i
];
2124 const char *model
= nd
->model
? nd
->model
: pcmc
->default_nic_model
;
2126 if (g_str_equal(model
, "ne2k_isa")) {
2127 pc_init_ne2k_isa(isa_bus
, nd
);
2129 pci_nic_init_nofail(nd
, pci_bus
, model
, NULL
);
2132 rom_reset_order_override();
2135 void ioapic_init_gsi(GSIState
*gsi_state
, const char *parent_name
)
2141 if (kvm_ioapic_in_kernel()) {
2142 dev
= qdev_create(NULL
, TYPE_KVM_IOAPIC
);
2144 dev
= qdev_create(NULL
, TYPE_IOAPIC
);
2147 object_property_add_child(object_resolve_path(parent_name
, NULL
),
2148 "ioapic", OBJECT(dev
), NULL
);
2150 qdev_init_nofail(dev
);
2151 d
= SYS_BUS_DEVICE(dev
);
2152 sysbus_mmio_map(d
, 0, IO_APIC_DEFAULT_ADDRESS
);
2154 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
2155 gsi_state
->ioapic_irq
[i
] = qdev_get_gpio_in(dev
, i
);
2159 static void pc_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2162 const PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2163 const PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2164 const MachineState
*ms
= MACHINE(hotplug_dev
);
2165 const bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2166 const uint64_t legacy_align
= TARGET_PAGE_SIZE
;
2167 Error
*local_err
= NULL
;
2170 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2171 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2172 * addition to cover this case.
2174 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2176 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2180 if (is_nvdimm
&& !ms
->nvdimms_state
->is_enabled
) {
2181 error_setg(errp
, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2185 hotplug_handler_pre_plug(pcms
->acpi_dev
, dev
, &local_err
);
2187 error_propagate(errp
, local_err
);
2191 pc_dimm_pre_plug(PC_DIMM(dev
), MACHINE(hotplug_dev
),
2192 pcmc
->enforce_aligned_dimm
? NULL
: &legacy_align
, errp
);
2195 static void pc_memory_plug(HotplugHandler
*hotplug_dev
,
2196 DeviceState
*dev
, Error
**errp
)
2198 Error
*local_err
= NULL
;
2199 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2200 MachineState
*ms
= MACHINE(hotplug_dev
);
2201 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
2203 pc_dimm_plug(PC_DIMM(dev
), MACHINE(pcms
), &local_err
);
2209 nvdimm_plug(ms
->nvdimms_state
);
2212 hotplug_handler_plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &error_abort
);
2214 error_propagate(errp
, local_err
);
2217 static void pc_memory_unplug_request(HotplugHandler
*hotplug_dev
,
2218 DeviceState
*dev
, Error
**errp
)
2220 Error
*local_err
= NULL
;
2221 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2224 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2225 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2226 * addition to cover this case.
2228 if (!pcms
->acpi_dev
|| !acpi_enabled
) {
2229 error_setg(&local_err
,
2230 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2234 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
2235 error_setg(&local_err
,
2236 "nvdimm device hot unplug is not supported yet.");
2240 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
,
2243 error_propagate(errp
, local_err
);
2246 static void pc_memory_unplug(HotplugHandler
*hotplug_dev
,
2247 DeviceState
*dev
, Error
**errp
)
2249 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2250 Error
*local_err
= NULL
;
2252 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2257 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(pcms
));
2258 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
2260 error_propagate(errp
, local_err
);
2263 static int pc_apic_cmp(const void *a
, const void *b
)
2265 CPUArchId
*apic_a
= (CPUArchId
*)a
;
2266 CPUArchId
*apic_b
= (CPUArchId
*)b
;
2268 return apic_a
->arch_id
- apic_b
->arch_id
;
2271 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
2272 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
2273 * entry corresponding to CPU's apic_id returns NULL.
2275 static CPUArchId
*pc_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2277 CPUArchId apic_id
, *found_cpu
;
2279 apic_id
.arch_id
= id
;
2280 found_cpu
= bsearch(&apic_id
, ms
->possible_cpus
->cpus
,
2281 ms
->possible_cpus
->len
, sizeof(*ms
->possible_cpus
->cpus
),
2283 if (found_cpu
&& idx
) {
2284 *idx
= found_cpu
- ms
->possible_cpus
->cpus
;
2289 static void pc_cpu_plug(HotplugHandler
*hotplug_dev
,
2290 DeviceState
*dev
, Error
**errp
)
2292 CPUArchId
*found_cpu
;
2293 Error
*local_err
= NULL
;
2294 X86CPU
*cpu
= X86_CPU(dev
);
2295 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2297 if (pcms
->acpi_dev
) {
2298 hotplug_handler_plug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2304 /* increment the number of CPUs */
2307 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2310 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2313 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2314 found_cpu
->cpu
= OBJECT(dev
);
2316 error_propagate(errp
, local_err
);
2318 static void pc_cpu_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2319 DeviceState
*dev
, Error
**errp
)
2322 Error
*local_err
= NULL
;
2323 X86CPU
*cpu
= X86_CPU(dev
);
2324 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2326 if (!pcms
->acpi_dev
) {
2327 error_setg(&local_err
, "CPU hot unplug not supported without ACPI");
2331 pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2334 error_setg(&local_err
, "Boot CPU is unpluggable");
2338 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
,
2345 error_propagate(errp
, local_err
);
2349 static void pc_cpu_unplug_cb(HotplugHandler
*hotplug_dev
,
2350 DeviceState
*dev
, Error
**errp
)
2352 CPUArchId
*found_cpu
;
2353 Error
*local_err
= NULL
;
2354 X86CPU
*cpu
= X86_CPU(dev
);
2355 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2357 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms
->acpi_dev
), dev
, &local_err
);
2362 found_cpu
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, NULL
);
2363 found_cpu
->cpu
= NULL
;
2364 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
2366 /* decrement the number of CPUs */
2368 /* Update the number of CPUs in CMOS */
2369 rtc_set_cpus_count(pcms
->rtc
, pcms
->boot_cpus
);
2370 fw_cfg_modify_i16(pcms
->fw_cfg
, FW_CFG_NB_CPUS
, pcms
->boot_cpus
);
2372 error_propagate(errp
, local_err
);
2375 static void pc_cpu_pre_plug(HotplugHandler
*hotplug_dev
,
2376 DeviceState
*dev
, Error
**errp
)
2380 CPUArchId
*cpu_slot
;
2381 X86CPUTopoInfo topo
;
2382 X86CPU
*cpu
= X86_CPU(dev
);
2383 CPUX86State
*env
= &cpu
->env
;
2384 MachineState
*ms
= MACHINE(hotplug_dev
);
2385 PCMachineState
*pcms
= PC_MACHINE(hotplug_dev
);
2386 unsigned int smp_cores
= ms
->smp
.cores
;
2387 unsigned int smp_threads
= ms
->smp
.threads
;
2389 if(!object_dynamic_cast(OBJECT(cpu
), ms
->cpu_type
)) {
2390 error_setg(errp
, "Invalid CPU type, expected cpu type: '%s'",
2395 env
->nr_dies
= pcms
->smp_dies
;
2398 * If APIC ID is not set,
2399 * set it based on socket/die/core/thread properties.
2401 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
2402 int max_socket
= (ms
->smp
.max_cpus
- 1) /
2403 smp_threads
/ smp_cores
/ pcms
->smp_dies
;
2405 if (cpu
->socket_id
< 0) {
2406 error_setg(errp
, "CPU socket-id is not set");
2408 } else if (cpu
->socket_id
> max_socket
) {
2409 error_setg(errp
, "Invalid CPU socket-id: %u must be in range 0:%u",
2410 cpu
->socket_id
, max_socket
);
2412 } else if (cpu
->die_id
> pcms
->smp_dies
- 1) {
2413 error_setg(errp
, "Invalid CPU die-id: %u must be in range 0:%u",
2414 cpu
->die_id
, max_socket
);
2417 if (cpu
->core_id
< 0) {
2418 error_setg(errp
, "CPU core-id is not set");
2420 } else if (cpu
->core_id
> (smp_cores
- 1)) {
2421 error_setg(errp
, "Invalid CPU core-id: %u must be in range 0:%u",
2422 cpu
->core_id
, smp_cores
- 1);
2425 if (cpu
->thread_id
< 0) {
2426 error_setg(errp
, "CPU thread-id is not set");
2428 } else if (cpu
->thread_id
> (smp_threads
- 1)) {
2429 error_setg(errp
, "Invalid CPU thread-id: %u must be in range 0:%u",
2430 cpu
->thread_id
, smp_threads
- 1);
2434 topo
.pkg_id
= cpu
->socket_id
;
2435 topo
.die_id
= cpu
->die_id
;
2436 topo
.core_id
= cpu
->core_id
;
2437 topo
.smt_id
= cpu
->thread_id
;
2438 cpu
->apic_id
= apicid_from_topo_ids(pcms
->smp_dies
, smp_cores
,
2439 smp_threads
, &topo
);
2442 cpu_slot
= pc_find_cpu_slot(MACHINE(pcms
), cpu
->apic_id
, &idx
);
2444 MachineState
*ms
= MACHINE(pcms
);
2446 x86_topo_ids_from_apicid(cpu
->apic_id
, pcms
->smp_dies
,
2447 smp_cores
, smp_threads
, &topo
);
2449 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
2450 " APIC ID %" PRIu32
", valid index range 0:%d",
2451 topo
.pkg_id
, topo
.die_id
, topo
.core_id
, topo
.smt_id
,
2452 cpu
->apic_id
, ms
->possible_cpus
->len
- 1);
2456 if (cpu_slot
->cpu
) {
2457 error_setg(errp
, "CPU[%d] with APIC ID %" PRIu32
" exists",
2462 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
2463 * so that machine_query_hotpluggable_cpus would show correct values
2465 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2466 * once -smp refactoring is complete and there will be CPU private
2467 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2468 x86_topo_ids_from_apicid(cpu
->apic_id
, pcms
->smp_dies
,
2469 smp_cores
, smp_threads
, &topo
);
2470 if (cpu
->socket_id
!= -1 && cpu
->socket_id
!= topo
.pkg_id
) {
2471 error_setg(errp
, "property socket-id: %u doesn't match set apic-id:"
2472 " 0x%x (socket-id: %u)", cpu
->socket_id
, cpu
->apic_id
, topo
.pkg_id
);
2475 cpu
->socket_id
= topo
.pkg_id
;
2477 if (cpu
->die_id
!= -1 && cpu
->die_id
!= topo
.die_id
) {
2478 error_setg(errp
, "property die-id: %u doesn't match set apic-id:"
2479 " 0x%x (die-id: %u)", cpu
->die_id
, cpu
->apic_id
, topo
.die_id
);
2482 cpu
->die_id
= topo
.die_id
;
2484 if (cpu
->core_id
!= -1 && cpu
->core_id
!= topo
.core_id
) {
2485 error_setg(errp
, "property core-id: %u doesn't match set apic-id:"
2486 " 0x%x (core-id: %u)", cpu
->core_id
, cpu
->apic_id
, topo
.core_id
);
2489 cpu
->core_id
= topo
.core_id
;
2491 if (cpu
->thread_id
!= -1 && cpu
->thread_id
!= topo
.smt_id
) {
2492 error_setg(errp
, "property thread-id: %u doesn't match set apic-id:"
2493 " 0x%x (thread-id: %u)", cpu
->thread_id
, cpu
->apic_id
, topo
.smt_id
);
2496 cpu
->thread_id
= topo
.smt_id
;
2498 if (hyperv_feat_enabled(cpu
, HYPERV_FEAT_VPINDEX
) &&
2499 !kvm_hv_vpindex_settable()) {
2500 error_setg(errp
, "kernel doesn't allow setting HyperV VP_INDEX");
2505 cs
->cpu_index
= idx
;
2507 numa_cpu_pre_plug(cpu_slot
, dev
, errp
);
2510 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler
*hotplug_dev
,
2511 DeviceState
*dev
, Error
**errp
)
2513 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2514 Error
*local_err
= NULL
;
2516 if (!hotplug_dev2
) {
2518 * Without a bus hotplug handler, we cannot control the plug/unplug
2519 * order. This should never be the case on x86, however better add
2522 error_setg(errp
, "virtio-pmem-pci not supported on this bus.");
2526 * First, see if we can plug this memory device at all. If that
2527 * succeeds, branch of to the actual hotplug handler.
2529 memory_device_pre_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
), NULL
,
2532 hotplug_handler_pre_plug(hotplug_dev2
, dev
, &local_err
);
2534 error_propagate(errp
, local_err
);
2537 static void pc_virtio_pmem_pci_plug(HotplugHandler
*hotplug_dev
,
2538 DeviceState
*dev
, Error
**errp
)
2540 HotplugHandler
*hotplug_dev2
= qdev_get_bus_hotplug_handler(dev
);
2541 Error
*local_err
= NULL
;
2544 * Plug the memory device first and then branch off to the actual
2545 * hotplug handler. If that one fails, we can easily undo the memory
2548 memory_device_plug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2549 hotplug_handler_plug(hotplug_dev2
, dev
, &local_err
);
2551 memory_device_unplug(MEMORY_DEVICE(dev
), MACHINE(hotplug_dev
));
2553 error_propagate(errp
, local_err
);
2556 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler
*hotplug_dev
,
2557 DeviceState
*dev
, Error
**errp
)
2559 /* We don't support virtio pmem hot unplug */
2560 error_setg(errp
, "virtio pmem device unplug not supported.");
2563 static void pc_virtio_pmem_pci_unplug(HotplugHandler
*hotplug_dev
,
2564 DeviceState
*dev
, Error
**errp
)
2566 /* We don't support virtio pmem hot unplug */
2569 static void pc_machine_device_pre_plug_cb(HotplugHandler
*hotplug_dev
,
2570 DeviceState
*dev
, Error
**errp
)
2572 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2573 pc_memory_pre_plug(hotplug_dev
, dev
, errp
);
2574 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2575 pc_cpu_pre_plug(hotplug_dev
, dev
, errp
);
2576 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
)) {
2577 pc_virtio_pmem_pci_pre_plug(hotplug_dev
, dev
, errp
);
2581 static void pc_machine_device_plug_cb(HotplugHandler
*hotplug_dev
,
2582 DeviceState
*dev
, Error
**errp
)
2584 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2585 pc_memory_plug(hotplug_dev
, dev
, errp
);
2586 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2587 pc_cpu_plug(hotplug_dev
, dev
, errp
);
2588 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
)) {
2589 pc_virtio_pmem_pci_plug(hotplug_dev
, dev
, errp
);
2593 static void pc_machine_device_unplug_request_cb(HotplugHandler
*hotplug_dev
,
2594 DeviceState
*dev
, Error
**errp
)
2596 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2597 pc_memory_unplug_request(hotplug_dev
, dev
, errp
);
2598 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2599 pc_cpu_unplug_request_cb(hotplug_dev
, dev
, errp
);
2600 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
)) {
2601 pc_virtio_pmem_pci_unplug_request(hotplug_dev
, dev
, errp
);
2603 error_setg(errp
, "acpi: device unplug request for not supported device"
2604 " type: %s", object_get_typename(OBJECT(dev
)));
2608 static void pc_machine_device_unplug_cb(HotplugHandler
*hotplug_dev
,
2609 DeviceState
*dev
, Error
**errp
)
2611 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2612 pc_memory_unplug(hotplug_dev
, dev
, errp
);
2613 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_CPU
)) {
2614 pc_cpu_unplug_cb(hotplug_dev
, dev
, errp
);
2615 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
)) {
2616 pc_virtio_pmem_pci_unplug(hotplug_dev
, dev
, errp
);
2618 error_setg(errp
, "acpi: device unplug for not supported device"
2619 " type: %s", object_get_typename(OBJECT(dev
)));
2623 static HotplugHandler
*pc_get_hotplug_handler(MachineState
*machine
,
2626 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2627 object_dynamic_cast(OBJECT(dev
), TYPE_CPU
) ||
2628 object_dynamic_cast(OBJECT(dev
), TYPE_VIRTIO_PMEM_PCI
)) {
2629 return HOTPLUG_HANDLER(machine
);
2636 pc_machine_get_device_memory_region_size(Object
*obj
, Visitor
*v
,
2637 const char *name
, void *opaque
,
2640 MachineState
*ms
= MACHINE(obj
);
2643 if (ms
->device_memory
) {
2644 value
= memory_region_size(&ms
->device_memory
->mr
);
2647 visit_type_int(v
, name
, &value
, errp
);
2650 static void pc_machine_get_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2651 const char *name
, void *opaque
,
2654 PCMachineState
*pcms
= PC_MACHINE(obj
);
2655 uint64_t value
= pcms
->max_ram_below_4g
;
2657 visit_type_size(v
, name
, &value
, errp
);
2660 static void pc_machine_set_max_ram_below_4g(Object
*obj
, Visitor
*v
,
2661 const char *name
, void *opaque
,
2664 PCMachineState
*pcms
= PC_MACHINE(obj
);
2665 Error
*error
= NULL
;
2668 visit_type_size(v
, name
, &value
, &error
);
2670 error_propagate(errp
, error
);
2673 if (value
> 4 * GiB
) {
2675 "Machine option 'max-ram-below-4g=%"PRIu64
2676 "' expects size less than or equal to 4G", value
);
2677 error_propagate(errp
, error
);
2681 if (value
< 1 * MiB
) {
2682 warn_report("Only %" PRIu64
" bytes of RAM below the 4GiB boundary,"
2683 "BIOS may not work with less than 1MiB", value
);
2686 pcms
->max_ram_below_4g
= value
;
2689 static void pc_machine_get_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2690 void *opaque
, Error
**errp
)
2692 PCMachineState
*pcms
= PC_MACHINE(obj
);
2693 OnOffAuto vmport
= pcms
->vmport
;
2695 visit_type_OnOffAuto(v
, name
, &vmport
, errp
);
2698 static void pc_machine_set_vmport(Object
*obj
, Visitor
*v
, const char *name
,
2699 void *opaque
, Error
**errp
)
2701 PCMachineState
*pcms
= PC_MACHINE(obj
);
2703 visit_type_OnOffAuto(v
, name
, &pcms
->vmport
, errp
);
2706 bool pc_machine_is_smm_enabled(PCMachineState
*pcms
)
2708 bool smm_available
= false;
2710 if (pcms
->smm
== ON_OFF_AUTO_OFF
) {
2714 if (tcg_enabled() || qtest_enabled()) {
2715 smm_available
= true;
2716 } else if (kvm_enabled()) {
2717 smm_available
= kvm_has_smm();
2720 if (smm_available
) {
2724 if (pcms
->smm
== ON_OFF_AUTO_ON
) {
2725 error_report("System Management Mode not supported by this hypervisor.");
2731 static void pc_machine_get_smm(Object
*obj
, Visitor
*v
, const char *name
,
2732 void *opaque
, Error
**errp
)
2734 PCMachineState
*pcms
= PC_MACHINE(obj
);
2735 OnOffAuto smm
= pcms
->smm
;
2737 visit_type_OnOffAuto(v
, name
, &smm
, errp
);
2740 static void pc_machine_set_smm(Object
*obj
, Visitor
*v
, const char *name
,
2741 void *opaque
, Error
**errp
)
2743 PCMachineState
*pcms
= PC_MACHINE(obj
);
2745 visit_type_OnOffAuto(v
, name
, &pcms
->smm
, errp
);
2748 static bool pc_machine_get_smbus(Object
*obj
, Error
**errp
)
2750 PCMachineState
*pcms
= PC_MACHINE(obj
);
2752 return pcms
->smbus_enabled
;
2755 static void pc_machine_set_smbus(Object
*obj
, bool value
, Error
**errp
)
2757 PCMachineState
*pcms
= PC_MACHINE(obj
);
2759 pcms
->smbus_enabled
= value
;
2762 static bool pc_machine_get_sata(Object
*obj
, Error
**errp
)
2764 PCMachineState
*pcms
= PC_MACHINE(obj
);
2766 return pcms
->sata_enabled
;
2769 static void pc_machine_set_sata(Object
*obj
, bool value
, Error
**errp
)
2771 PCMachineState
*pcms
= PC_MACHINE(obj
);
2773 pcms
->sata_enabled
= value
;
2776 static bool pc_machine_get_pit(Object
*obj
, Error
**errp
)
2778 PCMachineState
*pcms
= PC_MACHINE(obj
);
2780 return pcms
->pit_enabled
;
2783 static void pc_machine_set_pit(Object
*obj
, bool value
, Error
**errp
)
2785 PCMachineState
*pcms
= PC_MACHINE(obj
);
2787 pcms
->pit_enabled
= value
;
2790 static void pc_machine_initfn(Object
*obj
)
2792 PCMachineState
*pcms
= PC_MACHINE(obj
);
2794 pcms
->max_ram_below_4g
= 0; /* use default */
2795 pcms
->smm
= ON_OFF_AUTO_AUTO
;
2796 pcms
->vmport
= ON_OFF_AUTO_AUTO
;
2797 /* acpi build is enabled by default if machine supports it */
2798 pcms
->acpi_build_enabled
= PC_MACHINE_GET_CLASS(pcms
)->has_acpi_build
;
2799 pcms
->smbus_enabled
= true;
2800 pcms
->sata_enabled
= true;
2801 pcms
->pit_enabled
= true;
2804 pc_system_flash_create(pcms
);
2807 static void pc_machine_reset(MachineState
*machine
)
2812 qemu_devices_reset();
2814 /* Reset APIC after devices have been reset to cancel
2815 * any changes that qemu_devices_reset() might have done.
2820 if (cpu
->apic_state
) {
2821 device_reset(cpu
->apic_state
);
2826 static CpuInstanceProperties
2827 pc_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
2829 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2830 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
2832 assert(cpu_index
< possible_cpus
->len
);
2833 return possible_cpus
->cpus
[cpu_index
].props
;
2836 static int64_t pc_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
2838 X86CPUTopoInfo topo
;
2839 PCMachineState
*pcms
= PC_MACHINE(ms
);
2841 assert(idx
< ms
->possible_cpus
->len
);
2842 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[idx
].arch_id
,
2843 pcms
->smp_dies
, ms
->smp
.cores
,
2844 ms
->smp
.threads
, &topo
);
2845 return topo
.pkg_id
% nb_numa_nodes
;
2848 static const CPUArchIdList
*pc_possible_cpu_arch_ids(MachineState
*ms
)
2850 PCMachineState
*pcms
= PC_MACHINE(ms
);
2852 unsigned int max_cpus
= ms
->smp
.max_cpus
;
2854 if (ms
->possible_cpus
) {
2856 * make sure that max_cpus hasn't changed since the first use, i.e.
2857 * -smp hasn't been parsed after it
2859 assert(ms
->possible_cpus
->len
== max_cpus
);
2860 return ms
->possible_cpus
;
2863 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
2864 sizeof(CPUArchId
) * max_cpus
);
2865 ms
->possible_cpus
->len
= max_cpus
;
2866 for (i
= 0; i
< ms
->possible_cpus
->len
; i
++) {
2867 X86CPUTopoInfo topo
;
2869 ms
->possible_cpus
->cpus
[i
].type
= ms
->cpu_type
;
2870 ms
->possible_cpus
->cpus
[i
].vcpus_count
= 1;
2871 ms
->possible_cpus
->cpus
[i
].arch_id
= x86_cpu_apic_id_from_index(pcms
, i
);
2872 x86_topo_ids_from_apicid(ms
->possible_cpus
->cpus
[i
].arch_id
,
2873 pcms
->smp_dies
, ms
->smp
.cores
,
2874 ms
->smp
.threads
, &topo
);
2875 ms
->possible_cpus
->cpus
[i
].props
.has_socket_id
= true;
2876 ms
->possible_cpus
->cpus
[i
].props
.socket_id
= topo
.pkg_id
;
2877 ms
->possible_cpus
->cpus
[i
].props
.has_die_id
= true;
2878 ms
->possible_cpus
->cpus
[i
].props
.die_id
= topo
.die_id
;
2879 ms
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
2880 ms
->possible_cpus
->cpus
[i
].props
.core_id
= topo
.core_id
;
2881 ms
->possible_cpus
->cpus
[i
].props
.has_thread_id
= true;
2882 ms
->possible_cpus
->cpus
[i
].props
.thread_id
= topo
.smt_id
;
2884 return ms
->possible_cpus
;
2887 static void x86_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2889 /* cpu index isn't used */
2893 X86CPU
*cpu
= X86_CPU(cs
);
2895 if (!cpu
->apic_state
) {
2896 cpu_interrupt(cs
, CPU_INTERRUPT_NMI
);
2898 apic_deliver_nmi(cpu
->apic_state
);
2903 static void pc_machine_class_init(ObjectClass
*oc
, void *data
)
2905 MachineClass
*mc
= MACHINE_CLASS(oc
);
2906 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(oc
);
2907 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
2908 NMIClass
*nc
= NMI_CLASS(oc
);
2910 pcmc
->pci_enabled
= true;
2911 pcmc
->has_acpi_build
= true;
2912 pcmc
->rsdp_in_ram
= true;
2913 pcmc
->smbios_defaults
= true;
2914 pcmc
->smbios_uuid_encoded
= true;
2915 pcmc
->gigabyte_align
= true;
2916 pcmc
->has_reserved_memory
= true;
2917 pcmc
->kvmclock_enabled
= true;
2918 pcmc
->enforce_aligned_dimm
= true;
2919 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2920 * to be used at the moment, 32K should be enough for a while. */
2921 pcmc
->acpi_data_size
= 0x20000 + 0x8000;
2922 pcmc
->save_tsc_khz
= true;
2923 pcmc
->linuxboot_dma_enabled
= true;
2924 pcmc
->pvh_enabled
= true;
2925 assert(!mc
->get_hotplug_handler
);
2926 mc
->get_hotplug_handler
= pc_get_hotplug_handler
;
2927 mc
->cpu_index_to_instance_props
= pc_cpu_index_to_props
;
2928 mc
->get_default_cpu_node_id
= pc_get_default_cpu_node_id
;
2929 mc
->possible_cpu_arch_ids
= pc_possible_cpu_arch_ids
;
2930 mc
->auto_enable_numa_with_memhp
= true;
2931 mc
->has_hotpluggable_cpus
= true;
2932 mc
->default_boot_order
= "cad";
2933 mc
->hot_add_cpu
= pc_hot_add_cpu
;
2934 mc
->smp_parse
= pc_smp_parse
;
2935 mc
->block_default_type
= IF_IDE
;
2937 mc
->reset
= pc_machine_reset
;
2938 hc
->pre_plug
= pc_machine_device_pre_plug_cb
;
2939 hc
->plug
= pc_machine_device_plug_cb
;
2940 hc
->unplug_request
= pc_machine_device_unplug_request_cb
;
2941 hc
->unplug
= pc_machine_device_unplug_cb
;
2942 nc
->nmi_monitor_handler
= x86_nmi
;
2943 mc
->default_cpu_type
= TARGET_DEFAULT_CPU_TYPE
;
2944 mc
->nvdimm_supported
= true;
2945 mc
->numa_mem_supported
= true;
2947 object_class_property_add(oc
, PC_MACHINE_DEVMEM_REGION_SIZE
, "int",
2948 pc_machine_get_device_memory_region_size
, NULL
,
2949 NULL
, NULL
, &error_abort
);
2951 object_class_property_add(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
, "size",
2952 pc_machine_get_max_ram_below_4g
, pc_machine_set_max_ram_below_4g
,
2953 NULL
, NULL
, &error_abort
);
2955 object_class_property_set_description(oc
, PC_MACHINE_MAX_RAM_BELOW_4G
,
2956 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort
);
2958 object_class_property_add(oc
, PC_MACHINE_SMM
, "OnOffAuto",
2959 pc_machine_get_smm
, pc_machine_set_smm
,
2960 NULL
, NULL
, &error_abort
);
2961 object_class_property_set_description(oc
, PC_MACHINE_SMM
,
2962 "Enable SMM (pc & q35)", &error_abort
);
2964 object_class_property_add(oc
, PC_MACHINE_VMPORT
, "OnOffAuto",
2965 pc_machine_get_vmport
, pc_machine_set_vmport
,
2966 NULL
, NULL
, &error_abort
);
2967 object_class_property_set_description(oc
, PC_MACHINE_VMPORT
,
2968 "Enable vmport (pc & q35)", &error_abort
);
2970 object_class_property_add_bool(oc
, PC_MACHINE_SMBUS
,
2971 pc_machine_get_smbus
, pc_machine_set_smbus
, &error_abort
);
2973 object_class_property_add_bool(oc
, PC_MACHINE_SATA
,
2974 pc_machine_get_sata
, pc_machine_set_sata
, &error_abort
);
2976 object_class_property_add_bool(oc
, PC_MACHINE_PIT
,
2977 pc_machine_get_pit
, pc_machine_set_pit
, &error_abort
);
2980 static const TypeInfo pc_machine_info
= {
2981 .name
= TYPE_PC_MACHINE
,
2982 .parent
= TYPE_MACHINE
,
2984 .instance_size
= sizeof(PCMachineState
),
2985 .instance_init
= pc_machine_initfn
,
2986 .class_size
= sizeof(PCMachineClass
),
2987 .class_init
= pc_machine_class_init
,
2988 .interfaces
= (InterfaceInfo
[]) {
2989 { TYPE_HOTPLUG_HANDLER
},
2995 static void pc_machine_register_types(void)
2997 type_register_static(&pc_machine_info
);
3000 type_init(pc_machine_register_types
)