1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
31 #include "target/i386/cpu.h"
32 #include "hw/misc/pvpanic.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/acpi/piix4.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/timer/mc146818rtc_regs.h"
49 #include "hw/mem/memory-device.h"
50 #include "sysemu/numa.h"
52 /* Supported chipsets: */
53 #include "hw/acpi/piix4.h"
54 #include "hw/acpi/pcihp.h"
55 #include "hw/i386/ich9.h"
56 #include "hw/pci/pci_bus.h"
57 #include "hw/pci-host/q35.h"
58 #include "hw/i386/x86-iommu.h"
60 #include "hw/acpi/aml-build.h"
61 #include "hw/acpi/utils.h"
62 #include "hw/acpi/pci.h"
64 #include "qom/qom-qobject.h"
65 #include "hw/i386/amd_iommu.h"
66 #include "hw/i386/intel_iommu.h"
68 #include "hw/acpi/ipmi.h"
70 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
71 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
72 * a little bit, there should be plenty of free space since the DSDT
73 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
75 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
76 #define ACPI_BUILD_ALIGN_SIZE 0x1000
78 #define ACPI_BUILD_TABLE_SIZE 0x20000
80 /* #define DEBUG_ACPI_BUILD */
81 #ifdef DEBUG_ACPI_BUILD
82 #define ACPI_BUILD_DPRINTF(fmt, ...) \
83 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
85 #define ACPI_BUILD_DPRINTF(fmt, ...)
88 /* Default IOAPIC ID */
89 #define ACPI_BUILD_IOAPIC_ID 0x0
91 typedef struct AcpiPmInfo
{
97 uint16_t cpu_hp_io_base
;
98 uint16_t pcihp_io_base
;
99 uint16_t pcihp_io_len
;
102 typedef struct AcpiMiscInfo
{
105 TPMVersion tpm_version
;
106 const unsigned char *dsdt_code
;
108 uint16_t pvpanic_port
;
109 uint16_t applesmc_io_base
;
112 typedef struct AcpiBuildPciBusHotplugState
{
113 GArray
*device_table
;
114 GArray
*notify_table
;
115 struct AcpiBuildPciBusHotplugState
*parent
;
116 bool pcihp_bridge_en
;
117 } AcpiBuildPciBusHotplugState
;
119 typedef struct FwCfgTPMConfig
{
120 uint32_t tpmppi_address
;
122 uint8_t tpmppi_version
;
123 } QEMU_PACKED FwCfgTPMConfig
;
125 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
);
127 static void init_common_fadt_data(MachineState
*ms
, Object
*o
,
130 uint32_t io
= object_property_get_uint(o
, ACPI_PM_PROP_PM_IO_BASE
, NULL
);
131 AmlAddressSpace as
= AML_AS_SYSTEM_IO
;
132 AcpiFadtData fadt
= {
135 (1 << ACPI_FADT_F_WBINVD
) |
136 (1 << ACPI_FADT_F_PROC_C1
) |
137 (1 << ACPI_FADT_F_SLP_BUTTON
) |
138 (1 << ACPI_FADT_F_RTC_S4
) |
139 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
) |
140 /* APIC destination mode ("Flat Logical") has an upper limit of 8
141 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
144 ((ms
->smp
.max_cpus
> 8) ?
145 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
) : 0),
146 .int_model
= 1 /* Multiple APIC */,
147 .rtc_century
= RTC_CENTURY
,
148 .plvl2_lat
= 0xfff /* C2 state not supported */,
149 .plvl3_lat
= 0xfff /* C3 state not supported */,
150 .smi_cmd
= ACPI_PORT_SMI_CMD
,
151 .sci_int
= object_property_get_uint(o
, ACPI_PM_PROP_SCI_INT
, NULL
),
153 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_ENABLE_CMD
, NULL
),
155 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_DISABLE_CMD
, NULL
),
156 .pm1a_evt
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
},
157 .pm1a_cnt
= { .space_id
= as
, .bit_width
= 2 * 8,
158 .address
= io
+ 0x04 },
159 .pm_tmr
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
+ 0x08 },
160 .gpe0_blk
= { .space_id
= as
, .bit_width
=
161 object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK_LEN
, NULL
) * 8,
162 .address
= object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK
, NULL
)
168 static Object
*object_resolve_type_unambiguous(const char *typename
)
171 Object
*o
= object_resolve_path_type("", typename
, &ambig
);
179 static void acpi_get_pm_info(MachineState
*machine
, AcpiPmInfo
*pm
)
181 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
182 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
183 Object
*obj
= piix
? piix
: lpc
;
185 pm
->cpu_hp_io_base
= 0;
186 pm
->pcihp_io_base
= 0;
187 pm
->pcihp_io_len
= 0;
190 init_common_fadt_data(machine
, obj
, &pm
->fadt
);
192 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
194 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
196 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
198 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
201 struct AcpiGenericAddress r
= { .space_id
= AML_AS_SYSTEM_IO
,
202 .bit_width
= 8, .address
= ICH9_RST_CNT_IOPORT
};
203 pm
->fadt
.reset_reg
= r
;
204 pm
->fadt
.reset_val
= 0xf;
205 pm
->fadt
.flags
|= 1 << ACPI_FADT_F_RESET_REG_SUP
;
206 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
209 /* The above need not be conditional on machine type because the reset port
210 * happens to be the same on PIIX (pc) and ICH9 (q35). */
211 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= RCR_IOPORT
);
213 /* Fill in optional s3/s4 related properties */
214 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
216 pm
->s3_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
218 pm
->s3_disabled
= false;
221 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
223 pm
->s4_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
225 pm
->s4_disabled
= false;
228 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
230 pm
->s4_val
= qnum_get_uint(qobject_to(QNum
, o
));
236 pm
->pcihp_bridge_en
=
237 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
241 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
243 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
244 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
245 assert(!!piix
!= !!lpc
);
248 info
->is_piix4
= true;
251 info
->is_piix4
= false;
254 info
->has_hpet
= hpet_find();
255 info
->tpm_version
= tpm_get_version(tpm_find());
256 info
->pvpanic_port
= pvpanic_port();
257 info
->applesmc_io_base
= applesmc_port();
261 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
262 * On i386 arch we only have two pci hosts, so we can look only for them.
264 static Object
*acpi_get_i386_pci_host(void)
268 host
= OBJECT_CHECK(PCIHostState
,
269 object_resolve_path("/machine/i440fx", NULL
),
270 TYPE_PCI_HOST_BRIDGE
);
272 host
= OBJECT_CHECK(PCIHostState
,
273 object_resolve_path("/machine/q35", NULL
),
274 TYPE_PCI_HOST_BRIDGE
);
280 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
284 pci_host
= acpi_get_i386_pci_host();
287 range_set_bounds1(hole
,
288 object_property_get_uint(pci_host
,
289 PCI_HOST_PROP_PCI_HOLE_START
,
291 object_property_get_uint(pci_host
,
292 PCI_HOST_PROP_PCI_HOLE_END
,
294 range_set_bounds1(hole64
,
295 object_property_get_uint(pci_host
,
296 PCI_HOST_PROP_PCI_HOLE64_START
,
298 object_property_get_uint(pci_host
,
299 PCI_HOST_PROP_PCI_HOLE64_END
,
303 static void acpi_align_size(GArray
*blob
, unsigned align
)
305 /* Align size to multiple of given size. This reduces the chance
306 * we need to change size in the future (breaking cross version migration).
308 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
313 build_facs(GArray
*table_data
)
315 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
316 memcpy(&facs
->signature
, "FACS", 4);
317 facs
->length
= cpu_to_le32(sizeof(*facs
));
320 void pc_madt_cpu_entry(AcpiDeviceIf
*adev
, int uid
,
321 const CPUArchIdList
*apic_ids
, GArray
*entry
)
323 uint32_t apic_id
= apic_ids
->cpus
[uid
].arch_id
;
325 /* ACPI spec says that LAPIC entry for non present
326 * CPU may be omitted from MADT or it must be marked
327 * as disabled. However omitting non present CPU from
328 * MADT breaks hotplug on linux. So possible CPUs
329 * should be put in MADT but kept disabled.
332 AcpiMadtProcessorApic
*apic
= acpi_data_push(entry
, sizeof *apic
);
334 apic
->type
= ACPI_APIC_PROCESSOR
;
335 apic
->length
= sizeof(*apic
);
336 apic
->processor_id
= uid
;
337 apic
->local_apic_id
= apic_id
;
338 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
339 apic
->flags
= cpu_to_le32(1);
341 apic
->flags
= cpu_to_le32(0);
344 AcpiMadtProcessorX2Apic
*apic
= acpi_data_push(entry
, sizeof *apic
);
346 apic
->type
= ACPI_APIC_LOCAL_X2APIC
;
347 apic
->length
= sizeof(*apic
);
348 apic
->uid
= cpu_to_le32(uid
);
349 apic
->x2apic_id
= cpu_to_le32(apic_id
);
350 if (apic_ids
->cpus
[uid
].cpu
!= NULL
) {
351 apic
->flags
= cpu_to_le32(1);
353 apic
->flags
= cpu_to_le32(0);
359 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
361 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
362 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
363 int madt_start
= table_data
->len
;
364 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_GET_CLASS(pcms
->acpi_dev
);
365 AcpiDeviceIf
*adev
= ACPI_DEVICE_IF(pcms
->acpi_dev
);
366 bool x2apic_mode
= false;
368 AcpiMultipleApicTable
*madt
;
369 AcpiMadtIoApic
*io_apic
;
370 AcpiMadtIntsrcovr
*intsrcovr
;
373 madt
= acpi_data_push(table_data
, sizeof *madt
);
374 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
375 madt
->flags
= cpu_to_le32(1);
377 for (i
= 0; i
< apic_ids
->len
; i
++) {
378 adevc
->madt_cpu(adev
, i
, apic_ids
, table_data
);
379 if (apic_ids
->cpus
[i
].arch_id
> 254) {
384 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
385 io_apic
->type
= ACPI_APIC_IO
;
386 io_apic
->length
= sizeof(*io_apic
);
387 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
388 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
389 io_apic
->interrupt
= cpu_to_le32(0);
391 if (pcms
->apic_xrupt_override
) {
392 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
393 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
394 intsrcovr
->length
= sizeof(*intsrcovr
);
395 intsrcovr
->source
= 0;
396 intsrcovr
->gsi
= cpu_to_le32(2);
397 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
399 for (i
= 1; i
< 16; i
++) {
400 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
401 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
402 /* No need for a INT source override structure. */
405 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
406 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
407 intsrcovr
->length
= sizeof(*intsrcovr
);
408 intsrcovr
->source
= i
;
409 intsrcovr
->gsi
= cpu_to_le32(i
);
410 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
414 AcpiMadtLocalX2ApicNmi
*local_nmi
;
416 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
417 local_nmi
->type
= ACPI_APIC_LOCAL_X2APIC_NMI
;
418 local_nmi
->length
= sizeof(*local_nmi
);
419 local_nmi
->uid
= 0xFFFFFFFF; /* all processors */
420 local_nmi
->flags
= cpu_to_le16(0);
421 local_nmi
->lint
= 1; /* ACPI_LINT1 */
423 AcpiMadtLocalNmi
*local_nmi
;
425 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
426 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
427 local_nmi
->length
= sizeof(*local_nmi
);
428 local_nmi
->processor_id
= 0xff; /* all processors */
429 local_nmi
->flags
= cpu_to_le16(0);
430 local_nmi
->lint
= 1; /* ACPI_LINT1 */
433 build_header(linker
, table_data
,
434 (void *)(table_data
->data
+ madt_start
), "APIC",
435 table_data
->len
- madt_start
, 1, NULL
, NULL
);
438 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
441 int32_t devfn
= PCI_DEVFN(slot
, 0);
443 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
444 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
445 aml_append(method
, if_ctx
);
448 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
449 bool pcihp_bridge_en
)
451 Aml
*dev
, *notify_method
= NULL
, *method
;
456 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
458 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
460 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
461 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
464 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
467 PCIDevice
*pdev
= bus
->devices
[i
];
468 int slot
= PCI_SLOT(i
);
469 bool hotplug_enabled_dev
;
473 if (bsel
) { /* add hotplug slots for non present devices */
474 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
475 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
476 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
477 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
479 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
481 aml_append(dev
, method
);
482 aml_append(parent_scope
, dev
);
484 build_append_pcihp_notify_entry(notify_method
, slot
);
489 pc
= PCI_DEVICE_GET_CLASS(pdev
);
490 dc
= DEVICE_GET_CLASS(pdev
);
492 /* When hotplug for bridges is enabled, bridges are
493 * described in ACPI separately (see build_pci_bus_end).
494 * In this case they aren't themselves hot-pluggable.
495 * Hotplugged bridges *are* hot-pluggable.
497 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
498 !DEVICE(pdev
)->hotplugged
;
500 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
502 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
506 /* start to compose PCI slot descriptor */
507 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
508 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
510 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
511 /* add VGA specific AML methods */
514 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
520 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
521 aml_append(method
, aml_return(aml_int(0)));
522 aml_append(dev
, method
);
524 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
525 aml_append(method
, aml_return(aml_int(0)));
526 aml_append(dev
, method
);
528 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
529 aml_append(method
, aml_return(aml_int(s3d
)));
530 aml_append(dev
, method
);
531 } else if (hotplug_enabled_dev
) {
532 /* add _SUN/_EJ0 to make slot hotpluggable */
533 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
535 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
537 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
539 aml_append(dev
, method
);
542 build_append_pcihp_notify_entry(notify_method
, slot
);
544 } else if (bridge_in_acpi
) {
546 * device is coldplugged bridge,
547 * add child device descriptions into its scope
549 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
551 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
553 /* slot descriptor has been composed, add it into parent context */
554 aml_append(parent_scope
, dev
);
558 aml_append(parent_scope
, notify_method
);
561 /* Append PCNT method to notify about events on local and child buses.
562 * Add unconditionally for root since DSDT expects it.
564 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
566 /* If bus supports hotplug select it and notify about local events */
568 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
570 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
572 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
575 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
579 /* Notify about child bus events in any case */
580 if (pcihp_bridge_en
) {
581 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
582 int32_t devfn
= sec
->parent_dev
->devfn
;
584 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
588 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
591 aml_append(parent_scope
, method
);
597 * @link_name: link name for PCI route entry
599 * build AML package containing a PCI route entry for @link_name
601 static Aml
*build_prt_entry(const char *link_name
)
603 Aml
*a_zero
= aml_int(0);
604 Aml
*pkg
= aml_package(4);
605 aml_append(pkg
, a_zero
);
606 aml_append(pkg
, a_zero
);
607 aml_append(pkg
, aml_name("%s", link_name
));
608 aml_append(pkg
, a_zero
);
613 * initialize_route - Initialize the interrupt routing rule
614 * through a specific LINK:
615 * if (lnk_idx == idx)
616 * route using link 'link_name'
618 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
619 Aml
*lnk_idx
, int idx
)
621 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
622 Aml
*pkg
= build_prt_entry(link_name
);
624 aml_append(if_ctx
, aml_store(pkg
, route
));
630 * build_prt - Define interrupt rounting rules
632 * Returns an array of 128 routes, one for each device,
633 * based on device location.
634 * The main goal is to equaly distribute the interrupts
635 * over the 4 existing ACPI links (works only for i440fx).
636 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
639 static Aml
*build_prt(bool is_pci0_prt
)
641 Aml
*method
, *while_ctx
, *pin
, *res
;
643 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
646 aml_append(method
, aml_store(aml_package(128), res
));
647 aml_append(method
, aml_store(aml_int(0), pin
));
649 /* while (pin < 128) */
650 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
652 Aml
*slot
= aml_local(2);
653 Aml
*lnk_idx
= aml_local(3);
654 Aml
*route
= aml_local(4);
656 /* slot = pin >> 2 */
657 aml_append(while_ctx
,
658 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
659 /* lnk_idx = (slot + pin) & 3 */
660 aml_append(while_ctx
,
661 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
664 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
665 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
667 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
669 /* device 1 is the power-management device, needs SCI */
670 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
672 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
675 aml_store(build_prt_entry("LNKS"), route
));
677 aml_append(if_device_1
, if_pin_4
);
678 else_pin_4
= aml_else();
680 aml_append(else_pin_4
,
681 aml_store(build_prt_entry("LNKA"), route
));
683 aml_append(if_device_1
, else_pin_4
);
685 aml_append(while_ctx
, if_device_1
);
687 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
689 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
690 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
692 /* route[0] = 0x[slot]FFFF */
693 aml_append(while_ctx
,
694 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
696 aml_index(route
, aml_int(0))));
697 /* route[1] = pin & 3 */
698 aml_append(while_ctx
,
699 aml_store(aml_and(pin
, aml_int(3), NULL
),
700 aml_index(route
, aml_int(1))));
701 /* res[pin] = route */
702 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
704 aml_append(while_ctx
, aml_increment(pin
));
706 aml_append(method
, while_ctx
);
708 aml_append(method
, aml_return(res
));
713 typedef struct CrsRangeEntry
{
718 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
720 CrsRangeEntry
*entry
;
722 entry
= g_malloc(sizeof(*entry
));
724 entry
->limit
= limit
;
726 g_ptr_array_add(ranges
, entry
);
729 static void crs_range_free(gpointer data
)
731 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
735 typedef struct CrsRangeSet
{
736 GPtrArray
*io_ranges
;
737 GPtrArray
*mem_ranges
;
738 GPtrArray
*mem_64bit_ranges
;
741 static void crs_range_set_init(CrsRangeSet
*range_set
)
743 range_set
->io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
744 range_set
->mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
745 range_set
->mem_64bit_ranges
=
746 g_ptr_array_new_with_free_func(crs_range_free
);
749 static void crs_range_set_free(CrsRangeSet
*range_set
)
751 g_ptr_array_free(range_set
->io_ranges
, true);
752 g_ptr_array_free(range_set
->mem_ranges
, true);
753 g_ptr_array_free(range_set
->mem_64bit_ranges
, true);
756 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
758 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
759 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
761 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
766 * interval, computes the 'free' ranges from the same interval.
767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
768 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
770 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
771 uint64_t start
, uint64_t end
)
773 GPtrArray
*free_ranges
= g_ptr_array_new();
774 uint64_t free_base
= start
;
777 g_ptr_array_sort(ranges
, crs_range_compare
);
778 for (i
= 0; i
< ranges
->len
; i
++) {
779 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
781 if (free_base
< used
->base
) {
782 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
785 free_base
= used
->limit
+ 1;
788 if (free_base
< end
) {
789 crs_range_insert(free_ranges
, free_base
, end
);
792 g_ptr_array_set_size(ranges
, 0);
793 for (i
= 0; i
< free_ranges
->len
; i
++) {
794 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
797 g_ptr_array_free(free_ranges
, true);
801 * crs_range_merge - merges adjacent ranges in the given array.
802 * Array elements are deleted and replaced with the merged ranges.
804 static void crs_range_merge(GPtrArray
*range
)
806 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
807 CrsRangeEntry
*entry
;
808 uint64_t range_base
, range_limit
;
815 g_ptr_array_sort(range
, crs_range_compare
);
817 entry
= g_ptr_array_index(range
, 0);
818 range_base
= entry
->base
;
819 range_limit
= entry
->limit
;
820 for (i
= 1; i
< range
->len
; i
++) {
821 entry
= g_ptr_array_index(range
, i
);
822 if (entry
->base
- 1 == range_limit
) {
823 range_limit
= entry
->limit
;
825 crs_range_insert(tmp
, range_base
, range_limit
);
826 range_base
= entry
->base
;
827 range_limit
= entry
->limit
;
830 crs_range_insert(tmp
, range_base
, range_limit
);
832 g_ptr_array_set_size(range
, 0);
833 for (i
= 0; i
< tmp
->len
; i
++) {
834 entry
= g_ptr_array_index(tmp
, i
);
835 crs_range_insert(range
, entry
->base
, entry
->limit
);
837 g_ptr_array_free(tmp
, true);
840 static Aml
*build_crs(PCIHostState
*host
, CrsRangeSet
*range_set
)
842 Aml
*crs
= aml_resource_template();
843 CrsRangeSet temp_range_set
;
844 CrsRangeEntry
*entry
;
845 uint8_t max_bus
= pci_bus_num(host
->bus
);
850 crs_range_set_init(&temp_range_set
);
851 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
852 uint64_t range_base
, range_limit
;
853 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
859 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
860 PCIIORegion
*r
= &dev
->io_regions
[i
];
862 range_base
= r
->addr
;
863 range_limit
= r
->addr
+ r
->size
- 1;
866 * Work-around for old bioses
867 * that do not support multiple root buses
869 if (!range_base
|| range_base
> range_limit
) {
873 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
874 crs_range_insert(temp_range_set
.io_ranges
,
875 range_base
, range_limit
);
876 } else { /* "memory" */
877 crs_range_insert(temp_range_set
.mem_ranges
,
878 range_base
, range_limit
);
882 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
883 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
884 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
885 if (subordinate
> max_bus
) {
886 max_bus
= subordinate
;
889 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
890 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
893 * Work-around for old bioses
894 * that do not support multiple root buses
896 if (range_base
&& range_base
<= range_limit
) {
897 crs_range_insert(temp_range_set
.io_ranges
,
898 range_base
, range_limit
);
902 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
904 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
907 * Work-around for old bioses
908 * that do not support multiple root buses
910 if (range_base
&& range_base
<= range_limit
) {
911 uint64_t length
= range_limit
- range_base
+ 1;
912 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
913 crs_range_insert(temp_range_set
.mem_ranges
,
914 range_base
, range_limit
);
916 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
917 range_base
, range_limit
);
922 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
924 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
927 * Work-around for old bioses
928 * that do not support multiple root buses
930 if (range_base
&& range_base
<= range_limit
) {
931 uint64_t length
= range_limit
- range_base
+ 1;
932 if (range_limit
<= UINT32_MAX
&& length
<= UINT32_MAX
) {
933 crs_range_insert(temp_range_set
.mem_ranges
,
934 range_base
, range_limit
);
936 crs_range_insert(temp_range_set
.mem_64bit_ranges
,
937 range_base
, range_limit
);
943 crs_range_merge(temp_range_set
.io_ranges
);
944 for (i
= 0; i
< temp_range_set
.io_ranges
->len
; i
++) {
945 entry
= g_ptr_array_index(temp_range_set
.io_ranges
, i
);
947 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
948 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
949 0, entry
->base
, entry
->limit
, 0,
950 entry
->limit
- entry
->base
+ 1));
951 crs_range_insert(range_set
->io_ranges
, entry
->base
, entry
->limit
);
954 crs_range_merge(temp_range_set
.mem_ranges
);
955 for (i
= 0; i
< temp_range_set
.mem_ranges
->len
; i
++) {
956 entry
= g_ptr_array_index(temp_range_set
.mem_ranges
, i
);
958 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
959 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
961 0, entry
->base
, entry
->limit
, 0,
962 entry
->limit
- entry
->base
+ 1));
963 crs_range_insert(range_set
->mem_ranges
, entry
->base
, entry
->limit
);
966 crs_range_merge(temp_range_set
.mem_64bit_ranges
);
967 for (i
= 0; i
< temp_range_set
.mem_64bit_ranges
->len
; i
++) {
968 entry
= g_ptr_array_index(temp_range_set
.mem_64bit_ranges
, i
);
970 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
971 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
973 0, entry
->base
, entry
->limit
, 0,
974 entry
->limit
- entry
->base
+ 1));
975 crs_range_insert(range_set
->mem_64bit_ranges
,
976 entry
->base
, entry
->limit
);
979 crs_range_set_free(&temp_range_set
);
982 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
984 pci_bus_num(host
->bus
),
987 max_bus
- pci_bus_num(host
->bus
) + 1));
992 static void build_hpet_aml(Aml
*table
)
998 Aml
*scope
= aml_scope("_SB");
999 Aml
*dev
= aml_device("HPET");
1000 Aml
*zero
= aml_int(0);
1001 Aml
*id
= aml_local(0);
1002 Aml
*period
= aml_local(1);
1004 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1005 aml_append(dev
, aml_name_decl("_UID", zero
));
1008 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1010 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1011 aml_append(field
, aml_named_field("VEND", 32));
1012 aml_append(field
, aml_named_field("PRD", 32));
1013 aml_append(dev
, field
);
1015 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1016 aml_append(method
, aml_store(aml_name("VEND"), id
));
1017 aml_append(method
, aml_store(aml_name("PRD"), period
));
1018 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1019 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1020 aml_equal(id
, aml_int(0xffff))));
1022 aml_append(if_ctx
, aml_return(zero
));
1024 aml_append(method
, if_ctx
);
1026 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1027 aml_lgreater(period
, aml_int(100000000))));
1029 aml_append(if_ctx
, aml_return(zero
));
1031 aml_append(method
, if_ctx
);
1033 aml_append(method
, aml_return(aml_int(0x0F)));
1034 aml_append(dev
, method
);
1036 crs
= aml_resource_template();
1037 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1038 aml_append(dev
, aml_name_decl("_CRS", crs
));
1040 aml_append(scope
, dev
);
1041 aml_append(table
, scope
);
1044 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1047 uint8_t maxc
, maxh
, maxs
;
1049 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1051 dev
= aml_device("FLP%c", 'A' + idx
);
1053 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1055 fdi
= aml_package(16);
1056 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1058 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1060 * the values below are the limits of the drive, and are thus independent
1061 * of the inserted media
1063 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1064 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1065 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1067 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1068 * the drive type, so shall we
1070 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1071 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1072 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1073 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1074 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1075 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1076 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1077 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1078 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1079 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1080 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1082 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1086 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1092 #define ACPI_FDE_MAX_FD 4
1093 uint32_t fde_buf
[5] = {
1094 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1095 cpu_to_le32(2) /* tape presence (2 == never present) */
1098 dev
= aml_device("FDC0");
1099 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1101 crs
= aml_resource_template();
1102 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1103 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1104 aml_append(crs
, aml_irq_no_flags(6));
1106 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1107 aml_append(dev
, aml_name_decl("_CRS", crs
));
1109 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1110 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1112 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1113 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1114 aml_append(dev
, build_fdinfo_aml(i
, type
));
1117 aml_append(dev
, aml_name_decl("_FDE",
1118 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1123 static Aml
*build_rtc_device_aml(void)
1128 dev
= aml_device("RTC");
1129 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1130 crs
= aml_resource_template();
1131 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1132 aml_append(crs
, aml_irq_no_flags(8));
1133 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1134 aml_append(dev
, aml_name_decl("_CRS", crs
));
1139 static Aml
*build_kbd_device_aml(void)
1145 dev
= aml_device("KBD");
1146 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1148 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1149 aml_append(method
, aml_return(aml_int(0x0f)));
1150 aml_append(dev
, method
);
1152 crs
= aml_resource_template();
1153 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1154 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1155 aml_append(crs
, aml_irq_no_flags(1));
1156 aml_append(dev
, aml_name_decl("_CRS", crs
));
1161 static Aml
*build_mouse_device_aml(void)
1167 dev
= aml_device("MOU");
1168 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1170 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1171 aml_append(method
, aml_return(aml_int(0x0f)));
1172 aml_append(dev
, method
);
1174 crs
= aml_resource_template();
1175 aml_append(crs
, aml_irq_no_flags(12));
1176 aml_append(dev
, aml_name_decl("_CRS", crs
));
1181 static Aml
*build_lpt_device_aml(void)
1188 Aml
*zero
= aml_int(0);
1189 Aml
*is_present
= aml_local(0);
1191 dev
= aml_device("LPT");
1192 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1194 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1195 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1196 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1198 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1200 aml_append(method
, if_ctx
);
1201 else_ctx
= aml_else();
1203 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1205 aml_append(method
, else_ctx
);
1206 aml_append(dev
, method
);
1208 crs
= aml_resource_template();
1209 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1210 aml_append(crs
, aml_irq_no_flags(7));
1211 aml_append(dev
, aml_name_decl("_CRS", crs
));
1216 static Aml
*build_com_device_aml(uint8_t uid
)
1223 Aml
*zero
= aml_int(0);
1224 Aml
*is_present
= aml_local(0);
1225 const char *enabled_field
= "CAEN";
1227 uint16_t io_port
= 0x03F8;
1229 assert(uid
== 1 || uid
== 2);
1231 enabled_field
= "CBEN";
1236 dev
= aml_device("COM%d", uid
);
1237 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1238 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1240 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1241 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1242 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1244 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1246 aml_append(method
, if_ctx
);
1247 else_ctx
= aml_else();
1249 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1251 aml_append(method
, else_ctx
);
1252 aml_append(dev
, method
);
1254 crs
= aml_resource_template();
1255 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1256 aml_append(crs
, aml_irq_no_flags(irq
));
1257 aml_append(dev
, aml_name_decl("_CRS", crs
));
1262 static void build_isa_devices_aml(Aml
*table
)
1264 ISADevice
*fdc
= pc_find_fdc0();
1267 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1268 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
1270 aml_append(scope
, build_rtc_device_aml());
1271 aml_append(scope
, build_kbd_device_aml());
1272 aml_append(scope
, build_mouse_device_aml());
1274 aml_append(scope
, build_fdc_device_aml(fdc
));
1276 aml_append(scope
, build_lpt_device_aml());
1277 aml_append(scope
, build_com_device_aml(1));
1278 aml_append(scope
, build_com_device_aml(2));
1281 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1283 error_report("No ISA bus, unable to define IPMI ACPI data");
1285 build_acpi_ipmi_devices(scope
, BUS(obj
));
1288 aml_append(table
, scope
);
1291 static void build_dbg_aml(Aml
*table
)
1296 Aml
*scope
= aml_scope("\\");
1297 Aml
*buf
= aml_local(0);
1298 Aml
*len
= aml_local(1);
1299 Aml
*idx
= aml_local(2);
1302 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1303 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1304 aml_append(field
, aml_named_field("DBGB", 8));
1305 aml_append(scope
, field
);
1307 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1309 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1310 aml_append(method
, aml_to_buffer(buf
, buf
));
1311 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1312 aml_append(method
, aml_store(aml_int(0), idx
));
1314 while_ctx
= aml_while(aml_lless(idx
, len
));
1315 aml_append(while_ctx
,
1316 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1317 aml_append(while_ctx
, aml_increment(idx
));
1318 aml_append(method
, while_ctx
);
1320 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1321 aml_append(scope
, method
);
1323 aml_append(table
, scope
);
1326 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1331 uint32_t irqs
[] = {5, 10, 11};
1333 dev
= aml_device("%s", name
);
1334 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1335 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1337 crs
= aml_resource_template();
1338 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1339 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1340 aml_append(dev
, aml_name_decl("_PRS", crs
));
1342 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1343 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1344 aml_append(dev
, method
);
1346 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1347 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1348 aml_append(dev
, method
);
1350 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1351 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1352 aml_append(dev
, method
);
1354 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1355 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1356 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1357 aml_append(dev
, method
);
1362 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1369 dev
= aml_device("%s", name
);
1370 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1371 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1373 crs
= aml_resource_template();
1375 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1376 AML_SHARED
, &irqs
, 1));
1377 aml_append(dev
, aml_name_decl("_PRS", crs
));
1379 aml_append(dev
, aml_name_decl("_CRS", crs
));
1382 * _DIS can be no-op because the interrupt cannot be disabled.
1384 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1385 aml_append(dev
, method
);
1387 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1388 aml_append(dev
, method
);
1393 /* _CRS method - get current settings */
1394 static Aml
*build_iqcr_method(bool is_piix4
)
1398 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1399 Aml
*crs
= aml_resource_template();
1402 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1403 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1404 aml_append(method
, aml_name_decl("PRR0", crs
));
1407 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1410 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1411 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1412 aml_append(method
, if_ctx
);
1415 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1419 aml_append(method
, aml_return(aml_name("PRR0")));
1423 /* _STA method - get status */
1424 static Aml
*build_irq_status_method(void)
1427 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1429 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1430 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1431 aml_append(method
, if_ctx
);
1432 aml_append(method
, aml_return(aml_int(0x0B)));
1436 static void build_piix4_pci0_int(Aml
*table
)
1443 Aml
*sb_scope
= aml_scope("_SB");
1444 Aml
*pci0_scope
= aml_scope("PCI0");
1446 aml_append(pci0_scope
, build_prt(true));
1447 aml_append(sb_scope
, pci0_scope
);
1449 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1450 aml_append(field
, aml_named_field("PRQ0", 8));
1451 aml_append(field
, aml_named_field("PRQ1", 8));
1452 aml_append(field
, aml_named_field("PRQ2", 8));
1453 aml_append(field
, aml_named_field("PRQ3", 8));
1454 aml_append(sb_scope
, field
);
1456 aml_append(sb_scope
, build_irq_status_method());
1457 aml_append(sb_scope
, build_iqcr_method(true));
1459 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1460 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1461 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1462 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1464 dev
= aml_device("LNKS");
1466 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1467 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1469 crs
= aml_resource_template();
1471 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1472 AML_ACTIVE_HIGH
, AML_SHARED
,
1474 aml_append(dev
, aml_name_decl("_PRS", crs
));
1476 /* The SCI cannot be disabled and is always attached to GSI 9,
1477 * so these are no-ops. We only need this link to override the
1478 * polarity to active high and match the content of the MADT.
1480 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1481 aml_append(method
, aml_return(aml_int(0x0b)));
1482 aml_append(dev
, method
);
1484 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1485 aml_append(dev
, method
);
1487 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1488 aml_append(method
, aml_return(aml_name("_PRS")));
1489 aml_append(dev
, method
);
1491 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1492 aml_append(dev
, method
);
1494 aml_append(sb_scope
, dev
);
1496 aml_append(table
, sb_scope
);
1499 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1504 char base
= name
[3] < 'E' ? 'A' : 'E';
1505 char *s
= g_strdup(name
);
1506 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1508 assert(strlen(s
) == 4);
1510 head
= name
[3] - base
;
1511 for (i
= 0; i
< 4; i
++) {
1515 s
[3] = base
+ head
+ i
;
1516 pkg
= aml_package(4);
1517 aml_append(pkg
, a_nr
);
1518 aml_append(pkg
, aml_int(i
));
1519 aml_append(pkg
, aml_name("%s", s
));
1520 aml_append(pkg
, aml_int(0));
1521 aml_append(ctx
, pkg
);
1526 static Aml
*build_q35_routing_table(const char *str
)
1530 char *name
= g_strdup_printf("%s ", str
);
1532 pkg
= aml_package(128);
1533 for (i
= 0; i
< 0x18; i
++) {
1534 name
[3] = 'E' + (i
& 0x3);
1535 append_q35_prt_entry(pkg
, i
, name
);
1539 append_q35_prt_entry(pkg
, 0x18, name
);
1541 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1542 for (i
= 0x0019; i
< 0x1e; i
++) {
1544 append_q35_prt_entry(pkg
, i
, name
);
1547 /* PCIe->PCI bridge. use PIRQ[E-H] */
1549 append_q35_prt_entry(pkg
, 0x1e, name
);
1551 append_q35_prt_entry(pkg
, 0x1f, name
);
1557 static void build_q35_pci0_int(Aml
*table
)
1561 Aml
*sb_scope
= aml_scope("_SB");
1562 Aml
*pci0_scope
= aml_scope("PCI0");
1564 /* Zero => PIC mode, One => APIC Mode */
1565 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1566 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1568 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1570 aml_append(table
, method
);
1572 aml_append(pci0_scope
,
1573 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1574 aml_append(pci0_scope
,
1575 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1577 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1582 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1584 /* Note: we provide the same info as the PCI routing
1585 table of the Bochs BIOS */
1586 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1587 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1588 aml_append(method
, if_ctx
);
1589 else_ctx
= aml_else();
1590 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1591 aml_append(method
, else_ctx
);
1593 aml_append(pci0_scope
, method
);
1594 aml_append(sb_scope
, pci0_scope
);
1596 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1597 aml_append(field
, aml_named_field("PRQA", 8));
1598 aml_append(field
, aml_named_field("PRQB", 8));
1599 aml_append(field
, aml_named_field("PRQC", 8));
1600 aml_append(field
, aml_named_field("PRQD", 8));
1601 aml_append(field
, aml_reserved_field(0x20));
1602 aml_append(field
, aml_named_field("PRQE", 8));
1603 aml_append(field
, aml_named_field("PRQF", 8));
1604 aml_append(field
, aml_named_field("PRQG", 8));
1605 aml_append(field
, aml_named_field("PRQH", 8));
1606 aml_append(sb_scope
, field
);
1608 aml_append(sb_scope
, build_irq_status_method());
1609 aml_append(sb_scope
, build_iqcr_method(false));
1611 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1612 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1613 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1614 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1615 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1616 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1617 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1618 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1620 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1621 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1622 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1623 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1624 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1625 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1626 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1627 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1629 aml_append(table
, sb_scope
);
1632 static void build_q35_isa_bridge(Aml
*table
)
1638 scope
= aml_scope("_SB.PCI0");
1639 dev
= aml_device("ISA");
1640 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1642 /* ICH9 PCI to ISA irq remapping */
1643 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1644 aml_int(0x60), 0x0C));
1646 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1647 aml_int(0x80), 0x02));
1648 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1649 aml_append(field
, aml_named_field("COMA", 3));
1650 aml_append(field
, aml_reserved_field(1));
1651 aml_append(field
, aml_named_field("COMB", 3));
1652 aml_append(field
, aml_reserved_field(1));
1653 aml_append(field
, aml_named_field("LPTD", 2));
1654 aml_append(dev
, field
);
1656 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1657 aml_int(0x82), 0x02));
1659 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1660 aml_append(field
, aml_named_field("CAEN", 1));
1661 aml_append(field
, aml_named_field("CBEN", 1));
1662 aml_append(field
, aml_named_field("LPEN", 1));
1663 aml_append(dev
, field
);
1665 aml_append(scope
, dev
);
1666 aml_append(table
, scope
);
1669 static void build_piix4_pm(Aml
*table
)
1674 scope
= aml_scope("_SB.PCI0");
1675 dev
= aml_device("PX13");
1676 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1678 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1679 aml_int(0x00), 0xff));
1680 aml_append(scope
, dev
);
1681 aml_append(table
, scope
);
1684 static void build_piix4_isa_bridge(Aml
*table
)
1690 scope
= aml_scope("_SB.PCI0");
1691 dev
= aml_device("ISA");
1692 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1694 /* PIIX PCI to ISA irq remapping */
1695 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1696 aml_int(0x60), 0x04));
1698 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1699 /* Offset(0x5f),, 7, */
1700 aml_append(field
, aml_reserved_field(0x2f8));
1701 aml_append(field
, aml_reserved_field(7));
1702 aml_append(field
, aml_named_field("LPEN", 1));
1703 /* Offset(0x67),, 3, */
1704 aml_append(field
, aml_reserved_field(0x38));
1705 aml_append(field
, aml_reserved_field(3));
1706 aml_append(field
, aml_named_field("CAEN", 1));
1707 aml_append(field
, aml_reserved_field(3));
1708 aml_append(field
, aml_named_field("CBEN", 1));
1709 aml_append(dev
, field
);
1711 aml_append(scope
, dev
);
1712 aml_append(table
, scope
);
1715 static void build_piix4_pci_hotplug(Aml
*table
)
1721 scope
= aml_scope("_SB.PCI0");
1724 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1725 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1726 aml_append(field
, aml_named_field("PCIU", 32));
1727 aml_append(field
, aml_named_field("PCID", 32));
1728 aml_append(scope
, field
);
1731 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1732 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1733 aml_append(field
, aml_named_field("B0EJ", 32));
1734 aml_append(scope
, field
);
1737 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1738 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1739 aml_append(field
, aml_named_field("BNUM", 32));
1740 aml_append(scope
, field
);
1742 aml_append(scope
, aml_mutex("BLCK", 0));
1744 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1745 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1746 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1748 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1749 aml_append(method
, aml_release(aml_name("BLCK")));
1750 aml_append(method
, aml_return(aml_int(0)));
1751 aml_append(scope
, method
);
1753 aml_append(table
, scope
);
1756 static Aml
*build_q35_osc_method(void)
1762 Aml
*a_cwd1
= aml_name("CDW1");
1763 Aml
*a_ctrl
= aml_local(0);
1765 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1766 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1768 if_ctx
= aml_if(aml_equal(
1769 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1770 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1771 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1773 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1776 * Always allow native PME, AER (no dependencies)
1777 * Allow SHPC (PCI bridges can have SHPC controller)
1779 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1F), a_ctrl
));
1781 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1782 /* Unknown revision */
1783 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1784 aml_append(if_ctx
, if_ctx2
);
1786 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1787 /* Capabilities bits were masked */
1788 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1789 aml_append(if_ctx
, if_ctx2
);
1791 /* Update DWORD3 in the buffer */
1792 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1793 aml_append(method
, if_ctx
);
1795 else_ctx
= aml_else();
1796 /* Unrecognized UUID */
1797 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1798 aml_append(method
, else_ctx
);
1800 aml_append(method
, aml_return(aml_arg(3)));
1805 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1806 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1807 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1809 CrsRangeEntry
*entry
;
1810 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1811 CrsRangeSet crs_range_set
;
1812 PCMachineState
*pcms
= PC_MACHINE(machine
);
1813 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1815 uint32_t nr_mem
= machine
->ram_slots
;
1816 int root_bus_limit
= 0xFF;
1818 TPMIf
*tpm
= tpm_find();
1821 dsdt
= init_aml_allocator();
1823 /* Reserve space for header */
1824 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1826 build_dbg_aml(dsdt
);
1827 if (misc
->is_piix4
) {
1828 sb_scope
= aml_scope("_SB");
1829 dev
= aml_device("PCI0");
1830 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1831 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1832 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1833 aml_append(sb_scope
, dev
);
1834 aml_append(dsdt
, sb_scope
);
1836 build_hpet_aml(dsdt
);
1837 build_piix4_pm(dsdt
);
1838 build_piix4_isa_bridge(dsdt
);
1839 build_isa_devices_aml(dsdt
);
1840 build_piix4_pci_hotplug(dsdt
);
1841 build_piix4_pci0_int(dsdt
);
1843 sb_scope
= aml_scope("_SB");
1844 dev
= aml_device("PCI0");
1845 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1846 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1847 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1848 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1849 aml_append(dev
, build_q35_osc_method());
1850 aml_append(sb_scope
, dev
);
1851 aml_append(dsdt
, sb_scope
);
1853 build_hpet_aml(dsdt
);
1854 build_q35_isa_bridge(dsdt
);
1855 build_isa_devices_aml(dsdt
);
1856 build_q35_pci0_int(dsdt
);
1859 if (pcmc
->legacy_cpu_hotplug
) {
1860 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1862 CPUHotplugFeatures opts
= {
1863 .acpi_1_compatible
= true, .has_legacy_cphp
= true
1865 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1866 "\\_SB.PCI0", "\\_GPE._E02");
1868 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0", "\\_GPE._E03");
1870 scope
= aml_scope("_GPE");
1872 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1874 if (misc
->is_piix4
) {
1875 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1877 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1878 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1879 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1880 aml_append(scope
, method
);
1883 if (machine
->nvdimms_state
->is_enabled
) {
1884 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1885 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1887 aml_append(scope
, method
);
1890 aml_append(dsdt
, scope
);
1892 crs_range_set_init(&crs_range_set
);
1893 bus
= PC_MACHINE(machine
)->bus
;
1895 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1896 uint8_t bus_num
= pci_bus_num(bus
);
1897 uint8_t numa_node
= pci_bus_numa_node(bus
);
1899 /* look only for expander root buses */
1900 if (!pci_bus_is_root(bus
)) {
1904 if (bus_num
< root_bus_limit
) {
1905 root_bus_limit
= bus_num
- 1;
1908 scope
= aml_scope("\\_SB");
1909 dev
= aml_device("PC%.02X", bus_num
);
1910 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1911 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1912 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1913 if (pci_bus_is_express(bus
)) {
1914 aml_append(dev
, build_q35_osc_method());
1917 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1918 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1921 aml_append(dev
, build_prt(false));
1922 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
);
1923 aml_append(dev
, aml_name_decl("_CRS", crs
));
1924 aml_append(scope
, dev
);
1925 aml_append(dsdt
, scope
);
1930 * At this point crs_range_set has all the ranges used by pci
1931 * busses *other* than PCI0. These ranges will be excluded from
1932 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1935 if (acpi_get_mcfg(&mcfg
)) {
1936 crs_range_insert(crs_range_set
.mem_ranges
,
1937 mcfg
.base
, mcfg
.base
+ mcfg
.size
- 1);
1940 scope
= aml_scope("\\_SB.PCI0");
1941 /* build PCI0._CRS */
1942 crs
= aml_resource_template();
1944 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1945 0x0000, 0x0, root_bus_limit
,
1946 0x0000, root_bus_limit
+ 1));
1947 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1950 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1951 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1952 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1954 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1955 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1956 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1958 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1959 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1960 0x0000, entry
->base
, entry
->limit
,
1961 0x0000, entry
->limit
- entry
->base
+ 1));
1965 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1966 AML_CACHEABLE
, AML_READ_WRITE
,
1967 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1969 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
1970 range_lob(pci_hole
),
1971 range_upb(pci_hole
));
1972 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
1973 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
1975 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1976 AML_NON_CACHEABLE
, AML_READ_WRITE
,
1977 0, entry
->base
, entry
->limit
,
1978 0, entry
->limit
- entry
->base
+ 1));
1981 if (!range_is_empty(pci_hole64
)) {
1982 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
1983 range_lob(pci_hole64
),
1984 range_upb(pci_hole64
));
1985 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
1986 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
1988 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1990 AML_CACHEABLE
, AML_READ_WRITE
,
1991 0, entry
->base
, entry
->limit
,
1992 0, entry
->limit
- entry
->base
+ 1));
1996 if (TPM_IS_TIS(tpm_find())) {
1997 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1998 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2000 aml_append(scope
, aml_name_decl("_CRS", crs
));
2002 /* reserve GPE0 block resources */
2003 dev
= aml_device("GPE0");
2004 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2005 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2006 /* device present, functioning, decoding, not shown in UI */
2007 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2008 crs
= aml_resource_template();
2012 pm
->fadt
.gpe0_blk
.address
,
2013 pm
->fadt
.gpe0_blk
.address
,
2015 pm
->fadt
.gpe0_blk
.bit_width
/ 8)
2017 aml_append(dev
, aml_name_decl("_CRS", crs
));
2018 aml_append(scope
, dev
);
2020 crs_range_set_free(&crs_range_set
);
2022 /* reserve PCIHP resources */
2023 if (pm
->pcihp_io_len
) {
2024 dev
= aml_device("PHPR");
2025 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2027 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2028 /* device present, functioning, decoding, not shown in UI */
2029 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2030 crs
= aml_resource_template();
2032 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2035 aml_append(dev
, aml_name_decl("_CRS", crs
));
2036 aml_append(scope
, dev
);
2038 aml_append(dsdt
, scope
);
2040 /* create S3_ / S4_ / S5_ packages if necessary */
2041 scope
= aml_scope("\\");
2042 if (!pm
->s3_disabled
) {
2043 pkg
= aml_package(4);
2044 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2045 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2046 aml_append(pkg
, aml_int(0)); /* reserved */
2047 aml_append(pkg
, aml_int(0)); /* reserved */
2048 aml_append(scope
, aml_name_decl("_S3", pkg
));
2051 if (!pm
->s4_disabled
) {
2052 pkg
= aml_package(4);
2053 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2054 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2055 aml_append(pkg
, aml_int(pm
->s4_val
));
2056 aml_append(pkg
, aml_int(0)); /* reserved */
2057 aml_append(pkg
, aml_int(0)); /* reserved */
2058 aml_append(scope
, aml_name_decl("_S4", pkg
));
2061 pkg
= aml_package(4);
2062 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2063 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2064 aml_append(pkg
, aml_int(0)); /* reserved */
2065 aml_append(pkg
, aml_int(0)); /* reserved */
2066 aml_append(scope
, aml_name_decl("_S5", pkg
));
2067 aml_append(dsdt
, scope
);
2069 /* create fw_cfg node, unconditionally */
2071 /* when using port i/o, the 8-bit data register *always* overlaps
2072 * with half of the 16-bit control register. Hence, the total size
2073 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2074 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2075 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2076 "dma_enabled", NULL
) ?
2077 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2080 scope
= aml_scope("\\_SB.PCI0");
2081 dev
= aml_device("FWCF");
2083 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2085 /* device present, functioning, decoding, not shown in UI */
2086 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2088 crs
= aml_resource_template();
2090 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2092 aml_append(dev
, aml_name_decl("_CRS", crs
));
2094 aml_append(scope
, dev
);
2095 aml_append(dsdt
, scope
);
2098 if (misc
->applesmc_io_base
) {
2099 scope
= aml_scope("\\_SB.PCI0.ISA");
2100 dev
= aml_device("SMC");
2102 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2103 /* device present, functioning, decoding, not shown in UI */
2104 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2106 crs
= aml_resource_template();
2108 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2109 0x01, APPLESMC_MAX_DATA_LENGTH
)
2111 aml_append(crs
, aml_irq_no_flags(6));
2112 aml_append(dev
, aml_name_decl("_CRS", crs
));
2114 aml_append(scope
, dev
);
2115 aml_append(dsdt
, scope
);
2118 if (misc
->pvpanic_port
) {
2119 scope
= aml_scope("\\_SB.PCI0.ISA");
2121 dev
= aml_device("PEVT");
2122 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2124 crs
= aml_resource_template();
2126 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2128 aml_append(dev
, aml_name_decl("_CRS", crs
));
2130 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2131 aml_int(misc
->pvpanic_port
), 1));
2132 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2133 aml_append(field
, aml_named_field("PEPT", 8));
2134 aml_append(dev
, field
);
2136 /* device present, functioning, decoding, shown in UI */
2137 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2139 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2140 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2141 aml_append(method
, aml_return(aml_local(0)));
2142 aml_append(dev
, method
);
2144 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2145 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2146 aml_append(dev
, method
);
2148 aml_append(scope
, dev
);
2149 aml_append(dsdt
, scope
);
2152 sb_scope
= aml_scope("\\_SB");
2157 pci_host
= acpi_get_i386_pci_host();
2159 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2163 Aml
*scope
= aml_scope("PCI0");
2164 /* Scan all PCI buses. Generate tables to support hotplug. */
2165 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2167 if (TPM_IS_TIS(tpm
)) {
2168 if (misc
->tpm_version
== TPM_VERSION_2_0
) {
2169 dev
= aml_device("TPM");
2170 aml_append(dev
, aml_name_decl("_HID",
2171 aml_string("MSFT0101")));
2173 dev
= aml_device("ISA.TPM");
2174 aml_append(dev
, aml_name_decl("_HID",
2175 aml_eisaid("PNP0C31")));
2178 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2179 crs
= aml_resource_template();
2180 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2181 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2183 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2184 Rewrite to take IRQ from TPM device model and
2185 fix default IRQ value there to use some unused IRQ
2187 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2188 aml_append(dev
, aml_name_decl("_CRS", crs
));
2190 tpm_build_ppi_acpi(tpm
, dev
);
2192 aml_append(scope
, dev
);
2195 aml_append(sb_scope
, scope
);
2199 if (TPM_IS_CRB(tpm
)) {
2200 dev
= aml_device("TPM");
2201 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
2202 crs
= aml_resource_template();
2203 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
2204 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
2205 aml_append(dev
, aml_name_decl("_CRS", crs
));
2207 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
2208 aml_append(method
, aml_return(aml_int(0x0f)));
2209 aml_append(dev
, method
);
2211 tpm_build_ppi_acpi(tpm
, dev
);
2213 aml_append(sb_scope
, dev
);
2216 aml_append(dsdt
, sb_scope
);
2218 /* copy AML table into ACPI tables blob and patch header there */
2219 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2220 build_header(linker
, table_data
,
2221 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2222 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2223 free_aml_allocator();
2227 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2231 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2232 /* Note timer_block_id value must be kept in sync with value advertised by
2235 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2236 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2237 build_header(linker
, table_data
,
2238 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2242 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2244 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2245 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2246 unsigned log_addr_offset
=
2247 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2249 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2250 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2251 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2253 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2254 false /* high memory */);
2256 /* log area start address to be filled by Guest linker */
2257 bios_linker_loader_add_pointer(linker
,
2258 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2259 ACPI_BUILD_TPMLOG_FILE
, 0);
2261 build_header(linker
, table_data
,
2262 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2266 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2268 Acpi20TPM2
*tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2269 unsigned log_addr_size
= sizeof(tpm2_ptr
->log_area_start_address
);
2270 unsigned log_addr_offset
=
2271 (char *)&tpm2_ptr
->log_area_start_address
- table_data
->data
;
2273 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2274 if (TPM_IS_TIS(tpm_find())) {
2275 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2276 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2277 } else if (TPM_IS_CRB(tpm_find())) {
2278 tpm2_ptr
->control_area_address
= cpu_to_le64(TPM_CRB_ADDR_CTRL
);
2279 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_CRB
);
2281 g_warn_if_reached();
2284 tpm2_ptr
->log_area_minimum_length
=
2285 cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2287 /* log area start address to be filled by Guest linker */
2288 bios_linker_loader_add_pointer(linker
, ACPI_BUILD_TABLE_FILE
,
2289 log_addr_offset
, log_addr_size
,
2290 ACPI_BUILD_TPMLOG_FILE
, 0);
2291 build_header(linker
, table_data
,
2292 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2295 #define HOLE_640K_START (640 * KiB)
2296 #define HOLE_640K_END (1 * MiB)
2299 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2301 AcpiSystemResourceAffinityTable
*srat
;
2302 AcpiSratMemoryAffinity
*numamem
;
2305 int srat_start
, numa_start
, slots
;
2306 uint64_t mem_len
, mem_base
, next_base
;
2307 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2308 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2309 PCMachineState
*pcms
= PC_MACHINE(machine
);
2310 ram_addr_t hotplugabble_address_space_size
=
2311 object_property_get_int(OBJECT(pcms
), PC_MACHINE_DEVMEM_REGION_SIZE
,
2314 srat_start
= table_data
->len
;
2316 srat
= acpi_data_push(table_data
, sizeof *srat
);
2317 srat
->reserved1
= cpu_to_le32(1);
2319 for (i
= 0; i
< apic_ids
->len
; i
++) {
2320 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
2321 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
2323 if (apic_id
< 255) {
2324 AcpiSratProcessorAffinity
*core
;
2326 core
= acpi_data_push(table_data
, sizeof *core
);
2327 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2328 core
->length
= sizeof(*core
);
2329 core
->local_apic_id
= apic_id
;
2330 core
->proximity_lo
= node_id
;
2331 memset(core
->proximity_hi
, 0, 3);
2332 core
->local_sapic_eid
= 0;
2333 core
->flags
= cpu_to_le32(1);
2335 AcpiSratProcessorX2ApicAffinity
*core
;
2337 core
= acpi_data_push(table_data
, sizeof *core
);
2338 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
2339 core
->length
= sizeof(*core
);
2340 core
->x2apic_id
= cpu_to_le32(apic_id
);
2341 core
->proximity_domain
= cpu_to_le32(node_id
);
2342 core
->flags
= cpu_to_le32(1);
2347 /* the memory map is a bit tricky, it contains at least one hole
2348 * from 640k-1M and possibly another one from 3.5G-4G.
2351 numa_start
= table_data
->len
;
2353 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2354 mem_base
= next_base
;
2355 mem_len
= pcms
->node_mem
[i
- 1];
2356 next_base
= mem_base
+ mem_len
;
2358 /* Cut out the 640K hole */
2359 if (mem_base
<= HOLE_640K_START
&&
2360 next_base
> HOLE_640K_START
) {
2361 mem_len
-= next_base
- HOLE_640K_START
;
2363 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2364 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2365 MEM_AFFINITY_ENABLED
);
2368 /* Check for the rare case: 640K < RAM < 1M */
2369 if (next_base
<= HOLE_640K_END
) {
2370 next_base
= HOLE_640K_END
;
2373 mem_base
= HOLE_640K_END
;
2374 mem_len
= next_base
- HOLE_640K_END
;
2377 /* Cut out the ACPI_PCI hole */
2378 if (mem_base
<= pcms
->below_4g_mem_size
&&
2379 next_base
> pcms
->below_4g_mem_size
) {
2380 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2382 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2383 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2384 MEM_AFFINITY_ENABLED
);
2386 mem_base
= 1ULL << 32;
2387 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2388 next_base
= mem_base
+ mem_len
;
2392 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2393 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2394 MEM_AFFINITY_ENABLED
);
2397 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2398 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2399 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2400 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2404 * Entry is required for Windows to enable memory hotplug in OS
2405 * and for Linux to enable SWIOTLB when booted with less than
2406 * 4G of RAM. Windows works better if the entry sets proximity
2407 * to the highest NUMA node in the machine.
2408 * Memory devices may override proximity set by this entry,
2409 * providing _PXM method if necessary.
2411 if (hotplugabble_address_space_size
) {
2412 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2413 build_srat_memory(numamem
, machine
->device_memory
->base
,
2414 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
2415 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2418 build_header(linker
, table_data
,
2419 (void *)(table_data
->data
+ srat_start
),
2421 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2425 * VT-d spec 8.1 DMA Remapping Reporting Structure
2426 * (version Oct. 2014 or later)
2429 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2431 int dmar_start
= table_data
->len
;
2433 AcpiTableDmar
*dmar
;
2434 AcpiDmarHardwareUnit
*drhd
;
2435 AcpiDmarRootPortATS
*atsr
;
2436 uint8_t dmar_flags
= 0;
2437 X86IOMMUState
*iommu
= x86_iommu_get_default();
2438 AcpiDmarDeviceScope
*scope
= NULL
;
2439 /* Root complex IOAPIC use one path[0] only */
2440 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2441 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
2444 if (x86_iommu_ir_supported(iommu
)) {
2445 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2448 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2449 dmar
->host_address_width
= intel_iommu
->aw_bits
- 1;
2450 dmar
->flags
= dmar_flags
;
2452 /* DMAR Remapping Hardware Unit Definition structure */
2453 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2454 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2455 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2456 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2457 drhd
->pci_segment
= cpu_to_le16(0);
2458 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2460 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2461 * 8.3.1 (version Oct. 2014 or later). */
2462 scope
= &drhd
->scope
[0];
2463 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2464 scope
->length
= ioapic_scope_size
;
2465 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2466 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2467 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2468 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2470 if (iommu
->dt_supported
) {
2471 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2472 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2473 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2474 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2475 atsr
->pci_segment
= cpu_to_le16(0);
2478 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2479 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2482 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2483 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2485 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2488 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
)
2490 int ivhd_table_len
= 28;
2491 int iommu_start
= table_data
->len
;
2492 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2495 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2496 /* IVinfo - IO virtualization information common to all
2497 * IOMMU units in a system
2499 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2501 build_append_int_noprefix(table_data
, 0, 8);
2503 /* IVHD definition - type 10h */
2504 build_append_int_noprefix(table_data
, 0x10, 1);
2505 /* virtualization flags */
2506 build_append_int_noprefix(table_data
,
2507 (1UL << 0) | /* HtTunEn */
2508 (1UL << 4) | /* iotblSup */
2509 (1UL << 6) | /* PrefSup */
2510 (1UL << 7), /* PPRSup */
2514 * When interrupt remapping is supported, we add a special IVHD device
2517 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2518 ivhd_table_len
+= 8;
2521 build_append_int_noprefix(table_data
, ivhd_table_len
, 2);
2523 build_append_int_noprefix(table_data
, s
->devid
, 2);
2524 /* Capability offset */
2525 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2526 /* IOMMU base address */
2527 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2528 /* PCI Segment Group */
2529 build_append_int_noprefix(table_data
, 0, 2);
2531 build_append_int_noprefix(table_data
, 0, 2);
2532 /* IOMMU Feature Reporting */
2533 build_append_int_noprefix(table_data
,
2534 (48UL << 30) | /* HATS */
2535 (48UL << 28) | /* GATS */
2536 (1UL << 2) | /* GTSup */
2537 (1UL << 6), /* GASup */
2540 * Type 1 device entry reporting all devices
2541 * These are 4-byte device entries currently reporting the range of
2542 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2544 build_append_int_noprefix(table_data
, 0x0000001, 4);
2547 * Add a special IVHD device type.
2548 * Refer to spec - Table 95: IVHD device entry type codes
2550 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2551 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2553 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2554 build_append_int_noprefix(table_data
,
2555 (0x1ull
<< 56) | /* type IOAPIC */
2556 (IOAPIC_SB_DEVID
<< 40) | /* IOAPIC devid */
2557 0x48, /* special device */
2561 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2562 "IVRS", table_data
->len
- iommu_start
, 1, NULL
, NULL
);
2566 struct AcpiBuildState
{
2567 /* Copy of table in RAM (for patching). */
2568 MemoryRegion
*table_mr
;
2569 /* Is table patched? */
2572 MemoryRegion
*rsdp_mr
;
2573 MemoryRegion
*linker_mr
;
2576 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2581 pci_host
= acpi_get_i386_pci_host();
2584 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2588 mcfg
->base
= qnum_get_uint(qobject_to(QNum
, o
));
2590 if (mcfg
->base
== PCIE_BASE_ADDR_UNMAPPED
) {
2594 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2596 mcfg
->size
= qnum_get_uint(qobject_to(QNum
, o
));
2602 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2604 PCMachineState
*pcms
= PC_MACHINE(machine
);
2605 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2606 GArray
*table_offsets
;
2607 unsigned facs
, dsdt
, rsdt
, fadt
;
2611 Range pci_hole
, pci_hole64
;
2614 GArray
*tables_blob
= tables
->table_data
;
2615 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2616 Object
*vmgenid_dev
;
2618 acpi_get_pm_info(machine
, &pm
);
2619 acpi_get_misc_info(&misc
);
2620 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2621 acpi_get_slic_oem(&slic_oem
);
2623 table_offsets
= g_array_new(false, true /* clear */,
2625 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2627 bios_linker_loader_alloc(tables
->linker
,
2628 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2629 64 /* Ensure FACS is aligned */,
2630 false /* high memory */);
2633 * FACS is pointed to by FADT.
2634 * We place it first since it's the only table that has alignment
2637 facs
= tables_blob
->len
;
2638 build_facs(tables_blob
);
2640 /* DSDT is pointed to by FADT */
2641 dsdt
= tables_blob
->len
;
2642 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2643 &pci_hole
, &pci_hole64
, machine
);
2645 /* Count the size of the DSDT and SSDT, we will need it for legacy
2646 * sizing of ACPI tables.
2648 aml_len
+= tables_blob
->len
- dsdt
;
2650 /* ACPI tables pointed to by RSDT */
2651 fadt
= tables_blob
->len
;
2652 acpi_add_table(table_offsets
, tables_blob
);
2653 pm
.fadt
.facs_tbl_offset
= &facs
;
2654 pm
.fadt
.dsdt_tbl_offset
= &dsdt
;
2655 pm
.fadt
.xdsdt_tbl_offset
= &dsdt
;
2656 build_fadt(tables_blob
, tables
->linker
, &pm
.fadt
,
2657 slic_oem
.id
, slic_oem
.table_id
);
2658 aml_len
+= tables_blob
->len
- fadt
;
2660 acpi_add_table(table_offsets
, tables_blob
);
2661 build_madt(tables_blob
, tables
->linker
, pcms
);
2663 vmgenid_dev
= find_vmgenid_dev();
2665 acpi_add_table(table_offsets
, tables_blob
);
2666 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2667 tables
->vmgenid
, tables
->linker
);
2670 if (misc
.has_hpet
) {
2671 acpi_add_table(table_offsets
, tables_blob
);
2672 build_hpet(tables_blob
, tables
->linker
);
2674 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2675 acpi_add_table(table_offsets
, tables_blob
);
2676 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2678 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2679 acpi_add_table(table_offsets
, tables_blob
);
2680 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
);
2683 if (pcms
->numa_nodes
) {
2684 acpi_add_table(table_offsets
, tables_blob
);
2685 build_srat(tables_blob
, tables
->linker
, machine
);
2686 if (have_numa_distance
) {
2687 acpi_add_table(table_offsets
, tables_blob
);
2688 build_slit(tables_blob
, tables
->linker
);
2691 if (acpi_get_mcfg(&mcfg
)) {
2692 acpi_add_table(table_offsets
, tables_blob
);
2693 build_mcfg(tables_blob
, tables
->linker
, &mcfg
);
2695 if (x86_iommu_get_default()) {
2696 IommuType IOMMUType
= x86_iommu_get_type();
2697 if (IOMMUType
== TYPE_AMD
) {
2698 acpi_add_table(table_offsets
, tables_blob
);
2699 build_amd_iommu(tables_blob
, tables
->linker
);
2700 } else if (IOMMUType
== TYPE_INTEL
) {
2701 acpi_add_table(table_offsets
, tables_blob
);
2702 build_dmar_q35(tables_blob
, tables
->linker
);
2705 if (machine
->nvdimms_state
->is_enabled
) {
2706 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2707 machine
->nvdimms_state
, machine
->ram_slots
);
2710 /* Add tables supplied by user (if any) */
2711 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2712 unsigned len
= acpi_table_len(u
);
2714 acpi_add_table(table_offsets
, tables_blob
);
2715 g_array_append_vals(tables_blob
, u
, len
);
2718 /* RSDT is pointed to by RSDP */
2719 rsdt
= tables_blob
->len
;
2720 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2721 slic_oem
.id
, slic_oem
.table_id
);
2723 /* RSDP is in FSEG memory, so allocate it separately */
2725 AcpiRsdpData rsdp_data
= {
2727 .oem_id
= ACPI_BUILD_APPNAME6
,
2728 .xsdt_tbl_offset
= NULL
,
2729 .rsdt_tbl_offset
= &rsdt
,
2731 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
2732 if (!pcmc
->rsdp_in_ram
) {
2733 /* We used to allocate some extra space for RSDP revision 2 but
2734 * only used the RSDP revision 0 space. The extra bytes were
2735 * zeroed out and not used.
2736 * Here we continue wasting those extra 16 bytes to make sure we
2737 * don't break migration for machine types 2.2 and older due to
2738 * RSDP blob size mismatch.
2740 build_append_int_noprefix(tables
->rsdp
, 0, 16);
2744 /* We'll expose it all to Guest so we want to reduce
2745 * chance of size changes.
2747 * We used to align the tables to 4k, but of course this would
2748 * too simple to be enough. 4k turned out to be too small an
2749 * alignment very soon, and in fact it is almost impossible to
2750 * keep the table size stable for all (max_cpus, max_memory_slots)
2751 * combinations. So the table size is always 64k for pc-i440fx-2.1
2752 * and we give an error if the table grows beyond that limit.
2754 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2755 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2756 * than 2.0 and we can always pad the smaller tables with zeros. We can
2757 * then use the exact size of the 2.0 tables.
2759 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2761 if (pcmc
->legacy_acpi_table_size
) {
2762 /* Subtracting aml_len gives the size of fixed tables. Then add the
2763 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2765 int legacy_aml_len
=
2766 pcmc
->legacy_acpi_table_size
+
2767 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* pcms
->apic_id_limit
;
2768 int legacy_table_size
=
2769 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2770 ACPI_BUILD_ALIGN_SIZE
);
2771 if (tables_blob
->len
> legacy_table_size
) {
2772 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2773 warn_report("ACPI table size %u exceeds %d bytes,"
2774 " migration may not work",
2775 tables_blob
->len
, legacy_table_size
);
2776 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2777 " or PCI bridges.");
2779 g_array_set_size(tables_blob
, legacy_table_size
);
2781 /* Make sure we have a buffer in case we need to resize the tables. */
2782 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2783 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2784 warn_report("ACPI table size %u exceeds %d bytes,"
2785 " migration may not work",
2786 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2787 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2788 " or PCI bridges.");
2790 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2793 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2795 /* Cleanup memory that's no longer used. */
2796 g_array_free(table_offsets
, true);
2799 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2801 uint32_t size
= acpi_data_len(data
);
2803 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2804 memory_region_ram_resize(mr
, size
, &error_abort
);
2806 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2807 memory_region_set_dirty(mr
, 0, size
);
2810 static void acpi_build_update(void *build_opaque
)
2812 AcpiBuildState
*build_state
= build_opaque
;
2813 AcpiBuildTables tables
;
2815 /* No state to update or already patched? Nothing to do. */
2816 if (!build_state
|| build_state
->patched
) {
2819 build_state
->patched
= 1;
2821 acpi_build_tables_init(&tables
);
2823 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2825 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2827 if (build_state
->rsdp
) {
2828 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2830 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2833 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2834 acpi_build_tables_cleanup(&tables
, true);
2837 static void acpi_build_reset(void *build_opaque
)
2839 AcpiBuildState
*build_state
= build_opaque
;
2840 build_state
->patched
= 0;
2843 static const VMStateDescription vmstate_acpi_build
= {
2844 .name
= "acpi_build",
2846 .minimum_version_id
= 1,
2847 .fields
= (VMStateField
[]) {
2848 VMSTATE_UINT8(patched
, AcpiBuildState
),
2849 VMSTATE_END_OF_LIST()
2853 void acpi_setup(void)
2855 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2856 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2857 AcpiBuildTables tables
;
2858 AcpiBuildState
*build_state
;
2859 Object
*vmgenid_dev
;
2861 static FwCfgTPMConfig tpm_config
;
2863 if (!pcms
->fw_cfg
) {
2864 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2868 if (!pcms
->acpi_build_enabled
) {
2869 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2873 if (!acpi_enabled
) {
2874 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2878 build_state
= g_malloc0(sizeof *build_state
);
2880 acpi_build_tables_init(&tables
);
2881 acpi_build(&tables
, MACHINE(pcms
));
2883 /* Now expose it all to Guest */
2884 build_state
->table_mr
= acpi_add_rom_blob(acpi_build_update
,
2885 build_state
, tables
.table_data
,
2886 ACPI_BUILD_TABLE_FILE
,
2887 ACPI_BUILD_TABLE_MAX_SIZE
);
2888 assert(build_state
->table_mr
!= NULL
);
2890 build_state
->linker_mr
=
2891 acpi_add_rom_blob(acpi_build_update
, build_state
,
2892 tables
.linker
->cmd_blob
, "etc/table-loader", 0);
2894 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2895 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2898 if (tpm
&& object_property_get_bool(OBJECT(tpm
), "ppi", &error_abort
)) {
2899 tpm_config
= (FwCfgTPMConfig
) {
2900 .tpmppi_address
= cpu_to_le32(TPM_PPI_ADDR_BASE
),
2901 .tpm_version
= tpm_get_version(tpm
),
2902 .tpmppi_version
= TPM_PPI_VERSION_1_30
2904 fw_cfg_add_file(pcms
->fw_cfg
, "etc/tpm/config",
2905 &tpm_config
, sizeof tpm_config
);
2908 vmgenid_dev
= find_vmgenid_dev();
2910 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), pcms
->fw_cfg
,
2914 if (!pcmc
->rsdp_in_ram
) {
2916 * Keep for compatibility with old machine types.
2917 * Though RSDP is small, its contents isn't immutable, so
2918 * we'll update it along with the rest of tables on guest access.
2920 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2922 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2923 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2924 acpi_build_update
, NULL
, build_state
,
2925 build_state
->rsdp
, rsdp_size
, true);
2926 build_state
->rsdp_mr
= NULL
;
2928 build_state
->rsdp
= NULL
;
2929 build_state
->rsdp_mr
= acpi_add_rom_blob(acpi_build_update
,
2930 build_state
, tables
.rsdp
,
2931 ACPI_BUILD_RSDP_FILE
, 0);
2934 qemu_register_reset(acpi_build_reset
, build_state
);
2935 acpi_build_reset(build_state
);
2936 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2938 /* Cleanup tables but don't free the memory: we track it
2941 acpi_build_tables_cleanup(&tables
, false);