hw/arm/mps2-tz.c

   1 /*
   2  * ARM V2M MPS2 board emulation, trustzone aware FPGA images
   3  *
   4  * Copyright (c) 2017 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
  13  * FPGA but is otherwise the same as the 2). Since the CPU itself
  14  * and most of the devices are in the FPGA, the details of the board
  15  * as seen by the guest depend significantly on the FPGA image.
  16  * This source file covers the following FPGA images, for TrustZone cores:
  17  *  "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
  18  *
  19  * Links to the TRM for the board itself and to the various Application
  20  * Notes which document the FPGA images can be found here:
  21  * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
  22  *
  23  * Board TRM:
  24  * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
  25  * Application Note AN505:
  26  * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
  27  *
  28  * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
  29  * (ARM ECM0601256) for the details of some of the device layout:
  30  *   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  31  */
  32
  33 #include "qemu/osdep.h"
  34 #include "qapi/error.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "hw/arm/armv7m.h"
  38 #include "hw/or-irq.h"
  39 #include "hw/boards.h"
  40 #include "exec/address-spaces.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/misc/unimp.h"
  43 #include "hw/char/cmsdk-apb-uart.h"
  44 #include "hw/timer/cmsdk-apb-timer.h"
  45 #include "hw/misc/mps2-scc.h"
  46 #include "hw/misc/mps2-fpgaio.h"
  47 #include "hw/arm/iotkit.h"
  48 #include "hw/devices.h"
  49 #include "net/net.h"
  50 #include "hw/core/split-irq.h"
  51
  52 typedef enum MPS2TZFPGAType {
  53     FPGA_AN505,
  54 } MPS2TZFPGAType;
  55
  56 typedef struct {
  57     MachineClass parent;
  58     MPS2TZFPGAType fpga_type;
  59     uint32_t scc_id;
  60 } MPS2TZMachineClass;
  61
  62 typedef struct {
  63     MachineState parent;
  64
  65     IoTKit iotkit;
  66     MemoryRegion psram;
  67     MemoryRegion ssram1;
  68     MemoryRegion ssram1_m;
  69     MemoryRegion ssram23;
  70     MPS2SCC scc;
  71     MPS2FPGAIO fpgaio;
  72     TZPPC ppc[5];
  73     UnimplementedDeviceState ssram_mpc[3];
  74     UnimplementedDeviceState spi[5];
  75     UnimplementedDeviceState i2c[4];
  76     UnimplementedDeviceState i2s_audio;
  77     UnimplementedDeviceState gpio[4];
  78     UnimplementedDeviceState dma[4];
  79     UnimplementedDeviceState gfx;
  80     CMSDKAPBUART uart[5];
  81     SplitIRQ sec_resp_splitter;
  82     qemu_or_irq uart_irq_orgate;
  83     DeviceState *lan9118;
  84 } MPS2TZMachineState;
  85
  86 #define TYPE_MPS2TZ_MACHINE "mps2tz"
  87 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
  88
  89 #define MPS2TZ_MACHINE(obj) \
  90     OBJECT_CHECK(MPS2TZMachineState, obj, TYPE_MPS2TZ_MACHINE)
  91 #define MPS2TZ_MACHINE_GET_CLASS(obj) \
  92     OBJECT_GET_CLASS(MPS2TZMachineClass, obj, TYPE_MPS2TZ_MACHINE)
  93 #define MPS2TZ_MACHINE_CLASS(klass) \
  94     OBJECT_CLASS_CHECK(MPS2TZMachineClass, klass, TYPE_MPS2TZ_MACHINE)
  95
  96 /* Main SYSCLK frequency in Hz */
  97 #define SYSCLK_FRQ 20000000
  98
  99 /* Initialize the auxiliary RAM region @mr and map it into
 100  * the memory map at @base.
 101  */
 102 static void make_ram(MemoryRegion *mr, const char *name,
 103                      hwaddr base, hwaddr size)
 104 {
 105     memory_region_init_ram(mr, NULL, name, size, &error_fatal);
 106     memory_region_add_subregion(get_system_memory(), base, mr);
 107 }
 108
 109 /* Create an alias of an entire original MemoryRegion @orig
 110  * located at @base in the memory map.
 111  */
 112 static void make_ram_alias(MemoryRegion *mr, const char *name,
 113                            MemoryRegion *orig, hwaddr base)
 114 {
 115     memory_region_init_alias(mr, NULL, name, orig, 0,
 116                              memory_region_size(orig));
 117     memory_region_add_subregion(get_system_memory(), base, mr);
 118 }
 119
 120 static void init_sysbus_child(Object *parent, const char *childname,
 121                               void *child, size_t childsize,
 122                               const char *childtype)
 123 {
 124     object_initialize(child, childsize, childtype);
 125     object_property_add_child(parent, childname, OBJECT(child), &error_abort);
 126     qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
 127
 128 }
 129
 130 /* Most of the devices in the AN505 FPGA image sit behind
 131  * Peripheral Protection Controllers. These data structures
 132  * define the layout of which devices sit behind which PPCs.
 133  * The devfn for each port is a function which creates, configures
 134  * and initializes the device, returning the MemoryRegion which
 135  * needs to be plugged into the downstream end of the PPC port.
 136  */
 137 typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque,
 138                                 const char *name, hwaddr size);
 139
 140 typedef struct PPCPortInfo {
 141     const char *name;
 142     MakeDevFn *devfn;
 143     void *opaque;
 144     hwaddr addr;
 145     hwaddr size;
 146 } PPCPortInfo;
 147
 148 typedef struct PPCInfo {
 149     const char *name;
 150     PPCPortInfo ports[TZ_NUM_PORTS];
 151 } PPCInfo;
 152
 153 static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
 154                                        void *opaque,
 155                                        const char *name, hwaddr size)
 156 {
 157     /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
 158      * and return a pointer to its MemoryRegion.
 159      */
 160     UnimplementedDeviceState *uds = opaque;
 161
 162     init_sysbus_child(OBJECT(mms), name, uds,
 163                       sizeof(UnimplementedDeviceState),
 164                       TYPE_UNIMPLEMENTED_DEVICE);
 165     qdev_prop_set_string(DEVICE(uds), "name", name);
 166     qdev_prop_set_uint64(DEVICE(uds), "size", size);
 167     object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
 168     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
 169 }
 170
 171 static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
 172                                const char *name, hwaddr size)
 173 {
 174     CMSDKAPBUART *uart = opaque;
 175     int i = uart - &mms->uart[0];
 176     int rxirqno = i * 2;
 177     int txirqno = i * 2 + 1;
 178     int combirqno = i + 10;
 179     SysBusDevice *s;
 180     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 181     DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
 182
 183     init_sysbus_child(OBJECT(mms), name, uart,
 184                       sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);
 185     qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
 186     qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
 187     object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
 188     s = SYS_BUS_DEVICE(uart);
 189     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev,
 190                                                     "EXP_IRQ", txirqno));
 191     sysbus_connect_irq(s, 1, qdev_get_gpio_in_named(iotkitdev,
 192                                                     "EXP_IRQ", rxirqno));
 193     sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
 194     sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
 195     sysbus_connect_irq(s, 4, qdev_get_gpio_in_named(iotkitdev,
 196                                                     "EXP_IRQ", combirqno));
 197     return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
 198 }
 199
 200 static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque,
 201                               const char *name, hwaddr size)
 202 {
 203     MPS2SCC *scc = opaque;
 204     DeviceState *sccdev;
 205     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
 206
 207     object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);
 208     sccdev = DEVICE(scc);
 209     qdev_set_parent_bus(sccdev, sysbus_get_default());
 210     qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
 211     qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008);
 212     qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
 213     object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal);
 214     return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
 215 }
 216
 217 static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque,
 218                                  const char *name, hwaddr size)
 219 {
 220     MPS2FPGAIO *fpgaio = opaque;
 221
 222     object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
 223     qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default());
 224     object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
 225     return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
 226 }
 227
 228 static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
 229                                   const char *name, hwaddr size)
 230 {
 231     SysBusDevice *s;
 232     DeviceState *iotkitdev = DEVICE(&mms->iotkit);
 233     NICInfo *nd = &nd_table[0];
 234
 235     /* In hardware this is a LAN9220; the LAN9118 is software compatible
 236      * except that it doesn't support the checksum-offload feature.
 237      */
 238     qemu_check_nic_model(nd, "lan9118");
 239     mms->lan9118 = qdev_create(NULL, "lan9118");
 240     qdev_set_nic_properties(mms->lan9118, nd);
 241     qdev_init_nofail(mms->lan9118);
 242
 243     s = SYS_BUS_DEVICE(mms->lan9118);
 244     sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16));
 245     return sysbus_mmio_get_region(s, 0);
 246 }
 247
 248 static void mps2tz_common_init(MachineState *machine)
 249 {
 250     MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine);
 251     MachineClass *mc = MACHINE_GET_CLASS(machine);
 252     MemoryRegion *system_memory = get_system_memory();
 253     DeviceState *iotkitdev;
 254     DeviceState *dev_splitter;
 255     int i;
 256
 257     if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 258         error_report("This board can only be used with CPU %s",
 259                      mc->default_cpu_type);
 260         exit(1);
 261     }
 262
 263     init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,
 264                       sizeof(mms->iotkit), TYPE_IOTKIT);
 265     iotkitdev = DEVICE(&mms->iotkit);
 266     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
 267                              "memory", &error_abort);
 268     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", 92);
 269     qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
 270     object_property_set_bool(OBJECT(&mms->iotkit), true, "realized",
 271                              &error_fatal);
 272
 273     /* The sec_resp_cfg output from the IoTKit must be split into multiple
 274      * lines, one for each of the PPCs we create here.
 275      */
 276     object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
 277                       TYPE_SPLIT_IRQ);
 278     object_property_add_child(OBJECT(machine), "sec-resp-splitter",
 279                               OBJECT(&mms->sec_resp_splitter), &error_abort);
 280     object_property_set_int(OBJECT(&mms->sec_resp_splitter), 5,
 281                             "num-lines", &error_fatal);
 282     object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
 283                              "realized", &error_fatal);
 284     dev_splitter = DEVICE(&mms->sec_resp_splitter);
 285     qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
 286                                 qdev_get_gpio_in(dev_splitter, 0));
 287
 288     /* The IoTKit sets up much of the memory layout, including
 289      * the aliases between secure and non-secure regions in the
 290      * address space. The FPGA itself contains:
 291      *
 292      * 0x00000000..0x003fffff  SSRAM1
 293      * 0x00400000..0x007fffff  alias of SSRAM1
 294      * 0x28000000..0x283fffff  4MB SSRAM2 + SSRAM3
 295      * 0x40100000..0x4fffffff  AHB Master Expansion 1 interface devices
 296      * 0x80000000..0x80ffffff  16MB PSRAM
 297      */
 298
 299     /* The FPGA images have an odd combination of different RAMs,
 300      * because in hardware they are different implementations and
 301      * connected to different buses, giving varying performance/size
 302      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
 303      * call the 16MB our "system memory", as it's the largest lump.
 304      */
 305     memory_region_allocate_system_memory(&mms->psram,
 306                                          NULL, "mps.ram", 0x01000000);
 307     memory_region_add_subregion(system_memory, 0x80000000, &mms->psram);
 308
 309     /* The SSRAM memories should all be behind Memory Protection Controllers,
 310      * but we don't implement that yet.
 311      */
 312     make_ram(&mms->ssram1, "mps.ssram1", 0x00000000, 0x00400000);
 313     make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x00400000);
 314
 315     make_ram(&mms->ssram23, "mps.ssram23", 0x28000000, 0x00400000);
 316
 317     /* The overflow IRQs for all UARTs are ORed together.
 318      * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
 319      * Create the OR gate for this.
 320      */
 321     object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
 322                       TYPE_OR_IRQ);
 323     object_property_add_child(OBJECT(mms), "uart-irq-orgate",
 324                               OBJECT(&mms->uart_irq_orgate), &error_abort);
 325     object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
 326                             &error_fatal);
 327     object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
 328                              "realized", &error_fatal);
 329     qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
 330                           qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 15));
 331
 332     /* Most of the devices in the FPGA are behind Peripheral Protection
 333      * Controllers. The required order for initializing things is:
 334      *  + initialize the PPC
 335      *  + initialize, configure and realize downstream devices
 336      *  + connect downstream device MemoryRegions to the PPC
 337      *  + realize the PPC
 338      *  + map the PPC's MemoryRegions to the places in the address map
 339      *    where the downstream devices should appear
 340      *  + wire up the PPC's control lines to the IoTKit object
 341      */
 342
 343     const PPCInfo ppcs[] = { {
 344             .name = "apb_ppcexp0",
 345             .ports = {
 346                 { "ssram-mpc0", make_unimp_dev, &mms->ssram_mpc[0],
 347                   0x58007000, 0x1000 },
 348                 { "ssram-mpc1", make_unimp_dev, &mms->ssram_mpc[1],
 349                   0x58008000, 0x1000 },
 350                 { "ssram-mpc2", make_unimp_dev, &mms->ssram_mpc[2],
 351                   0x58009000, 0x1000 },
 352             },
 353         }, {
 354             .name = "apb_ppcexp1",
 355             .ports = {
 356                 { "spi0", make_unimp_dev, &mms->spi[0], 0x40205000, 0x1000 },
 357                 { "spi1", make_unimp_dev, &mms->spi[1], 0x40206000, 0x1000 },
 358                 { "spi2", make_unimp_dev, &mms->spi[2], 0x40209000, 0x1000 },
 359                 { "spi3", make_unimp_dev, &mms->spi[3], 0x4020a000, 0x1000 },
 360                 { "spi4", make_unimp_dev, &mms->spi[4], 0x4020b000, 0x1000 },
 361                 { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 },
 362                 { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 },
 363                 { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 },
 364                 { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 },
 365                 { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 },
 366                 { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 },
 367                 { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 },
 368                 { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 },
 369                 { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 },
 370             },
 371         }, {
 372             .name = "apb_ppcexp2",
 373             .ports = {
 374                 { "scc", make_scc, &mms->scc, 0x40300000, 0x1000 },
 375                 { "i2s-audio", make_unimp_dev, &mms->i2s_audio,
 376                   0x40301000, 0x1000 },
 377                 { "fpgaio", make_fpgaio, &mms->fpgaio, 0x40302000, 0x1000 },
 378             },
 379         }, {
 380             .name = "ahb_ppcexp0",
 381             .ports = {
 382                 { "gfx", make_unimp_dev, &mms->gfx, 0x41000000, 0x140000 },
 383                 { "gpio0", make_unimp_dev, &mms->gpio[0], 0x40100000, 0x1000 },
 384                 { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 },
 385                 { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 },
 386                 { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 },
 387                 { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 },
 388             },
 389         }, {
 390             .name = "ahb_ppcexp1",
 391             .ports = {
 392                 { "dma0", make_unimp_dev, &mms->dma[0], 0x40110000, 0x1000 },
 393                 { "dma1", make_unimp_dev, &mms->dma[1], 0x40111000, 0x1000 },
 394                 { "dma2", make_unimp_dev, &mms->dma[2], 0x40112000, 0x1000 },
 395                 { "dma3", make_unimp_dev, &mms->dma[3], 0x40113000, 0x1000 },
 396             },
 397         },
 398     };
 399
 400     for (i = 0; i < ARRAY_SIZE(ppcs); i++) {
 401         const PPCInfo *ppcinfo = &ppcs[i];
 402         TZPPC *ppc = &mms->ppc[i];
 403         DeviceState *ppcdev;
 404         int port;
 405         char *gpioname;
 406
 407         init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc,
 408                           sizeof(TZPPC), TYPE_TZ_PPC);
 409         ppcdev = DEVICE(ppc);
 410
 411         for (port = 0; port < TZ_NUM_PORTS; port++) {
 412             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 413             MemoryRegion *mr;
 414             char *portname;
 415
 416             if (!pinfo->devfn) {
 417                 continue;
 418             }
 419
 420             mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
 421             portname = g_strdup_printf("port[%d]", port);
 422             object_property_set_link(OBJECT(ppc), OBJECT(mr),
 423                                      portname, &error_fatal);
 424             g_free(portname);
 425         }
 426
 427         object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal);
 428
 429         for (port = 0; port < TZ_NUM_PORTS; port++) {
 430             const PPCPortInfo *pinfo = &ppcinfo->ports[port];
 431
 432             if (!pinfo->devfn) {
 433                 continue;
 434             }
 435             sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
 436
 437             gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
 438             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 439                                         qdev_get_gpio_in_named(ppcdev,
 440                                                                "cfg_nonsec",
 441                                                                port));
 442             g_free(gpioname);
 443             gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
 444             qdev_connect_gpio_out_named(iotkitdev, gpioname, port,
 445                                         qdev_get_gpio_in_named(ppcdev,
 446                                                                "cfg_ap", port));
 447             g_free(gpioname);
 448         }
 449
 450         gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
 451         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 452                                     qdev_get_gpio_in_named(ppcdev,
 453                                                            "irq_enable", 0));
 454         g_free(gpioname);
 455         gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
 456         qdev_connect_gpio_out_named(iotkitdev, gpioname, 0,
 457                                     qdev_get_gpio_in_named(ppcdev,
 458                                                            "irq_clear", 0));
 459         g_free(gpioname);
 460         gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
 461         qdev_connect_gpio_out_named(ppcdev, "irq", 0,
 462                                     qdev_get_gpio_in_named(iotkitdev,
 463                                                            gpioname, 0));
 464         g_free(gpioname);
 465
 466         qdev_connect_gpio_out(dev_splitter, i,
 467                               qdev_get_gpio_in_named(ppcdev,
 468                                                      "cfg_sec_resp", 0));
 469     }
 470
 471     create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
 472
 473     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000);
 474 }
 475
 476 static void mps2tz_class_init(ObjectClass *oc, void *data)
 477 {
 478     MachineClass *mc = MACHINE_CLASS(oc);
 479
 480     mc->init = mps2tz_common_init;
 481     mc->max_cpus = 1;
 482 }
 483
 484 static void mps2tz_an505_class_init(ObjectClass *oc, void *data)
 485 {
 486     MachineClass *mc = MACHINE_CLASS(oc);
 487     MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 488
 489     mc->desc = "ARM MPS2 with AN505 FPGA image for Cortex-M33";
 490     mmc->fpga_type = FPGA_AN505;
 491     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
 492     mmc->scc_id = 0x41040000 | (505 << 4);
 493 }
 494
 495 static const TypeInfo mps2tz_info = {
 496     .name = TYPE_MPS2TZ_MACHINE,
 497     .parent = TYPE_MACHINE,
 498     .abstract = true,
 499     .instance_size = sizeof(MPS2TZMachineState),
 500     .class_size = sizeof(MPS2TZMachineClass),
 501     .class_init = mps2tz_class_init,
 502 };
 503
 504 static const TypeInfo mps2tz_an505_info = {
 505     .name = TYPE_MPS2TZ_AN505_MACHINE,
 506     .parent = TYPE_MPS2TZ_MACHINE,
 507     .class_init = mps2tz_an505_class_init,
 508 };
 509
 510 static void mps2tz_machine_init(void)
 511 {
 512     type_register_static(&mps2tz_info);
 513     type_register_static(&mps2tz_an505_info);
 514 }
 515
 516 type_init(mps2tz_machine_init);