tap: factor out common tap initialization
[qemu/ar7.git] / hw / a15mpcore.c
blobfe6c34ca53315c7a978f7c22d50d32a951532c93
1 /*
2 * Cortex-A15MPCore internal peripheral emulation.
4 * Copyright (c) 2012 Linaro Limited.
5 * Written by Peter Maydell.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "sysbus.h"
23 /* A15MP private memory region. */
25 typedef struct A15MPPrivState {
26 SysBusDevice busdev;
27 uint32_t num_cpu;
28 uint32_t num_irq;
29 MemoryRegion container;
30 DeviceState *gic;
31 } A15MPPrivState;
33 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
35 A15MPPrivState *s = (A15MPPrivState *)opaque;
36 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
39 static int a15mp_priv_init(SysBusDevice *dev)
41 A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
42 SysBusDevice *busdev;
44 s->gic = qdev_create(NULL, "arm_gic");
45 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
46 qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
47 qdev_prop_set_uint32(s->gic, "revision", 2);
48 qdev_init_nofail(s->gic);
49 busdev = SYS_BUS_DEVICE(s->gic);
51 /* Pass through outbound IRQ lines from the GIC */
52 sysbus_pass_irq(dev, busdev);
54 /* Pass through inbound GPIO lines to the GIC */
55 qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32);
57 /* Memory map (addresses are offsets from PERIPHBASE):
58 * 0x0000-0x0fff -- reserved
59 * 0x1000-0x1fff -- GIC Distributor
60 * 0x2000-0x2fff -- GIC CPU interface
61 * 0x4000-0x4fff -- GIC virtual interface control (not modelled)
62 * 0x5000-0x5fff -- GIC virtual interface control (not modelled)
63 * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
65 memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
66 memory_region_add_subregion(&s->container, 0x1000,
67 sysbus_mmio_get_region(busdev, 0));
68 memory_region_add_subregion(&s->container, 0x2000,
69 sysbus_mmio_get_region(busdev, 1));
71 sysbus_init_mmio(dev, &s->container);
72 return 0;
75 static Property a15mp_priv_properties[] = {
76 DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
77 /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
78 * IRQ lines (with another 32 internal). We default to 64+32, which
79 * is the number provided by the Cortex-A15MP test chip in the
80 * Versatile Express A15 development board.
81 * Other boards may differ and should set this property appropriately.
83 DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96),
84 DEFINE_PROP_END_OF_LIST(),
87 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
89 DeviceClass *dc = DEVICE_CLASS(klass);
90 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
91 k->init = a15mp_priv_init;
92 dc->props = a15mp_priv_properties;
93 /* We currently have no savable state */
96 static const TypeInfo a15mp_priv_info = {
97 .name = "a15mpcore_priv",
98 .parent = TYPE_SYS_BUS_DEVICE,
99 .instance_size = sizeof(A15MPPrivState),
100 .class_init = a15mp_priv_class_init,
103 static void a15mp_register_types(void)
105 type_register_static(&a15mp_priv_info);
108 type_init(a15mp_register_types)