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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200213-pull-request' into...
[qemu/ar7.git] / hw / scsi / esp-pci.c
blobd5a1f9e0174886ccd4614037580c6f30ad365740
1 /*
2 * QEMU ESP/NCR53C9x emulation
3 *
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/pci/pci.h"
28 #include "hw/irq.h"
29 #include "hw/nvram/eeprom93xx.h"
30 #include "hw/scsi/esp.h"
31 #include "migration/vmstate.h"
32 #include "trace.h"
33 #include "qapi/error.h"
34 #include "qemu/log.h"
35 #include "qemu/module.h"
36
37 #define TYPE_AM53C974_DEVICE "am53c974"
38
39 #define PCI_ESP(obj) \
40 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
41
42 #define DMA_CMD 0x0
43 #define DMA_STC 0x1
44 #define DMA_SPA 0x2
45 #define DMA_WBC 0x3
46 #define DMA_WAC 0x4
47 #define DMA_STAT 0x5
48 #define DMA_SMDLA 0x6
49 #define DMA_WMAC 0x7
50
51 #define DMA_CMD_MASK 0x03
52 #define DMA_CMD_DIAG 0x04
53 #define DMA_CMD_MDL 0x10
54 #define DMA_CMD_INTE_P 0x20
55 #define DMA_CMD_INTE_D 0x40
56 #define DMA_CMD_DIR 0x80
57
58 #define DMA_STAT_PWDN 0x01
59 #define DMA_STAT_ERROR 0x02
60 #define DMA_STAT_ABORT 0x04
61 #define DMA_STAT_DONE 0x08
62 #define DMA_STAT_SCSIINT 0x10
63 #define DMA_STAT_BCMBLT 0x20
64
65 #define SBAC_STATUS (1 << 24)
66
67 typedef struct PCIESPState {
68 /*< private >*/
69 PCIDevice parent_obj;
70 /*< public >*/
71
72 MemoryRegion io;
73 uint32_t dma_regs[8];
74 uint32_t sbac;
75 ESPState esp;
76 } PCIESPState;
77
78 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
79 {
80 trace_esp_pci_dma_idle(val);
81 esp_dma_enable(&pci->esp, 0, 0);
82 }
83
84 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
85 {
86 trace_esp_pci_dma_blast(val);
87 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
88 }
89
90 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
91 {
92 trace_esp_pci_dma_abort(val);
93 if (pci->esp.current_req) {
94 scsi_req_cancel(pci->esp.current_req);
95 }
96 }
97
98 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
99 {
100 trace_esp_pci_dma_start(val);
101
102 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
103 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
104 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
105
106 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
107 | DMA_STAT_DONE | DMA_STAT_ABORT
108 | DMA_STAT_ERROR | DMA_STAT_PWDN);
109
110 esp_dma_enable(&pci->esp, 0, 1);
111 }
112
113 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
114 {
115 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
116 switch (saddr) {
117 case DMA_CMD:
118 pci->dma_regs[saddr] = val;
119 switch (val & DMA_CMD_MASK) {
120 case 0x0: /* IDLE */
121 esp_pci_handle_idle(pci, val);
122 break;
123 case 0x1: /* BLAST */
124 esp_pci_handle_blast(pci, val);
125 break;
126 case 0x2: /* ABORT */
127 esp_pci_handle_abort(pci, val);
128 break;
129 case 0x3: /* START */
130 esp_pci_handle_start(pci, val);
131 break;
132 default: /* can't happen */
133 abort();
134 }
135 break;
136 case DMA_STC:
137 case DMA_SPA:
138 case DMA_SMDLA:
139 pci->dma_regs[saddr] = val;
140 break;
141 case DMA_STAT:
142 if (pci->sbac & SBAC_STATUS) {
143 /* clear some bits on write */
144 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
145 pci->dma_regs[DMA_STAT] &= ~(val & mask);
146 }
147 break;
148 default:
149 trace_esp_pci_error_invalid_write_dma(val, saddr);
150 return;
151 }
152 }
153
154 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
155 {
156 uint32_t val;
157
158 val = pci->dma_regs[saddr];
159 if (saddr == DMA_STAT) {
160 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
161 val |= DMA_STAT_SCSIINT;
162 }
163 if (!(pci->sbac & SBAC_STATUS)) {
164 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
165 DMA_STAT_DONE);
166 }
167 }
168
169 trace_esp_pci_dma_read(saddr, val);
170 return val;
171 }
172
173 static void esp_pci_io_write(void *opaque, hwaddr addr,
174 uint64_t val, unsigned int size)
175 {
176 PCIESPState *pci = opaque;
177
178 if (size < 4 || addr & 3) {
179 /* need to upgrade request: we only support 4-bytes accesses */
180 uint32_t current = 0, mask;
181 int shift;
182
183 if (addr < 0x40) {
184 current = pci->esp.wregs[addr >> 2];
185 } else if (addr < 0x60) {
186 current = pci->dma_regs[(addr - 0x40) >> 2];
187 } else if (addr < 0x74) {
188 current = pci->sbac;
189 }
190
191 shift = (4 - size) * 8;
192 mask = (~(uint32_t)0 << shift) >> shift;
193
194 shift = ((4 - (addr & 3)) & 3) * 8;
195 val <<= shift;
196 val |= current & ~(mask << shift);
197 addr &= ~3;
198 size = 4;
199 }
200
201 if (addr < 0x40) {
202 /* SCSI core reg */
203 esp_reg_write(&pci->esp, addr >> 2, val);
204 } else if (addr < 0x60) {
205 /* PCI DMA CCB */
206 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
207 } else if (addr == 0x70) {
208 /* DMA SCSI Bus and control */
209 trace_esp_pci_sbac_write(pci->sbac, val);
210 pci->sbac = val;
211 } else {
212 trace_esp_pci_error_invalid_write((int)addr);
213 }
214 }
215
216 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
217 unsigned int size)
218 {
219 PCIESPState *pci = opaque;
220 uint32_t ret;
221
222 if (addr < 0x40) {
223 /* SCSI core reg */
224 ret = esp_reg_read(&pci->esp, addr >> 2);
225 } else if (addr < 0x60) {
226 /* PCI DMA CCB */
227 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
228 } else if (addr == 0x70) {
229 /* DMA SCSI Bus and control */
230 trace_esp_pci_sbac_read(pci->sbac);
231 ret = pci->sbac;
232 } else {
233 /* Invalid region */
234 trace_esp_pci_error_invalid_read((int)addr);
235 ret = 0;
236 }
237
238 /* give only requested data */
239 ret >>= (addr & 3) * 8;
240 ret &= ~(~(uint64_t)0 << (8 * size));
241
242 return ret;
243 }
244
245 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
246 DMADirection dir)
247 {
248 dma_addr_t addr;
249 DMADirection expected_dir;
250
251 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
252 expected_dir = DMA_DIRECTION_FROM_DEVICE;
253 } else {
254 expected_dir = DMA_DIRECTION_TO_DEVICE;
255 }
256
257 if (dir != expected_dir) {
258 trace_esp_pci_error_invalid_dma_direction();
259 return;
260 }
261
262 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
263 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
264 }
265
266 addr = pci->dma_regs[DMA_SPA];
267 if (pci->dma_regs[DMA_WBC] < len) {
268 len = pci->dma_regs[DMA_WBC];
269 }
270
271 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
272
273 /* update status registers */
274 pci->dma_regs[DMA_WBC] -= len;
275 pci->dma_regs[DMA_WAC] += len;
276 if (pci->dma_regs[DMA_WBC] == 0) {
277 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
278 }
279 }
280
281 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
282 {
283 PCIESPState *pci = opaque;
284 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
285 }
286
287 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
288 {
289 PCIESPState *pci = opaque;
290 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
291 }
292
293 static const MemoryRegionOps esp_pci_io_ops = {
294 .read = esp_pci_io_read,
295 .write = esp_pci_io_write,
296 .endianness = DEVICE_LITTLE_ENDIAN,
297 .impl = {
298 .min_access_size = 1,
299 .max_access_size = 4,
300 },
301 };
302
303 static void esp_pci_hard_reset(DeviceState *dev)
304 {
305 PCIESPState *pci = PCI_ESP(dev);
306 esp_hard_reset(&pci->esp);
307 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
308 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
309 pci->dma_regs[DMA_WBC] &= ~0xffff;
310 pci->dma_regs[DMA_WAC] = 0xffffffff;
311 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
312 | DMA_STAT_DONE | DMA_STAT_ABORT
313 | DMA_STAT_ERROR);
314 pci->dma_regs[DMA_WMAC] = 0xfffffffd;
315 }
316
317 static const VMStateDescription vmstate_esp_pci_scsi = {
318 .name = "pciespscsi",
319 .version_id = 1,
320 .minimum_version_id = 1,
321 .fields = (VMStateField[]) {
322 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
323 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
324 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
325 VMSTATE_END_OF_LIST()
326 }
327 };
328
329 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
330 size_t resid)
331 {
332 ESPState *s = req->hba_private;
333 PCIESPState *pci = container_of(s, PCIESPState, esp);
334
335 esp_command_complete(req, status, resid);
336 pci->dma_regs[DMA_WBC] = 0;
337 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
338 }
339
340 static const struct SCSIBusInfo esp_pci_scsi_info = {
341 .tcq = false,
342 .max_target = ESP_MAX_DEVS,
343 .max_lun = 7,
344
345 .transfer_data = esp_transfer_data,
346 .complete = esp_pci_command_complete,
347 .cancel = esp_request_cancelled,
348 };
349
350 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
351 {
352 PCIESPState *pci = PCI_ESP(dev);
353 DeviceState *d = DEVICE(dev);
354 ESPState *s = &pci->esp;
355 uint8_t *pci_conf;
356
357 pci_conf = dev->config;
358
359 /* Interrupt pin A */
360 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
361
362 s->dma_memory_read = esp_pci_dma_memory_read;
363 s->dma_memory_write = esp_pci_dma_memory_write;
364 s->dma_opaque = pci;
365 s->chip_id = TCHI_AM53C974;
366 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
367 "esp-io", 0x80);
368
369 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
370 s->irq = pci_allocate_irq(dev);
371
372 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
373 }
374
375 static void esp_pci_scsi_uninit(PCIDevice *d)
376 {
377 PCIESPState *pci = PCI_ESP(d);
378
379 qemu_free_irq(pci->esp.irq);
380 }
381
382 static void esp_pci_class_init(ObjectClass *klass, void *data)
383 {
384 DeviceClass *dc = DEVICE_CLASS(klass);
385 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
386
387 k->realize = esp_pci_scsi_realize;
388 k->exit = esp_pci_scsi_uninit;
389 k->vendor_id = PCI_VENDOR_ID_AMD;
390 k->device_id = PCI_DEVICE_ID_AMD_SCSI;
391 k->revision = 0x10;
392 k->class_id = PCI_CLASS_STORAGE_SCSI;
393 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
394 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
395 dc->reset = esp_pci_hard_reset;
396 dc->vmsd = &vmstate_esp_pci_scsi;
397 }
398
399 static const TypeInfo esp_pci_info = {
400 .name = TYPE_AM53C974_DEVICE,
401 .parent = TYPE_PCI_DEVICE,
402 .instance_size = sizeof(PCIESPState),
403 .class_init = esp_pci_class_init,
404 .interfaces = (InterfaceInfo[]) {
405 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
406 { },
407 },
408 };
409
410 typedef struct {
411 PCIESPState pci;
412 eeprom_t *eeprom;
413 } DC390State;
414
415 #define TYPE_DC390_DEVICE "dc390"
416 #define DC390(obj) \
417 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
418
419 #define EE_ADAPT_SCSI_ID 64
420 #define EE_MODE2 65
421 #define EE_DELAY 66
422 #define EE_TAG_CMD_NUM 67
423 #define EE_ADAPT_OPTIONS 68
424 #define EE_BOOT_SCSI_ID 69
425 #define EE_BOOT_SCSI_LUN 70
426 #define EE_CHKSUM1 126
427 #define EE_CHKSUM2 127
428
429 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
430 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
431 #define EE_ADAPT_OPTION_INT13 0x04
432 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
433
434
435 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
436 {
437 DC390State *pci = DC390(dev);
438 uint32_t val;
439
440 val = pci_default_read_config(dev, addr, l);
441
442 if (addr == 0x00 && l == 1) {
443 /* First byte of address space is AND-ed with EEPROM DO line */
444 if (!eeprom93xx_read(pci->eeprom)) {
445 val &= ~0xff;
446 }
447 }
448
449 return val;
450 }
451
452 static void dc390_write_config(PCIDevice *dev,
453 uint32_t addr, uint32_t val, int l)
454 {
455 DC390State *pci = DC390(dev);
456 if (addr == 0x80) {
457 /* EEPROM write */
458 int eesk = val & 0x80 ? 1 : 0;
459 int eedi = val & 0x40 ? 1 : 0;
460 eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
461 } else if (addr == 0xc0) {
462 /* EEPROM CS low */
463 eeprom93xx_write(pci->eeprom, 0, 0, 0);
464 } else {
465 pci_default_write_config(dev, addr, val, l);
466 }
467 }
468
469 static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
470 {
471 DC390State *pci = DC390(dev);
472 Error *err = NULL;
473 uint8_t *contents;
474 uint16_t chksum = 0;
475 int i;
476
477 /* init base class */
478 esp_pci_scsi_realize(dev, &err);
479 if (err) {
480 error_propagate(errp, err);
481 return;
482 }
483
484 /* EEPROM */
485 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
486
487 /* set default eeprom values */
488 contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
489
490 for (i = 0; i < 16; i++) {
491 contents[i * 2] = 0x57;
492 contents[i * 2 + 1] = 0x00;
493 }
494 contents[EE_ADAPT_SCSI_ID] = 7;
495 contents[EE_MODE2] = 0x0f;
496 contents[EE_TAG_CMD_NUM] = 0x04;
497 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
498 | EE_ADAPT_OPTION_BOOT_FROM_CDROM
499 | EE_ADAPT_OPTION_INT13;
500
501 /* update eeprom checksum */
502 for (i = 0; i < EE_CHKSUM1; i += 2) {
503 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
504 }
505 chksum = 0x1234 - chksum;
506 contents[EE_CHKSUM1] = chksum & 0xff;
507 contents[EE_CHKSUM2] = chksum >> 8;
508 }
509
510 static void dc390_class_init(ObjectClass *klass, void *data)
511 {
512 DeviceClass *dc = DEVICE_CLASS(klass);
513 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
514
515 k->realize = dc390_scsi_realize;
516 k->config_read = dc390_read_config;
517 k->config_write = dc390_write_config;
518 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
519 dc->desc = "Tekram DC-390 SCSI adapter";
520 }
521
522 static const TypeInfo dc390_info = {
523 .name = "dc390",
524 .parent = TYPE_AM53C974_DEVICE,
525 .instance_size = sizeof(DC390State),
526 .class_init = dc390_class_init,
527 };
528
529 static void esp_pci_register_types(void)
530 {
531 type_register_static(&esp_pci_info);
532 type_register_static(&dc390_info);
533 }
534
535 type_init(esp_pci_register_types)
AR7 emulation for QEMU