2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "sysemu/kvm.h"
25 #ifndef CONFIG_USER_ONLY
26 #include "sysemu/sysemu.h"
27 #include "sysemu/hw_accel.h"
28 #include "monitor/monitor.h"
29 #include "hw/i386/apic_internal.h"
32 static void cpu_x86_version(CPUX86State
*env
, int *family
, int *model
)
34 int cpuver
= env
->cpuid_version
;
36 if (family
== NULL
|| model
== NULL
) {
40 *family
= (cpuver
>> 8) & 0x0f;
41 *model
= ((cpuver
>> 12) & 0xf0) + ((cpuver
>> 4) & 0x0f);
44 /* Broadcast MCA signal for processor version 06H_EH and above */
45 int cpu_x86_support_mca_broadcast(CPUX86State
*env
)
50 cpu_x86_version(env
, &family
, &model
);
51 if ((family
== 6 && model
>= 14) || family
> 6) {
58 /***********************************************************/
61 static const char *cc_op_str
[CC_OP_NB
] = {
128 cpu_x86_dump_seg_cache(CPUX86State
*env
, FILE *f
, fprintf_function cpu_fprintf
,
129 const char *name
, struct SegmentCache
*sc
)
132 if (env
->hflags
& HF_CS64_MASK
) {
133 cpu_fprintf(f
, "%-3s=%04x %016" PRIx64
" %08x %08x", name
,
134 sc
->selector
, sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
138 cpu_fprintf(f
, "%-3s=%04x %08x %08x %08x", name
, sc
->selector
,
139 (uint32_t)sc
->base
, sc
->limit
, sc
->flags
& 0x00ffff00);
142 if (!(env
->hflags
& HF_PE_MASK
) || !(sc
->flags
& DESC_P_MASK
))
145 cpu_fprintf(f
, " DPL=%d ", (sc
->flags
& DESC_DPL_MASK
) >> DESC_DPL_SHIFT
);
146 if (sc
->flags
& DESC_S_MASK
) {
147 if (sc
->flags
& DESC_CS_MASK
) {
148 cpu_fprintf(f
, (sc
->flags
& DESC_L_MASK
) ? "CS64" :
149 ((sc
->flags
& DESC_B_MASK
) ? "CS32" : "CS16"));
150 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_C_MASK
) ? 'C' : '-',
151 (sc
->flags
& DESC_R_MASK
) ? 'R' : '-');
154 (sc
->flags
& DESC_B_MASK
|| env
->hflags
& HF_LMA_MASK
)
156 cpu_fprintf(f
, " [%c%c", (sc
->flags
& DESC_E_MASK
) ? 'E' : '-',
157 (sc
->flags
& DESC_W_MASK
) ? 'W' : '-');
159 cpu_fprintf(f
, "%c]", (sc
->flags
& DESC_A_MASK
) ? 'A' : '-');
161 static const char *sys_type_name
[2][16] = {
163 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
164 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
165 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
166 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
169 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
170 "Reserved", "Reserved", "Reserved", "Reserved",
171 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
172 "Reserved", "IntGate64", "TrapGate64"
176 sys_type_name
[(env
->hflags
& HF_LMA_MASK
) ? 1 : 0]
177 [(sc
->flags
& DESC_TYPE_MASK
)
178 >> DESC_TYPE_SHIFT
]);
181 cpu_fprintf(f
, "\n");
184 #ifndef CONFIG_USER_ONLY
186 /* ARRAY_SIZE check is not required because
187 * DeliveryMode(dm) has a size of 3 bit.
189 static inline const char *dm2str(uint32_t dm
)
191 static const char *str
[] = {
204 static void dump_apic_lvt(FILE *f
, fprintf_function cpu_fprintf
,
205 const char *name
, uint32_t lvt
, bool is_timer
)
207 uint32_t dm
= (lvt
& APIC_LVT_DELIV_MOD
) >> APIC_LVT_DELIV_MOD_SHIFT
;
209 "%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
211 lvt
& APIC_LVT_INT_POLARITY
? "active-lo" : "active-hi",
212 lvt
& APIC_LVT_LEVEL_TRIGGER
? "level" : "edge",
213 lvt
& APIC_LVT_MASKED
? "masked" : "",
214 lvt
& APIC_LVT_DELIV_STS
? "pending" : "",
216 "" : lvt
& APIC_LVT_TIMER_PERIODIC
?
217 "periodic" : lvt
& APIC_LVT_TIMER_TSCDEADLINE
?
218 "tsc-deadline" : "one-shot",
220 if (dm
!= APIC_DM_NMI
) {
221 cpu_fprintf(f
, " (vec %u)\n", lvt
& APIC_VECTOR_MASK
);
223 cpu_fprintf(f
, "\n");
227 /* ARRAY_SIZE check is not required because
228 * destination shorthand has a size of 2 bit.
230 static inline const char *shorthand2str(uint32_t shorthand
)
232 const char *str
[] = {
233 "no-shorthand", "self", "all-self", "all"
235 return str
[shorthand
];
238 static inline uint8_t divider_conf(uint32_t divide_conf
)
240 uint8_t divide_val
= ((divide_conf
& 0x8) >> 1) | (divide_conf
& 0x3);
242 return divide_val
== 7 ? 1 : 2 << divide_val
;
245 static inline void mask2str(char *str
, uint32_t val
, uint8_t size
)
248 *str
++ = (val
>> size
) & 1 ? '1' : '0';
253 #define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
255 static void dump_apic_icr(FILE *f
, fprintf_function cpu_fprintf
,
256 APICCommonState
*s
, CPUX86State
*env
)
258 uint32_t icr
= s
->icr
[0], icr2
= s
->icr
[1];
259 uint8_t dest_shorthand
= \
260 (icr
& APIC_ICR_DEST_SHORT
) >> APIC_ICR_DEST_SHORT_SHIFT
;
261 bool logical_mod
= icr
& APIC_ICR_DEST_MOD
;
262 char apic_id_str
[MAX_LOGICAL_APIC_ID_MASK_SIZE
+ 1];
266 cpu_fprintf(f
, "ICR\t 0x%08x %s %s %s %s\n",
268 logical_mod
? "logical" : "physical",
269 icr
& APIC_ICR_TRIGGER_MOD
? "level" : "edge",
270 icr
& APIC_ICR_LEVEL
? "assert" : "de-assert",
271 shorthand2str(dest_shorthand
));
273 cpu_fprintf(f
, "ICR2\t 0x%08x", icr2
);
274 if (dest_shorthand
!= 0) {
275 cpu_fprintf(f
, "\n");
278 x2apic
= env
->features
[FEAT_1_ECX
] & CPUID_EXT_X2APIC
;
279 dest_field
= x2apic
? icr2
: icr2
>> APIC_ICR_DEST_SHIFT
;
283 cpu_fprintf(f
, " cpu %u (X2APIC ID)\n", dest_field
);
285 cpu_fprintf(f
, " cpu %u (APIC ID)\n",
286 dest_field
& APIC_LOGDEST_XAPIC_ID
);
291 if (s
->dest_mode
== 0xf) { /* flat mode */
292 mask2str(apic_id_str
, icr2
>> APIC_ICR_DEST_SHIFT
, 8);
293 cpu_fprintf(f
, " mask %s (APIC ID)\n", apic_id_str
);
294 } else if (s
->dest_mode
== 0) { /* cluster mode */
296 mask2str(apic_id_str
, dest_field
& APIC_LOGDEST_X2APIC_ID
, 16);
297 cpu_fprintf(f
, " cluster %u mask %s (X2APIC ID)\n",
298 dest_field
>> APIC_LOGDEST_X2APIC_SHIFT
, apic_id_str
);
300 mask2str(apic_id_str
, dest_field
& APIC_LOGDEST_XAPIC_ID
, 4);
301 cpu_fprintf(f
, " cluster %u mask %s (APIC ID)\n",
302 dest_field
>> APIC_LOGDEST_XAPIC_SHIFT
, apic_id_str
);
307 static void dump_apic_interrupt(FILE *f
, fprintf_function cpu_fprintf
,
308 const char *name
, uint32_t *ireg_tab
,
313 cpu_fprintf(f
, "%s\t ", name
);
314 for (i
= 0; i
< 256; i
++) {
315 if (apic_get_bit(ireg_tab
, i
)) {
316 cpu_fprintf(f
, "%u%s ", i
,
317 apic_get_bit(tmr_tab
, i
) ? "(level)" : "");
321 cpu_fprintf(f
, "%s\n", empty
? "(none)" : "");
324 void x86_cpu_dump_local_apic_state(CPUState
*cs
, FILE *f
,
325 fprintf_function cpu_fprintf
, int flags
)
327 X86CPU
*cpu
= X86_CPU(cs
);
328 APICCommonState
*s
= APIC_COMMON(cpu
->apic_state
);
329 uint32_t *lvt
= s
->lvt
;
331 cpu_fprintf(f
, "dumping local APIC state for CPU %-2u\n\n",
332 CPU(cpu
)->cpu_index
);
333 dump_apic_lvt(f
, cpu_fprintf
, "LVT0", lvt
[APIC_LVT_LINT0
], false);
334 dump_apic_lvt(f
, cpu_fprintf
, "LVT1", lvt
[APIC_LVT_LINT1
], false);
335 dump_apic_lvt(f
, cpu_fprintf
, "LVTPC", lvt
[APIC_LVT_PERFORM
], false);
336 dump_apic_lvt(f
, cpu_fprintf
, "LVTERR", lvt
[APIC_LVT_ERROR
], false);
337 dump_apic_lvt(f
, cpu_fprintf
, "LVTTHMR", lvt
[APIC_LVT_THERMAL
], false);
338 dump_apic_lvt(f
, cpu_fprintf
, "LVTT", lvt
[APIC_LVT_TIMER
], true);
340 cpu_fprintf(f
, "Timer\t DCR=0x%x (divide by %u) initial_count = %u\n",
341 s
->divide_conf
& APIC_DCR_MASK
,
342 divider_conf(s
->divide_conf
),
345 cpu_fprintf(f
, "SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
347 s
->spurious_vec
& APIC_SPURIO_ENABLED
? "enabled" : "disabled",
348 s
->spurious_vec
& APIC_SPURIO_FOCUS
? "on" : "off",
349 s
->spurious_vec
& APIC_VECTOR_MASK
);
351 dump_apic_icr(f
, cpu_fprintf
, s
, &cpu
->env
);
353 cpu_fprintf(f
, "ESR\t 0x%08x\n", s
->esr
);
355 dump_apic_interrupt(f
, cpu_fprintf
, "ISR", s
->isr
, s
->tmr
);
356 dump_apic_interrupt(f
, cpu_fprintf
, "IRR", s
->irr
, s
->tmr
);
358 cpu_fprintf(f
, "\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
359 s
->arb_id
, s
->tpr
, s
->dest_mode
, s
->log_dest
);
360 if (s
->dest_mode
== 0) {
361 cpu_fprintf(f
, "(cluster %u: id %u)",
362 s
->log_dest
>> APIC_LOGDEST_XAPIC_SHIFT
,
363 s
->log_dest
& APIC_LOGDEST_XAPIC_ID
);
365 cpu_fprintf(f
, " PPR 0x%02x\n", apic_get_ppr(s
));
368 void x86_cpu_dump_local_apic_state(CPUState
*cs
, FILE *f
,
369 fprintf_function cpu_fprintf
, int flags
)
372 #endif /* !CONFIG_USER_ONLY */
374 #define DUMP_CODE_BYTES_TOTAL 50
375 #define DUMP_CODE_BYTES_BACKWARD 20
377 void x86_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
380 X86CPU
*cpu
= X86_CPU(cs
);
381 CPUX86State
*env
= &cpu
->env
;
384 static const char *seg_name
[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
386 eflags
= cpu_compute_eflags(env
);
388 if (env
->hflags
& HF_CS64_MASK
) {
390 "RAX=%016" PRIx64
" RBX=%016" PRIx64
" RCX=%016" PRIx64
" RDX=%016" PRIx64
"\n"
391 "RSI=%016" PRIx64
" RDI=%016" PRIx64
" RBP=%016" PRIx64
" RSP=%016" PRIx64
"\n"
392 "R8 =%016" PRIx64
" R9 =%016" PRIx64
" R10=%016" PRIx64
" R11=%016" PRIx64
"\n"
393 "R12=%016" PRIx64
" R13=%016" PRIx64
" R14=%016" PRIx64
" R15=%016" PRIx64
"\n"
394 "RIP=%016" PRIx64
" RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
412 eflags
& DF_MASK
? 'D' : '-',
413 eflags
& CC_O
? 'O' : '-',
414 eflags
& CC_S
? 'S' : '-',
415 eflags
& CC_Z
? 'Z' : '-',
416 eflags
& CC_A
? 'A' : '-',
417 eflags
& CC_P
? 'P' : '-',
418 eflags
& CC_C
? 'C' : '-',
419 env
->hflags
& HF_CPL_MASK
,
420 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
421 (env
->a20_mask
>> 20) & 1,
422 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
427 cpu_fprintf(f
, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
428 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
429 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
430 (uint32_t)env
->regs
[R_EAX
],
431 (uint32_t)env
->regs
[R_EBX
],
432 (uint32_t)env
->regs
[R_ECX
],
433 (uint32_t)env
->regs
[R_EDX
],
434 (uint32_t)env
->regs
[R_ESI
],
435 (uint32_t)env
->regs
[R_EDI
],
436 (uint32_t)env
->regs
[R_EBP
],
437 (uint32_t)env
->regs
[R_ESP
],
438 (uint32_t)env
->eip
, eflags
,
439 eflags
& DF_MASK
? 'D' : '-',
440 eflags
& CC_O
? 'O' : '-',
441 eflags
& CC_S
? 'S' : '-',
442 eflags
& CC_Z
? 'Z' : '-',
443 eflags
& CC_A
? 'A' : '-',
444 eflags
& CC_P
? 'P' : '-',
445 eflags
& CC_C
? 'C' : '-',
446 env
->hflags
& HF_CPL_MASK
,
447 (env
->hflags
>> HF_INHIBIT_IRQ_SHIFT
) & 1,
448 (env
->a20_mask
>> 20) & 1,
449 (env
->hflags
>> HF_SMM_SHIFT
) & 1,
453 for(i
= 0; i
< 6; i
++) {
454 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, seg_name
[i
],
457 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "LDT", &env
->ldt
);
458 cpu_x86_dump_seg_cache(env
, f
, cpu_fprintf
, "TR", &env
->tr
);
461 if (env
->hflags
& HF_LMA_MASK
) {
462 cpu_fprintf(f
, "GDT= %016" PRIx64
" %08x\n",
463 env
->gdt
.base
, env
->gdt
.limit
);
464 cpu_fprintf(f
, "IDT= %016" PRIx64
" %08x\n",
465 env
->idt
.base
, env
->idt
.limit
);
466 cpu_fprintf(f
, "CR0=%08x CR2=%016" PRIx64
" CR3=%016" PRIx64
" CR4=%08x\n",
467 (uint32_t)env
->cr
[0],
470 (uint32_t)env
->cr
[4]);
471 for(i
= 0; i
< 4; i
++)
472 cpu_fprintf(f
, "DR%d=%016" PRIx64
" ", i
, env
->dr
[i
]);
473 cpu_fprintf(f
, "\nDR6=%016" PRIx64
" DR7=%016" PRIx64
"\n",
474 env
->dr
[6], env
->dr
[7]);
478 cpu_fprintf(f
, "GDT= %08x %08x\n",
479 (uint32_t)env
->gdt
.base
, env
->gdt
.limit
);
480 cpu_fprintf(f
, "IDT= %08x %08x\n",
481 (uint32_t)env
->idt
.base
, env
->idt
.limit
);
482 cpu_fprintf(f
, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
483 (uint32_t)env
->cr
[0],
484 (uint32_t)env
->cr
[2],
485 (uint32_t)env
->cr
[3],
486 (uint32_t)env
->cr
[4]);
487 for(i
= 0; i
< 4; i
++) {
488 cpu_fprintf(f
, "DR%d=" TARGET_FMT_lx
" ", i
, env
->dr
[i
]);
490 cpu_fprintf(f
, "\nDR6=" TARGET_FMT_lx
" DR7=" TARGET_FMT_lx
"\n",
491 env
->dr
[6], env
->dr
[7]);
493 if (flags
& CPU_DUMP_CCOP
) {
494 if ((unsigned)env
->cc_op
< CC_OP_NB
)
495 snprintf(cc_op_name
, sizeof(cc_op_name
), "%s", cc_op_str
[env
->cc_op
]);
497 snprintf(cc_op_name
, sizeof(cc_op_name
), "[%d]", env
->cc_op
);
499 if (env
->hflags
& HF_CS64_MASK
) {
500 cpu_fprintf(f
, "CCS=%016" PRIx64
" CCD=%016" PRIx64
" CCO=%-8s\n",
501 env
->cc_src
, env
->cc_dst
,
506 cpu_fprintf(f
, "CCS=%08x CCD=%08x CCO=%-8s\n",
507 (uint32_t)env
->cc_src
, (uint32_t)env
->cc_dst
,
511 cpu_fprintf(f
, "EFER=%016" PRIx64
"\n", env
->efer
);
512 if (flags
& CPU_DUMP_FPU
) {
515 for(i
= 0; i
< 8; i
++) {
516 fptag
|= ((!env
->fptags
[i
]) << i
);
518 cpu_fprintf(f
, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
520 (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11,
526 u
.d
= env
->fpregs
[i
].d
;
527 cpu_fprintf(f
, "FPR%d=%016" PRIx64
" %04x",
528 i
, u
.l
.lower
, u
.l
.upper
);
530 cpu_fprintf(f
, "\n");
534 if (env
->hflags
& HF_CS64_MASK
)
539 cpu_fprintf(f
, "XMM%02d=%08x%08x%08x%08x",
541 env
->xmm_regs
[i
].ZMM_L(3),
542 env
->xmm_regs
[i
].ZMM_L(2),
543 env
->xmm_regs
[i
].ZMM_L(1),
544 env
->xmm_regs
[i
].ZMM_L(0));
546 cpu_fprintf(f
, "\n");
551 if (flags
& CPU_DUMP_CODE
) {
552 target_ulong base
= env
->segs
[R_CS
].base
+ env
->eip
;
553 target_ulong offs
= MIN(env
->eip
, DUMP_CODE_BYTES_BACKWARD
);
557 cpu_fprintf(f
, "Code=");
558 for (i
= 0; i
< DUMP_CODE_BYTES_TOTAL
; i
++) {
559 if (cpu_memory_rw_debug(cs
, base
- offs
+ i
, &code
, 1, 0) == 0) {
560 snprintf(codestr
, sizeof(codestr
), "%02x", code
);
562 snprintf(codestr
, sizeof(codestr
), "??");
564 cpu_fprintf(f
, "%s%s%s%s", i
> 0 ? " " : "",
565 i
== offs
? "<" : "", codestr
, i
== offs
? ">" : "");
567 cpu_fprintf(f
, "\n");
571 /***********************************************************/
573 /* XXX: add PGE support */
575 void x86_cpu_set_a20(X86CPU
*cpu
, int a20_state
)
577 CPUX86State
*env
= &cpu
->env
;
579 a20_state
= (a20_state
!= 0);
580 if (a20_state
!= ((env
->a20_mask
>> 20) & 1)) {
581 CPUState
*cs
= CPU(cpu
);
583 qemu_log_mask(CPU_LOG_MMU
, "A20 update: a20=%d\n", a20_state
);
584 /* if the cpu is currently executing code, we must unlink it and
585 all the potentially executing TB */
586 cpu_interrupt(cs
, CPU_INTERRUPT_EXITTB
);
588 /* when a20 is changed, all the MMU mappings are invalid, so
589 we must flush everything */
591 env
->a20_mask
= ~(1 << 20) | (a20_state
<< 20);
595 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
)
597 X86CPU
*cpu
= x86_env_get_cpu(env
);
600 qemu_log_mask(CPU_LOG_MMU
, "CR0 update: CR0=0x%08x\n", new_cr0
);
601 if ((new_cr0
& (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
)) !=
602 (env
->cr
[0] & (CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
))) {
607 if (!(env
->cr
[0] & CR0_PG_MASK
) && (new_cr0
& CR0_PG_MASK
) &&
608 (env
->efer
& MSR_EFER_LME
)) {
609 /* enter in long mode */
610 /* XXX: generate an exception */
611 if (!(env
->cr
[4] & CR4_PAE_MASK
))
613 env
->efer
|= MSR_EFER_LMA
;
614 env
->hflags
|= HF_LMA_MASK
;
615 } else if ((env
->cr
[0] & CR0_PG_MASK
) && !(new_cr0
& CR0_PG_MASK
) &&
616 (env
->efer
& MSR_EFER_LMA
)) {
618 env
->efer
&= ~MSR_EFER_LMA
;
619 env
->hflags
&= ~(HF_LMA_MASK
| HF_CS64_MASK
);
620 env
->eip
&= 0xffffffff;
623 env
->cr
[0] = new_cr0
| CR0_ET_MASK
;
625 /* update PE flag in hidden flags */
626 pe_state
= (env
->cr
[0] & CR0_PE_MASK
);
627 env
->hflags
= (env
->hflags
& ~HF_PE_MASK
) | (pe_state
<< HF_PE_SHIFT
);
628 /* ensure that ADDSEG is always set in real mode */
629 env
->hflags
|= ((pe_state
^ 1) << HF_ADDSEG_SHIFT
);
630 /* update FPU flags */
631 env
->hflags
= (env
->hflags
& ~(HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
)) |
632 ((new_cr0
<< (HF_MP_SHIFT
- 1)) & (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
));
635 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
637 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
)
639 X86CPU
*cpu
= x86_env_get_cpu(env
);
641 env
->cr
[3] = new_cr3
;
642 if (env
->cr
[0] & CR0_PG_MASK
) {
643 qemu_log_mask(CPU_LOG_MMU
,
644 "CR3 update: CR3=" TARGET_FMT_lx
"\n", new_cr3
);
649 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
)
651 X86CPU
*cpu
= x86_env_get_cpu(env
);
654 #if defined(DEBUG_MMU)
655 printf("CR4 update: %08x -> %08x\n", (uint32_t)env
->cr
[4], new_cr4
);
657 if ((new_cr4
^ env
->cr
[4]) &
658 (CR4_PGE_MASK
| CR4_PAE_MASK
| CR4_PSE_MASK
|
659 CR4_SMEP_MASK
| CR4_SMAP_MASK
| CR4_LA57_MASK
)) {
663 /* Clear bits we're going to recompute. */
664 hflags
= env
->hflags
& ~(HF_OSFXSR_MASK
| HF_SMAP_MASK
);
667 if (!(env
->features
[FEAT_1_EDX
] & CPUID_SSE
)) {
668 new_cr4
&= ~CR4_OSFXSR_MASK
;
670 if (new_cr4
& CR4_OSFXSR_MASK
) {
671 hflags
|= HF_OSFXSR_MASK
;
674 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SMAP
)) {
675 new_cr4
&= ~CR4_SMAP_MASK
;
677 if (new_cr4
& CR4_SMAP_MASK
) {
678 hflags
|= HF_SMAP_MASK
;
681 if (!(env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_PKU
)) {
682 new_cr4
&= ~CR4_PKE_MASK
;
685 env
->cr
[4] = new_cr4
;
686 env
->hflags
= hflags
;
688 cpu_sync_bndcs_hflags(env
);
691 #if defined(CONFIG_USER_ONLY)
693 int x86_cpu_handle_mmu_fault(CPUState
*cs
, vaddr addr
,
694 int is_write
, int mmu_idx
)
696 X86CPU
*cpu
= X86_CPU(cs
);
697 CPUX86State
*env
= &cpu
->env
;
699 /* user mode only emulation */
702 env
->error_code
= (is_write
<< PG_ERROR_W_BIT
);
703 env
->error_code
|= PG_ERROR_U_MASK
;
704 cs
->exception_index
= EXCP0E_PAGE
;
705 env
->exception_is_int
= 0;
706 env
->exception_next_eip
= -1;
713 * -1 = cannot handle fault
714 * 0 = nothing more to do
715 * 1 = generate PF fault
717 int x86_cpu_handle_mmu_fault(CPUState
*cs
, vaddr addr
,
718 int is_write1
, int mmu_idx
)
720 X86CPU
*cpu
= X86_CPU(cs
);
721 CPUX86State
*env
= &cpu
->env
;
723 target_ulong pde_addr
, pte_addr
;
725 int is_dirty
, prot
, page_size
, is_write
, is_user
;
727 uint64_t rsvd_mask
= PG_HI_RSVD_MASK
;
728 uint32_t page_offset
;
731 is_user
= mmu_idx
== MMU_USER_IDX
;
732 #if defined(DEBUG_MMU)
733 printf("MMU fault: addr=%" VADDR_PRIx
" w=%d u=%d eip=" TARGET_FMT_lx
"\n",
734 addr
, is_write1
, is_user
, env
->eip
);
736 is_write
= is_write1
& 1;
738 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
741 if (!(env
->hflags
& HF_LMA_MASK
)) {
742 /* Without long mode we can only address 32bits in real mode */
746 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
751 if (!(env
->efer
& MSR_EFER_NXE
)) {
752 rsvd_mask
|= PG_NX_MASK
;
755 if (env
->cr
[4] & CR4_PAE_MASK
) {
757 target_ulong pdpe_addr
;
760 if (env
->hflags
& HF_LMA_MASK
) {
761 bool la57
= env
->cr
[4] & CR4_LA57_MASK
;
762 uint64_t pml5e_addr
, pml5e
;
763 uint64_t pml4e_addr
, pml4e
;
766 /* test virtual address sign extension */
767 sext
= la57
? (int64_t)addr
>> 56 : (int64_t)addr
>> 47;
768 if (sext
!= 0 && sext
!= -1) {
770 cs
->exception_index
= EXCP0D_GPF
;
775 pml5e_addr
= ((env
->cr
[3] & ~0xfff) +
776 (((addr
>> 48) & 0x1ff) << 3)) & env
->a20_mask
;
777 pml5e
= x86_ldq_phys(cs
, pml5e_addr
);
778 if (!(pml5e
& PG_PRESENT_MASK
)) {
781 if (pml5e
& (rsvd_mask
| PG_PSE_MASK
)) {
784 if (!(pml5e
& PG_ACCESSED_MASK
)) {
785 pml5e
|= PG_ACCESSED_MASK
;
786 x86_stl_phys_notdirty(cs
, pml5e_addr
, pml5e
);
788 ptep
= pml5e
^ PG_NX_MASK
;
791 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
794 pml4e_addr
= ((pml5e
& PG_ADDRESS_MASK
) +
795 (((addr
>> 39) & 0x1ff) << 3)) & env
->a20_mask
;
796 pml4e
= x86_ldq_phys(cs
, pml4e_addr
);
797 if (!(pml4e
& PG_PRESENT_MASK
)) {
800 if (pml4e
& (rsvd_mask
| PG_PSE_MASK
)) {
803 if (!(pml4e
& PG_ACCESSED_MASK
)) {
804 pml4e
|= PG_ACCESSED_MASK
;
805 x86_stl_phys_notdirty(cs
, pml4e_addr
, pml4e
);
807 ptep
&= pml4e
^ PG_NX_MASK
;
808 pdpe_addr
= ((pml4e
& PG_ADDRESS_MASK
) + (((addr
>> 30) & 0x1ff) << 3)) &
810 pdpe
= x86_ldq_phys(cs
, pdpe_addr
);
811 if (!(pdpe
& PG_PRESENT_MASK
)) {
814 if (pdpe
& rsvd_mask
) {
817 ptep
&= pdpe
^ PG_NX_MASK
;
818 if (!(pdpe
& PG_ACCESSED_MASK
)) {
819 pdpe
|= PG_ACCESSED_MASK
;
820 x86_stl_phys_notdirty(cs
, pdpe_addr
, pdpe
);
822 if (pdpe
& PG_PSE_MASK
) {
824 page_size
= 1024 * 1024 * 1024;
825 pte_addr
= pdpe_addr
;
827 goto do_check_protect
;
832 /* XXX: load them when cr3 is loaded ? */
833 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
835 pdpe
= x86_ldq_phys(cs
, pdpe_addr
);
836 if (!(pdpe
& PG_PRESENT_MASK
)) {
839 rsvd_mask
|= PG_HI_USER_MASK
;
840 if (pdpe
& (rsvd_mask
| PG_NX_MASK
)) {
843 ptep
= PG_NX_MASK
| PG_USER_MASK
| PG_RW_MASK
;
846 pde_addr
= ((pdpe
& PG_ADDRESS_MASK
) + (((addr
>> 21) & 0x1ff) << 3)) &
848 pde
= x86_ldq_phys(cs
, pde_addr
);
849 if (!(pde
& PG_PRESENT_MASK
)) {
852 if (pde
& rsvd_mask
) {
855 ptep
&= pde
^ PG_NX_MASK
;
856 if (pde
& PG_PSE_MASK
) {
858 page_size
= 2048 * 1024;
861 goto do_check_protect
;
864 if (!(pde
& PG_ACCESSED_MASK
)) {
865 pde
|= PG_ACCESSED_MASK
;
866 x86_stl_phys_notdirty(cs
, pde_addr
, pde
);
868 pte_addr
= ((pde
& PG_ADDRESS_MASK
) + (((addr
>> 12) & 0x1ff) << 3)) &
870 pte
= x86_ldq_phys(cs
, pte_addr
);
871 if (!(pte
& PG_PRESENT_MASK
)) {
874 if (pte
& rsvd_mask
) {
877 /* combine pde and pte nx, user and rw protections */
878 ptep
&= pte
^ PG_NX_MASK
;
883 /* page directory entry */
884 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) &
886 pde
= x86_ldl_phys(cs
, pde_addr
);
887 if (!(pde
& PG_PRESENT_MASK
)) {
890 ptep
= pde
| PG_NX_MASK
;
892 /* if PSE bit is set, then we use a 4MB page */
893 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
894 page_size
= 4096 * 1024;
897 /* Bits 20-13 provide bits 39-32 of the address, bit 21 is reserved.
898 * Leave bits 20-13 in place for setting accessed/dirty bits below.
900 pte
= pde
| ((pde
& 0x1fe000LL
) << (32 - 13));
901 rsvd_mask
= 0x200000;
902 goto do_check_protect_pse36
;
905 if (!(pde
& PG_ACCESSED_MASK
)) {
906 pde
|= PG_ACCESSED_MASK
;
907 x86_stl_phys_notdirty(cs
, pde_addr
, pde
);
910 /* page directory entry */
911 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) &
913 pte
= x86_ldl_phys(cs
, pte_addr
);
914 if (!(pte
& PG_PRESENT_MASK
)) {
917 /* combine pde and pte user and rw protections */
918 ptep
&= pte
| PG_NX_MASK
;
924 rsvd_mask
|= (page_size
- 1) & PG_ADDRESS_MASK
& ~PG_PSE_PAT_MASK
;
925 do_check_protect_pse36
:
926 if (pte
& rsvd_mask
) {
931 /* can the page can be put in the TLB? prot will tell us */
932 if (is_user
&& !(ptep
& PG_USER_MASK
)) {
933 goto do_fault_protect
;
937 if (mmu_idx
!= MMU_KSMAP_IDX
|| !(ptep
& PG_USER_MASK
)) {
939 if ((ptep
& PG_RW_MASK
) || (!is_user
&& !(env
->cr
[0] & CR0_WP_MASK
))) {
943 if (!(ptep
& PG_NX_MASK
) &&
944 (mmu_idx
== MMU_USER_IDX
||
945 !((env
->cr
[4] & CR4_SMEP_MASK
) && (ptep
& PG_USER_MASK
)))) {
948 if ((env
->cr
[4] & CR4_PKE_MASK
) && (env
->hflags
& HF_LMA_MASK
) &&
949 (ptep
& PG_USER_MASK
) && env
->pkru
) {
950 uint32_t pk
= (pte
& PG_PKRU_MASK
) >> PG_PKRU_BIT
;
951 uint32_t pkru_ad
= (env
->pkru
>> pk
* 2) & 1;
952 uint32_t pkru_wd
= (env
->pkru
>> pk
* 2) & 2;
953 uint32_t pkru_prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
956 pkru_prot
&= ~(PAGE_READ
| PAGE_WRITE
);
957 } else if (pkru_wd
&& (is_user
|| env
->cr
[0] & CR0_WP_MASK
)) {
958 pkru_prot
&= ~PAGE_WRITE
;
962 if ((pkru_prot
& (1 << is_write1
)) == 0) {
963 assert(is_write1
!= 2);
964 error_code
|= PG_ERROR_PK_MASK
;
965 goto do_fault_protect
;
969 if ((prot
& (1 << is_write1
)) == 0) {
970 goto do_fault_protect
;
974 is_dirty
= is_write
&& !(pte
& PG_DIRTY_MASK
);
975 if (!(pte
& PG_ACCESSED_MASK
) || is_dirty
) {
976 pte
|= PG_ACCESSED_MASK
;
978 pte
|= PG_DIRTY_MASK
;
980 x86_stl_phys_notdirty(cs
, pte_addr
, pte
);
983 if (!(pte
& PG_DIRTY_MASK
)) {
984 /* only set write access if already dirty... otherwise wait
991 pte
= pte
& env
->a20_mask
;
993 /* align to page_size */
994 pte
&= PG_ADDRESS_MASK
& ~(page_size
- 1);
996 /* Even if 4MB pages, we map only one 4KB page in the cache to
997 avoid filling it too fast */
998 vaddr
= addr
& TARGET_PAGE_MASK
;
999 page_offset
= vaddr
& (page_size
- 1);
1000 paddr
= pte
+ page_offset
;
1002 assert(prot
& (1 << is_write1
));
1003 tlb_set_page_with_attrs(cs
, vaddr
, paddr
, cpu_get_mem_attrs(env
),
1004 prot
, mmu_idx
, page_size
);
1007 error_code
|= PG_ERROR_RSVD_MASK
;
1009 error_code
|= PG_ERROR_P_MASK
;
1011 error_code
|= (is_write
<< PG_ERROR_W_BIT
);
1013 error_code
|= PG_ERROR_U_MASK
;
1014 if (is_write1
== 2 &&
1015 (((env
->efer
& MSR_EFER_NXE
) &&
1016 (env
->cr
[4] & CR4_PAE_MASK
)) ||
1017 (env
->cr
[4] & CR4_SMEP_MASK
)))
1018 error_code
|= PG_ERROR_I_D_MASK
;
1019 if (env
->intercept_exceptions
& (1 << EXCP0E_PAGE
)) {
1020 /* cr2 is not modified in case of exceptions */
1022 env
->vm_vmcb
+ offsetof(struct vmcb
, control
.exit_info_2
),
1027 env
->error_code
= error_code
;
1028 cs
->exception_index
= EXCP0E_PAGE
;
1032 hwaddr
x86_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
1034 X86CPU
*cpu
= X86_CPU(cs
);
1035 CPUX86State
*env
= &cpu
->env
;
1036 target_ulong pde_addr
, pte_addr
;
1038 uint32_t page_offset
;
1041 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
1042 pte
= addr
& env
->a20_mask
;
1044 } else if (env
->cr
[4] & CR4_PAE_MASK
) {
1045 target_ulong pdpe_addr
;
1048 #ifdef TARGET_X86_64
1049 if (env
->hflags
& HF_LMA_MASK
) {
1050 bool la57
= env
->cr
[4] & CR4_LA57_MASK
;
1051 uint64_t pml5e_addr
, pml5e
;
1052 uint64_t pml4e_addr
, pml4e
;
1055 /* test virtual address sign extension */
1056 sext
= la57
? (int64_t)addr
>> 56 : (int64_t)addr
>> 47;
1057 if (sext
!= 0 && sext
!= -1) {
1062 pml5e_addr
= ((env
->cr
[3] & ~0xfff) +
1063 (((addr
>> 48) & 0x1ff) << 3)) & env
->a20_mask
;
1064 pml5e
= x86_ldq_phys(cs
, pml5e_addr
);
1065 if (!(pml5e
& PG_PRESENT_MASK
)) {
1072 pml4e_addr
= ((pml5e
& PG_ADDRESS_MASK
) +
1073 (((addr
>> 39) & 0x1ff) << 3)) & env
->a20_mask
;
1074 pml4e
= x86_ldq_phys(cs
, pml4e_addr
);
1075 if (!(pml4e
& PG_PRESENT_MASK
)) {
1078 pdpe_addr
= ((pml4e
& PG_ADDRESS_MASK
) +
1079 (((addr
>> 30) & 0x1ff) << 3)) & env
->a20_mask
;
1080 pdpe
= x86_ldq_phys(cs
, pdpe_addr
);
1081 if (!(pdpe
& PG_PRESENT_MASK
)) {
1084 if (pdpe
& PG_PSE_MASK
) {
1085 page_size
= 1024 * 1024 * 1024;
1093 pdpe_addr
= ((env
->cr
[3] & ~0x1f) + ((addr
>> 27) & 0x18)) &
1095 pdpe
= x86_ldq_phys(cs
, pdpe_addr
);
1096 if (!(pdpe
& PG_PRESENT_MASK
))
1100 pde_addr
= ((pdpe
& PG_ADDRESS_MASK
) +
1101 (((addr
>> 21) & 0x1ff) << 3)) & env
->a20_mask
;
1102 pde
= x86_ldq_phys(cs
, pde_addr
);
1103 if (!(pde
& PG_PRESENT_MASK
)) {
1106 if (pde
& PG_PSE_MASK
) {
1108 page_size
= 2048 * 1024;
1112 pte_addr
= ((pde
& PG_ADDRESS_MASK
) +
1113 (((addr
>> 12) & 0x1ff) << 3)) & env
->a20_mask
;
1115 pte
= x86_ldq_phys(cs
, pte_addr
);
1117 if (!(pte
& PG_PRESENT_MASK
)) {
1123 /* page directory entry */
1124 pde_addr
= ((env
->cr
[3] & ~0xfff) + ((addr
>> 20) & 0xffc)) & env
->a20_mask
;
1125 pde
= x86_ldl_phys(cs
, pde_addr
);
1126 if (!(pde
& PG_PRESENT_MASK
))
1128 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
1129 pte
= pde
| ((pde
& 0x1fe000LL
) << (32 - 13));
1130 page_size
= 4096 * 1024;
1132 /* page directory entry */
1133 pte_addr
= ((pde
& ~0xfff) + ((addr
>> 10) & 0xffc)) & env
->a20_mask
;
1134 pte
= x86_ldl_phys(cs
, pte_addr
);
1135 if (!(pte
& PG_PRESENT_MASK
)) {
1140 pte
= pte
& env
->a20_mask
;
1143 #ifdef TARGET_X86_64
1146 pte
&= PG_ADDRESS_MASK
& ~(page_size
- 1);
1147 page_offset
= (addr
& TARGET_PAGE_MASK
) & (page_size
- 1);
1148 return pte
| page_offset
;
1151 typedef struct MCEInjectionParams
{
1155 uint64_t mcg_status
;
1159 } MCEInjectionParams
;
1161 static void do_inject_x86_mce(CPUState
*cs
, run_on_cpu_data data
)
1163 MCEInjectionParams
*params
= data
.host_ptr
;
1164 X86CPU
*cpu
= X86_CPU(cs
);
1165 CPUX86State
*cenv
= &cpu
->env
;
1166 uint64_t *banks
= cenv
->mce_banks
+ 4 * params
->bank
;
1168 cpu_synchronize_state(cs
);
1171 * If there is an MCE exception being processed, ignore this SRAO MCE
1172 * unless unconditional injection was requested.
1174 if (!(params
->flags
& MCE_INJECT_UNCOND_AO
)
1175 && !(params
->status
& MCI_STATUS_AR
)
1176 && (cenv
->mcg_status
& MCG_STATUS_MCIP
)) {
1180 if (params
->status
& MCI_STATUS_UC
) {
1182 * if MSR_MCG_CTL is not all 1s, the uncorrected error
1183 * reporting is disabled
1185 if ((cenv
->mcg_cap
& MCG_CTL_P
) && cenv
->mcg_ctl
!= ~(uint64_t)0) {
1186 monitor_printf(params
->mon
,
1187 "CPU %d: Uncorrected error reporting disabled\n",
1193 * if MSR_MCi_CTL is not all 1s, the uncorrected error
1194 * reporting is disabled for the bank
1196 if (banks
[0] != ~(uint64_t)0) {
1197 monitor_printf(params
->mon
,
1198 "CPU %d: Uncorrected error reporting disabled for"
1200 cs
->cpu_index
, params
->bank
);
1204 if ((cenv
->mcg_status
& MCG_STATUS_MCIP
) ||
1205 !(cenv
->cr
[4] & CR4_MCE_MASK
)) {
1206 monitor_printf(params
->mon
,
1207 "CPU %d: Previous MCE still in progress, raising"
1210 qemu_log_mask(CPU_LOG_RESET
, "Triple fault\n");
1211 qemu_system_reset_request();
1214 if (banks
[1] & MCI_STATUS_VAL
) {
1215 params
->status
|= MCI_STATUS_OVER
;
1217 banks
[2] = params
->addr
;
1218 banks
[3] = params
->misc
;
1219 cenv
->mcg_status
= params
->mcg_status
;
1220 banks
[1] = params
->status
;
1221 cpu_interrupt(cs
, CPU_INTERRUPT_MCE
);
1222 } else if (!(banks
[1] & MCI_STATUS_VAL
)
1223 || !(banks
[1] & MCI_STATUS_UC
)) {
1224 if (banks
[1] & MCI_STATUS_VAL
) {
1225 params
->status
|= MCI_STATUS_OVER
;
1227 banks
[2] = params
->addr
;
1228 banks
[3] = params
->misc
;
1229 banks
[1] = params
->status
;
1231 banks
[1] |= MCI_STATUS_OVER
;
1235 void cpu_x86_inject_mce(Monitor
*mon
, X86CPU
*cpu
, int bank
,
1236 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
1237 uint64_t misc
, int flags
)
1239 CPUState
*cs
= CPU(cpu
);
1240 CPUX86State
*cenv
= &cpu
->env
;
1241 MCEInjectionParams params
= {
1245 .mcg_status
= mcg_status
,
1250 unsigned bank_num
= cenv
->mcg_cap
& 0xff;
1252 if (!cenv
->mcg_cap
) {
1253 monitor_printf(mon
, "MCE injection not supported\n");
1256 if (bank
>= bank_num
) {
1257 monitor_printf(mon
, "Invalid MCE bank number\n");
1260 if (!(status
& MCI_STATUS_VAL
)) {
1261 monitor_printf(mon
, "Invalid MCE status code\n");
1264 if ((flags
& MCE_INJECT_BROADCAST
)
1265 && !cpu_x86_support_mca_broadcast(cenv
)) {
1266 monitor_printf(mon
, "Guest CPU does not support MCA broadcast\n");
1270 run_on_cpu(cs
, do_inject_x86_mce
, RUN_ON_CPU_HOST_PTR(¶ms
));
1271 if (flags
& MCE_INJECT_BROADCAST
) {
1275 params
.status
= MCI_STATUS_VAL
| MCI_STATUS_UC
;
1276 params
.mcg_status
= MCG_STATUS_MCIP
| MCG_STATUS_RIPV
;
1279 CPU_FOREACH(other_cs
) {
1280 if (other_cs
== cs
) {
1283 run_on_cpu(other_cs
, do_inject_x86_mce
, RUN_ON_CPU_HOST_PTR(¶ms
));
1288 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
)
1290 X86CPU
*cpu
= x86_env_get_cpu(env
);
1291 CPUState
*cs
= CPU(cpu
);
1293 if (kvm_enabled()) {
1294 env
->tpr_access_type
= access
;
1296 cpu_interrupt(cs
, CPU_INTERRUPT_TPR
);
1298 cpu_restore_state(cs
, cs
->mem_io_pc
);
1300 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
, access
);
1303 #endif /* !CONFIG_USER_ONLY */
1305 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
1306 target_ulong
*base
, unsigned int *limit
,
1307 unsigned int *flags
)
1309 X86CPU
*cpu
= x86_env_get_cpu(env
);
1310 CPUState
*cs
= CPU(cpu
);
1320 index
= selector
& ~7;
1321 ptr
= dt
->base
+ index
;
1322 if ((index
+ 7) > dt
->limit
1323 || cpu_memory_rw_debug(cs
, ptr
, (uint8_t *)&e1
, sizeof(e1
), 0) != 0
1324 || cpu_memory_rw_debug(cs
, ptr
+4, (uint8_t *)&e2
, sizeof(e2
), 0) != 0)
1327 *base
= ((e1
>> 16) | ((e2
& 0xff) << 16) | (e2
& 0xff000000));
1328 *limit
= (e1
& 0xffff) | (e2
& 0x000f0000);
1329 if (e2
& DESC_G_MASK
)
1330 *limit
= (*limit
<< 12) | 0xfff;
1336 #if !defined(CONFIG_USER_ONLY)
1337 void do_cpu_init(X86CPU
*cpu
)
1339 CPUState
*cs
= CPU(cpu
);
1340 CPUX86State
*env
= &cpu
->env
;
1341 CPUX86State
*save
= g_new(CPUX86State
, 1);
1342 int sipi
= cs
->interrupt_request
& CPU_INTERRUPT_SIPI
;
1347 cs
->interrupt_request
= sipi
;
1348 memcpy(&env
->start_init_save
, &save
->start_init_save
,
1349 offsetof(CPUX86State
, end_init_save
) -
1350 offsetof(CPUX86State
, start_init_save
));
1353 if (kvm_enabled()) {
1354 kvm_arch_do_init_vcpu(cpu
);
1356 apic_init_reset(cpu
->apic_state
);
1359 void do_cpu_sipi(X86CPU
*cpu
)
1361 apic_sipi(cpu
->apic_state
);
1364 void do_cpu_init(X86CPU
*cpu
)
1367 void do_cpu_sipi(X86CPU
*cpu
)
1372 /* Frob eflags into and out of the CPU temporary format. */
1374 void x86_cpu_exec_enter(CPUState
*cs
)
1376 X86CPU
*cpu
= X86_CPU(cs
);
1377 CPUX86State
*env
= &cpu
->env
;
1379 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
1380 env
->df
= 1 - (2 * ((env
->eflags
>> 10) & 1));
1381 CC_OP
= CC_OP_EFLAGS
;
1382 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
1385 void x86_cpu_exec_exit(CPUState
*cs
)
1387 X86CPU
*cpu
= X86_CPU(cs
);
1388 CPUX86State
*env
= &cpu
->env
;
1390 env
->eflags
= cpu_compute_eflags(env
);
1393 #ifndef CONFIG_USER_ONLY
1394 uint8_t x86_ldub_phys(CPUState
*cs
, hwaddr addr
)
1396 X86CPU
*cpu
= X86_CPU(cs
);
1397 CPUX86State
*env
= &cpu
->env
;
1399 return address_space_ldub(cs
->as
, addr
,
1400 cpu_get_mem_attrs(env
),
1404 uint32_t x86_lduw_phys(CPUState
*cs
, hwaddr addr
)
1406 X86CPU
*cpu
= X86_CPU(cs
);
1407 CPUX86State
*env
= &cpu
->env
;
1409 return address_space_lduw(cs
->as
, addr
,
1410 cpu_get_mem_attrs(env
),
1414 uint32_t x86_ldl_phys(CPUState
*cs
, hwaddr addr
)
1416 X86CPU
*cpu
= X86_CPU(cs
);
1417 CPUX86State
*env
= &cpu
->env
;
1419 return address_space_ldl(cs
->as
, addr
,
1420 cpu_get_mem_attrs(env
),
1424 uint64_t x86_ldq_phys(CPUState
*cs
, hwaddr addr
)
1426 X86CPU
*cpu
= X86_CPU(cs
);
1427 CPUX86State
*env
= &cpu
->env
;
1429 return address_space_ldq(cs
->as
, addr
,
1430 cpu_get_mem_attrs(env
),
1434 void x86_stb_phys(CPUState
*cs
, hwaddr addr
, uint8_t val
)
1436 X86CPU
*cpu
= X86_CPU(cs
);
1437 CPUX86State
*env
= &cpu
->env
;
1439 address_space_stb(cs
->as
, addr
, val
,
1440 cpu_get_mem_attrs(env
),
1444 void x86_stl_phys_notdirty(CPUState
*cs
, hwaddr addr
, uint32_t val
)
1446 X86CPU
*cpu
= X86_CPU(cs
);
1447 CPUX86State
*env
= &cpu
->env
;
1449 address_space_stl_notdirty(cs
->as
, addr
, val
,
1450 cpu_get_mem_attrs(env
),
1454 void x86_stw_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
)
1456 X86CPU
*cpu
= X86_CPU(cs
);
1457 CPUX86State
*env
= &cpu
->env
;
1459 address_space_stw(cs
->as
, addr
, val
,
1460 cpu_get_mem_attrs(env
),
1464 void x86_stl_phys(CPUState
*cs
, hwaddr addr
, uint32_t val
)
1466 X86CPU
*cpu
= X86_CPU(cs
);
1467 CPUX86State
*env
= &cpu
->env
;
1469 address_space_stl(cs
->as
, addr
, val
,
1470 cpu_get_mem_attrs(env
),
1474 void x86_stq_phys(CPUState
*cs
, hwaddr addr
, uint64_t val
)
1476 X86CPU
*cpu
= X86_CPU(cs
);
1477 CPUX86State
*env
= &cpu
->env
;
1479 address_space_stq(cs
->as
, addr
, val
,
1480 cpu_get_mem_attrs(env
),