hw/usb/xlnx-versal-usb2-ctrl-regs.c

   1 /*
   2  * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
   3  * USB2.0 controller
   4  *
   5  * This module should control phy_reset, permanent device plugs, frame length
   6  * time adjust & setting of coherency paths. None of which are emulated in
   7  * present model.
   8  *
   9  * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a copy
  12  * of this software and associated documentation files (the "Software"), to deal
  13  * in the Software without restriction, including without limitation the rights
  14  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  15  * copies of the Software, and to permit persons to whom the Software is
  16  * furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice shall be included in
  19  * all copies or substantial portions of the Software.
  20  *
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  24  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  26  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  27  * THE SOFTWARE.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "hw/sysbus.h"
  32 #include "hw/irq.h"
  33 #include "hw/register.h"
  34 #include "qemu/bitops.h"
  35 #include "qemu/log.h"
  36 #include "qom/object.h"
  37 #include "migration/vmstate.h"
  38 #include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"
  39
  40 #ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG
  41 #define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0
  42 #endif
  43
  44 REG32(BUS_FILTER, 0x30)
  45     FIELD(BUS_FILTER, BYPASS, 0, 4)
  46 REG32(PORT, 0x34)
  47     FIELD(PORT, HOST_SMI_BAR_WR, 4, 1)
  48     FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1)
  49     FIELD(PORT, HOST_MSI_ENABLE, 2, 1)
  50     FIELD(PORT, PWR_CTRL_PRSNT, 1, 1)
  51     FIELD(PORT, HUB_PERM_ATTACH, 0, 1)
  52 REG32(JITTER_ADJUST, 0x38)
  53     FIELD(JITTER_ADJUST, FLADJ, 0, 6)
  54 REG32(BIGENDIAN, 0x40)
  55     FIELD(BIGENDIAN, ENDIAN_GS, 0, 1)
  56 REG32(COHERENCY, 0x44)
  57     FIELD(COHERENCY, USB_COHERENCY, 0, 1)
  58 REG32(XHC_BME, 0x48)
  59     FIELD(XHC_BME, XHC_BME, 0, 1)
  60 REG32(REG_CTRL, 0x60)
  61     FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
  62 REG32(IR_STATUS, 0x64)
  63     FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1)
  64     FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1)
  65 REG32(IR_MASK, 0x68)
  66     FIELD(IR_MASK, HOST_SYS_ERR, 1, 1)
  67     FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1)
  68 REG32(IR_ENABLE, 0x6c)
  69     FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1)
  70     FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1)
  71 REG32(IR_DISABLE, 0x70)
  72     FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1)
  73     FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1)
  74 REG32(USB3, 0x78)
  75
  76 static void ir_update_irq(VersalUsb2CtrlRegs *s)
  77 {
  78     bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
  79     qemu_set_irq(s->irq_ir, pending);
  80 }
  81
  82 static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
  83 {
  84     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
  85     /*
  86      * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
  87      * May be combine both the modules.
  88      */
  89     ir_update_irq(s);
  90 }
  91
  92 static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
  93 {
  94     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
  95     uint32_t val = val64;
  96
  97     s->regs[R_IR_MASK] &= ~val;
  98     ir_update_irq(s);
  99     return 0;
 100 }
 101
 102 static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
 103 {
 104     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
 105     uint32_t val = val64;
 106
 107     s->regs[R_IR_MASK] |= val;
 108     ir_update_irq(s);
 109     return 0;
 110 }
 111
 112 static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] = {
 113     {   .name = "BUS_FILTER",  .addr = A_BUS_FILTER,
 114         .rsvd = 0xfffffff0,
 115     },{ .name = "PORT",  .addr = A_PORT,
 116         .rsvd = 0xffffffe0,
 117     },{ .name = "JITTER_ADJUST",  .addr = A_JITTER_ADJUST,
 118         .reset = 0x20,
 119         .rsvd = 0xffffffc0,
 120     },{ .name = "BIGENDIAN",  .addr = A_BIGENDIAN,
 121         .rsvd = 0xfffffffe,
 122     },{ .name = "COHERENCY",  .addr = A_COHERENCY,
 123         .rsvd = 0xfffffffe,
 124     },{ .name = "XHC_BME",  .addr = A_XHC_BME,
 125         .reset = 0x1,
 126         .rsvd = 0xfffffffe,
 127     },{ .name = "REG_CTRL",  .addr = A_REG_CTRL,
 128         .rsvd = 0xfffffffe,
 129     },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
 130         .rsvd = 0xfffffffc,
 131         .w1c = 0x3,
 132         .post_write = ir_status_postw,
 133     },{ .name = "IR_MASK",  .addr = A_IR_MASK,
 134         .reset = 0x3,
 135         .rsvd = 0xfffffffc,
 136         .ro = 0x3,
 137     },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
 138         .rsvd = 0xfffffffc,
 139         .pre_write = ir_enable_prew,
 140     },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
 141         .rsvd = 0xfffffffc,
 142         .pre_write = ir_disable_prew,
 143     },{ .name = "USB3",  .addr = A_USB3,
 144     }
 145 };
 146
 147 static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
 148 {
 149     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
 150     unsigned int i;
 151
 152     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 153         register_reset(&s->regs_info[i]);
 154     }
 155 }
 156
 157 static void usb2_ctrl_regs_reset_hold(Object *obj)
 158 {
 159     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
 160
 161     ir_update_irq(s);
 162 }
 163
 164 static const MemoryRegionOps usb2_ctrl_regs_ops = {
 165     .read = register_read_memory,
 166     .write = register_write_memory,
 167     .endianness = DEVICE_LITTLE_ENDIAN,
 168     .valid = {
 169         .min_access_size = 4,
 170         .max_access_size = 4,
 171     },
 172 };
 173
 174 static void usb2_ctrl_regs_init(Object *obj)
 175 {
 176     VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
 177     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 178     RegisterInfoArray *reg_array;
 179
 180     memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
 181                        USB2_REGS_R_MAX * 4);
 182     reg_array =
 183         register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info,
 184                               ARRAY_SIZE(usb2_ctrl_regs_regs_info),
 185                               s->regs_info, s->regs,
 186                               &usb2_ctrl_regs_ops,
 187                               XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG,
 188                               USB2_REGS_R_MAX * 4);
 189     memory_region_add_subregion(&s->iomem,
 190                                 0x0,
 191                                 &reg_array->mem);
 192     sysbus_init_mmio(sbd, &s->iomem);
 193     sysbus_init_irq(sbd, &s->irq_ir);
 194 }
 195
 196 static const VMStateDescription vmstate_usb2_ctrl_regs = {
 197     .name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
 198     .version_id = 1,
 199     .minimum_version_id = 1,
 200     .fields = (VMStateField[]) {
 201         VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX),
 202         VMSTATE_END_OF_LIST(),
 203     }
 204 };
 205
 206 static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(klass);
 209     ResettableClass *rc = RESETTABLE_CLASS(klass);
 210
 211     rc->phases.enter = usb2_ctrl_regs_reset_init;
 212     rc->phases.hold  = usb2_ctrl_regs_reset_hold;
 213     dc->vmsd = &vmstate_usb2_ctrl_regs;
 214 }
 215
 216 static const TypeInfo usb2_ctrl_regs_info = {
 217     .name          = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
 218     .parent        = TYPE_SYS_BUS_DEVICE,
 219     .instance_size = sizeof(VersalUsb2CtrlRegs),
 220     .class_init    = usb2_ctrl_regs_class_init,
 221     .instance_init = usb2_ctrl_regs_init,
 222 };
 223
 224 static void usb2_ctrl_regs_register_types(void)
 225 {
 226     type_register_static(&usb2_ctrl_regs_info);
 227 }
 228
 229 type_init(usb2_ctrl_regs_register_types)