2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
27 #include "sysemu/block-backend.h"
28 #include "sysemu/blockdev.h"
29 #include "sysemu/dma.h"
30 #include "qemu/timer.h"
31 #include "qemu/bitops.h"
32 #include "sdhci-internal.h"
34 /* host controller debug messages */
39 #define DPRINT_L1(fmt, args...) \
42 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
45 #define DPRINT_L2(fmt, args...) \
47 if (SDHC_DEBUG > 1) { \
48 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
51 #define ERRPRINT(fmt, args...) \
54 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
58 #define TYPE_SDHCI_BUS "sdhci-bus"
59 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
61 /* Default SD/MMC host controller features information, which will be
62 * presented in CAPABILITIES register of generic SD host controller at reset.
63 * If not stated otherwise:
64 * 0 - not supported, 1 - supported, other - prohibited.
66 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
67 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
68 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
69 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
70 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
71 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */
72 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
73 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
74 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
75 /* Maximum host controller R/W buffers size
76 * Possible values: 512, 1024, 2048 bytes */
77 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
78 /* Maximum clock frequency for SDclock in MHz
79 * value in range 10-63 MHz, 0 - not defined */
80 #define SDHC_CAPAB_BASECLKFREQ 52ul
81 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
82 /* Timeout clock frequency 1-63, 0 - not defined */
83 #define SDHC_CAPAB_TOCLKFREQ 52ul
85 /* Now check all parameters and calculate CAPABILITIES REGISTER value */
86 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
87 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
88 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
90 #error Capabilities features can have value 0 or 1 only!
93 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512
94 #define MAX_BLOCK_LENGTH 0ul
95 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
96 #define MAX_BLOCK_LENGTH 1ul
97 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
98 #define MAX_BLOCK_LENGTH 2ul
100 #error Max host controller block size can have value 512, 1024 or 2048 only!
103 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
104 SDHC_CAPAB_BASECLKFREQ > 63
105 #error SDclock frequency can have value in range 0, 10-63 only!
108 #if SDHC_CAPAB_TOCLKFREQ > 63
109 #error Timeout clock frequency can have value in range 0-63 only!
112 #define SDHC_CAPAB_REG_DEFAULT \
113 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
114 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
115 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
116 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
117 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
118 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
119 (SDHC_CAPAB_TOCLKFREQ))
121 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
123 static uint8_t sdhci_slotint(SDHCIState
*s
)
125 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
126 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
127 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
130 static inline void sdhci_update_irq(SDHCIState
*s
)
132 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
135 static void sdhci_raise_insertion_irq(void *opaque
)
137 SDHCIState
*s
= (SDHCIState
*)opaque
;
139 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
140 timer_mod(s
->insert_timer
,
141 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
143 s
->prnsts
= 0x1ff0000;
144 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
145 s
->norintsts
|= SDHC_NIS_INSERT
;
151 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
153 SDHCIState
*s
= (SDHCIState
*)dev
;
154 DPRINT_L1("Card state changed: %s!\n", level
? "insert" : "eject");
156 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
157 /* Give target some time to notice card ejection */
158 timer_mod(s
->insert_timer
,
159 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
162 s
->prnsts
= 0x1ff0000;
163 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
164 s
->norintsts
|= SDHC_NIS_INSERT
;
167 s
->prnsts
= 0x1fa0000;
168 s
->pwrcon
&= ~SDHC_POWER_ON
;
169 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
170 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
171 s
->norintsts
|= SDHC_NIS_REMOVE
;
178 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
180 SDHCIState
*s
= (SDHCIState
*)dev
;
183 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
186 s
->prnsts
|= SDHC_WRITE_PROTECT
;
190 static void sdhci_reset(SDHCIState
*s
)
192 DeviceState
*dev
= DEVICE(s
);
194 timer_del(s
->insert_timer
);
195 timer_del(s
->transfer_timer
);
196 /* Set all registers to 0. Capabilities registers are not cleared
197 * and assumed to always preserve their value, given to them during
199 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
201 /* Reset other state based on current card insertion/readonly status */
202 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
203 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
206 s
->stopped_state
= sdhc_not_stopped
;
207 s
->pending_insert
= false;
210 static void sdhci_data_transfer(void *opaque
);
212 static void sdhci_send_command(SDHCIState
*s
)
215 uint8_t response
[16];
220 request
.cmd
= s
->cmdreg
>> 8;
221 request
.arg
= s
->argument
;
222 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request
.cmd
, request
.arg
);
223 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
225 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
227 s
->rspreg
[0] = (response
[0] << 24) | (response
[1] << 16) |
228 (response
[2] << 8) | response
[3];
229 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
230 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s
->rspreg
[0]);
231 } else if (rlen
== 16) {
232 s
->rspreg
[0] = (response
[11] << 24) | (response
[12] << 16) |
233 (response
[13] << 8) | response
[14];
234 s
->rspreg
[1] = (response
[7] << 24) | (response
[8] << 16) |
235 (response
[9] << 8) | response
[10];
236 s
->rspreg
[2] = (response
[3] << 24) | (response
[4] << 16) |
237 (response
[5] << 8) | response
[6];
238 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
240 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
241 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
242 s
->rspreg
[3], s
->rspreg
[2], s
->rspreg
[1], s
->rspreg
[0]);
244 ERRPRINT("Timeout waiting for command response\n");
245 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
246 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
247 s
->norintsts
|= SDHC_NIS_ERR
;
251 if ((s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
252 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
253 s
->norintsts
|= SDHC_NIS_TRSCMP
;
257 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
258 s
->norintsts
|= SDHC_NIS_CMDCMP
;
263 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
265 sdhci_data_transfer(s
);
269 static void sdhci_end_transfer(SDHCIState
*s
)
271 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
272 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
274 uint8_t response
[16];
278 DPRINT_L1("Automatically issue CMD%d %08x\n", request
.cmd
, request
.arg
);
279 sdbus_do_command(&s
->sdbus
, &request
, response
);
280 /* Auto CMD12 response goes to the upper Response register */
281 s
->rspreg
[3] = (response
[0] << 24) | (response
[1] << 16) |
282 (response
[2] << 8) | response
[3];
285 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
286 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
287 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
289 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
290 s
->norintsts
|= SDHC_NIS_TRSCMP
;
297 * Programmed i/o data transfer
300 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
301 static void sdhci_read_block_from_card(SDHCIState
*s
)
305 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
306 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
310 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
311 s
->fifo_buffer
[index
] = sdbus_read_data(&s
->sdbus
);
314 /* New data now available for READ through Buffer Port Register */
315 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
316 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
317 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
320 /* Clear DAT line active status if that was the last block */
321 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
322 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
323 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
326 /* If stop at block gap request was set and it's not the last block of
327 * data - generate Block Event interrupt */
328 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
330 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
331 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
332 s
->norintsts
|= SDHC_EIS_BLKGAP
;
339 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
340 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
345 /* first check that a valid data exists in host controller input buffer */
346 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
347 ERRPRINT("Trying to read from empty buffer\n");
351 for (i
= 0; i
< size
; i
++) {
352 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
354 /* check if we've read all valid data (blksize bytes) from buffer */
355 if ((s
->data_count
) >= (s
->blksize
& 0x0fff)) {
356 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
358 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
359 s
->data_count
= 0; /* next buff read must start at position [0] */
361 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
365 /* if that was the last block of data */
366 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
367 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
368 /* stop at gap request */
369 (s
->stopped_state
== sdhc_gap_read
&&
370 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
371 sdhci_end_transfer(s
);
372 } else { /* if there are more data, read next block from card */
373 sdhci_read_block_from_card(s
);
382 /* Write data from host controller FIFO to card */
383 static void sdhci_write_block_to_card(SDHCIState
*s
)
387 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
388 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
389 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
395 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
396 if (s
->blkcnt
== 0) {
403 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
404 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[index
]);
407 /* Next data can be written through BUFFER DATORT register */
408 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
410 /* Finish transfer if that was the last block of data */
411 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
412 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
413 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
414 sdhci_end_transfer(s
);
415 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
416 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
419 /* Generate Block Gap Event if requested and if not the last block */
420 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
422 s
->prnsts
&= ~SDHC_DOING_WRITE
;
423 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
424 s
->norintsts
|= SDHC_EIS_BLKGAP
;
426 sdhci_end_transfer(s
);
432 /* Write @size bytes of @value data to host controller @s Buffer Data Port
434 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
438 /* Check that there is free space left in a buffer */
439 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
440 ERRPRINT("Can't write to data buffer: buffer full\n");
444 for (i
= 0; i
< size
; i
++) {
445 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
448 if (s
->data_count
>= (s
->blksize
& 0x0fff)) {
449 DPRINT_L2("write buffer filled with %u bytes of data\n",
452 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
453 if (s
->prnsts
& SDHC_DOING_WRITE
) {
454 sdhci_write_block_to_card(s
);
461 * Single DMA data transfer
464 /* Multi block SDMA transfer */
465 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
467 bool page_aligned
= false;
468 unsigned int n
, begin
;
469 const uint16_t block_size
= s
->blksize
& 0x0fff;
470 uint32_t boundary_chk
= 1 << (((s
->blksize
& 0xf000) >> 12) + 12);
471 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
473 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
474 * possible stop at page boundary if initial address is not page aligned,
475 * allow them to work properly */
476 if ((s
->sdmasysad
% boundary_chk
) == 0) {
480 if (s
->trnmod
& SDHC_TRNS_READ
) {
481 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
482 SDHC_DAT_LINE_ACTIVE
;
484 if (s
->data_count
== 0) {
485 for (n
= 0; n
< block_size
; n
++) {
486 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
489 begin
= s
->data_count
;
490 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
491 s
->data_count
= boundary_count
+ begin
;
494 s
->data_count
= block_size
;
495 boundary_count
-= block_size
- begin
;
496 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
500 dma_memory_write(&address_space_memory
, s
->sdmasysad
,
501 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
502 s
->sdmasysad
+= s
->data_count
- begin
;
503 if (s
->data_count
== block_size
) {
506 if (page_aligned
&& boundary_count
== 0) {
511 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
512 SDHC_DAT_LINE_ACTIVE
;
514 begin
= s
->data_count
;
515 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
516 s
->data_count
= boundary_count
+ begin
;
519 s
->data_count
= block_size
;
520 boundary_count
-= block_size
- begin
;
522 dma_memory_read(&address_space_memory
, s
->sdmasysad
,
523 &s
->fifo_buffer
[begin
], s
->data_count
);
524 s
->sdmasysad
+= s
->data_count
- begin
;
525 if (s
->data_count
== block_size
) {
526 for (n
= 0; n
< block_size
; n
++) {
527 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
530 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
534 if (page_aligned
&& boundary_count
== 0) {
540 if (s
->blkcnt
== 0) {
541 sdhci_end_transfer(s
);
543 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
544 s
->norintsts
|= SDHC_NIS_DMA
;
550 /* single block SDMA transfer */
552 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
555 uint32_t datacnt
= s
->blksize
& 0x0fff;
557 if (s
->trnmod
& SDHC_TRNS_READ
) {
558 for (n
= 0; n
< datacnt
; n
++) {
559 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
561 dma_memory_write(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
564 dma_memory_read(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
566 for (n
= 0; n
< datacnt
; n
++) {
567 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
571 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
575 sdhci_end_transfer(s
);
578 typedef struct ADMADescr
{
585 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
589 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
590 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
591 case SDHC_CTRL_ADMA2_32
:
592 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma2
,
594 adma2
= le64_to_cpu(adma2
);
595 /* The spec does not specify endianness of descriptor table.
596 * We currently assume that it is LE.
598 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
599 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
600 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
603 case SDHC_CTRL_ADMA1_32
:
604 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma1
,
606 adma1
= le32_to_cpu(adma1
);
607 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
608 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
610 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
611 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
616 case SDHC_CTRL_ADMA2_64
:
617 dma_memory_read(&address_space_memory
, entry_addr
,
618 (uint8_t *)(&dscr
->attr
), 1);
619 dma_memory_read(&address_space_memory
, entry_addr
+ 2,
620 (uint8_t *)(&dscr
->length
), 2);
621 dscr
->length
= le16_to_cpu(dscr
->length
);
622 dma_memory_read(&address_space_memory
, entry_addr
+ 4,
623 (uint8_t *)(&dscr
->addr
), 8);
624 dscr
->attr
= le64_to_cpu(dscr
->attr
);
625 dscr
->attr
&= 0xfffffff8;
631 /* Advanced DMA data transfer */
633 static void sdhci_do_adma(SDHCIState
*s
)
635 unsigned int n
, begin
, length
;
636 const uint16_t block_size
= s
->blksize
& 0x0fff;
640 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
641 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
643 get_adma_description(s
, &dscr
);
644 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx
", len=%d, attr=%x\n",
645 dscr
.addr
, dscr
.length
, dscr
.attr
);
647 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
648 /* Indicate that error occurred in ST_FDS state */
649 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
650 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
652 /* Generate ADMA error interrupt */
653 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
654 s
->errintsts
|= SDHC_EIS_ADMAERR
;
655 s
->norintsts
|= SDHC_NIS_ERR
;
662 length
= dscr
.length
? dscr
.length
: 65536;
664 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
665 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
667 if (s
->trnmod
& SDHC_TRNS_READ
) {
669 if (s
->data_count
== 0) {
670 for (n
= 0; n
< block_size
; n
++) {
671 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
674 begin
= s
->data_count
;
675 if ((length
+ begin
) < block_size
) {
676 s
->data_count
= length
+ begin
;
679 s
->data_count
= block_size
;
680 length
-= block_size
- begin
;
682 dma_memory_write(&address_space_memory
, dscr
.addr
,
683 &s
->fifo_buffer
[begin
],
684 s
->data_count
- begin
);
685 dscr
.addr
+= s
->data_count
- begin
;
686 if (s
->data_count
== block_size
) {
688 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
690 if (s
->blkcnt
== 0) {
698 begin
= s
->data_count
;
699 if ((length
+ begin
) < block_size
) {
700 s
->data_count
= length
+ begin
;
703 s
->data_count
= block_size
;
704 length
-= block_size
- begin
;
706 dma_memory_read(&address_space_memory
, dscr
.addr
,
707 &s
->fifo_buffer
[begin
],
708 s
->data_count
- begin
);
709 dscr
.addr
+= s
->data_count
- begin
;
710 if (s
->data_count
== block_size
) {
711 for (n
= 0; n
< block_size
; n
++) {
712 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
715 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
717 if (s
->blkcnt
== 0) {
724 s
->admasysaddr
+= dscr
.incr
;
726 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
727 s
->admasysaddr
= dscr
.addr
;
728 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64
"\n",
732 s
->admasysaddr
+= dscr
.incr
;
736 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
737 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64
"\n",
739 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
740 s
->norintsts
|= SDHC_NIS_DMA
;
746 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
747 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
748 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
749 DPRINT_L2("ADMA transfer completed\n");
750 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
751 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
753 ERRPRINT("SD/MMC host ADMA length mismatch\n");
754 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
755 SDHC_ADMAERR_STATE_ST_TFR
;
756 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
757 ERRPRINT("Set ADMA error flag\n");
758 s
->errintsts
|= SDHC_EIS_ADMAERR
;
759 s
->norintsts
|= SDHC_NIS_ERR
;
764 sdhci_end_transfer(s
);
770 /* we have unfinished business - reschedule to continue ADMA */
771 timer_mod(s
->transfer_timer
,
772 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
775 /* Perform data transfer according to controller configuration */
777 static void sdhci_data_transfer(void *opaque
)
779 SDHCIState
*s
= (SDHCIState
*)opaque
;
781 if (s
->trnmod
& SDHC_TRNS_DMA
) {
782 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
784 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
785 (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || s
->blkcnt
== 0)) {
789 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
790 sdhci_sdma_transfer_single_block(s
);
792 sdhci_sdma_transfer_multi_blocks(s
);
796 case SDHC_CTRL_ADMA1_32
:
797 if (!(s
->capareg
& SDHC_CAN_DO_ADMA1
)) {
798 ERRPRINT("ADMA1 not supported\n");
804 case SDHC_CTRL_ADMA2_32
:
805 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
)) {
806 ERRPRINT("ADMA2 not supported\n");
812 case SDHC_CTRL_ADMA2_64
:
813 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
) ||
814 !(s
->capareg
& SDHC_64_BIT_BUS_SUPPORT
)) {
815 ERRPRINT("64 bit ADMA not supported\n");
822 ERRPRINT("Unsupported DMA type\n");
826 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
827 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
828 SDHC_DAT_LINE_ACTIVE
;
829 sdhci_read_block_from_card(s
);
831 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
832 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
833 sdhci_write_block_to_card(s
);
838 static bool sdhci_can_issue_command(SDHCIState
*s
)
840 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
841 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
842 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
843 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
844 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
851 /* The Buffer Data Port register must be accessed in sequential and
852 * continuous manner */
854 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
856 if ((s
->data_count
& 0x3) != byte_num
) {
857 ERRPRINT("Non-sequential access to Buffer Data Port register"
864 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
866 SDHCIState
*s
= (SDHCIState
*)opaque
;
869 switch (offset
& ~0x3) {
874 ret
= s
->blksize
| (s
->blkcnt
<< 16);
880 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
882 case SDHC_RSPREG0
... SDHC_RSPREG3
:
883 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
886 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
887 ret
= sdhci_read_dataport(s
, size
);
888 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
,
897 ret
= s
->hostctl
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
901 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
904 ret
= s
->norintsts
| (s
->errintsts
<< 16);
906 case SDHC_NORINTSTSEN
:
907 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
909 case SDHC_NORINTSIGEN
:
910 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
912 case SDHC_ACMD12ERRSTS
:
913 ret
= s
->acmd12errsts
;
924 case SDHC_ADMASYSADDR
:
925 ret
= (uint32_t)s
->admasysaddr
;
927 case SDHC_ADMASYSADDR
+ 4:
928 ret
= (uint32_t)(s
->admasysaddr
>> 32);
930 case SDHC_SLOT_INT_STATUS
:
931 ret
= (SD_HOST_SPECv2_VERS
<< 16) | sdhci_slotint(s
);
934 ERRPRINT("bad %ub read: addr[0x%04x]\n", size
, (int)offset
);
938 ret
>>= (offset
& 0x3) * 8;
939 ret
&= (1ULL << (size
* 8)) - 1;
940 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
, ret
, ret
);
944 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
946 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
949 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
951 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
952 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
953 if (s
->stopped_state
== sdhc_gap_read
) {
954 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
955 sdhci_read_block_from_card(s
);
957 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
958 sdhci_write_block_to_card(s
);
960 s
->stopped_state
= sdhc_not_stopped
;
961 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
962 if (s
->prnsts
& SDHC_DOING_READ
) {
963 s
->stopped_state
= sdhc_gap_read
;
964 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
965 s
->stopped_state
= sdhc_gap_write
;
970 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
977 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
978 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
980 case SDHC_RESET_DATA
:
982 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
983 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
984 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
985 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
986 s
->stopped_state
= sdhc_not_stopped
;
987 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
988 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
994 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
996 SDHCIState
*s
= (SDHCIState
*)opaque
;
997 unsigned shift
= 8 * (offset
& 0x3);
998 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
999 uint32_t value
= val
;
1002 switch (offset
& ~0x3) {
1004 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1005 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1006 /* Writing to last byte of sdmasysad might trigger transfer */
1007 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1008 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl
) == SDHC_CTRL_SDMA
) {
1009 sdhci_sdma_transfer_multi_blocks(s
);
1013 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1014 MASKED_WRITE(s
->blksize
, mask
, value
);
1015 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1018 /* Limit block size to the maximum buffer size */
1019 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1020 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1021 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1024 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1029 MASKED_WRITE(s
->argument
, mask
, value
);
1032 /* DMA can be enabled only if it is supported as indicated by
1033 * capabilities register */
1034 if (!(s
->capareg
& SDHC_CAN_DO_DMA
)) {
1035 value
&= ~SDHC_TRNS_DMA
;
1037 MASKED_WRITE(s
->trnmod
, mask
, value
);
1038 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1040 /* Writing to the upper byte of CMDREG triggers SD command generation */
1041 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1045 sdhci_send_command(s
);
1048 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1049 sdhci_write_dataport(s
, value
>> shift
, size
);
1053 if (!(mask
& 0xFF0000)) {
1054 sdhci_blkgap_write(s
, value
>> 16);
1056 MASKED_WRITE(s
->hostctl
, mask
, value
);
1057 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1058 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1059 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1060 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1061 s
->pwrcon
&= ~SDHC_POWER_ON
;
1065 if (!(mask
& 0xFF000000)) {
1066 sdhci_reset_write(s
, value
>> 24);
1068 MASKED_WRITE(s
->clkcon
, mask
, value
);
1069 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1070 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1071 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1073 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1076 case SDHC_NORINTSTS
:
1077 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1078 value
&= ~SDHC_NIS_CARDINT
;
1080 s
->norintsts
&= mask
| ~value
;
1081 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1083 s
->norintsts
|= SDHC_NIS_ERR
;
1085 s
->norintsts
&= ~SDHC_NIS_ERR
;
1087 sdhci_update_irq(s
);
1089 case SDHC_NORINTSTSEN
:
1090 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1091 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1092 s
->norintsts
&= s
->norintstsen
;
1093 s
->errintsts
&= s
->errintstsen
;
1095 s
->norintsts
|= SDHC_NIS_ERR
;
1097 s
->norintsts
&= ~SDHC_NIS_ERR
;
1099 /* Quirk for Raspberry Pi: pending card insert interrupt
1100 * appears when first enabled after power on */
1101 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert
) {
1102 s
->norintsts
|= SDHC_NIS_INSERT
;
1103 s
->pending_insert
= false;
1105 sdhci_update_irq(s
);
1107 case SDHC_NORINTSIGEN
:
1108 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1109 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1110 sdhci_update_irq(s
);
1113 MASKED_WRITE(s
->admaerr
, mask
, value
);
1115 case SDHC_ADMASYSADDR
:
1116 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1117 (uint64_t)mask
)) | (uint64_t)value
;
1119 case SDHC_ADMASYSADDR
+ 4:
1120 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1121 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1124 s
->acmd12errsts
|= value
;
1125 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1126 if (s
->acmd12errsts
) {
1127 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1130 s
->norintsts
|= SDHC_NIS_ERR
;
1132 sdhci_update_irq(s
);
1135 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
1136 size
, (int)offset
, value
>> shift
, value
>> shift
);
1139 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
1140 size
, (int)offset
, value
>> shift
, value
>> shift
);
1143 static const MemoryRegionOps sdhci_mmio_ops
= {
1145 .write
= sdhci_write
,
1147 .min_access_size
= 1,
1148 .max_access_size
= 4,
1151 .endianness
= DEVICE_LITTLE_ENDIAN
,
1154 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
1156 switch (SDHC_CAPAB_BLOCKSIZE(s
->capareg
)) {
1164 hw_error("SDHC: unsupported value for maximum block size\n");
1169 static void sdhci_initfn(SDHCIState
*s
)
1171 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1172 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1174 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1175 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1178 static void sdhci_uninitfn(SDHCIState
*s
)
1180 timer_del(s
->insert_timer
);
1181 timer_free(s
->insert_timer
);
1182 timer_del(s
->transfer_timer
);
1183 timer_free(s
->transfer_timer
);
1184 qemu_free_irq(s
->eject_cb
);
1185 qemu_free_irq(s
->ro_cb
);
1187 g_free(s
->fifo_buffer
);
1188 s
->fifo_buffer
= NULL
;
1191 const VMStateDescription sdhci_vmstate
= {
1194 .minimum_version_id
= 1,
1195 .fields
= (VMStateField
[]) {
1196 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1197 VMSTATE_UINT16(blksize
, SDHCIState
),
1198 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1199 VMSTATE_UINT32(argument
, SDHCIState
),
1200 VMSTATE_UINT16(trnmod
, SDHCIState
),
1201 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1202 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1203 VMSTATE_UINT32(prnsts
, SDHCIState
),
1204 VMSTATE_UINT8(hostctl
, SDHCIState
),
1205 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1206 VMSTATE_UINT8(blkgap
, SDHCIState
),
1207 VMSTATE_UINT8(wakcon
, SDHCIState
),
1208 VMSTATE_UINT16(clkcon
, SDHCIState
),
1209 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1210 VMSTATE_UINT8(admaerr
, SDHCIState
),
1211 VMSTATE_UINT16(norintsts
, SDHCIState
),
1212 VMSTATE_UINT16(errintsts
, SDHCIState
),
1213 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1214 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1215 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1216 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1217 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1218 VMSTATE_UINT16(data_count
, SDHCIState
),
1219 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1220 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1221 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, 0, buf_maxsz
),
1222 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1223 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1224 VMSTATE_BOOL(pending_insert
, SDHCIState
),
1225 VMSTATE_END_OF_LIST()
1229 /* Capabilities registers provide information on supported features of this
1230 * specific host controller implementation */
1231 static Property sdhci_pci_properties
[] = {
1232 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1233 SDHC_CAPAB_REG_DEFAULT
),
1234 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1235 DEFINE_PROP_END_OF_LIST(),
1238 static void sdhci_pci_realize(PCIDevice
*dev
, Error
**errp
)
1240 SDHCIState
*s
= PCI_SDHCI(dev
);
1241 dev
->config
[PCI_CLASS_PROG
] = 0x01; /* Standard Host supported DMA */
1242 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1244 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1245 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1246 s
->irq
= pci_allocate_irq(dev
);
1247 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1248 SDHC_REGISTERS_MAP_SIZE
);
1249 pci_register_bar(dev
, 0, 0, &s
->iomem
);
1252 static void sdhci_pci_exit(PCIDevice
*dev
)
1254 SDHCIState
*s
= PCI_SDHCI(dev
);
1258 static void sdhci_pci_class_init(ObjectClass
*klass
, void *data
)
1260 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1261 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1263 k
->realize
= sdhci_pci_realize
;
1264 k
->exit
= sdhci_pci_exit
;
1265 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
1266 k
->device_id
= PCI_DEVICE_ID_REDHAT_SDHCI
;
1267 k
->class_id
= PCI_CLASS_SYSTEM_SDHCI
;
1268 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1269 dc
->vmsd
= &sdhci_vmstate
;
1270 dc
->props
= sdhci_pci_properties
;
1273 static const TypeInfo sdhci_pci_info
= {
1274 .name
= TYPE_PCI_SDHCI
,
1275 .parent
= TYPE_PCI_DEVICE
,
1276 .instance_size
= sizeof(SDHCIState
),
1277 .class_init
= sdhci_pci_class_init
,
1280 static Property sdhci_sysbus_properties
[] = {
1281 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1282 SDHC_CAPAB_REG_DEFAULT
),
1283 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1284 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert
,
1286 DEFINE_PROP_END_OF_LIST(),
1289 static void sdhci_sysbus_init(Object
*obj
)
1291 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1296 static void sdhci_sysbus_finalize(Object
*obj
)
1298 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1302 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1304 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1305 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1307 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1308 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1309 sysbus_init_irq(sbd
, &s
->irq
);
1310 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1311 SDHC_REGISTERS_MAP_SIZE
);
1312 sysbus_init_mmio(sbd
, &s
->iomem
);
1315 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1317 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1319 dc
->vmsd
= &sdhci_vmstate
;
1320 dc
->props
= sdhci_sysbus_properties
;
1321 dc
->realize
= sdhci_sysbus_realize
;
1324 static const TypeInfo sdhci_sysbus_info
= {
1325 .name
= TYPE_SYSBUS_SDHCI
,
1326 .parent
= TYPE_SYS_BUS_DEVICE
,
1327 .instance_size
= sizeof(SDHCIState
),
1328 .instance_init
= sdhci_sysbus_init
,
1329 .instance_finalize
= sdhci_sysbus_finalize
,
1330 .class_init
= sdhci_sysbus_class_init
,
1333 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1335 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1337 sbc
->set_inserted
= sdhci_set_inserted
;
1338 sbc
->set_readonly
= sdhci_set_readonly
;
1341 static const TypeInfo sdhci_bus_info
= {
1342 .name
= TYPE_SDHCI_BUS
,
1343 .parent
= TYPE_SD_BUS
,
1344 .instance_size
= sizeof(SDBus
),
1345 .class_init
= sdhci_bus_class_init
,
1348 static void sdhci_register_types(void)
1350 type_register_static(&sdhci_pci_info
);
1351 type_register_static(&sdhci_sysbus_info
);
1352 type_register_static(&sdhci_bus_info
);
1355 type_init(sdhci_register_types
)