2 * QEMU sPAPR PCI host originated from Uninorth PCI host
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
30 #include "hw/sysbus.h"
31 #include "migration/vmstate.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/msi.h"
34 #include "hw/pci/msix.h"
35 #include "hw/pci/pci_host.h"
36 #include "hw/ppc/spapr.h"
37 #include "hw/pci-host/spapr.h"
38 #include "exec/address-spaces.h"
39 #include "exec/ram_addr.h"
42 #include "qemu/error-report.h"
43 #include "qemu/module.h"
44 #include "qapi/qmp/qerror.h"
45 #include "hw/ppc/fdt.h"
46 #include "hw/pci/pci_bridge.h"
47 #include "hw/pci/pci_bus.h"
48 #include "hw/pci/pci_ids.h"
49 #include "hw/ppc/spapr_drc.h"
50 #include "hw/qdev-properties.h"
51 #include "sysemu/device_tree.h"
52 #include "sysemu/kvm.h"
53 #include "sysemu/hostmem.h"
54 #include "sysemu/numa.h"
56 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
57 #define RTAS_QUERY_FN 0
58 #define RTAS_CHANGE_FN 1
59 #define RTAS_RESET_FN 2
60 #define RTAS_CHANGE_MSI_FN 3
61 #define RTAS_CHANGE_MSIX_FN 4
63 /* Interrupt types to return on RTAS_CHANGE_* */
64 #define RTAS_TYPE_MSI 1
65 #define RTAS_TYPE_MSIX 2
67 SpaprPhbState
*spapr_pci_find_phb(SpaprMachineState
*spapr
, uint64_t buid
)
71 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
72 if (sphb
->buid
!= buid
) {
81 PCIDevice
*spapr_pci_find_dev(SpaprMachineState
*spapr
, uint64_t buid
,
84 SpaprPhbState
*sphb
= spapr_pci_find_phb(spapr
, buid
);
85 PCIHostState
*phb
= PCI_HOST_BRIDGE(sphb
);
86 int bus_num
= (config_addr
>> 16) & 0xFF;
87 int devfn
= (config_addr
>> 8) & 0xFF;
93 return pci_find_device(phb
->bus
, bus_num
, devfn
);
96 static uint32_t rtas_pci_cfgaddr(uint32_t arg
)
98 /* This handles the encoding of extended config space addresses */
99 return ((arg
>> 20) & 0xf00) | (arg
& 0xff);
102 static void finish_read_pci_config(SpaprMachineState
*spapr
, uint64_t buid
,
103 uint32_t addr
, uint32_t size
,
109 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
110 /* access must be 1, 2 or 4 bytes */
111 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
115 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
116 addr
= rtas_pci_cfgaddr(addr
);
118 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
119 /* Access must be to a valid device, within bounds and
120 * naturally aligned */
121 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
125 val
= pci_host_config_read_common(pci_dev
, addr
,
126 pci_config_size(pci_dev
), size
);
128 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
129 rtas_st(rets
, 1, val
);
132 static void rtas_ibm_read_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
133 uint32_t token
, uint32_t nargs
,
135 uint32_t nret
, target_ulong rets
)
140 if ((nargs
!= 4) || (nret
!= 2)) {
141 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
145 buid
= rtas_ldq(args
, 1);
146 size
= rtas_ld(args
, 3);
147 addr
= rtas_ld(args
, 0);
149 finish_read_pci_config(spapr
, buid
, addr
, size
, rets
);
152 static void rtas_read_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
153 uint32_t token
, uint32_t nargs
,
155 uint32_t nret
, target_ulong rets
)
159 if ((nargs
!= 2) || (nret
!= 2)) {
160 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
164 size
= rtas_ld(args
, 1);
165 addr
= rtas_ld(args
, 0);
167 finish_read_pci_config(spapr
, 0, addr
, size
, rets
);
170 static void finish_write_pci_config(SpaprMachineState
*spapr
, uint64_t buid
,
171 uint32_t addr
, uint32_t size
,
172 uint32_t val
, target_ulong rets
)
176 if ((size
!= 1) && (size
!= 2) && (size
!= 4)) {
177 /* access must be 1, 2 or 4 bytes */
178 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
182 pci_dev
= spapr_pci_find_dev(spapr
, buid
, addr
);
183 addr
= rtas_pci_cfgaddr(addr
);
185 if (!pci_dev
|| (addr
% size
) || (addr
>= pci_config_size(pci_dev
))) {
186 /* Access must be to a valid device, within bounds and
187 * naturally aligned */
188 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
192 pci_host_config_write_common(pci_dev
, addr
, pci_config_size(pci_dev
),
195 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
198 static void rtas_ibm_write_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
199 uint32_t token
, uint32_t nargs
,
201 uint32_t nret
, target_ulong rets
)
204 uint32_t val
, size
, addr
;
206 if ((nargs
!= 5) || (nret
!= 1)) {
207 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
211 buid
= rtas_ldq(args
, 1);
212 val
= rtas_ld(args
, 4);
213 size
= rtas_ld(args
, 3);
214 addr
= rtas_ld(args
, 0);
216 finish_write_pci_config(spapr
, buid
, addr
, size
, val
, rets
);
219 static void rtas_write_pci_config(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
220 uint32_t token
, uint32_t nargs
,
222 uint32_t nret
, target_ulong rets
)
224 uint32_t val
, size
, addr
;
226 if ((nargs
!= 3) || (nret
!= 1)) {
227 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
232 val
= rtas_ld(args
, 2);
233 size
= rtas_ld(args
, 1);
234 addr
= rtas_ld(args
, 0);
236 finish_write_pci_config(spapr
, 0, addr
, size
, val
, rets
);
240 * Set MSI/MSIX message data.
241 * This is required for msi_notify()/msix_notify() which
242 * will write at the addresses via spapr_msi_write().
244 * If hwaddr == 0, all entries will have .data == first_irq i.e.
245 * table will be reset.
247 static void spapr_msi_setmsg(PCIDevice
*pdev
, hwaddr addr
, bool msix
,
248 unsigned first_irq
, unsigned req_num
)
251 MSIMessage msg
= { .address
= addr
, .data
= first_irq
};
254 msi_set_message(pdev
, msg
);
255 trace_spapr_pci_msi_setup(pdev
->name
, 0, msg
.address
);
259 for (i
= 0; i
< req_num
; ++i
) {
260 msix_set_message(pdev
, i
, msg
);
261 trace_spapr_pci_msi_setup(pdev
->name
, i
, msg
.address
);
268 static void rtas_ibm_change_msi(PowerPCCPU
*cpu
, SpaprMachineState
*spapr
,
269 uint32_t token
, uint32_t nargs
,
270 target_ulong args
, uint32_t nret
,
273 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
274 uint32_t config_addr
= rtas_ld(args
, 0);
275 uint64_t buid
= rtas_ldq(args
, 1);
276 unsigned int func
= rtas_ld(args
, 3);
277 unsigned int req_num
= rtas_ld(args
, 4); /* 0 == remove all */
278 unsigned int seq_num
= rtas_ld(args
, 5);
279 unsigned int ret_intr_type
;
280 unsigned int irq
, max_irqs
= 0;
281 SpaprPhbState
*phb
= NULL
;
282 PCIDevice
*pdev
= NULL
;
284 int *config_addr_key
;
288 /* Fins SpaprPhbState */
289 phb
= spapr_pci_find_phb(spapr
, buid
);
291 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
294 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
300 if (msi_present(pdev
)) {
301 ret_intr_type
= RTAS_TYPE_MSI
;
302 } else if (msix_present(pdev
)) {
303 ret_intr_type
= RTAS_TYPE_MSIX
;
305 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
309 case RTAS_CHANGE_MSI_FN
:
310 if (msi_present(pdev
)) {
311 ret_intr_type
= RTAS_TYPE_MSI
;
313 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
317 case RTAS_CHANGE_MSIX_FN
:
318 if (msix_present(pdev
)) {
319 ret_intr_type
= RTAS_TYPE_MSIX
;
321 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
326 error_report("rtas_ibm_change_msi(%u) is not implemented", func
);
327 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
331 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
336 trace_spapr_pci_msi("Releasing wrong config", config_addr
);
337 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
341 if (!smc
->legacy_irq_allocation
) {
342 spapr_irq_msi_free(spapr
, msi
->first_irq
, msi
->num
);
344 spapr_irq_free(spapr
, msi
->first_irq
, msi
->num
);
345 if (msi_present(pdev
)) {
346 spapr_msi_setmsg(pdev
, 0, false, 0, 0);
348 if (msix_present(pdev
)) {
349 spapr_msi_setmsg(pdev
, 0, true, 0, 0);
351 g_hash_table_remove(phb
->msi
, &config_addr
);
353 trace_spapr_pci_msi("Released MSIs", config_addr
);
354 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
361 /* Check if the device supports as many IRQs as requested */
362 if (ret_intr_type
== RTAS_TYPE_MSI
) {
363 max_irqs
= msi_nr_vectors_allocated(pdev
);
364 } else if (ret_intr_type
== RTAS_TYPE_MSIX
) {
365 max_irqs
= pdev
->msix_entries_nr
;
368 error_report("Requested interrupt type %d is not enabled for device %x",
369 ret_intr_type
, config_addr
);
370 rtas_st(rets
, 0, -1); /* Hardware error */
373 /* Correct the number if the guest asked for too many */
374 if (req_num
> max_irqs
) {
375 trace_spapr_pci_msi_retry(config_addr
, req_num
, max_irqs
);
377 irq
= 0; /* to avoid misleading trace */
382 if (smc
->legacy_irq_allocation
) {
383 irq
= spapr_irq_find(spapr
, req_num
, ret_intr_type
== RTAS_TYPE_MSI
,
386 irq
= spapr_irq_msi_alloc(spapr
, req_num
,
387 ret_intr_type
== RTAS_TYPE_MSI
, &err
);
390 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
392 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
396 for (i
= 0; i
< req_num
; i
++) {
397 spapr_irq_claim(spapr
, irq
+ i
, false, &err
);
400 spapr_irq_free(spapr
, irq
, i
);
402 if (!smc
->legacy_irq_allocation
) {
403 spapr_irq_msi_free(spapr
, irq
, req_num
);
405 error_reportf_err(err
, "Can't allocate MSIs for device %x: ",
407 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
412 /* Release previous MSIs */
414 if (!smc
->legacy_irq_allocation
) {
415 spapr_irq_msi_free(spapr
, msi
->first_irq
, msi
->num
);
417 spapr_irq_free(spapr
, msi
->first_irq
, msi
->num
);
418 g_hash_table_remove(phb
->msi
, &config_addr
);
421 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
422 spapr_msi_setmsg(pdev
, SPAPR_PCI_MSI_WINDOW
, ret_intr_type
== RTAS_TYPE_MSIX
,
425 /* Add MSI device to cache */
426 msi
= g_new(spapr_pci_msi
, 1);
427 msi
->first_irq
= irq
;
429 config_addr_key
= g_new(int, 1);
430 *config_addr_key
= config_addr
;
431 g_hash_table_insert(phb
->msi
, config_addr_key
, msi
);
434 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
435 rtas_st(rets
, 1, req_num
);
436 rtas_st(rets
, 2, ++seq_num
);
438 rtas_st(rets
, 3, ret_intr_type
);
441 trace_spapr_pci_rtas_ibm_change_msi(config_addr
, func
, req_num
, irq
);
444 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU
*cpu
,
445 SpaprMachineState
*spapr
,
452 uint32_t config_addr
= rtas_ld(args
, 0);
453 uint64_t buid
= rtas_ldq(args
, 1);
454 unsigned int intr_src_num
= -1, ioa_intr_num
= rtas_ld(args
, 3);
455 SpaprPhbState
*phb
= NULL
;
456 PCIDevice
*pdev
= NULL
;
459 /* Find SpaprPhbState */
460 phb
= spapr_pci_find_phb(spapr
, buid
);
462 pdev
= spapr_pci_find_dev(spapr
, buid
, config_addr
);
465 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
469 /* Find device descriptor and start IRQ */
470 msi
= (spapr_pci_msi
*) g_hash_table_lookup(phb
->msi
, &config_addr
);
471 if (!msi
|| !msi
->first_irq
|| !msi
->num
|| (ioa_intr_num
>= msi
->num
)) {
472 trace_spapr_pci_msi("Failed to return vector", config_addr
);
473 rtas_st(rets
, 0, RTAS_OUT_HW_ERROR
);
476 intr_src_num
= msi
->first_irq
+ ioa_intr_num
;
477 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num
,
480 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
481 rtas_st(rets
, 1, intr_src_num
);
482 rtas_st(rets
, 2, 1);/* 0 == level; 1 == edge */
485 static void rtas_ibm_set_eeh_option(PowerPCCPU
*cpu
,
486 SpaprMachineState
*spapr
,
487 uint32_t token
, uint32_t nargs
,
488 target_ulong args
, uint32_t nret
,
492 uint32_t addr
, option
;
496 if ((nargs
!= 4) || (nret
!= 1)) {
497 goto param_error_exit
;
500 buid
= rtas_ldq(args
, 1);
501 addr
= rtas_ld(args
, 0);
502 option
= rtas_ld(args
, 3);
504 sphb
= spapr_pci_find_phb(spapr
, buid
);
506 goto param_error_exit
;
509 if (!spapr_phb_eeh_available(sphb
)) {
510 goto param_error_exit
;
513 ret
= spapr_phb_vfio_eeh_set_option(sphb
, addr
, option
);
514 rtas_st(rets
, 0, ret
);
518 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
521 static void rtas_ibm_get_config_addr_info2(PowerPCCPU
*cpu
,
522 SpaprMachineState
*spapr
,
523 uint32_t token
, uint32_t nargs
,
524 target_ulong args
, uint32_t nret
,
529 uint32_t addr
, option
;
532 if ((nargs
!= 4) || (nret
!= 2)) {
533 goto param_error_exit
;
536 buid
= rtas_ldq(args
, 1);
537 sphb
= spapr_pci_find_phb(spapr
, buid
);
539 goto param_error_exit
;
542 if (!spapr_phb_eeh_available(sphb
)) {
543 goto param_error_exit
;
547 * We always have PE address of form "00BB0001". "BB"
548 * represents the bus number of PE's primary bus.
550 option
= rtas_ld(args
, 3);
552 case RTAS_GET_PE_ADDR
:
553 addr
= rtas_ld(args
, 0);
554 pdev
= spapr_pci_find_dev(spapr
, buid
, addr
);
556 goto param_error_exit
;
559 rtas_st(rets
, 1, (pci_bus_num(pci_get_bus(pdev
)) << 16) + 1);
561 case RTAS_GET_PE_MODE
:
562 rtas_st(rets
, 1, RTAS_PE_MODE_SHARED
);
565 goto param_error_exit
;
568 rtas_st(rets
, 0, RTAS_OUT_SUCCESS
);
572 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
575 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU
*cpu
,
576 SpaprMachineState
*spapr
,
577 uint32_t token
, uint32_t nargs
,
578 target_ulong args
, uint32_t nret
,
585 if ((nargs
!= 3) || (nret
!= 4 && nret
!= 5)) {
586 goto param_error_exit
;
589 buid
= rtas_ldq(args
, 1);
590 sphb
= spapr_pci_find_phb(spapr
, buid
);
592 goto param_error_exit
;
595 if (!spapr_phb_eeh_available(sphb
)) {
596 goto param_error_exit
;
599 ret
= spapr_phb_vfio_eeh_get_state(sphb
, &state
);
600 rtas_st(rets
, 0, ret
);
601 if (ret
!= RTAS_OUT_SUCCESS
) {
605 rtas_st(rets
, 1, state
);
606 rtas_st(rets
, 2, RTAS_EEH_SUPPORT
);
607 rtas_st(rets
, 3, RTAS_EEH_PE_UNAVAIL_INFO
);
609 rtas_st(rets
, 4, RTAS_EEH_PE_RECOVER_INFO
);
614 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
617 static void rtas_ibm_set_slot_reset(PowerPCCPU
*cpu
,
618 SpaprMachineState
*spapr
,
619 uint32_t token
, uint32_t nargs
,
620 target_ulong args
, uint32_t nret
,
628 if ((nargs
!= 4) || (nret
!= 1)) {
629 goto param_error_exit
;
632 buid
= rtas_ldq(args
, 1);
633 option
= rtas_ld(args
, 3);
634 sphb
= spapr_pci_find_phb(spapr
, buid
);
636 goto param_error_exit
;
639 if (!spapr_phb_eeh_available(sphb
)) {
640 goto param_error_exit
;
643 ret
= spapr_phb_vfio_eeh_reset(sphb
, option
);
644 rtas_st(rets
, 0, ret
);
648 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
651 static void rtas_ibm_configure_pe(PowerPCCPU
*cpu
,
652 SpaprMachineState
*spapr
,
653 uint32_t token
, uint32_t nargs
,
654 target_ulong args
, uint32_t nret
,
661 if ((nargs
!= 3) || (nret
!= 1)) {
662 goto param_error_exit
;
665 buid
= rtas_ldq(args
, 1);
666 sphb
= spapr_pci_find_phb(spapr
, buid
);
668 goto param_error_exit
;
671 if (!spapr_phb_eeh_available(sphb
)) {
672 goto param_error_exit
;
675 ret
= spapr_phb_vfio_eeh_configure(sphb
);
676 rtas_st(rets
, 0, ret
);
680 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
683 /* To support it later */
684 static void rtas_ibm_slot_error_detail(PowerPCCPU
*cpu
,
685 SpaprMachineState
*spapr
,
686 uint32_t token
, uint32_t nargs
,
687 target_ulong args
, uint32_t nret
,
694 if ((nargs
!= 8) || (nret
!= 1)) {
695 goto param_error_exit
;
698 buid
= rtas_ldq(args
, 1);
699 sphb
= spapr_pci_find_phb(spapr
, buid
);
701 goto param_error_exit
;
704 if (!spapr_phb_eeh_available(sphb
)) {
705 goto param_error_exit
;
708 option
= rtas_ld(args
, 7);
710 case RTAS_SLOT_TEMP_ERR_LOG
:
711 case RTAS_SLOT_PERM_ERR_LOG
:
714 goto param_error_exit
;
717 /* We don't have error log yet */
718 rtas_st(rets
, 0, RTAS_OUT_NO_ERRORS_FOUND
);
722 rtas_st(rets
, 0, RTAS_OUT_PARAM_ERROR
);
725 static void pci_spapr_set_irq(void *opaque
, int irq_num
, int level
)
728 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
729 * corresponding qemu_irq.
731 SpaprPhbState
*phb
= opaque
;
733 trace_spapr_pci_lsi_set(phb
->dtbusname
, irq_num
, phb
->lsi_table
[irq_num
].irq
);
734 qemu_set_irq(spapr_phb_lsi_qirq(phb
, irq_num
), level
);
737 static PCIINTxRoute
spapr_route_intx_pin_to_irq(void *opaque
, int pin
)
739 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(opaque
);
742 route
.mode
= PCI_INTX_ENABLED
;
743 route
.irq
= sphb
->lsi_table
[pin
].irq
;
749 * MSI/MSIX memory region implementation.
750 * The handler handles both MSI and MSIX.
751 * The vector number is encoded in least bits in data.
753 static void spapr_msi_write(void *opaque
, hwaddr addr
,
754 uint64_t data
, unsigned size
)
756 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
759 trace_spapr_pci_msi_write(addr
, data
, irq
);
761 qemu_irq_pulse(spapr_qirq(spapr
, irq
));
764 static const MemoryRegionOps spapr_msi_ops
= {
765 /* There is no .read as the read result is undefined by PCI spec */
767 .write
= spapr_msi_write
,
768 .endianness
= DEVICE_LITTLE_ENDIAN
774 static AddressSpace
*spapr_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
776 SpaprPhbState
*phb
= opaque
;
778 return &phb
->iommu_as
;
781 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState
*sphb
, PCIDevice
*pdev
)
783 char *path
= NULL
, *buf
= NULL
, *host
= NULL
;
785 /* Get the PCI VFIO host id */
786 host
= object_property_get_str(OBJECT(pdev
), "host", NULL
);
791 /* Construct the path of the file that will give us the DT location */
792 path
= g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host
);
794 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
799 /* Construct and read from host device tree the loc-code */
800 path
= g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf
);
802 if (!g_file_get_contents(path
, &buf
, NULL
, NULL
)) {
812 static char *spapr_phb_get_loc_code(SpaprPhbState
*sphb
, PCIDevice
*pdev
)
815 const char *devtype
= "qemu";
816 uint32_t busnr
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
))));
818 if (object_dynamic_cast(OBJECT(pdev
), "vfio-pci")) {
819 buf
= spapr_phb_vfio_get_loc_code(sphb
, pdev
);
826 * For emulated devices and VFIO-failure case, make up
829 buf
= g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
830 devtype
, pdev
->name
, sphb
->index
, busnr
,
831 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
));
835 /* Macros to operate with address in OF binding to PCI */
836 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
837 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
838 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
839 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
840 #define b_ss(x) b_x((x), 24, 2) /* the space code */
841 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
842 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
843 #define b_fff(x) b_x((x), 8, 3) /* function number */
844 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
846 /* for 'reg'/'assigned-addresses' OF properties */
847 #define RESOURCE_CELLS_SIZE 2
848 #define RESOURCE_CELLS_ADDRESS 3
850 typedef struct ResourceFields
{
856 } QEMU_PACKED ResourceFields
;
858 typedef struct ResourceProps
{
859 ResourceFields reg
[8];
860 ResourceFields assigned
[7];
862 uint32_t assigned_len
;
865 /* fill in the 'reg'/'assigned-resources' OF properties for
866 * a PCI device. 'reg' describes resource requirements for a
867 * device's IO/MEM regions, 'assigned-addresses' describes the
868 * actual resource assignments.
870 * the properties are arrays of ('phys-addr', 'size') pairs describing
871 * the addressable regions of the PCI device, where 'phys-addr' is a
872 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
873 * (phys.hi, phys.mid, phys.lo), and 'size' is a
874 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
876 * phys.hi = 0xYYXXXXZZ, where:
881 * ||| + 00 if configuration space
882 * ||| + 01 if IO region,
883 * ||| + 10 if 32-bit MEM region
884 * ||| + 11 if 64-bit MEM region
886 * ||+------ for non-relocatable IO: 1 if aliased
887 * || for relocatable IO: 1 if below 64KB
888 * || for MEM: 1 if below 1MB
889 * |+------- 1 if region is prefetchable
890 * +-------- 1 if region is non-relocatable
891 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
893 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
896 * phys.mid and phys.lo correspond respectively to the hi/lo portions
897 * of the actual address of the region.
899 * how the phys-addr/size values are used differ slightly between
900 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has
901 * an additional description for the config space region of the
902 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0
903 * to describe the region as relocatable, with an address-mapping
904 * that corresponds directly to the PHB's address space for the
905 * resource. 'assigned-addresses' always has n=1 set with an absolute
906 * address assigned for the resource. in general, 'assigned-addresses'
907 * won't be populated, since addresses for PCI devices are generally
908 * unmapped initially and left to the guest to assign.
910 * note also that addresses defined in these properties are, at least
911 * for PAPR guests, relative to the PHBs IO/MEM windows, and
912 * correspond directly to the addresses in the BARs.
914 * in accordance with PCI Bus Binding to Open Firmware,
915 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
918 static void populate_resource_props(PCIDevice
*d
, ResourceProps
*rp
)
920 int bus_num
= pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d
))));
921 uint32_t dev_id
= (b_bbbbbbbb(bus_num
) |
922 b_ddddd(PCI_SLOT(d
->devfn
)) |
923 b_fff(PCI_FUNC(d
->devfn
)));
924 ResourceFields
*reg
, *assigned
;
925 int i
, reg_idx
= 0, assigned_idx
= 0;
927 /* config space region */
928 reg
= &rp
->reg
[reg_idx
++];
929 reg
->phys_hi
= cpu_to_be32(dev_id
);
935 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
936 if (!d
->io_regions
[i
].size
) {
940 reg
= &rp
->reg
[reg_idx
++];
942 reg
->phys_hi
= cpu_to_be32(dev_id
| b_rrrrrrrr(pci_bar(d
, i
)));
943 if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_SPACE_IO
) {
944 reg
->phys_hi
|= cpu_to_be32(b_ss(1));
945 } else if (d
->io_regions
[i
].type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
946 reg
->phys_hi
|= cpu_to_be32(b_ss(3));
948 reg
->phys_hi
|= cpu_to_be32(b_ss(2));
952 reg
->size_hi
= cpu_to_be32(d
->io_regions
[i
].size
>> 32);
953 reg
->size_lo
= cpu_to_be32(d
->io_regions
[i
].size
);
955 if (d
->io_regions
[i
].addr
== PCI_BAR_UNMAPPED
) {
959 assigned
= &rp
->assigned
[assigned_idx
++];
960 assigned
->phys_hi
= cpu_to_be32(be32_to_cpu(reg
->phys_hi
) | b_n(1));
961 assigned
->phys_mid
= cpu_to_be32(d
->io_regions
[i
].addr
>> 32);
962 assigned
->phys_lo
= cpu_to_be32(d
->io_regions
[i
].addr
);
963 assigned
->size_hi
= reg
->size_hi
;
964 assigned
->size_lo
= reg
->size_lo
;
967 rp
->reg_len
= reg_idx
* sizeof(ResourceFields
);
968 rp
->assigned_len
= assigned_idx
* sizeof(ResourceFields
);
971 typedef struct PCIClass PCIClass
;
972 typedef struct PCISubClass PCISubClass
;
973 typedef struct PCIIFace PCIIFace
;
983 const PCIIFace
*iface
;
988 const PCISubClass
*subc
;
991 static const PCISubClass undef_subclass
[] = {
992 { PCI_CLASS_NOT_DEFINED_VGA
, "display", NULL
},
993 { 0xFF, NULL
, NULL
},
996 static const PCISubClass mass_subclass
[] = {
997 { PCI_CLASS_STORAGE_SCSI
, "scsi", NULL
},
998 { PCI_CLASS_STORAGE_IDE
, "ide", NULL
},
999 { PCI_CLASS_STORAGE_FLOPPY
, "fdc", NULL
},
1000 { PCI_CLASS_STORAGE_IPI
, "ipi", NULL
},
1001 { PCI_CLASS_STORAGE_RAID
, "raid", NULL
},
1002 { PCI_CLASS_STORAGE_ATA
, "ata", NULL
},
1003 { PCI_CLASS_STORAGE_SATA
, "sata", NULL
},
1004 { PCI_CLASS_STORAGE_SAS
, "sas", NULL
},
1005 { 0xFF, NULL
, NULL
},
1008 static const PCISubClass net_subclass
[] = {
1009 { PCI_CLASS_NETWORK_ETHERNET
, "ethernet", NULL
},
1010 { PCI_CLASS_NETWORK_TOKEN_RING
, "token-ring", NULL
},
1011 { PCI_CLASS_NETWORK_FDDI
, "fddi", NULL
},
1012 { PCI_CLASS_NETWORK_ATM
, "atm", NULL
},
1013 { PCI_CLASS_NETWORK_ISDN
, "isdn", NULL
},
1014 { PCI_CLASS_NETWORK_WORLDFIP
, "worldfip", NULL
},
1015 { PCI_CLASS_NETWORK_PICMG214
, "picmg", NULL
},
1016 { 0xFF, NULL
, NULL
},
1019 static const PCISubClass displ_subclass
[] = {
1020 { PCI_CLASS_DISPLAY_VGA
, "vga", NULL
},
1021 { PCI_CLASS_DISPLAY_XGA
, "xga", NULL
},
1022 { PCI_CLASS_DISPLAY_3D
, "3d-controller", NULL
},
1023 { 0xFF, NULL
, NULL
},
1026 static const PCISubClass media_subclass
[] = {
1027 { PCI_CLASS_MULTIMEDIA_VIDEO
, "video", NULL
},
1028 { PCI_CLASS_MULTIMEDIA_AUDIO
, "sound", NULL
},
1029 { PCI_CLASS_MULTIMEDIA_PHONE
, "telephony", NULL
},
1030 { 0xFF, NULL
, NULL
},
1033 static const PCISubClass mem_subclass
[] = {
1034 { PCI_CLASS_MEMORY_RAM
, "memory", NULL
},
1035 { PCI_CLASS_MEMORY_FLASH
, "flash", NULL
},
1036 { 0xFF, NULL
, NULL
},
1039 static const PCISubClass bridg_subclass
[] = {
1040 { PCI_CLASS_BRIDGE_HOST
, "host", NULL
},
1041 { PCI_CLASS_BRIDGE_ISA
, "isa", NULL
},
1042 { PCI_CLASS_BRIDGE_EISA
, "eisa", NULL
},
1043 { PCI_CLASS_BRIDGE_MC
, "mca", NULL
},
1044 { PCI_CLASS_BRIDGE_PCI
, "pci", NULL
},
1045 { PCI_CLASS_BRIDGE_PCMCIA
, "pcmcia", NULL
},
1046 { PCI_CLASS_BRIDGE_NUBUS
, "nubus", NULL
},
1047 { PCI_CLASS_BRIDGE_CARDBUS
, "cardbus", NULL
},
1048 { PCI_CLASS_BRIDGE_RACEWAY
, "raceway", NULL
},
1049 { PCI_CLASS_BRIDGE_PCI_SEMITP
, "semi-transparent-pci", NULL
},
1050 { PCI_CLASS_BRIDGE_IB_PCI
, "infiniband", NULL
},
1051 { 0xFF, NULL
, NULL
},
1054 static const PCISubClass comm_subclass
[] = {
1055 { PCI_CLASS_COMMUNICATION_SERIAL
, "serial", NULL
},
1056 { PCI_CLASS_COMMUNICATION_PARALLEL
, "parallel", NULL
},
1057 { PCI_CLASS_COMMUNICATION_MULTISERIAL
, "multiport-serial", NULL
},
1058 { PCI_CLASS_COMMUNICATION_MODEM
, "modem", NULL
},
1059 { PCI_CLASS_COMMUNICATION_GPIB
, "gpib", NULL
},
1060 { PCI_CLASS_COMMUNICATION_SC
, "smart-card", NULL
},
1061 { 0xFF, NULL
, NULL
, },
1064 static const PCIIFace pic_iface
[] = {
1065 { PCI_CLASS_SYSTEM_PIC_IOAPIC
, "io-apic" },
1066 { PCI_CLASS_SYSTEM_PIC_IOXAPIC
, "io-xapic" },
1070 static const PCISubClass sys_subclass
[] = {
1071 { PCI_CLASS_SYSTEM_PIC
, "interrupt-controller", pic_iface
},
1072 { PCI_CLASS_SYSTEM_DMA
, "dma-controller", NULL
},
1073 { PCI_CLASS_SYSTEM_TIMER
, "timer", NULL
},
1074 { PCI_CLASS_SYSTEM_RTC
, "rtc", NULL
},
1075 { PCI_CLASS_SYSTEM_PCI_HOTPLUG
, "hot-plug-controller", NULL
},
1076 { PCI_CLASS_SYSTEM_SDHCI
, "sd-host-controller", NULL
},
1077 { 0xFF, NULL
, NULL
},
1080 static const PCISubClass inp_subclass
[] = {
1081 { PCI_CLASS_INPUT_KEYBOARD
, "keyboard", NULL
},
1082 { PCI_CLASS_INPUT_PEN
, "pen", NULL
},
1083 { PCI_CLASS_INPUT_MOUSE
, "mouse", NULL
},
1084 { PCI_CLASS_INPUT_SCANNER
, "scanner", NULL
},
1085 { PCI_CLASS_INPUT_GAMEPORT
, "gameport", NULL
},
1086 { 0xFF, NULL
, NULL
},
1089 static const PCISubClass dock_subclass
[] = {
1090 { PCI_CLASS_DOCKING_GENERIC
, "dock", NULL
},
1091 { 0xFF, NULL
, NULL
},
1094 static const PCISubClass cpu_subclass
[] = {
1095 { PCI_CLASS_PROCESSOR_PENTIUM
, "pentium", NULL
},
1096 { PCI_CLASS_PROCESSOR_POWERPC
, "powerpc", NULL
},
1097 { PCI_CLASS_PROCESSOR_MIPS
, "mips", NULL
},
1098 { PCI_CLASS_PROCESSOR_CO
, "co-processor", NULL
},
1099 { 0xFF, NULL
, NULL
},
1102 static const PCIIFace usb_iface
[] = {
1103 { PCI_CLASS_SERIAL_USB_UHCI
, "usb-uhci" },
1104 { PCI_CLASS_SERIAL_USB_OHCI
, "usb-ohci", },
1105 { PCI_CLASS_SERIAL_USB_EHCI
, "usb-ehci" },
1106 { PCI_CLASS_SERIAL_USB_XHCI
, "usb-xhci" },
1107 { PCI_CLASS_SERIAL_USB_UNKNOWN
, "usb-unknown" },
1108 { PCI_CLASS_SERIAL_USB_DEVICE
, "usb-device" },
1112 static const PCISubClass ser_subclass
[] = {
1113 { PCI_CLASS_SERIAL_FIREWIRE
, "firewire", NULL
},
1114 { PCI_CLASS_SERIAL_ACCESS
, "access-bus", NULL
},
1115 { PCI_CLASS_SERIAL_SSA
, "ssa", NULL
},
1116 { PCI_CLASS_SERIAL_USB
, "usb", usb_iface
},
1117 { PCI_CLASS_SERIAL_FIBER
, "fibre-channel", NULL
},
1118 { PCI_CLASS_SERIAL_SMBUS
, "smb", NULL
},
1119 { PCI_CLASS_SERIAL_IB
, "infiniband", NULL
},
1120 { PCI_CLASS_SERIAL_IPMI
, "ipmi", NULL
},
1121 { PCI_CLASS_SERIAL_SERCOS
, "sercos", NULL
},
1122 { PCI_CLASS_SERIAL_CANBUS
, "canbus", NULL
},
1123 { 0xFF, NULL
, NULL
},
1126 static const PCISubClass wrl_subclass
[] = {
1127 { PCI_CLASS_WIRELESS_IRDA
, "irda", NULL
},
1128 { PCI_CLASS_WIRELESS_CIR
, "consumer-ir", NULL
},
1129 { PCI_CLASS_WIRELESS_RF_CONTROLLER
, "rf-controller", NULL
},
1130 { PCI_CLASS_WIRELESS_BLUETOOTH
, "bluetooth", NULL
},
1131 { PCI_CLASS_WIRELESS_BROADBAND
, "broadband", NULL
},
1132 { 0xFF, NULL
, NULL
},
1135 static const PCISubClass sat_subclass
[] = {
1136 { PCI_CLASS_SATELLITE_TV
, "satellite-tv", NULL
},
1137 { PCI_CLASS_SATELLITE_AUDIO
, "satellite-audio", NULL
},
1138 { PCI_CLASS_SATELLITE_VOICE
, "satellite-voice", NULL
},
1139 { PCI_CLASS_SATELLITE_DATA
, "satellite-data", NULL
},
1140 { 0xFF, NULL
, NULL
},
1143 static const PCISubClass crypt_subclass
[] = {
1144 { PCI_CLASS_CRYPT_NETWORK
, "network-encryption", NULL
},
1145 { PCI_CLASS_CRYPT_ENTERTAINMENT
,
1146 "entertainment-encryption", NULL
},
1147 { 0xFF, NULL
, NULL
},
1150 static const PCISubClass spc_subclass
[] = {
1151 { PCI_CLASS_SP_DPIO
, "dpio", NULL
},
1152 { PCI_CLASS_SP_PERF
, "counter", NULL
},
1153 { PCI_CLASS_SP_SYNCH
, "measurement", NULL
},
1154 { PCI_CLASS_SP_MANAGEMENT
, "management-card", NULL
},
1155 { 0xFF, NULL
, NULL
},
1158 static const PCIClass pci_classes
[] = {
1159 { "legacy-device", undef_subclass
},
1160 { "mass-storage", mass_subclass
},
1161 { "network", net_subclass
},
1162 { "display", displ_subclass
, },
1163 { "multimedia-device", media_subclass
},
1164 { "memory-controller", mem_subclass
},
1165 { "unknown-bridge", bridg_subclass
},
1166 { "communication-controller", comm_subclass
},
1167 { "system-peripheral", sys_subclass
},
1168 { "input-controller", inp_subclass
},
1169 { "docking-station", dock_subclass
},
1170 { "cpu", cpu_subclass
},
1171 { "serial-bus", ser_subclass
},
1172 { "wireless-controller", wrl_subclass
},
1173 { "intelligent-io", NULL
},
1174 { "satellite-device", sat_subclass
},
1175 { "encryption", crypt_subclass
},
1176 { "data-processing-controller", spc_subclass
},
1179 static const char *dt_name_from_class(uint8_t class, uint8_t subclass
,
1182 const PCIClass
*pclass
;
1183 const PCISubClass
*psubclass
;
1184 const PCIIFace
*piface
;
1187 if (class >= ARRAY_SIZE(pci_classes
)) {
1191 pclass
= pci_classes
+ class;
1192 name
= pclass
->name
;
1194 if (pclass
->subc
== NULL
) {
1198 psubclass
= pclass
->subc
;
1199 while ((psubclass
->subclass
& 0xff) != 0xff) {
1200 if ((psubclass
->subclass
& 0xff) == subclass
) {
1201 name
= psubclass
->name
;
1207 piface
= psubclass
->iface
;
1208 if (piface
== NULL
) {
1211 while ((piface
->iface
& 0xff) != 0xff) {
1212 if ((piface
->iface
& 0xff) == iface
) {
1213 name
= piface
->name
;
1223 * DRC helper functions
1226 static uint32_t drc_id_from_devfn(SpaprPhbState
*phb
,
1227 uint8_t chassis
, int32_t devfn
)
1229 return (phb
->index
<< 16) | (chassis
<< 8) | devfn
;
1232 static SpaprDrc
*drc_from_devfn(SpaprPhbState
*phb
,
1233 uint8_t chassis
, int32_t devfn
)
1235 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI
,
1236 drc_id_from_devfn(phb
, chassis
, devfn
));
1239 static uint8_t chassis_from_bus(PCIBus
*bus
, Error
**errp
)
1241 if (pci_bus_is_root(bus
)) {
1244 PCIDevice
*bridge
= pci_bridge_get_device(bus
);
1246 return object_property_get_uint(OBJECT(bridge
), "chassis_nr", errp
);
1250 static SpaprDrc
*drc_from_dev(SpaprPhbState
*phb
, PCIDevice
*dev
)
1252 Error
*local_err
= NULL
;
1253 uint8_t chassis
= chassis_from_bus(pci_get_bus(dev
), &local_err
);
1256 error_report_err(local_err
);
1260 return drc_from_devfn(phb
, chassis
, dev
->devfn
);
1263 static void add_drcs(SpaprPhbState
*phb
, PCIBus
*bus
, Error
**errp
)
1268 Error
*local_err
= NULL
;
1270 if (!phb
->dr_enabled
) {
1274 chassis
= chassis_from_bus(bus
, &local_err
);
1276 error_propagate(errp
, local_err
);
1280 if (pci_bus_is_root(bus
)) {
1281 owner
= OBJECT(phb
);
1283 owner
= OBJECT(pci_bridge_get_device(bus
));
1286 for (i
= 0; i
< PCI_SLOT_MAX
* PCI_FUNC_MAX
; i
++) {
1287 spapr_dr_connector_new(owner
, TYPE_SPAPR_DRC_PCI
,
1288 drc_id_from_devfn(phb
, chassis
, i
));
1292 static void remove_drcs(SpaprPhbState
*phb
, PCIBus
*bus
, Error
**errp
)
1296 Error
*local_err
= NULL
;
1298 if (!phb
->dr_enabled
) {
1302 chassis
= chassis_from_bus(bus
, &local_err
);
1304 error_propagate(errp
, local_err
);
1308 for (i
= PCI_SLOT_MAX
* PCI_FUNC_MAX
- 1; i
>= 0; i
--) {
1309 SpaprDrc
*drc
= drc_from_devfn(phb
, chassis
, i
);
1312 object_unparent(OBJECT(drc
));
1317 typedef struct PciWalkFdt
{
1320 SpaprPhbState
*sphb
;
1324 static int spapr_dt_pci_device(SpaprPhbState
*sphb
, PCIDevice
*dev
,
1325 void *fdt
, int parent_offset
);
1327 static void spapr_dt_pci_device_cb(PCIBus
*bus
, PCIDevice
*pdev
,
1330 PciWalkFdt
*p
= opaque
;
1334 /* Something's already broken, don't keep going */
1338 err
= spapr_dt_pci_device(p
->sphb
, pdev
, p
->fdt
, p
->offset
);
1344 /* Augment PCI device node with bridge specific information */
1345 static int spapr_dt_pci_bus(SpaprPhbState
*sphb
, PCIBus
*bus
,
1346 void *fdt
, int offset
)
1349 PciWalkFdt cbinfo
= {
1357 _FDT(fdt_setprop_cell(fdt
, offset
, "#address-cells",
1358 RESOURCE_CELLS_ADDRESS
));
1359 _FDT(fdt_setprop_cell(fdt
, offset
, "#size-cells",
1360 RESOURCE_CELLS_SIZE
));
1363 pci_for_each_device_reverse(bus
, pci_bus_num(bus
),
1364 spapr_dt_pci_device_cb
, &cbinfo
);
1369 if (pci_bus_is_root(bus
)) {
1370 owner
= OBJECT(sphb
);
1372 owner
= OBJECT(pci_bridge_get_device(bus
));
1375 ret
= spapr_dt_drc(fdt
, offset
, owner
,
1376 SPAPR_DR_CONNECTOR_TYPE_PCI
);
1384 /* create OF node for pci device and required OF DT properties */
1385 static int spapr_dt_pci_device(SpaprPhbState
*sphb
, PCIDevice
*dev
,
1386 void *fdt
, int parent_offset
)
1389 const gchar
*basename
;
1391 int slot
= PCI_SLOT(dev
->devfn
);
1392 int func
= PCI_FUNC(dev
->devfn
);
1393 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1395 SpaprDrc
*drc
= drc_from_dev(sphb
, dev
);
1396 uint32_t vendor_id
= pci_default_read_config(dev
, PCI_VENDOR_ID
, 2);
1397 uint32_t device_id
= pci_default_read_config(dev
, PCI_DEVICE_ID
, 2);
1398 uint32_t revision_id
= pci_default_read_config(dev
, PCI_REVISION_ID
, 1);
1399 uint32_t ccode
= pci_default_read_config(dev
, PCI_CLASS_PROG
, 3);
1400 uint32_t irq_pin
= pci_default_read_config(dev
, PCI_INTERRUPT_PIN
, 1);
1401 uint32_t subsystem_id
= pci_default_read_config(dev
, PCI_SUBSYSTEM_ID
, 2);
1402 uint32_t subsystem_vendor_id
=
1403 pci_default_read_config(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2);
1404 uint32_t cache_line_size
=
1405 pci_default_read_config(dev
, PCI_CACHE_LINE_SIZE
, 1);
1406 uint32_t pci_status
= pci_default_read_config(dev
, PCI_STATUS
, 2);
1409 basename
= dt_name_from_class((ccode
>> 16) & 0xff, (ccode
>> 8) & 0xff,
1413 nodename
= g_strdup_printf("%s@%x,%x", basename
, slot
, func
);
1415 nodename
= g_strdup_printf("%s@%x", basename
, slot
);
1418 _FDT(offset
= fdt_add_subnode(fdt
, parent_offset
, nodename
));
1422 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1423 _FDT(fdt_setprop_cell(fdt
, offset
, "vendor-id", vendor_id
));
1424 _FDT(fdt_setprop_cell(fdt
, offset
, "device-id", device_id
));
1425 _FDT(fdt_setprop_cell(fdt
, offset
, "revision-id", revision_id
));
1427 _FDT(fdt_setprop_cell(fdt
, offset
, "class-code", ccode
));
1429 _FDT(fdt_setprop_cell(fdt
, offset
, "interrupts", irq_pin
));
1433 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-id", subsystem_id
));
1436 if (subsystem_vendor_id
) {
1437 _FDT(fdt_setprop_cell(fdt
, offset
, "subsystem-vendor-id",
1438 subsystem_vendor_id
));
1441 _FDT(fdt_setprop_cell(fdt
, offset
, "cache-line-size", cache_line_size
));
1444 /* the following fdt cells are masked off the pci status register */
1445 _FDT(fdt_setprop_cell(fdt
, offset
, "devsel-speed",
1446 PCI_STATUS_DEVSEL_MASK
& pci_status
));
1448 if (pci_status
& PCI_STATUS_FAST_BACK
) {
1449 _FDT(fdt_setprop(fdt
, offset
, "fast-back-to-back", NULL
, 0));
1451 if (pci_status
& PCI_STATUS_66MHZ
) {
1452 _FDT(fdt_setprop(fdt
, offset
, "66mhz-capable", NULL
, 0));
1454 if (pci_status
& PCI_STATUS_UDF
) {
1455 _FDT(fdt_setprop(fdt
, offset
, "udf-supported", NULL
, 0));
1458 loc_code
= spapr_phb_get_loc_code(sphb
, dev
);
1459 _FDT(fdt_setprop_string(fdt
, offset
, "ibm,loc-code", loc_code
));
1463 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index",
1464 spapr_drc_index(drc
)));
1467 if (msi_present(dev
)) {
1468 uint32_t max_msi
= msi_nr_vectors_allocated(dev
);
1470 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi", max_msi
));
1473 if (msix_present(dev
)) {
1474 uint32_t max_msix
= dev
->msix_entries_nr
;
1476 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,req#msi-x", max_msix
));
1480 populate_resource_props(dev
, &rp
);
1481 _FDT(fdt_setprop(fdt
, offset
, "reg", (uint8_t *)rp
.reg
, rp
.reg_len
));
1482 _FDT(fdt_setprop(fdt
, offset
, "assigned-addresses",
1483 (uint8_t *)rp
.assigned
, rp
.assigned_len
));
1485 if (sphb
->pcie_ecs
&& pci_is_express(dev
)) {
1486 _FDT(fdt_setprop_cell(fdt
, offset
, "ibm,pci-config-space-type", 0x1));
1489 spapr_phb_nvgpu_populate_pcidev_dt(dev
, fdt
, offset
, sphb
);
1491 if (!pc
->is_bridge
) {
1492 /* Properties only for non-bridges */
1493 uint32_t min_grant
= pci_default_read_config(dev
, PCI_MIN_GNT
, 1);
1494 uint32_t max_latency
= pci_default_read_config(dev
, PCI_MAX_LAT
, 1);
1495 _FDT(fdt_setprop_cell(fdt
, offset
, "min-grant", min_grant
));
1496 _FDT(fdt_setprop_cell(fdt
, offset
, "max-latency", max_latency
));
1499 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
1501 return spapr_dt_pci_bus(sphb
, sec_bus
, fdt
, offset
);
1505 /* Callback to be called during DRC release. */
1506 void spapr_phb_remove_pci_device_cb(DeviceState
*dev
)
1508 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
1510 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
1511 object_unparent(OBJECT(dev
));
1514 int spapr_pci_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
1515 void *fdt
, int *fdt_start_offset
, Error
**errp
)
1517 HotplugHandler
*plug_handler
= qdev_get_hotplug_handler(drc
->dev
);
1518 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(plug_handler
);
1519 PCIDevice
*pdev
= PCI_DEVICE(drc
->dev
);
1521 *fdt_start_offset
= spapr_dt_pci_device(sphb
, pdev
, fdt
, 0);
1525 static void spapr_pci_bridge_plug(SpaprPhbState
*phb
,
1529 Error
*local_err
= NULL
;
1530 PCIBus
*bus
= pci_bridge_get_sec_bus(bridge
);
1532 add_drcs(phb
, bus
, &local_err
);
1534 error_propagate(errp
, local_err
);
1539 static void spapr_pci_plug(HotplugHandler
*plug_handler
,
1540 DeviceState
*plugged_dev
, Error
**errp
)
1542 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1543 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1544 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1545 SpaprDrc
*drc
= drc_from_dev(phb
, pdev
);
1546 Error
*local_err
= NULL
;
1547 PCIBus
*bus
= PCI_BUS(qdev_get_parent_bus(DEVICE(pdev
)));
1548 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1550 /* if DR is disabled we don't need to do anything in the case of
1551 * hotplug or coldplug callbacks
1553 if (!phb
->dr_enabled
) {
1554 /* if this is a hotplug operation initiated by the user
1555 * we need to let them know it's not enabled
1557 if (plugged_dev
->hotplugged
) {
1558 error_setg(&local_err
, QERR_BUS_NO_HOTPLUG
,
1559 object_get_typename(OBJECT(phb
)));
1566 if (pc
->is_bridge
) {
1567 spapr_pci_bridge_plug(phb
, PCI_BRIDGE(plugged_dev
), &local_err
);
1569 error_propagate(errp
, local_err
);
1574 /* Following the QEMU convention used for PCIe multifunction
1575 * hotplug, we do not allow functions to be hotplugged to a
1576 * slot that already has function 0 present
1578 if (plugged_dev
->hotplugged
&& bus
->devices
[PCI_DEVFN(slotnr
, 0)] &&
1579 PCI_FUNC(pdev
->devfn
) != 0) {
1580 error_setg(&local_err
, "PCI: slot %d function 0 already ocuppied by %s,"
1581 " additional functions can no longer be exposed to guest.",
1582 slotnr
, bus
->devices
[PCI_DEVFN(slotnr
, 0)]->name
);
1586 spapr_drc_attach(drc
, DEVICE(pdev
), &local_err
);
1591 /* If this is function 0, signal hotplug for all the device functions.
1592 * Otherwise defer sending the hotplug event.
1594 if (!spapr_drc_hotplugged(plugged_dev
)) {
1595 spapr_drc_reset(drc
);
1596 } else if (PCI_FUNC(pdev
->devfn
) == 0) {
1598 uint8_t chassis
= chassis_from_bus(pci_get_bus(pdev
), &local_err
);
1601 error_propagate(errp
, local_err
);
1605 for (i
= 0; i
< 8; i
++) {
1607 SpaprDrcClass
*func_drck
;
1608 SpaprDREntitySense state
;
1610 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1611 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1612 state
= func_drck
->dr_entity_sense(func_drc
);
1614 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1615 spapr_hotplug_req_add_by_index(func_drc
);
1621 error_propagate(errp
, local_err
);
1624 static void spapr_pci_bridge_unplug(SpaprPhbState
*phb
,
1628 Error
*local_err
= NULL
;
1629 PCIBus
*bus
= pci_bridge_get_sec_bus(bridge
);
1631 remove_drcs(phb
, bus
, &local_err
);
1633 error_propagate(errp
, local_err
);
1638 static void spapr_pci_unplug(HotplugHandler
*plug_handler
,
1639 DeviceState
*plugged_dev
, Error
**errp
)
1641 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1642 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1644 /* some version guests do not wait for completion of a device
1645 * cleanup (generally done asynchronously by the kernel) before
1646 * signaling to QEMU that the device is safe, but instead sleep
1647 * for some 'safe' period of time. unfortunately on a busy host
1648 * this sleep isn't guaranteed to be long enough, resulting in
1649 * bad things like IRQ lines being left asserted during final
1650 * device removal. to deal with this we call reset just prior
1651 * to finalizing the device, which will put the device back into
1652 * an 'idle' state, as the device cleanup code expects.
1654 pci_device_reset(PCI_DEVICE(plugged_dev
));
1656 if (pc
->is_bridge
) {
1657 Error
*local_err
= NULL
;
1658 spapr_pci_bridge_unplug(phb
, PCI_BRIDGE(plugged_dev
), &local_err
);
1660 error_propagate(errp
, local_err
);
1665 object_property_set_bool(OBJECT(plugged_dev
), false, "realized", NULL
);
1668 static void spapr_pci_unplug_request(HotplugHandler
*plug_handler
,
1669 DeviceState
*plugged_dev
, Error
**errp
)
1671 SpaprPhbState
*phb
= SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler
));
1672 PCIDevice
*pdev
= PCI_DEVICE(plugged_dev
);
1673 SpaprDrc
*drc
= drc_from_dev(phb
, pdev
);
1675 if (!phb
->dr_enabled
) {
1676 error_setg(errp
, QERR_BUS_NO_HOTPLUG
,
1677 object_get_typename(OBJECT(phb
)));
1682 g_assert(drc
->dev
== plugged_dev
);
1684 if (!spapr_drc_unplug_requested(drc
)) {
1685 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(plugged_dev
);
1686 uint32_t slotnr
= PCI_SLOT(pdev
->devfn
);
1688 SpaprDrcClass
*func_drck
;
1689 SpaprDREntitySense state
;
1691 Error
*local_err
= NULL
;
1692 uint8_t chassis
= chassis_from_bus(pci_get_bus(pdev
), &local_err
);
1695 error_propagate(errp
, local_err
);
1699 if (pc
->is_bridge
) {
1700 error_setg(errp
, "PCI: Hot unplug of PCI bridges not supported");
1703 /* ensure any other present functions are pending unplug */
1704 if (PCI_FUNC(pdev
->devfn
) == 0) {
1705 for (i
= 1; i
< 8; i
++) {
1706 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1707 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1708 state
= func_drck
->dr_entity_sense(func_drc
);
1709 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
1710 && !spapr_drc_unplug_requested(func_drc
)) {
1712 "PCI: slot %d, function %d still present. "
1713 "Must unplug all non-0 functions first.",
1720 spapr_drc_detach(drc
);
1722 /* if this isn't func 0, defer unplug event. otherwise signal removal
1723 * for all present functions
1725 if (PCI_FUNC(pdev
->devfn
) == 0) {
1726 for (i
= 7; i
>= 0; i
--) {
1727 func_drc
= drc_from_devfn(phb
, chassis
, PCI_DEVFN(slotnr
, i
));
1728 func_drck
= SPAPR_DR_CONNECTOR_GET_CLASS(func_drc
);
1729 state
= func_drck
->dr_entity_sense(func_drc
);
1730 if (state
== SPAPR_DR_ENTITY_SENSE_PRESENT
) {
1731 spapr_hotplug_req_remove_by_index(func_drc
);
1738 static void spapr_phb_finalizefn(Object
*obj
)
1740 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(obj
);
1742 g_free(sphb
->dtbusname
);
1743 sphb
->dtbusname
= NULL
;
1746 static void spapr_phb_unrealize(DeviceState
*dev
, Error
**errp
)
1748 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
1749 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1750 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1751 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(phb
);
1752 SpaprTceTable
*tcet
;
1754 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1755 Error
*local_err
= NULL
;
1757 spapr_phb_nvgpu_free(sphb
);
1760 g_hash_table_unref(sphb
->msi
);
1765 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1766 * via PHB's unrealize->object_finalize
1768 for (i
= windows_supported
- 1; i
>= 0; i
--) {
1769 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
1771 memory_region_del_subregion(&sphb
->iommu_root
,
1772 spapr_tce_get_iommu(tcet
));
1776 remove_drcs(sphb
, phb
->bus
, &local_err
);
1778 error_propagate(errp
, local_err
);
1782 for (i
= PCI_NUM_PINS
- 1; i
>= 0; i
--) {
1783 if (sphb
->lsi_table
[i
].irq
) {
1784 spapr_irq_free(spapr
, sphb
->lsi_table
[i
].irq
, 1);
1785 sphb
->lsi_table
[i
].irq
= 0;
1789 QLIST_REMOVE(sphb
, list
);
1791 memory_region_del_subregion(&sphb
->iommu_root
, &sphb
->msiwindow
);
1794 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1795 * unmapped all sections. Remove the listeners now, before destroying the
1798 address_space_remove_listeners(&sphb
->iommu_as
);
1799 address_space_destroy(&sphb
->iommu_as
);
1801 qbus_set_hotplug_handler(BUS(phb
->bus
), NULL
, &error_abort
);
1802 pci_unregister_root_bus(phb
->bus
);
1804 memory_region_del_subregion(get_system_memory(), &sphb
->iowindow
);
1805 if (sphb
->mem64_win_pciaddr
!= (hwaddr
)-1) {
1806 memory_region_del_subregion(get_system_memory(), &sphb
->mem64window
);
1808 memory_region_del_subregion(get_system_memory(), &sphb
->mem32window
);
1811 static void spapr_phb_realize(DeviceState
*dev
, Error
**errp
)
1813 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1814 * tries to add a sPAPR PHB to a non-pseries machine.
1816 SpaprMachineState
*spapr
=
1817 (SpaprMachineState
*) object_dynamic_cast(qdev_get_machine(),
1818 TYPE_SPAPR_MACHINE
);
1819 SpaprMachineClass
*smc
= spapr
? SPAPR_MACHINE_GET_CLASS(spapr
) : NULL
;
1820 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
1821 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(s
);
1822 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
1826 uint64_t msi_window_size
= 4096;
1827 SpaprTceTable
*tcet
;
1828 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
1829 Error
*local_err
= NULL
;
1832 error_setg(errp
, TYPE_SPAPR_PCI_HOST_BRIDGE
" needs a pseries machine");
1836 assert(sphb
->index
!= (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1838 if (sphb
->mem64_win_size
!= 0) {
1839 if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1840 error_setg(errp
, "32-bit memory window of size 0x%"HWADDR_PRIx
1841 " (max 2 GiB)", sphb
->mem_win_size
);
1845 /* 64-bit window defaults to identity mapping */
1846 sphb
->mem64_win_pciaddr
= sphb
->mem64_win_addr
;
1847 } else if (sphb
->mem_win_size
> SPAPR_PCI_MEM32_WIN_SIZE
) {
1849 * For compatibility with old configuration, if no 64-bit MMIO
1850 * window is specified, but the ordinary (32-bit) memory
1851 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit
1852 * window, with a 64-bit MMIO window following on immediately
1855 sphb
->mem64_win_size
= sphb
->mem_win_size
- SPAPR_PCI_MEM32_WIN_SIZE
;
1856 sphb
->mem64_win_addr
= sphb
->mem_win_addr
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1857 sphb
->mem64_win_pciaddr
=
1858 SPAPR_PCI_MEM_WIN_BUS_OFFSET
+ SPAPR_PCI_MEM32_WIN_SIZE
;
1859 sphb
->mem_win_size
= SPAPR_PCI_MEM32_WIN_SIZE
;
1862 if (spapr_pci_find_phb(spapr
, sphb
->buid
)) {
1865 error_setg(errp
, "PCI host bridges must have unique indexes");
1866 error_append_hint(errp
, "The following indexes are already in use:");
1867 QLIST_FOREACH(s
, &spapr
->phbs
, list
) {
1868 error_append_hint(errp
, " %d", s
->index
);
1870 error_append_hint(errp
, "\nTry another value for the index property\n");
1874 if (sphb
->numa_node
!= -1 &&
1875 (sphb
->numa_node
>= MAX_NODES
|| !numa_info
[sphb
->numa_node
].present
)) {
1876 error_setg(errp
, "Invalid NUMA node ID for PCI host bridge");
1880 sphb
->dtbusname
= g_strdup_printf("pci@%" PRIx64
, sphb
->buid
);
1882 /* Initialize memory regions */
1883 namebuf
= g_strdup_printf("%s.mmio", sphb
->dtbusname
);
1884 memory_region_init(&sphb
->memspace
, OBJECT(sphb
), namebuf
, UINT64_MAX
);
1887 namebuf
= g_strdup_printf("%s.mmio32-alias", sphb
->dtbusname
);
1888 memory_region_init_alias(&sphb
->mem32window
, OBJECT(sphb
),
1889 namebuf
, &sphb
->memspace
,
1890 SPAPR_PCI_MEM_WIN_BUS_OFFSET
, sphb
->mem_win_size
);
1892 memory_region_add_subregion(get_system_memory(), sphb
->mem_win_addr
,
1893 &sphb
->mem32window
);
1895 if (sphb
->mem64_win_size
!= 0) {
1896 namebuf
= g_strdup_printf("%s.mmio64-alias", sphb
->dtbusname
);
1897 memory_region_init_alias(&sphb
->mem64window
, OBJECT(sphb
),
1898 namebuf
, &sphb
->memspace
,
1899 sphb
->mem64_win_pciaddr
, sphb
->mem64_win_size
);
1902 memory_region_add_subregion(get_system_memory(),
1903 sphb
->mem64_win_addr
,
1904 &sphb
->mem64window
);
1907 /* Initialize IO regions */
1908 namebuf
= g_strdup_printf("%s.io", sphb
->dtbusname
);
1909 memory_region_init(&sphb
->iospace
, OBJECT(sphb
),
1910 namebuf
, SPAPR_PCI_IO_WIN_SIZE
);
1913 namebuf
= g_strdup_printf("%s.io-alias", sphb
->dtbusname
);
1914 memory_region_init_alias(&sphb
->iowindow
, OBJECT(sphb
), namebuf
,
1915 &sphb
->iospace
, 0, SPAPR_PCI_IO_WIN_SIZE
);
1917 memory_region_add_subregion(get_system_memory(), sphb
->io_win_addr
,
1920 bus
= pci_register_root_bus(dev
, NULL
,
1921 pci_spapr_set_irq
, pci_swizzle_map_irq_fn
, sphb
,
1922 &sphb
->memspace
, &sphb
->iospace
,
1923 PCI_DEVFN(0, 0), PCI_NUM_PINS
,
1927 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1928 * para-virtualized PCI bus *does* permit PCI-E extended config
1931 if (sphb
->pcie_ecs
) {
1932 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
1935 qbus_set_hotplug_handler(BUS(phb
->bus
), OBJECT(sphb
), NULL
);
1938 * Initialize PHB address space.
1939 * By default there will be at least one subregion for default
1941 * Later the guest might want to create another DMA window
1942 * which will become another memory subregion.
1944 namebuf
= g_strdup_printf("%s.iommu-root", sphb
->dtbusname
);
1945 memory_region_init(&sphb
->iommu_root
, OBJECT(sphb
),
1946 namebuf
, UINT64_MAX
);
1948 address_space_init(&sphb
->iommu_as
, &sphb
->iommu_root
,
1952 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1953 * we need to allocate some memory to catch those writes coming
1954 * from msi_notify()/msix_notify().
1955 * As MSIMessage:addr is going to be the same and MSIMessage:data
1956 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1959 * For KVM we want to ensure that this memory is a full page so that
1960 * our memory slot is of page size granularity.
1962 if (kvm_enabled()) {
1963 msi_window_size
= getpagesize();
1966 memory_region_init_io(&sphb
->msiwindow
, OBJECT(sphb
), &spapr_msi_ops
, spapr
,
1967 "msi", msi_window_size
);
1968 memory_region_add_subregion(&sphb
->iommu_root
, SPAPR_PCI_MSI_WINDOW
,
1971 pci_setup_iommu(bus
, spapr_pci_dma_iommu
, sphb
);
1973 pci_bus_set_route_irq_fn(bus
, spapr_route_intx_pin_to_irq
);
1975 QLIST_INSERT_HEAD(&spapr
->phbs
, sphb
, list
);
1977 /* Initialize the LSI table */
1978 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
1979 uint32_t irq
= SPAPR_IRQ_PCI_LSI
+ sphb
->index
* PCI_NUM_PINS
+ i
;
1981 if (smc
->legacy_irq_allocation
) {
1982 irq
= spapr_irq_findone(spapr
, &local_err
);
1984 error_propagate_prepend(errp
, local_err
,
1985 "can't allocate LSIs: ");
1987 * Older machines will never support PHB hotplug, ie, this is an
1988 * init only path and QEMU will terminate. No need to rollback.
1994 spapr_irq_claim(spapr
, irq
, true, &local_err
);
1996 error_propagate_prepend(errp
, local_err
, "can't allocate LSIs: ");
2000 sphb
->lsi_table
[i
].irq
= irq
;
2003 /* allocate connectors for child PCI devices */
2004 add_drcs(sphb
, phb
->bus
, &local_err
);
2006 error_propagate(errp
, local_err
);
2011 for (i
= 0; i
< windows_supported
; ++i
) {
2012 tcet
= spapr_tce_new_table(DEVICE(sphb
), sphb
->dma_liobn
[i
]);
2014 error_setg(errp
, "Creating window#%d failed for %s",
2015 i
, sphb
->dtbusname
);
2018 memory_region_add_subregion(&sphb
->iommu_root
, 0,
2019 spapr_tce_get_iommu(tcet
));
2022 sphb
->msi
= g_hash_table_new_full(g_int_hash
, g_int_equal
, g_free
, g_free
);
2026 spapr_phb_unrealize(dev
, NULL
);
2029 static int spapr_phb_children_reset(Object
*child
, void *opaque
)
2031 DeviceState
*dev
= (DeviceState
*) object_dynamic_cast(child
, TYPE_DEVICE
);
2040 void spapr_phb_dma_reset(SpaprPhbState
*sphb
)
2043 SpaprTceTable
*tcet
;
2045 for (i
= 0; i
< SPAPR_PCI_DMA_MAX_WINDOWS
; ++i
) {
2046 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[i
]);
2048 if (tcet
&& tcet
->nb_table
) {
2049 spapr_tce_table_disable(tcet
);
2053 /* Register default 32bit DMA window */
2054 tcet
= spapr_tce_find_by_liobn(sphb
->dma_liobn
[0]);
2055 spapr_tce_table_enable(tcet
, SPAPR_TCE_PAGE_SHIFT
, sphb
->dma_win_addr
,
2056 sphb
->dma_win_size
>> SPAPR_TCE_PAGE_SHIFT
);
2059 static void spapr_phb_reset(DeviceState
*qdev
)
2061 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(qdev
);
2064 spapr_phb_dma_reset(sphb
);
2065 spapr_phb_nvgpu_free(sphb
);
2066 spapr_phb_nvgpu_setup(sphb
, &errp
);
2068 error_report_err(errp
);
2071 /* Reset the IOMMU state */
2072 object_child_foreach(OBJECT(qdev
), spapr_phb_children_reset
, NULL
);
2074 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev
))) {
2075 spapr_phb_vfio_reset(qdev
);
2079 static Property spapr_phb_properties
[] = {
2080 DEFINE_PROP_UINT32("index", SpaprPhbState
, index
, -1),
2081 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState
, mem_win_size
,
2082 SPAPR_PCI_MEM32_WIN_SIZE
),
2083 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState
, mem64_win_size
,
2084 SPAPR_PCI_MEM64_WIN_SIZE
),
2085 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState
, io_win_size
,
2086 SPAPR_PCI_IO_WIN_SIZE
),
2087 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState
, dr_enabled
,
2089 /* Default DMA window is 0..1GB */
2090 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState
, dma_win_addr
, 0),
2091 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState
, dma_win_size
, 0x40000000),
2092 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState
, dma64_win_addr
,
2093 0x800000000000000ULL
),
2094 DEFINE_PROP_BOOL("ddw", SpaprPhbState
, ddw_enabled
, true),
2095 DEFINE_PROP_UINT64("pgsz", SpaprPhbState
, page_size_mask
,
2096 (1ULL << 12) | (1ULL << 16)),
2097 DEFINE_PROP_UINT32("numa_node", SpaprPhbState
, numa_node
, -1),
2098 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState
,
2099 pre_2_8_migration
, false),
2100 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState
,
2102 DEFINE_PROP_UINT64("gpa", SpaprPhbState
, nv2_gpa_win_addr
, 0),
2103 DEFINE_PROP_UINT64("atsd", SpaprPhbState
, nv2_atsd_win_addr
, 0),
2104 DEFINE_PROP_END_OF_LIST(),
2107 static const VMStateDescription vmstate_spapr_pci_lsi
= {
2108 .name
= "spapr_pci/lsi",
2110 .minimum_version_id
= 1,
2111 .fields
= (VMStateField
[]) {
2112 VMSTATE_UINT32_EQUAL(irq
, struct spapr_pci_lsi
, NULL
),
2114 VMSTATE_END_OF_LIST()
2118 static const VMStateDescription vmstate_spapr_pci_msi
= {
2119 .name
= "spapr_pci/msi",
2121 .minimum_version_id
= 1,
2122 .fields
= (VMStateField
[]) {
2123 VMSTATE_UINT32(key
, spapr_pci_msi_mig
),
2124 VMSTATE_UINT32(value
.first_irq
, spapr_pci_msi_mig
),
2125 VMSTATE_UINT32(value
.num
, spapr_pci_msi_mig
),
2126 VMSTATE_END_OF_LIST()
2130 static int spapr_pci_pre_save(void *opaque
)
2132 SpaprPhbState
*sphb
= opaque
;
2133 GHashTableIter iter
;
2134 gpointer key
, value
;
2137 if (sphb
->pre_2_8_migration
) {
2138 sphb
->mig_liobn
= sphb
->dma_liobn
[0];
2139 sphb
->mig_mem_win_addr
= sphb
->mem_win_addr
;
2140 sphb
->mig_mem_win_size
= sphb
->mem_win_size
;
2141 sphb
->mig_io_win_addr
= sphb
->io_win_addr
;
2142 sphb
->mig_io_win_size
= sphb
->io_win_size
;
2144 if ((sphb
->mem64_win_size
!= 0)
2145 && (sphb
->mem64_win_addr
2146 == (sphb
->mem_win_addr
+ sphb
->mem_win_size
))) {
2147 sphb
->mig_mem_win_size
+= sphb
->mem64_win_size
;
2151 g_free(sphb
->msi_devs
);
2152 sphb
->msi_devs
= NULL
;
2153 sphb
->msi_devs_num
= g_hash_table_size(sphb
->msi
);
2154 if (!sphb
->msi_devs_num
) {
2157 sphb
->msi_devs
= g_new(spapr_pci_msi_mig
, sphb
->msi_devs_num
);
2159 g_hash_table_iter_init(&iter
, sphb
->msi
);
2160 for (i
= 0; g_hash_table_iter_next(&iter
, &key
, &value
); ++i
) {
2161 sphb
->msi_devs
[i
].key
= *(uint32_t *) key
;
2162 sphb
->msi_devs
[i
].value
= *(spapr_pci_msi
*) value
;
2168 static int spapr_pci_post_load(void *opaque
, int version_id
)
2170 SpaprPhbState
*sphb
= opaque
;
2171 gpointer key
, value
;
2174 for (i
= 0; i
< sphb
->msi_devs_num
; ++i
) {
2175 key
= g_memdup(&sphb
->msi_devs
[i
].key
,
2176 sizeof(sphb
->msi_devs
[i
].key
));
2177 value
= g_memdup(&sphb
->msi_devs
[i
].value
,
2178 sizeof(sphb
->msi_devs
[i
].value
));
2179 g_hash_table_insert(sphb
->msi
, key
, value
);
2181 g_free(sphb
->msi_devs
);
2182 sphb
->msi_devs
= NULL
;
2183 sphb
->msi_devs_num
= 0;
2188 static bool pre_2_8_migration(void *opaque
, int version_id
)
2190 SpaprPhbState
*sphb
= opaque
;
2192 return sphb
->pre_2_8_migration
;
2195 static const VMStateDescription vmstate_spapr_pci
= {
2196 .name
= "spapr_pci",
2198 .minimum_version_id
= 2,
2199 .pre_save
= spapr_pci_pre_save
,
2200 .post_load
= spapr_pci_post_load
,
2201 .fields
= (VMStateField
[]) {
2202 VMSTATE_UINT64_EQUAL(buid
, SpaprPhbState
, NULL
),
2203 VMSTATE_UINT32_TEST(mig_liobn
, SpaprPhbState
, pre_2_8_migration
),
2204 VMSTATE_UINT64_TEST(mig_mem_win_addr
, SpaprPhbState
, pre_2_8_migration
),
2205 VMSTATE_UINT64_TEST(mig_mem_win_size
, SpaprPhbState
, pre_2_8_migration
),
2206 VMSTATE_UINT64_TEST(mig_io_win_addr
, SpaprPhbState
, pre_2_8_migration
),
2207 VMSTATE_UINT64_TEST(mig_io_win_size
, SpaprPhbState
, pre_2_8_migration
),
2208 VMSTATE_STRUCT_ARRAY(lsi_table
, SpaprPhbState
, PCI_NUM_PINS
, 0,
2209 vmstate_spapr_pci_lsi
, struct spapr_pci_lsi
),
2210 VMSTATE_INT32(msi_devs_num
, SpaprPhbState
),
2211 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs
, SpaprPhbState
, msi_devs_num
, 0,
2212 vmstate_spapr_pci_msi
, spapr_pci_msi_mig
),
2213 VMSTATE_END_OF_LIST()
2217 static const char *spapr_phb_root_bus_path(PCIHostState
*host_bridge
,
2220 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(host_bridge
);
2222 return sphb
->dtbusname
;
2225 static void spapr_phb_class_init(ObjectClass
*klass
, void *data
)
2227 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
2228 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2229 HotplugHandlerClass
*hp
= HOTPLUG_HANDLER_CLASS(klass
);
2231 hc
->root_bus_path
= spapr_phb_root_bus_path
;
2232 dc
->realize
= spapr_phb_realize
;
2233 dc
->unrealize
= spapr_phb_unrealize
;
2234 dc
->props
= spapr_phb_properties
;
2235 dc
->reset
= spapr_phb_reset
;
2236 dc
->vmsd
= &vmstate_spapr_pci
;
2237 /* Supported by TYPE_SPAPR_MACHINE */
2238 dc
->user_creatable
= true;
2239 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
2240 hp
->plug
= spapr_pci_plug
;
2241 hp
->unplug
= spapr_pci_unplug
;
2242 hp
->unplug_request
= spapr_pci_unplug_request
;
2245 static const TypeInfo spapr_phb_info
= {
2246 .name
= TYPE_SPAPR_PCI_HOST_BRIDGE
,
2247 .parent
= TYPE_PCI_HOST_BRIDGE
,
2248 .instance_size
= sizeof(SpaprPhbState
),
2249 .instance_finalize
= spapr_phb_finalizefn
,
2250 .class_init
= spapr_phb_class_init
,
2251 .interfaces
= (InterfaceInfo
[]) {
2252 { TYPE_HOTPLUG_HANDLER
},
2257 static void spapr_phb_pci_enumerate_bridge(PCIBus
*bus
, PCIDevice
*pdev
,
2260 unsigned int *bus_no
= opaque
;
2261 PCIBus
*sec_bus
= NULL
;
2263 if ((pci_default_read_config(pdev
, PCI_HEADER_TYPE
, 1) !=
2264 PCI_HEADER_TYPE_BRIDGE
)) {
2269 pci_default_write_config(pdev
, PCI_PRIMARY_BUS
, pci_dev_bus_num(pdev
), 1);
2270 pci_default_write_config(pdev
, PCI_SECONDARY_BUS
, *bus_no
, 1);
2271 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2273 sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
2278 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
2279 spapr_phb_pci_enumerate_bridge
, bus_no
);
2280 pci_default_write_config(pdev
, PCI_SUBORDINATE_BUS
, *bus_no
, 1);
2283 static void spapr_phb_pci_enumerate(SpaprPhbState
*phb
)
2285 PCIBus
*bus
= PCI_HOST_BRIDGE(phb
)->bus
;
2286 unsigned int bus_no
= 0;
2288 pci_for_each_device(bus
, pci_bus_num(bus
),
2289 spapr_phb_pci_enumerate_bridge
,
2294 int spapr_dt_phb(SpaprPhbState
*phb
, uint32_t intc_phandle
, void *fdt
,
2295 uint32_t nr_msis
, int *node_offset
)
2297 int bus_off
, i
, j
, ret
;
2298 uint32_t bus_range
[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2304 } QEMU_PACKED ranges
[] = {
2306 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2307 cpu_to_be64(phb
->io_win_addr
),
2308 cpu_to_be64(memory_region_size(&phb
->iospace
)),
2311 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET
),
2312 cpu_to_be64(phb
->mem_win_addr
),
2313 cpu_to_be64(phb
->mem_win_size
),
2316 cpu_to_be32(b_ss(3)), cpu_to_be64(phb
->mem64_win_pciaddr
),
2317 cpu_to_be64(phb
->mem64_win_addr
),
2318 cpu_to_be64(phb
->mem64_win_size
),
2321 const unsigned sizeof_ranges
=
2322 (phb
->mem64_win_size
? 3 : 2) * sizeof(ranges
[0]);
2323 uint64_t bus_reg
[] = { cpu_to_be64(phb
->buid
), 0 };
2324 uint32_t interrupt_map_mask
[] = {
2325 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2326 uint32_t interrupt_map
[PCI_SLOT_MAX
* PCI_NUM_PINS
][7];
2327 uint32_t ddw_applicable
[] = {
2328 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW
),
2329 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW
),
2330 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW
)
2332 uint32_t ddw_extensions
[] = {
2334 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW
)
2336 uint32_t associativity
[] = {cpu_to_be32(0x4),
2340 cpu_to_be32(phb
->numa_node
)};
2341 SpaprTceTable
*tcet
;
2345 /* Start populating the FDT */
2346 _FDT(bus_off
= fdt_add_subnode(fdt
, 0, phb
->dtbusname
));
2348 *node_offset
= bus_off
;
2351 /* Write PHB properties */
2352 _FDT(fdt_setprop_string(fdt
, bus_off
, "device_type", "pci"));
2353 _FDT(fdt_setprop_string(fdt
, bus_off
, "compatible", "IBM,Logical_PHB"));
2354 _FDT(fdt_setprop_cell(fdt
, bus_off
, "#interrupt-cells", 0x1));
2355 _FDT(fdt_setprop(fdt
, bus_off
, "used-by-rtas", NULL
, 0));
2356 _FDT(fdt_setprop(fdt
, bus_off
, "bus-range", &bus_range
, sizeof(bus_range
)));
2357 _FDT(fdt_setprop(fdt
, bus_off
, "ranges", &ranges
, sizeof_ranges
));
2358 _FDT(fdt_setprop(fdt
, bus_off
, "reg", &bus_reg
, sizeof(bus_reg
)));
2359 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pci-config-space-type", 0x1));
2360 _FDT(fdt_setprop_cell(fdt
, bus_off
, "ibm,pe-total-#msi", nr_msis
));
2362 /* Dynamic DMA window */
2363 if (phb
->ddw_enabled
) {
2364 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-applicable", &ddw_applicable
,
2365 sizeof(ddw_applicable
)));
2366 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,ddw-extensions",
2367 &ddw_extensions
, sizeof(ddw_extensions
)));
2370 /* Advertise NUMA via ibm,associativity */
2371 if (phb
->numa_node
!= -1) {
2372 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,associativity", associativity
,
2373 sizeof(associativity
)));
2376 /* Build the interrupt-map, this must matches what is done
2377 * in pci_swizzle_map_irq_fn
2379 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map-mask",
2380 &interrupt_map_mask
, sizeof(interrupt_map_mask
)));
2381 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
2382 for (j
= 0; j
< PCI_NUM_PINS
; j
++) {
2383 uint32_t *irqmap
= interrupt_map
[i
*PCI_NUM_PINS
+ j
];
2384 int lsi_num
= pci_swizzle(i
, j
);
2386 irqmap
[0] = cpu_to_be32(b_ddddd(i
)|b_fff(0));
2389 irqmap
[3] = cpu_to_be32(j
+1);
2390 irqmap
[4] = cpu_to_be32(intc_phandle
);
2391 spapr_dt_irq(&irqmap
[5], phb
->lsi_table
[lsi_num
].irq
, true);
2394 /* Write interrupt map */
2395 _FDT(fdt_setprop(fdt
, bus_off
, "interrupt-map", &interrupt_map
,
2396 sizeof(interrupt_map
)));
2398 tcet
= spapr_tce_find_by_liobn(phb
->dma_liobn
[0]);
2402 spapr_dma_dt(fdt
, bus_off
, "ibm,dma-window",
2403 tcet
->liobn
, tcet
->bus_offset
,
2404 tcet
->nb_table
<< tcet
->page_shift
);
2406 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, phb
->index
);
2408 uint32_t drc_index
= cpu_to_be32(spapr_drc_index(drc
));
2410 _FDT(fdt_setprop(fdt
, bus_off
, "ibm,my-drc-index", &drc_index
,
2411 sizeof(drc_index
)));
2414 /* Walk the bridges and program the bus numbers*/
2415 spapr_phb_pci_enumerate(phb
);
2416 _FDT(fdt_setprop_cell(fdt
, bus_off
, "qemu,phb-enumerated", 0x1));
2418 /* Walk the bridge and subordinate buses */
2419 ret
= spapr_dt_pci_bus(phb
, PCI_HOST_BRIDGE(phb
)->bus
, fdt
, bus_off
);
2424 spapr_phb_nvgpu_populate_dt(phb
, fdt
, bus_off
, &errp
);
2426 error_report_err(errp
);
2428 spapr_phb_nvgpu_ram_populate_dt(phb
, fdt
);
2433 void spapr_pci_rtas_init(void)
2435 spapr_rtas_register(RTAS_READ_PCI_CONFIG
, "read-pci-config",
2436 rtas_read_pci_config
);
2437 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG
, "write-pci-config",
2438 rtas_write_pci_config
);
2439 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG
, "ibm,read-pci-config",
2440 rtas_ibm_read_pci_config
);
2441 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG
, "ibm,write-pci-config",
2442 rtas_ibm_write_pci_config
);
2443 if (msi_nonbroken
) {
2444 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER
,
2445 "ibm,query-interrupt-source-number",
2446 rtas_ibm_query_interrupt_source_number
);
2447 spapr_rtas_register(RTAS_IBM_CHANGE_MSI
, "ibm,change-msi",
2448 rtas_ibm_change_msi
);
2451 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION
,
2452 "ibm,set-eeh-option",
2453 rtas_ibm_set_eeh_option
);
2454 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2
,
2455 "ibm,get-config-addr-info2",
2456 rtas_ibm_get_config_addr_info2
);
2457 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2
,
2458 "ibm,read-slot-reset-state2",
2459 rtas_ibm_read_slot_reset_state2
);
2460 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET
,
2461 "ibm,set-slot-reset",
2462 rtas_ibm_set_slot_reset
);
2463 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE
,
2465 rtas_ibm_configure_pe
);
2466 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL
,
2467 "ibm,slot-error-detail",
2468 rtas_ibm_slot_error_detail
);
2471 static void spapr_pci_register_types(void)
2473 type_register_static(&spapr_phb_info
);
2476 type_init(spapr_pci_register_types
)
2478 static int spapr_switch_one_vga(DeviceState
*dev
, void *opaque
)
2480 bool be
= *(bool *)opaque
;
2482 if (object_dynamic_cast(OBJECT(dev
), "VGA")
2483 || object_dynamic_cast(OBJECT(dev
), "secondary-vga")) {
2484 object_property_set_bool(OBJECT(dev
), be
, "big-endian-framebuffer",
2490 void spapr_pci_switch_vga(bool big_endian
)
2492 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
2493 SpaprPhbState
*sphb
;
2496 * For backward compatibility with existing guests, we switch
2497 * the endianness of the VGA controller when changing the guest
2500 QLIST_FOREACH(sphb
, &spapr
->phbs
, list
) {
2501 BusState
*bus
= &PCI_HOST_BRIDGE(sphb
)->bus
->qbus
;
2502 qbus_walk_children(bus
, spapr_switch_one_vga
, NULL
, NULL
, NULL
,