hw/ppc/pnv_xscom.c

   1 /*
   2  * QEMU PowerPC PowerNV XSCOM bus
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/module.h"
  23 #include "sysemu/hw_accel.h"
  24 #include "target/ppc/cpu.h"
  25 #include "hw/sysbus.h"
  26
  27 #include "hw/ppc/fdt.h"
  28 #include "hw/ppc/pnv.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30
  31 #include <libfdt.h>
  32
  33 /* PRD registers */
  34 #define PRD_P8_IPOLL_REG_MASK           0x01020013
  35 #define PRD_P8_IPOLL_REG_STATUS         0x01020014
  36 #define PRD_P9_IPOLL_REG_MASK           0x000F0033
  37 #define PRD_P9_IPOLL_REG_STATUS         0x000F0034
  38
  39 static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
  40 {
  41     /*
  42      * TODO: When the read/write comes from the monitor, NULL is
  43      * passed for the cpu, and no CPU completion is generated.
  44      */
  45     if (cs) {
  46         PowerPCCPU *cpu = POWERPC_CPU(cs);
  47         CPUPPCState *env = &cpu->env;
  48
  49         /*
  50          * TODO: Need a CPU helper to set HMER, also handle generation
  51          * of HMIs
  52          */
  53         cpu_synchronize_state(cs);
  54         env->spr[SPR_HMER] |= hmer_bits;
  55     }
  56 }
  57
  58 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
  59 {
  60     addr &= (PNV_XSCOM_SIZE - 1);
  61
  62     if (pnv_chip_is_power9(chip)) {
  63         return addr >> 3;
  64     } else {
  65         return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
  66     }
  67 }
  68
  69 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
  70 {
  71     switch (pcba) {
  72     case 0xf000f:
  73         return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
  74     case 0x18002:       /* ECID2 */
  75         return 0;
  76
  77     case 0x1010c00:     /* PIBAM FIR */
  78     case 0x1010c03:     /* PIBAM FIR MASK */
  79
  80         /* PRD registers */
  81     case PRD_P8_IPOLL_REG_MASK:
  82     case PRD_P8_IPOLL_REG_STATUS:
  83     case PRD_P9_IPOLL_REG_MASK:
  84     case PRD_P9_IPOLL_REG_STATUS:
  85
  86         /* P9 xscom reset */
  87     case 0x0090018:     /* Receive status reg */
  88     case 0x0090012:     /* log register */
  89     case 0x0090013:     /* error register */
  90
  91         /* P8 xscom reset */
  92     case 0x2020007:     /* ADU stuff, log register */
  93     case 0x2020009:     /* ADU stuff, error register */
  94     case 0x202000f:     /* ADU stuff, receive status register*/
  95         return 0;
  96     case 0x2013f00:     /* PBA stuff */
  97     case 0x2013f01:     /* PBA stuff */
  98     case 0x2013f02:     /* PBA stuff */
  99     case 0x2013f03:     /* PBA stuff */
 100     case 0x2013f04:     /* PBA stuff */
 101     case 0x2013f05:     /* PBA stuff */
 102     case 0x2013f06:     /* PBA stuff */
 103     case 0x2013f07:     /* PBA stuff */
 104         return 0;
 105     case 0x2013028:     /* CAPP stuff */
 106     case 0x201302a:     /* CAPP stuff */
 107     case 0x2013801:     /* CAPP stuff */
 108     case 0x2013802:     /* CAPP stuff */
 109         return 0;
 110     default:
 111         return -1;
 112     }
 113 }
 114
 115 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
 116 {
 117     /* We ignore writes to these */
 118     switch (pcba) {
 119     case 0xf000f:       /* chip id is RO */
 120     case 0x1010c00:     /* PIBAM FIR */
 121     case 0x1010c01:     /* PIBAM FIR */
 122     case 0x1010c02:     /* PIBAM FIR */
 123     case 0x1010c03:     /* PIBAM FIR MASK */
 124     case 0x1010c04:     /* PIBAM FIR MASK */
 125     case 0x1010c05:     /* PIBAM FIR MASK */
 126         /* P9 xscom reset */
 127     case 0x0090018:     /* Receive status reg */
 128     case 0x0090012:     /* log register */
 129     case 0x0090013:     /* error register */
 130
 131         /* P8 xscom reset */
 132     case 0x2020007:     /* ADU stuff, log register */
 133     case 0x2020009:     /* ADU stuff, error register */
 134     case 0x202000f:     /* ADU stuff, receive status register*/
 135
 136     case 0x2013028:     /* CAPP stuff */
 137     case 0x201302a:     /* CAPP stuff */
 138     case 0x2013801:     /* CAPP stuff */
 139     case 0x2013802:     /* CAPP stuff */
 140
 141         /* P8 PRD registers */
 142     case PRD_P8_IPOLL_REG_MASK:
 143     case PRD_P8_IPOLL_REG_STATUS:
 144     case PRD_P9_IPOLL_REG_MASK:
 145     case PRD_P9_IPOLL_REG_STATUS:
 146         return true;
 147     default:
 148         return false;
 149     }
 150 }
 151
 152 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
 153 {
 154     PnvChip *chip = opaque;
 155     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 156     uint64_t val = 0;
 157     MemTxResult result;
 158
 159     /* Handle some SCOMs here before dispatch */
 160     val = xscom_read_default(chip, pcba);
 161     if (val != -1) {
 162         goto complete;
 163     }
 164
 165     val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
 166                             MEMTXATTRS_UNSPECIFIED, &result);
 167     if (result != MEMTX_OK) {
 168         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
 169                       HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
 170         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 171         return 0;
 172     }
 173
 174 complete:
 175     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 176     return val;
 177 }
 178
 179 static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
 180                         unsigned width)
 181 {
 182     PnvChip *chip = opaque;
 183     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 184     MemTxResult result;
 185
 186     /* Handle some SCOMs here before dispatch */
 187     if (xscom_write_default(chip, pcba, val)) {
 188         goto complete;
 189     }
 190
 191     address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
 192                       MEMTXATTRS_UNSPECIFIED, &result);
 193     if (result != MEMTX_OK) {
 194         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
 195                       HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
 196                       addr, pcba, val);
 197         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 198         return;
 199     }
 200
 201 complete:
 202     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 203 }
 204
 205 const MemoryRegionOps pnv_xscom_ops = {
 206     .read = xscom_read,
 207     .write = xscom_write,
 208     .valid.min_access_size = 8,
 209     .valid.max_access_size = 8,
 210     .impl.min_access_size = 8,
 211     .impl.max_access_size = 8,
 212     .endianness = DEVICE_BIG_ENDIAN,
 213 };
 214
 215 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
 216 {
 217     SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
 218     char *name;
 219
 220     name = g_strdup_printf("xscom-%x", chip->chip_id);
 221     memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
 222                           chip, name, size);
 223     sysbus_init_mmio(sbd, &chip->xscom_mmio);
 224
 225     memory_region_init(&chip->xscom, OBJECT(chip), name, size);
 226     address_space_init(&chip->xscom_as, &chip->xscom, name);
 227     g_free(name);
 228 }
 229
 230 static const TypeInfo pnv_xscom_interface_info = {
 231     .name = TYPE_PNV_XSCOM_INTERFACE,
 232     .parent = TYPE_INTERFACE,
 233     .class_size = sizeof(PnvXScomInterfaceClass),
 234 };
 235
 236 static void pnv_xscom_register_types(void)
 237 {
 238     type_register_static(&pnv_xscom_interface_info);
 239 }
 240
 241 type_init(pnv_xscom_register_types)
 242
 243 typedef struct ForeachPopulateArgs {
 244     void *fdt;
 245     int xscom_offset;
 246 } ForeachPopulateArgs;
 247
 248 static int xscom_dt_child(Object *child, void *opaque)
 249 {
 250     if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
 251         ForeachPopulateArgs *args = opaque;
 252         PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
 253         PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
 254
 255         if (xc->dt_xscom) {
 256             _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
 257         }
 258     }
 259     return 0;
 260 }
 261
 262 static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
 263 static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
 264
 265 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
 266 {
 267     uint64_t reg[2];
 268     int xscom_offset;
 269     ForeachPopulateArgs args;
 270     char *name;
 271
 272     if (pnv_chip_is_power9(chip)) {
 273         reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
 274         reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
 275     } else {
 276         reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
 277         reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
 278     }
 279
 280     name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
 281     xscom_offset = fdt_add_subnode(fdt, root_offset, name);
 282     _FDT(xscom_offset);
 283     g_free(name);
 284     _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
 285     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
 286     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
 287     _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
 288
 289     if (pnv_chip_is_power9(chip)) {
 290         _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
 291                           sizeof(compat_p9))));
 292     } else {
 293         _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
 294                           sizeof(compat_p8))));
 295     }
 296
 297     _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
 298
 299     args.fdt = fdt;
 300     args.xscom_offset = xscom_offset;
 301
 302     object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
 303     return 0;
 304 }
 305
 306 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
 307 {
 308     memory_region_add_subregion(&chip->xscom, offset << 3, mr);
 309 }
 310
 311 void pnv_xscom_region_init(MemoryRegion *mr,
 312                            struct Object *owner,
 313                            const MemoryRegionOps *ops,
 314                            void *opaque,
 315                            const char *name,
 316                            uint64_t size)
 317 {
 318     memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
 319 }