1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QEMU LoongArch vector utilitites
5 * Copyright (c) 2023 Loongson Technology Corporation Limited
8 #ifndef LOONGARCH_VEC_H
9 #define LOONGARCH_VEC_H
12 #define B(x) B[(x) ^ 15]
13 #define H(x) H[(x) ^ 7]
14 #define W(x) W[(x) ^ 3]
15 #define D(x) D[(x) ^ 1]
16 #define UB(x) UB[(x) ^ 15]
17 #define UH(x) UH[(x) ^ 7]
18 #define UW(x) UW[(x) ^ 3]
19 #define UD(x) UD[(x) ^ 1]
31 #endif /* HOST_BIG_ENDIAN */
33 #define DO_ADD(a, b) (a + b)
34 #define DO_SUB(a, b) (a - b)
35 #define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1))
36 #define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1))
37 #define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a))
38 #define DO_VABS(a) ((a < 0) ? (-a) : (a))
39 #define DO_MIN(a, b) (a < b ? a : b)
40 #define DO_MAX(a, b) (a > b ? a : b)
41 #define DO_MUL(a, b) (a * b)
42 #define DO_MADD(a, b, c) (a + b * c)
43 #define DO_MSUB(a, b, c) (a - b * c)
45 #define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
46 #define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
47 #define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
48 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
49 #define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
50 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
52 #define DO_SIGNCOV(a, b) (a == 0 ? 0 : a < 0 ? -b : b)
54 #define R_SHIFT(a, b) (a >> b)
56 #define DO_CLO_B(N) (clz32(~N & 0xff) - 24)
57 #define DO_CLO_H(N) (clz32(~N & 0xffff) - 16)
58 #define DO_CLO_W(N) (clz32(~N))
59 #define DO_CLO_D(N) (clz64(~N))
60 #define DO_CLZ_B(N) (clz32(N) - 24)
61 #define DO_CLZ_H(N) (clz32(N) - 16)
62 #define DO_CLZ_W(N) (clz32(N))
63 #define DO_CLZ_D(N) (clz64(N))
65 #define DO_BITCLR(a, bit) (a & ~(1ull << bit))
66 #define DO_BITSET(a, bit) (a | 1ull << bit)
67 #define DO_BITREV(a, bit) (a ^ (1ull << bit))
69 #define VSEQ(a, b) (a == b ? -1 : 0)
70 #define VSLE(a, b) (a <= b ? -1 : 0)
71 #define VSLT(a, b) (a < b ? -1 : 0)
73 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
75 #endif /* LOONGARCH_VEC_H */