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x86: move acpi_dev from pc/microvm
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob0e0535d2e30cf3d492e0dcab17e3d73e8c6e9d55
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
55
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
64
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
68
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
72
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
75
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 */
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
85
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
92 #endif
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 uint8_t s4_val;
99 AcpiFadtData fadt;
100 uint16_t cpu_hp_io_base;
101 uint16_t pcihp_io_base;
102 uint16_t pcihp_io_len;
103 } AcpiPmInfo;
104
105 typedef struct AcpiMiscInfo {
106 bool is_piix4;
107 bool has_hpet;
108 TPMVersion tpm_version;
109 const unsigned char *dsdt_code;
110 unsigned dsdt_size;
111 uint16_t pvpanic_port;
112 uint16_t applesmc_io_base;
113 } AcpiMiscInfo;
114
115 typedef struct AcpiBuildPciBusHotplugState {
116 GArray *device_table;
117 GArray *notify_table;
118 struct AcpiBuildPciBusHotplugState *parent;
119 bool pcihp_bridge_en;
120 } AcpiBuildPciBusHotplugState;
121
122 typedef struct FwCfgTPMConfig {
123 uint32_t tpmppi_address;
124 uint8_t tpm_version;
125 uint8_t tpmppi_version;
126 } QEMU_PACKED FwCfgTPMConfig;
127
128 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
129
130 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
131 .space_id = AML_AS_SYSTEM_IO,
132 .address = NVDIMM_ACPI_IO_BASE,
133 .bit_width = NVDIMM_ACPI_IO_LEN << 3
134 };
135
136 static void init_common_fadt_data(MachineState *ms, Object *o,
137 AcpiFadtData *data)
138 {
139 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
140 AmlAddressSpace as = AML_AS_SYSTEM_IO;
141 AcpiFadtData fadt = {
142 .rev = 3,
143 .flags =
144 (1 << ACPI_FADT_F_WBINVD) |
145 (1 << ACPI_FADT_F_PROC_C1) |
146 (1 << ACPI_FADT_F_SLP_BUTTON) |
147 (1 << ACPI_FADT_F_RTC_S4) |
148 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
149 /* APIC destination mode ("Flat Logical") has an upper limit of 8
150 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
151 * used
152 */
153 ((ms->smp.max_cpus > 8) ?
154 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
155 .int_model = 1 /* Multiple APIC */,
156 .rtc_century = RTC_CENTURY,
157 .plvl2_lat = 0xfff /* C2 state not supported */,
158 .plvl3_lat = 0xfff /* C3 state not supported */,
159 .smi_cmd = ACPI_PORT_SMI_CMD,
160 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
161 .acpi_enable_cmd =
162 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL),
163 .acpi_disable_cmd =
164 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL),
165 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
166 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
167 .address = io + 0x04 },
168 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
169 .gpe0_blk = { .space_id = as, .bit_width =
170 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
171 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
172 },
173 };
174 *data = fadt;
175 }
176
177 static Object *object_resolve_type_unambiguous(const char *typename)
178 {
179 bool ambig;
180 Object *o = object_resolve_path_type("", typename, &ambig);
181
182 if (ambig || !o) {
183 return NULL;
184 }
185 return o;
186 }
187
188 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
189 {
190 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
191 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
192 Object *obj = piix ? piix : lpc;
193 QObject *o;
194 pm->cpu_hp_io_base = 0;
195 pm->pcihp_io_base = 0;
196 pm->pcihp_io_len = 0;
197
198 assert(obj);
199 init_common_fadt_data(machine, obj, &pm->fadt);
200 if (piix) {
201 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
202 pm->fadt.rev = 1;
203 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
204 pm->pcihp_io_base =
205 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
206 pm->pcihp_io_len =
207 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
208 }
209 if (lpc) {
210 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
211 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
212 pm->fadt.reset_reg = r;
213 pm->fadt.reset_val = 0xf;
214 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
215 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
216 }
217
218 /* The above need not be conditional on machine type because the reset port
219 * happens to be the same on PIIX (pc) and ICH9 (q35). */
220 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
221
222 /* Fill in optional s3/s4 related properties */
223 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
224 if (o) {
225 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
226 } else {
227 pm->s3_disabled = false;
228 }
229 qobject_unref(o);
230 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
231 if (o) {
232 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
233 } else {
234 pm->s4_disabled = false;
235 }
236 qobject_unref(o);
237 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
238 if (o) {
239 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
240 } else {
241 pm->s4_val = false;
242 }
243 qobject_unref(o);
244
245 pm->pcihp_bridge_en =
246 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
247 NULL);
248 }
249
250 static void acpi_get_misc_info(AcpiMiscInfo *info)
251 {
252 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
253 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
254 assert(!!piix != !!lpc);
255
256 if (piix) {
257 info->is_piix4 = true;
258 }
259 if (lpc) {
260 info->is_piix4 = false;
261 }
262
263 info->has_hpet = hpet_find();
264 info->tpm_version = tpm_get_version(tpm_find());
265 info->pvpanic_port = pvpanic_port();
266 info->applesmc_io_base = applesmc_port();
267 }
268
269 /*
270 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
271 * On i386 arch we only have two pci hosts, so we can look only for them.
272 */
273 static Object *acpi_get_i386_pci_host(void)
274 {
275 PCIHostState *host;
276
277 host = OBJECT_CHECK(PCIHostState,
278 object_resolve_path("/machine/i440fx", NULL),
279 TYPE_PCI_HOST_BRIDGE);
280 if (!host) {
281 host = OBJECT_CHECK(PCIHostState,
282 object_resolve_path("/machine/q35", NULL),
283 TYPE_PCI_HOST_BRIDGE);
284 }
285
286 return OBJECT(host);
287 }
288
289 static void acpi_get_pci_holes(Range *hole, Range *hole64)
290 {
291 Object *pci_host;
292
293 pci_host = acpi_get_i386_pci_host();
294 g_assert(pci_host);
295
296 range_set_bounds1(hole,
297 object_property_get_uint(pci_host,
298 PCI_HOST_PROP_PCI_HOLE_START,
299 NULL),
300 object_property_get_uint(pci_host,
301 PCI_HOST_PROP_PCI_HOLE_END,
302 NULL));
303 range_set_bounds1(hole64,
304 object_property_get_uint(pci_host,
305 PCI_HOST_PROP_PCI_HOLE64_START,
306 NULL),
307 object_property_get_uint(pci_host,
308 PCI_HOST_PROP_PCI_HOLE64_END,
309 NULL));
310 }
311
312 static void acpi_align_size(GArray *blob, unsigned align)
313 {
314 /* Align size to multiple of given size. This reduces the chance
315 * we need to change size in the future (breaking cross version migration).
316 */
317 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
318 }
319
320 /* FACS */
321 static void
322 build_facs(GArray *table_data)
323 {
324 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
325 memcpy(&facs->signature, "FACS", 4);
326 facs->length = cpu_to_le32(sizeof(*facs));
327 }
328
329 static void build_append_pcihp_notify_entry(Aml *method, int slot)
330 {
331 Aml *if_ctx;
332 int32_t devfn = PCI_DEVFN(slot, 0);
333
334 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
335 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
336 aml_append(method, if_ctx);
337 }
338
339 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
340 bool pcihp_bridge_en)
341 {
342 Aml *dev, *notify_method = NULL, *method;
343 QObject *bsel;
344 PCIBus *sec;
345 int i;
346
347 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
348 if (bsel) {
349 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
350
351 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
352 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
353 }
354
355 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
356 DeviceClass *dc;
357 PCIDeviceClass *pc;
358 PCIDevice *pdev = bus->devices[i];
359 int slot = PCI_SLOT(i);
360 bool hotplug_enabled_dev;
361 bool bridge_in_acpi;
362
363 if (!pdev) {
364 if (bsel) { /* add hotplug slots for non present devices */
365 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
366 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
367 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
368 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
369 aml_append(method,
370 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
371 );
372 aml_append(dev, method);
373 aml_append(parent_scope, dev);
374
375 build_append_pcihp_notify_entry(notify_method, slot);
376 }
377 continue;
378 }
379
380 pc = PCI_DEVICE_GET_CLASS(pdev);
381 dc = DEVICE_GET_CLASS(pdev);
382
383 /* When hotplug for bridges is enabled, bridges are
384 * described in ACPI separately (see build_pci_bus_end).
385 * In this case they aren't themselves hot-pluggable.
386 * Hotplugged bridges *are* hot-pluggable.
387 */
388 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
389 !DEVICE(pdev)->hotplugged;
390
391 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
392
393 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
394 continue;
395 }
396
397 /* start to compose PCI slot descriptor */
398 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
399 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
400
401 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
402 /* add VGA specific AML methods */
403 int s3d;
404
405 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
406 s3d = 3;
407 } else {
408 s3d = 0;
409 }
410
411 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
412 aml_append(method, aml_return(aml_int(0)));
413 aml_append(dev, method);
414
415 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
416 aml_append(method, aml_return(aml_int(0)));
417 aml_append(dev, method);
418
419 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
420 aml_append(method, aml_return(aml_int(s3d)));
421 aml_append(dev, method);
422 } else if (hotplug_enabled_dev) {
423 /* add _SUN/_EJ0 to make slot hotpluggable */
424 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
425
426 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
427 aml_append(method,
428 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
429 );
430 aml_append(dev, method);
431
432 if (bsel) {
433 build_append_pcihp_notify_entry(notify_method, slot);
434 }
435 } else if (bridge_in_acpi) {
436 /*
437 * device is coldplugged bridge,
438 * add child device descriptions into its scope
439 */
440 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
441
442 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
443 }
444 /* slot descriptor has been composed, add it into parent context */
445 aml_append(parent_scope, dev);
446 }
447
448 if (bsel) {
449 aml_append(parent_scope, notify_method);
450 }
451
452 /* Append PCNT method to notify about events on local and child buses.
453 * Add unconditionally for root since DSDT expects it.
454 */
455 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
456
457 /* If bus supports hotplug select it and notify about local events */
458 if (bsel) {
459 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
460
461 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
462 aml_append(method,
463 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
464 );
465 aml_append(method,
466 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
467 );
468 }
469
470 /* Notify about child bus events in any case */
471 if (pcihp_bridge_en) {
472 QLIST_FOREACH(sec, &bus->child, sibling) {
473 int32_t devfn = sec->parent_dev->devfn;
474
475 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
476 continue;
477 }
478
479 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
480 }
481 }
482 aml_append(parent_scope, method);
483 qobject_unref(bsel);
484 }
485
486 /**
487 * build_prt_entry:
488 * @link_name: link name for PCI route entry
489 *
490 * build AML package containing a PCI route entry for @link_name
491 */
492 static Aml *build_prt_entry(const char *link_name)
493 {
494 Aml *a_zero = aml_int(0);
495 Aml *pkg = aml_package(4);
496 aml_append(pkg, a_zero);
497 aml_append(pkg, a_zero);
498 aml_append(pkg, aml_name("%s", link_name));
499 aml_append(pkg, a_zero);
500 return pkg;
501 }
502
503 /*
504 * initialize_route - Initialize the interrupt routing rule
505 * through a specific LINK:
506 * if (lnk_idx == idx)
507 * route using link 'link_name'
508 */
509 static Aml *initialize_route(Aml *route, const char *link_name,
510 Aml *lnk_idx, int idx)
511 {
512 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
513 Aml *pkg = build_prt_entry(link_name);
514
515 aml_append(if_ctx, aml_store(pkg, route));
516
517 return if_ctx;
518 }
519
520 /*
521 * build_prt - Define interrupt rounting rules
522 *
523 * Returns an array of 128 routes, one for each device,
524 * based on device location.
525 * The main goal is to equaly distribute the interrupts
526 * over the 4 existing ACPI links (works only for i440fx).
527 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
528 *
529 */
530 static Aml *build_prt(bool is_pci0_prt)
531 {
532 Aml *method, *while_ctx, *pin, *res;
533
534 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
535 res = aml_local(0);
536 pin = aml_local(1);
537 aml_append(method, aml_store(aml_package(128), res));
538 aml_append(method, aml_store(aml_int(0), pin));
539
540 /* while (pin < 128) */
541 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
542 {
543 Aml *slot = aml_local(2);
544 Aml *lnk_idx = aml_local(3);
545 Aml *route = aml_local(4);
546
547 /* slot = pin >> 2 */
548 aml_append(while_ctx,
549 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
550 /* lnk_idx = (slot + pin) & 3 */
551 aml_append(while_ctx,
552 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
553 lnk_idx));
554
555 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
556 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
557 if (is_pci0_prt) {
558 Aml *if_device_1, *if_pin_4, *else_pin_4;
559
560 /* device 1 is the power-management device, needs SCI */
561 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
562 {
563 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
564 {
565 aml_append(if_pin_4,
566 aml_store(build_prt_entry("LNKS"), route));
567 }
568 aml_append(if_device_1, if_pin_4);
569 else_pin_4 = aml_else();
570 {
571 aml_append(else_pin_4,
572 aml_store(build_prt_entry("LNKA"), route));
573 }
574 aml_append(if_device_1, else_pin_4);
575 }
576 aml_append(while_ctx, if_device_1);
577 } else {
578 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
579 }
580 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
581 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
582
583 /* route[0] = 0x[slot]FFFF */
584 aml_append(while_ctx,
585 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
586 NULL),
587 aml_index(route, aml_int(0))));
588 /* route[1] = pin & 3 */
589 aml_append(while_ctx,
590 aml_store(aml_and(pin, aml_int(3), NULL),
591 aml_index(route, aml_int(1))));
592 /* res[pin] = route */
593 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
594 /* pin++ */
595 aml_append(while_ctx, aml_increment(pin));
596 }
597 aml_append(method, while_ctx);
598 /* return res*/
599 aml_append(method, aml_return(res));
600
601 return method;
602 }
603
604 typedef struct CrsRangeEntry {
605 uint64_t base;
606 uint64_t limit;
607 } CrsRangeEntry;
608
609 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
610 {
611 CrsRangeEntry *entry;
612
613 entry = g_malloc(sizeof(*entry));
614 entry->base = base;
615 entry->limit = limit;
616
617 g_ptr_array_add(ranges, entry);
618 }
619
620 static void crs_range_free(gpointer data)
621 {
622 CrsRangeEntry *entry = (CrsRangeEntry *)data;
623 g_free(entry);
624 }
625
626 typedef struct CrsRangeSet {
627 GPtrArray *io_ranges;
628 GPtrArray *mem_ranges;
629 GPtrArray *mem_64bit_ranges;
630 } CrsRangeSet;
631
632 static void crs_range_set_init(CrsRangeSet *range_set)
633 {
634 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
635 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
636 range_set->mem_64bit_ranges =
637 g_ptr_array_new_with_free_func(crs_range_free);
638 }
639
640 static void crs_range_set_free(CrsRangeSet *range_set)
641 {
642 g_ptr_array_free(range_set->io_ranges, true);
643 g_ptr_array_free(range_set->mem_ranges, true);
644 g_ptr_array_free(range_set->mem_64bit_ranges, true);
645 }
646
647 static gint crs_range_compare(gconstpointer a, gconstpointer b)
648 {
649 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
650 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
651
652 if (entry_a->base < entry_b->base) {
653 return -1;
654 } else if (entry_a->base > entry_b->base) {
655 return 1;
656 } else {
657 return 0;
658 }
659 }
660
661 /*
662 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
663 * interval, computes the 'free' ranges from the same interval.
664 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
665 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
666 */
667 static void crs_replace_with_free_ranges(GPtrArray *ranges,
668 uint64_t start, uint64_t end)
669 {
670 GPtrArray *free_ranges = g_ptr_array_new();
671 uint64_t free_base = start;
672 int i;
673
674 g_ptr_array_sort(ranges, crs_range_compare);
675 for (i = 0; i < ranges->len; i++) {
676 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
677
678 if (free_base < used->base) {
679 crs_range_insert(free_ranges, free_base, used->base - 1);
680 }
681
682 free_base = used->limit + 1;
683 }
684
685 if (free_base < end) {
686 crs_range_insert(free_ranges, free_base, end);
687 }
688
689 g_ptr_array_set_size(ranges, 0);
690 for (i = 0; i < free_ranges->len; i++) {
691 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
692 }
693
694 g_ptr_array_free(free_ranges, true);
695 }
696
697 /*
698 * crs_range_merge - merges adjacent ranges in the given array.
699 * Array elements are deleted and replaced with the merged ranges.
700 */
701 static void crs_range_merge(GPtrArray *range)
702 {
703 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
704 CrsRangeEntry *entry;
705 uint64_t range_base, range_limit;
706 int i;
707
708 if (!range->len) {
709 return;
710 }
711
712 g_ptr_array_sort(range, crs_range_compare);
713
714 entry = g_ptr_array_index(range, 0);
715 range_base = entry->base;
716 range_limit = entry->limit;
717 for (i = 1; i < range->len; i++) {
718 entry = g_ptr_array_index(range, i);
719 if (entry->base - 1 == range_limit) {
720 range_limit = entry->limit;
721 } else {
722 crs_range_insert(tmp, range_base, range_limit);
723 range_base = entry->base;
724 range_limit = entry->limit;
725 }
726 }
727 crs_range_insert(tmp, range_base, range_limit);
728
729 g_ptr_array_set_size(range, 0);
730 for (i = 0; i < tmp->len; i++) {
731 entry = g_ptr_array_index(tmp, i);
732 crs_range_insert(range, entry->base, entry->limit);
733 }
734 g_ptr_array_free(tmp, true);
735 }
736
737 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
738 {
739 Aml *crs = aml_resource_template();
740 CrsRangeSet temp_range_set;
741 CrsRangeEntry *entry;
742 uint8_t max_bus = pci_bus_num(host->bus);
743 uint8_t type;
744 int devfn;
745 int i;
746
747 crs_range_set_init(&temp_range_set);
748 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
749 uint64_t range_base, range_limit;
750 PCIDevice *dev = host->bus->devices[devfn];
751
752 if (!dev) {
753 continue;
754 }
755
756 for (i = 0; i < PCI_NUM_REGIONS; i++) {
757 PCIIORegion *r = &dev->io_regions[i];
758
759 range_base = r->addr;
760 range_limit = r->addr + r->size - 1;
761
762 /*
763 * Work-around for old bioses
764 * that do not support multiple root buses
765 */
766 if (!range_base || range_base > range_limit) {
767 continue;
768 }
769
770 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
771 crs_range_insert(temp_range_set.io_ranges,
772 range_base, range_limit);
773 } else { /* "memory" */
774 crs_range_insert(temp_range_set.mem_ranges,
775 range_base, range_limit);
776 }
777 }
778
779 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
780 if (type == PCI_HEADER_TYPE_BRIDGE) {
781 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
782 if (subordinate > max_bus) {
783 max_bus = subordinate;
784 }
785
786 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
787 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
788
789 /*
790 * Work-around for old bioses
791 * that do not support multiple root buses
792 */
793 if (range_base && range_base <= range_limit) {
794 crs_range_insert(temp_range_set.io_ranges,
795 range_base, range_limit);
796 }
797
798 range_base =
799 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
800 range_limit =
801 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
802
803 /*
804 * Work-around for old bioses
805 * that do not support multiple root buses
806 */
807 if (range_base && range_base <= range_limit) {
808 uint64_t length = range_limit - range_base + 1;
809 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
810 crs_range_insert(temp_range_set.mem_ranges,
811 range_base, range_limit);
812 } else {
813 crs_range_insert(temp_range_set.mem_64bit_ranges,
814 range_base, range_limit);
815 }
816 }
817
818 range_base =
819 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
820 range_limit =
821 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
822
823 /*
824 * Work-around for old bioses
825 * that do not support multiple root buses
826 */
827 if (range_base && range_base <= range_limit) {
828 uint64_t length = range_limit - range_base + 1;
829 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
830 crs_range_insert(temp_range_set.mem_ranges,
831 range_base, range_limit);
832 } else {
833 crs_range_insert(temp_range_set.mem_64bit_ranges,
834 range_base, range_limit);
835 }
836 }
837 }
838 }
839
840 crs_range_merge(temp_range_set.io_ranges);
841 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
842 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
843 aml_append(crs,
844 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
845 AML_POS_DECODE, AML_ENTIRE_RANGE,
846 0, entry->base, entry->limit, 0,
847 entry->limit - entry->base + 1));
848 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
849 }
850
851 crs_range_merge(temp_range_set.mem_ranges);
852 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
853 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
854 aml_append(crs,
855 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
856 AML_MAX_FIXED, AML_NON_CACHEABLE,
857 AML_READ_WRITE,
858 0, entry->base, entry->limit, 0,
859 entry->limit - entry->base + 1));
860 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
861 }
862
863 crs_range_merge(temp_range_set.mem_64bit_ranges);
864 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
865 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
866 aml_append(crs,
867 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
868 AML_MAX_FIXED, AML_NON_CACHEABLE,
869 AML_READ_WRITE,
870 0, entry->base, entry->limit, 0,
871 entry->limit - entry->base + 1));
872 crs_range_insert(range_set->mem_64bit_ranges,
873 entry->base, entry->limit);
874 }
875
876 crs_range_set_free(&temp_range_set);
877
878 aml_append(crs,
879 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
880 0,
881 pci_bus_num(host->bus),
882 max_bus,
883 0,
884 max_bus - pci_bus_num(host->bus) + 1));
885
886 return crs;
887 }
888
889 static void build_hpet_aml(Aml *table)
890 {
891 Aml *crs;
892 Aml *field;
893 Aml *method;
894 Aml *if_ctx;
895 Aml *scope = aml_scope("_SB");
896 Aml *dev = aml_device("HPET");
897 Aml *zero = aml_int(0);
898 Aml *id = aml_local(0);
899 Aml *period = aml_local(1);
900
901 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
902 aml_append(dev, aml_name_decl("_UID", zero));
903
904 aml_append(dev,
905 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
906 HPET_LEN));
907 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
908 aml_append(field, aml_named_field("VEND", 32));
909 aml_append(field, aml_named_field("PRD", 32));
910 aml_append(dev, field);
911
912 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
913 aml_append(method, aml_store(aml_name("VEND"), id));
914 aml_append(method, aml_store(aml_name("PRD"), period));
915 aml_append(method, aml_shiftright(id, aml_int(16), id));
916 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
917 aml_equal(id, aml_int(0xffff))));
918 {
919 aml_append(if_ctx, aml_return(zero));
920 }
921 aml_append(method, if_ctx);
922
923 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
924 aml_lgreater(period, aml_int(100000000))));
925 {
926 aml_append(if_ctx, aml_return(zero));
927 }
928 aml_append(method, if_ctx);
929
930 aml_append(method, aml_return(aml_int(0x0F)));
931 aml_append(dev, method);
932
933 crs = aml_resource_template();
934 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
935 aml_append(dev, aml_name_decl("_CRS", crs));
936
937 aml_append(scope, dev);
938 aml_append(table, scope);
939 }
940
941 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
942 {
943 Aml *dev;
944 Aml *method;
945 Aml *crs;
946
947 dev = aml_device("VMBS");
948 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
949 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
950 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
951 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
952
953 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
954 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
955 aml_name("STA")));
956 aml_append(dev, method);
957
958 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
959 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
960 aml_name("STA")));
961 aml_append(dev, method);
962
963 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
964 aml_append(method, aml_return(aml_name("STA")));
965 aml_append(dev, method);
966
967 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
968
969 crs = aml_resource_template();
970 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
971 aml_append(dev, aml_name_decl("_CRS", crs));
972
973 return dev;
974 }
975
976 static void build_isa_devices_aml(Aml *table)
977 {
978 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
979 bool ambiguous;
980 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
981 Aml *scope;
982
983 assert(obj && !ambiguous);
984
985 scope = aml_scope("_SB.PCI0.ISA");
986 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
987 isa_build_aml(ISA_BUS(obj), scope);
988
989 if (vmbus_bridge) {
990 aml_append(scope, build_vmbus_device_aml(vmbus_bridge));
991 }
992
993 aml_append(table, scope);
994 }
995
996 static void build_dbg_aml(Aml *table)
997 {
998 Aml *field;
999 Aml *method;
1000 Aml *while_ctx;
1001 Aml *scope = aml_scope("\\");
1002 Aml *buf = aml_local(0);
1003 Aml *len = aml_local(1);
1004 Aml *idx = aml_local(2);
1005
1006 aml_append(scope,
1007 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1008 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1009 aml_append(field, aml_named_field("DBGB", 8));
1010 aml_append(scope, field);
1011
1012 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1013
1014 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1015 aml_append(method, aml_to_buffer(buf, buf));
1016 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1017 aml_append(method, aml_store(aml_int(0), idx));
1018
1019 while_ctx = aml_while(aml_lless(idx, len));
1020 aml_append(while_ctx,
1021 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1022 aml_append(while_ctx, aml_increment(idx));
1023 aml_append(method, while_ctx);
1024
1025 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1026 aml_append(scope, method);
1027
1028 aml_append(table, scope);
1029 }
1030
1031 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1032 {
1033 Aml *dev;
1034 Aml *crs;
1035 Aml *method;
1036 uint32_t irqs[] = {5, 10, 11};
1037
1038 dev = aml_device("%s", name);
1039 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1040 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1041
1042 crs = aml_resource_template();
1043 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1044 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1045 aml_append(dev, aml_name_decl("_PRS", crs));
1046
1047 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1048 aml_append(method, aml_return(aml_call1("IQST", reg)));
1049 aml_append(dev, method);
1050
1051 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1052 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1053 aml_append(dev, method);
1054
1055 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1056 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1057 aml_append(dev, method);
1058
1059 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1060 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1061 aml_append(method, aml_store(aml_name("PRRI"), reg));
1062 aml_append(dev, method);
1063
1064 return dev;
1065 }
1066
1067 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1068 {
1069 Aml *dev;
1070 Aml *crs;
1071 Aml *method;
1072 uint32_t irqs;
1073
1074 dev = aml_device("%s", name);
1075 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1076 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1077
1078 crs = aml_resource_template();
1079 irqs = gsi;
1080 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1081 AML_SHARED, &irqs, 1));
1082 aml_append(dev, aml_name_decl("_PRS", crs));
1083
1084 aml_append(dev, aml_name_decl("_CRS", crs));
1085
1086 /*
1087 * _DIS can be no-op because the interrupt cannot be disabled.
1088 */
1089 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1090 aml_append(dev, method);
1091
1092 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1093 aml_append(dev, method);
1094
1095 return dev;
1096 }
1097
1098 /* _CRS method - get current settings */
1099 static Aml *build_iqcr_method(bool is_piix4)
1100 {
1101 Aml *if_ctx;
1102 uint32_t irqs;
1103 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1104 Aml *crs = aml_resource_template();
1105
1106 irqs = 0;
1107 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1108 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1109 aml_append(method, aml_name_decl("PRR0", crs));
1110
1111 aml_append(method,
1112 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1113
1114 if (is_piix4) {
1115 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1116 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1117 aml_append(method, if_ctx);
1118 } else {
1119 aml_append(method,
1120 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1121 aml_name("PRRI")));
1122 }
1123
1124 aml_append(method, aml_return(aml_name("PRR0")));
1125 return method;
1126 }
1127
1128 /* _STA method - get status */
1129 static Aml *build_irq_status_method(void)
1130 {
1131 Aml *if_ctx;
1132 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1133
1134 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1135 aml_append(if_ctx, aml_return(aml_int(0x09)));
1136 aml_append(method, if_ctx);
1137 aml_append(method, aml_return(aml_int(0x0B)));
1138 return method;
1139 }
1140
1141 static void build_piix4_pci0_int(Aml *table)
1142 {
1143 Aml *dev;
1144 Aml *crs;
1145 Aml *field;
1146 Aml *method;
1147 uint32_t irqs;
1148 Aml *sb_scope = aml_scope("_SB");
1149 Aml *pci0_scope = aml_scope("PCI0");
1150
1151 aml_append(pci0_scope, build_prt(true));
1152 aml_append(sb_scope, pci0_scope);
1153
1154 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1155 aml_append(field, aml_named_field("PRQ0", 8));
1156 aml_append(field, aml_named_field("PRQ1", 8));
1157 aml_append(field, aml_named_field("PRQ2", 8));
1158 aml_append(field, aml_named_field("PRQ3", 8));
1159 aml_append(sb_scope, field);
1160
1161 aml_append(sb_scope, build_irq_status_method());
1162 aml_append(sb_scope, build_iqcr_method(true));
1163
1164 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1165 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1166 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1167 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1168
1169 dev = aml_device("LNKS");
1170 {
1171 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1172 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1173
1174 crs = aml_resource_template();
1175 irqs = 9;
1176 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1177 AML_ACTIVE_HIGH, AML_SHARED,
1178 &irqs, 1));
1179 aml_append(dev, aml_name_decl("_PRS", crs));
1180
1181 /* The SCI cannot be disabled and is always attached to GSI 9,
1182 * so these are no-ops. We only need this link to override the
1183 * polarity to active high and match the content of the MADT.
1184 */
1185 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1186 aml_append(method, aml_return(aml_int(0x0b)));
1187 aml_append(dev, method);
1188
1189 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1190 aml_append(dev, method);
1191
1192 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1193 aml_append(method, aml_return(aml_name("_PRS")));
1194 aml_append(dev, method);
1195
1196 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1197 aml_append(dev, method);
1198 }
1199 aml_append(sb_scope, dev);
1200
1201 aml_append(table, sb_scope);
1202 }
1203
1204 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1205 {
1206 int i;
1207 int head;
1208 Aml *pkg;
1209 char base = name[3] < 'E' ? 'A' : 'E';
1210 char *s = g_strdup(name);
1211 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1212
1213 assert(strlen(s) == 4);
1214
1215 head = name[3] - base;
1216 for (i = 0; i < 4; i++) {
1217 if (head + i > 3) {
1218 head = i * -1;
1219 }
1220 s[3] = base + head + i;
1221 pkg = aml_package(4);
1222 aml_append(pkg, a_nr);
1223 aml_append(pkg, aml_int(i));
1224 aml_append(pkg, aml_name("%s", s));
1225 aml_append(pkg, aml_int(0));
1226 aml_append(ctx, pkg);
1227 }
1228 g_free(s);
1229 }
1230
1231 static Aml *build_q35_routing_table(const char *str)
1232 {
1233 int i;
1234 Aml *pkg;
1235 char *name = g_strdup_printf("%s ", str);
1236
1237 pkg = aml_package(128);
1238 for (i = 0; i < 0x18; i++) {
1239 name[3] = 'E' + (i & 0x3);
1240 append_q35_prt_entry(pkg, i, name);
1241 }
1242
1243 name[3] = 'E';
1244 append_q35_prt_entry(pkg, 0x18, name);
1245
1246 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1247 for (i = 0x0019; i < 0x1e; i++) {
1248 name[3] = 'A';
1249 append_q35_prt_entry(pkg, i, name);
1250 }
1251
1252 /* PCIe->PCI bridge. use PIRQ[E-H] */
1253 name[3] = 'E';
1254 append_q35_prt_entry(pkg, 0x1e, name);
1255 name[3] = 'A';
1256 append_q35_prt_entry(pkg, 0x1f, name);
1257
1258 g_free(name);
1259 return pkg;
1260 }
1261
1262 static void build_q35_pci0_int(Aml *table)
1263 {
1264 Aml *field;
1265 Aml *method;
1266 Aml *sb_scope = aml_scope("_SB");
1267 Aml *pci0_scope = aml_scope("PCI0");
1268
1269 /* Zero => PIC mode, One => APIC Mode */
1270 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1271 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1272 {
1273 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1274 }
1275 aml_append(table, method);
1276
1277 aml_append(pci0_scope,
1278 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1279 aml_append(pci0_scope,
1280 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1281
1282 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1283 {
1284 Aml *if_ctx;
1285 Aml *else_ctx;
1286
1287 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1288 section 6.2.8.1 */
1289 /* Note: we provide the same info as the PCI routing
1290 table of the Bochs BIOS */
1291 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1292 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1293 aml_append(method, if_ctx);
1294 else_ctx = aml_else();
1295 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1296 aml_append(method, else_ctx);
1297 }
1298 aml_append(pci0_scope, method);
1299 aml_append(sb_scope, pci0_scope);
1300
1301 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1302 aml_append(field, aml_named_field("PRQA", 8));
1303 aml_append(field, aml_named_field("PRQB", 8));
1304 aml_append(field, aml_named_field("PRQC", 8));
1305 aml_append(field, aml_named_field("PRQD", 8));
1306 aml_append(field, aml_reserved_field(0x20));
1307 aml_append(field, aml_named_field("PRQE", 8));
1308 aml_append(field, aml_named_field("PRQF", 8));
1309 aml_append(field, aml_named_field("PRQG", 8));
1310 aml_append(field, aml_named_field("PRQH", 8));
1311 aml_append(sb_scope, field);
1312
1313 aml_append(sb_scope, build_irq_status_method());
1314 aml_append(sb_scope, build_iqcr_method(false));
1315
1316 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1317 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1318 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1319 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1320 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1321 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1322 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1323 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1324
1325 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1326 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1327 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1328 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1329 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1330 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1331 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1332 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1333
1334 aml_append(table, sb_scope);
1335 }
1336
1337 static void build_q35_isa_bridge(Aml *table)
1338 {
1339 Aml *dev;
1340 Aml *scope;
1341
1342 scope = aml_scope("_SB.PCI0");
1343 dev = aml_device("ISA");
1344 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1345
1346 /* ICH9 PCI to ISA irq remapping */
1347 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1348 aml_int(0x60), 0x0C));
1349
1350 aml_append(scope, dev);
1351 aml_append(table, scope);
1352 }
1353
1354 static void build_piix4_isa_bridge(Aml *table)
1355 {
1356 Aml *dev;
1357 Aml *scope;
1358
1359 scope = aml_scope("_SB.PCI0");
1360 dev = aml_device("ISA");
1361 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1362
1363 /* PIIX PCI to ISA irq remapping */
1364 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1365 aml_int(0x60), 0x04));
1366
1367 aml_append(scope, dev);
1368 aml_append(table, scope);
1369 }
1370
1371 static void build_piix4_pci_hotplug(Aml *table)
1372 {
1373 Aml *scope;
1374 Aml *field;
1375 Aml *method;
1376
1377 scope = aml_scope("_SB.PCI0");
1378
1379 aml_append(scope,
1380 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1381 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1382 aml_append(field, aml_named_field("PCIU", 32));
1383 aml_append(field, aml_named_field("PCID", 32));
1384 aml_append(scope, field);
1385
1386 aml_append(scope,
1387 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1388 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1389 aml_append(field, aml_named_field("B0EJ", 32));
1390 aml_append(scope, field);
1391
1392 aml_append(scope,
1393 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1394 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1395 aml_append(field, aml_named_field("BNUM", 32));
1396 aml_append(scope, field);
1397
1398 aml_append(scope, aml_mutex("BLCK", 0));
1399
1400 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1401 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1402 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1403 aml_append(method,
1404 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1405 aml_append(method, aml_release(aml_name("BLCK")));
1406 aml_append(method, aml_return(aml_int(0)));
1407 aml_append(scope, method);
1408
1409 aml_append(table, scope);
1410 }
1411
1412 static Aml *build_q35_osc_method(void)
1413 {
1414 Aml *if_ctx;
1415 Aml *if_ctx2;
1416 Aml *else_ctx;
1417 Aml *method;
1418 Aml *a_cwd1 = aml_name("CDW1");
1419 Aml *a_ctrl = aml_local(0);
1420
1421 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1422 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1423
1424 if_ctx = aml_if(aml_equal(
1425 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1426 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1427 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1428
1429 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1430
1431 /*
1432 * Always allow native PME, AER (no dependencies)
1433 * Allow SHPC (PCI bridges can have SHPC controller)
1434 */
1435 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1436
1437 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1438 /* Unknown revision */
1439 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1440 aml_append(if_ctx, if_ctx2);
1441
1442 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1443 /* Capabilities bits were masked */
1444 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1445 aml_append(if_ctx, if_ctx2);
1446
1447 /* Update DWORD3 in the buffer */
1448 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1449 aml_append(method, if_ctx);
1450
1451 else_ctx = aml_else();
1452 /* Unrecognized UUID */
1453 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1454 aml_append(method, else_ctx);
1455
1456 aml_append(method, aml_return(aml_arg(3)));
1457 return method;
1458 }
1459
1460 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1461 {
1462 Aml *scope = aml_scope("_SB.PCI0");
1463 Aml *dev = aml_device("SMB0");
1464
1465 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1466 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1467 aml_append(scope, dev);
1468 aml_append(table, scope);
1469 }
1470
1471 static void
1472 build_dsdt(GArray *table_data, BIOSLinker *linker,
1473 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1474 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1475 {
1476 CrsRangeEntry *entry;
1477 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1478 CrsRangeSet crs_range_set;
1479 PCMachineState *pcms = PC_MACHINE(machine);
1480 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1481 X86MachineState *x86ms = X86_MACHINE(machine);
1482 AcpiMcfgInfo mcfg;
1483 uint32_t nr_mem = machine->ram_slots;
1484 int root_bus_limit = 0xFF;
1485 PCIBus *bus = NULL;
1486 TPMIf *tpm = tpm_find();
1487 int i;
1488
1489 dsdt = init_aml_allocator();
1490
1491 /* Reserve space for header */
1492 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1493
1494 build_dbg_aml(dsdt);
1495 if (misc->is_piix4) {
1496 sb_scope = aml_scope("_SB");
1497 dev = aml_device("PCI0");
1498 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1499 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1500 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1501 aml_append(sb_scope, dev);
1502 aml_append(dsdt, sb_scope);
1503
1504 build_hpet_aml(dsdt);
1505 build_piix4_isa_bridge(dsdt);
1506 build_isa_devices_aml(dsdt);
1507 build_piix4_pci_hotplug(dsdt);
1508 build_piix4_pci0_int(dsdt);
1509 } else {
1510 sb_scope = aml_scope("_SB");
1511 dev = aml_device("PCI0");
1512 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1513 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1514 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1515 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1516 aml_append(dev, build_q35_osc_method());
1517 aml_append(sb_scope, dev);
1518 aml_append(dsdt, sb_scope);
1519
1520 build_hpet_aml(dsdt);
1521 build_q35_isa_bridge(dsdt);
1522 build_isa_devices_aml(dsdt);
1523 build_q35_pci0_int(dsdt);
1524 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1525 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1526 }
1527 }
1528
1529 if (pcmc->legacy_cpu_hotplug) {
1530 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1531 } else {
1532 CPUHotplugFeatures opts = {
1533 .acpi_1_compatible = true, .has_legacy_cphp = true
1534 };
1535 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1536 "\\_SB.PCI0", "\\_GPE._E02");
1537 }
1538
1539 if (pcms->memhp_io_base && nr_mem) {
1540 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1541 "\\_GPE._E03", AML_SYSTEM_IO,
1542 pcms->memhp_io_base);
1543 }
1544
1545 scope = aml_scope("_GPE");
1546 {
1547 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1548
1549 if (misc->is_piix4) {
1550 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1551 aml_append(method,
1552 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1553 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1554 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1555 aml_append(scope, method);
1556 }
1557
1558 if (machine->nvdimms_state->is_enabled) {
1559 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1560 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1561 aml_int(0x80)));
1562 aml_append(scope, method);
1563 }
1564 }
1565 aml_append(dsdt, scope);
1566
1567 crs_range_set_init(&crs_range_set);
1568 bus = PC_MACHINE(machine)->bus;
1569 if (bus) {
1570 QLIST_FOREACH(bus, &bus->child, sibling) {
1571 uint8_t bus_num = pci_bus_num(bus);
1572 uint8_t numa_node = pci_bus_numa_node(bus);
1573
1574 /* look only for expander root buses */
1575 if (!pci_bus_is_root(bus)) {
1576 continue;
1577 }
1578
1579 if (bus_num < root_bus_limit) {
1580 root_bus_limit = bus_num - 1;
1581 }
1582
1583 scope = aml_scope("\\_SB");
1584 dev = aml_device("PC%.02X", bus_num);
1585 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1586 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1587 if (pci_bus_is_express(bus)) {
1588 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1589 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1590 aml_append(dev, build_q35_osc_method());
1591 } else {
1592 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1593 }
1594
1595 if (numa_node != NUMA_NODE_UNASSIGNED) {
1596 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1597 }
1598
1599 aml_append(dev, build_prt(false));
1600 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1601 aml_append(dev, aml_name_decl("_CRS", crs));
1602 aml_append(scope, dev);
1603 aml_append(dsdt, scope);
1604 }
1605 }
1606
1607 /*
1608 * At this point crs_range_set has all the ranges used by pci
1609 * busses *other* than PCI0. These ranges will be excluded from
1610 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1611 * too.
1612 */
1613 if (acpi_get_mcfg(&mcfg)) {
1614 crs_range_insert(crs_range_set.mem_ranges,
1615 mcfg.base, mcfg.base + mcfg.size - 1);
1616 }
1617
1618 scope = aml_scope("\\_SB.PCI0");
1619 /* build PCI0._CRS */
1620 crs = aml_resource_template();
1621 aml_append(crs,
1622 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1623 0x0000, 0x0, root_bus_limit,
1624 0x0000, root_bus_limit + 1));
1625 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1626
1627 aml_append(crs,
1628 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1629 AML_POS_DECODE, AML_ENTIRE_RANGE,
1630 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1631
1632 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1633 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1634 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1635 aml_append(crs,
1636 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1637 AML_POS_DECODE, AML_ENTIRE_RANGE,
1638 0x0000, entry->base, entry->limit,
1639 0x0000, entry->limit - entry->base + 1));
1640 }
1641
1642 aml_append(crs,
1643 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1644 AML_CACHEABLE, AML_READ_WRITE,
1645 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1646
1647 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1648 range_lob(pci_hole),
1649 range_upb(pci_hole));
1650 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1651 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1652 aml_append(crs,
1653 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1654 AML_NON_CACHEABLE, AML_READ_WRITE,
1655 0, entry->base, entry->limit,
1656 0, entry->limit - entry->base + 1));
1657 }
1658
1659 if (!range_is_empty(pci_hole64)) {
1660 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1661 range_lob(pci_hole64),
1662 range_upb(pci_hole64));
1663 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1664 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1665 aml_append(crs,
1666 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1667 AML_MAX_FIXED,
1668 AML_CACHEABLE, AML_READ_WRITE,
1669 0, entry->base, entry->limit,
1670 0, entry->limit - entry->base + 1));
1671 }
1672 }
1673
1674 if (TPM_IS_TIS_ISA(tpm_find())) {
1675 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1676 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1677 }
1678 aml_append(scope, aml_name_decl("_CRS", crs));
1679
1680 /* reserve GPE0 block resources */
1681 dev = aml_device("GPE0");
1682 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1683 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1684 /* device present, functioning, decoding, not shown in UI */
1685 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1686 crs = aml_resource_template();
1687 aml_append(crs,
1688 aml_io(
1689 AML_DECODE16,
1690 pm->fadt.gpe0_blk.address,
1691 pm->fadt.gpe0_blk.address,
1692 1,
1693 pm->fadt.gpe0_blk.bit_width / 8)
1694 );
1695 aml_append(dev, aml_name_decl("_CRS", crs));
1696 aml_append(scope, dev);
1697
1698 crs_range_set_free(&crs_range_set);
1699
1700 /* reserve PCIHP resources */
1701 if (pm->pcihp_io_len) {
1702 dev = aml_device("PHPR");
1703 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1704 aml_append(dev,
1705 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1706 /* device present, functioning, decoding, not shown in UI */
1707 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1708 crs = aml_resource_template();
1709 aml_append(crs,
1710 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1711 pm->pcihp_io_len)
1712 );
1713 aml_append(dev, aml_name_decl("_CRS", crs));
1714 aml_append(scope, dev);
1715 }
1716 aml_append(dsdt, scope);
1717
1718 /* create S3_ / S4_ / S5_ packages if necessary */
1719 scope = aml_scope("\\");
1720 if (!pm->s3_disabled) {
1721 pkg = aml_package(4);
1722 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1723 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1724 aml_append(pkg, aml_int(0)); /* reserved */
1725 aml_append(pkg, aml_int(0)); /* reserved */
1726 aml_append(scope, aml_name_decl("_S3", pkg));
1727 }
1728
1729 if (!pm->s4_disabled) {
1730 pkg = aml_package(4);
1731 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1732 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1733 aml_append(pkg, aml_int(pm->s4_val));
1734 aml_append(pkg, aml_int(0)); /* reserved */
1735 aml_append(pkg, aml_int(0)); /* reserved */
1736 aml_append(scope, aml_name_decl("_S4", pkg));
1737 }
1738
1739 pkg = aml_package(4);
1740 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1741 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1742 aml_append(pkg, aml_int(0)); /* reserved */
1743 aml_append(pkg, aml_int(0)); /* reserved */
1744 aml_append(scope, aml_name_decl("_S5", pkg));
1745 aml_append(dsdt, scope);
1746
1747 /* create fw_cfg node, unconditionally */
1748 {
1749 scope = aml_scope("\\_SB.PCI0");
1750 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1751 aml_append(dsdt, scope);
1752 }
1753
1754 if (misc->applesmc_io_base) {
1755 scope = aml_scope("\\_SB.PCI0.ISA");
1756 dev = aml_device("SMC");
1757
1758 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1759 /* device present, functioning, decoding, not shown in UI */
1760 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1761
1762 crs = aml_resource_template();
1763 aml_append(crs,
1764 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1765 0x01, APPLESMC_MAX_DATA_LENGTH)
1766 );
1767 aml_append(crs, aml_irq_no_flags(6));
1768 aml_append(dev, aml_name_decl("_CRS", crs));
1769
1770 aml_append(scope, dev);
1771 aml_append(dsdt, scope);
1772 }
1773
1774 if (misc->pvpanic_port) {
1775 scope = aml_scope("\\_SB.PCI0.ISA");
1776
1777 dev = aml_device("PEVT");
1778 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1779
1780 crs = aml_resource_template();
1781 aml_append(crs,
1782 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1783 );
1784 aml_append(dev, aml_name_decl("_CRS", crs));
1785
1786 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1787 aml_int(misc->pvpanic_port), 1));
1788 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1789 aml_append(field, aml_named_field("PEPT", 8));
1790 aml_append(dev, field);
1791
1792 /* device present, functioning, decoding, shown in UI */
1793 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1794
1795 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1796 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1797 aml_append(method, aml_return(aml_local(0)));
1798 aml_append(dev, method);
1799
1800 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1801 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1802 aml_append(dev, method);
1803
1804 aml_append(scope, dev);
1805 aml_append(dsdt, scope);
1806 }
1807
1808 sb_scope = aml_scope("\\_SB");
1809 {
1810 Object *pci_host;
1811 PCIBus *bus = NULL;
1812
1813 pci_host = acpi_get_i386_pci_host();
1814 if (pci_host) {
1815 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1816 }
1817
1818 if (bus) {
1819 Aml *scope = aml_scope("PCI0");
1820 /* Scan all PCI buses. Generate tables to support hotplug. */
1821 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1822
1823 if (TPM_IS_TIS_ISA(tpm)) {
1824 if (misc->tpm_version == TPM_VERSION_2_0) {
1825 dev = aml_device("TPM");
1826 aml_append(dev, aml_name_decl("_HID",
1827 aml_string("MSFT0101")));
1828 } else {
1829 dev = aml_device("ISA.TPM");
1830 aml_append(dev, aml_name_decl("_HID",
1831 aml_eisaid("PNP0C31")));
1832 }
1833
1834 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1835 crs = aml_resource_template();
1836 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1837 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1838 /*
1839 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1840 Rewrite to take IRQ from TPM device model and
1841 fix default IRQ value there to use some unused IRQ
1842 */
1843 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1844 aml_append(dev, aml_name_decl("_CRS", crs));
1845
1846 tpm_build_ppi_acpi(tpm, dev);
1847
1848 aml_append(scope, dev);
1849 }
1850
1851 aml_append(sb_scope, scope);
1852 }
1853 }
1854
1855 if (TPM_IS_CRB(tpm)) {
1856 dev = aml_device("TPM");
1857 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1858 crs = aml_resource_template();
1859 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1860 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1861 aml_append(dev, aml_name_decl("_CRS", crs));
1862
1863 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1864
1865 tpm_build_ppi_acpi(tpm, dev);
1866
1867 aml_append(sb_scope, dev);
1868 }
1869
1870 aml_append(dsdt, sb_scope);
1871
1872 /* copy AML table into ACPI tables blob and patch header there */
1873 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1874 build_header(linker, table_data,
1875 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1876 "DSDT", dsdt->buf->len, 1, NULL, NULL);
1877 free_aml_allocator();
1878 }
1879
1880 static void
1881 build_hpet(GArray *table_data, BIOSLinker *linker)
1882 {
1883 Acpi20Hpet *hpet;
1884
1885 hpet = acpi_data_push(table_data, sizeof(*hpet));
1886 /* Note timer_block_id value must be kept in sync with value advertised by
1887 * emulated hpet
1888 */
1889 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1890 hpet->addr.address = cpu_to_le64(HPET_BASE);
1891 build_header(linker, table_data,
1892 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
1893 }
1894
1895 static void
1896 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
1897 {
1898 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1899 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1900 unsigned log_addr_offset =
1901 (char *)&tcpa->log_area_start_address - table_data->data;
1902
1903 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1904 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1905 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1906
1907 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1908 false /* high memory */);
1909
1910 /* log area start address to be filled by Guest linker */
1911 bios_linker_loader_add_pointer(linker,
1912 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1913 ACPI_BUILD_TPMLOG_FILE, 0);
1914
1915 build_header(linker, table_data,
1916 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
1917 }
1918
1919 #define HOLE_640K_START (640 * KiB)
1920 #define HOLE_640K_END (1 * MiB)
1921
1922 static void
1923 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1924 {
1925 AcpiSystemResourceAffinityTable *srat;
1926 AcpiSratMemoryAffinity *numamem;
1927
1928 int i;
1929 int srat_start, numa_start, slots;
1930 uint64_t mem_len, mem_base, next_base;
1931 MachineClass *mc = MACHINE_GET_CLASS(machine);
1932 X86MachineState *x86ms = X86_MACHINE(machine);
1933 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1934 PCMachineState *pcms = PC_MACHINE(machine);
1935 ram_addr_t hotplugabble_address_space_size =
1936 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1937 NULL);
1938
1939 srat_start = table_data->len;
1940
1941 srat = acpi_data_push(table_data, sizeof *srat);
1942 srat->reserved1 = cpu_to_le32(1);
1943
1944 for (i = 0; i < apic_ids->len; i++) {
1945 int node_id = apic_ids->cpus[i].props.node_id;
1946 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1947
1948 if (apic_id < 255) {
1949 AcpiSratProcessorAffinity *core;
1950
1951 core = acpi_data_push(table_data, sizeof *core);
1952 core->type = ACPI_SRAT_PROCESSOR_APIC;
1953 core->length = sizeof(*core);
1954 core->local_apic_id = apic_id;
1955 core->proximity_lo = node_id;
1956 memset(core->proximity_hi, 0, 3);
1957 core->local_sapic_eid = 0;
1958 core->flags = cpu_to_le32(1);
1959 } else {
1960 AcpiSratProcessorX2ApicAffinity *core;
1961
1962 core = acpi_data_push(table_data, sizeof *core);
1963 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1964 core->length = sizeof(*core);
1965 core->x2apic_id = cpu_to_le32(apic_id);
1966 core->proximity_domain = cpu_to_le32(node_id);
1967 core->flags = cpu_to_le32(1);
1968 }
1969 }
1970
1971
1972 /* the memory map is a bit tricky, it contains at least one hole
1973 * from 640k-1M and possibly another one from 3.5G-4G.
1974 */
1975 next_base = 0;
1976 numa_start = table_data->len;
1977
1978 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1979 mem_base = next_base;
1980 mem_len = pcms->node_mem[i - 1];
1981 next_base = mem_base + mem_len;
1982
1983 /* Cut out the 640K hole */
1984 if (mem_base <= HOLE_640K_START &&
1985 next_base > HOLE_640K_START) {
1986 mem_len -= next_base - HOLE_640K_START;
1987 if (mem_len > 0) {
1988 numamem = acpi_data_push(table_data, sizeof *numamem);
1989 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1990 MEM_AFFINITY_ENABLED);
1991 }
1992
1993 /* Check for the rare case: 640K < RAM < 1M */
1994 if (next_base <= HOLE_640K_END) {
1995 next_base = HOLE_640K_END;
1996 continue;
1997 }
1998 mem_base = HOLE_640K_END;
1999 mem_len = next_base - HOLE_640K_END;
2000 }
2001
2002 /* Cut out the ACPI_PCI hole */
2003 if (mem_base <= x86ms->below_4g_mem_size &&
2004 next_base > x86ms->below_4g_mem_size) {
2005 mem_len -= next_base - x86ms->below_4g_mem_size;
2006 if (mem_len > 0) {
2007 numamem = acpi_data_push(table_data, sizeof *numamem);
2008 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2009 MEM_AFFINITY_ENABLED);
2010 }
2011 mem_base = 1ULL << 32;
2012 mem_len = next_base - x86ms->below_4g_mem_size;
2013 next_base = mem_base + mem_len;
2014 }
2015
2016 if (mem_len > 0) {
2017 numamem = acpi_data_push(table_data, sizeof *numamem);
2018 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2019 MEM_AFFINITY_ENABLED);
2020 }
2021 }
2022
2023 if (machine->nvdimms_state->is_enabled) {
2024 nvdimm_build_srat(table_data);
2025 }
2026
2027 slots = (table_data->len - numa_start) / sizeof *numamem;
2028 for (; slots < pcms->numa_nodes + 2; slots++) {
2029 numamem = acpi_data_push(table_data, sizeof *numamem);
2030 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2031 }
2032
2033 /*
2034 * Entry is required for Windows to enable memory hotplug in OS
2035 * and for Linux to enable SWIOTLB when booted with less than
2036 * 4G of RAM. Windows works better if the entry sets proximity
2037 * to the highest NUMA node in the machine.
2038 * Memory devices may override proximity set by this entry,
2039 * providing _PXM method if necessary.
2040 */
2041 if (hotplugabble_address_space_size) {
2042 numamem = acpi_data_push(table_data, sizeof *numamem);
2043 build_srat_memory(numamem, machine->device_memory->base,
2044 hotplugabble_address_space_size, pcms->numa_nodes - 1,
2045 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2046 }
2047
2048 build_header(linker, table_data,
2049 (void *)(table_data->data + srat_start),
2050 "SRAT",
2051 table_data->len - srat_start, 1, NULL, NULL);
2052 }
2053
2054 /*
2055 * VT-d spec 8.1 DMA Remapping Reporting Structure
2056 * (version Oct. 2014 or later)
2057 */
2058 static void
2059 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2060 {
2061 int dmar_start = table_data->len;
2062
2063 AcpiTableDmar *dmar;
2064 AcpiDmarHardwareUnit *drhd;
2065 AcpiDmarRootPortATS *atsr;
2066 uint8_t dmar_flags = 0;
2067 X86IOMMUState *iommu = x86_iommu_get_default();
2068 AcpiDmarDeviceScope *scope = NULL;
2069 /* Root complex IOAPIC use one path[0] only */
2070 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2071 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2072
2073 assert(iommu);
2074 if (x86_iommu_ir_supported(iommu)) {
2075 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2076 }
2077
2078 dmar = acpi_data_push(table_data, sizeof(*dmar));
2079 dmar->host_address_width = intel_iommu->aw_bits - 1;
2080 dmar->flags = dmar_flags;
2081
2082 /* DMAR Remapping Hardware Unit Definition structure */
2083 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2084 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2085 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2086 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2087 drhd->pci_segment = cpu_to_le16(0);
2088 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2089
2090 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2091 * 8.3.1 (version Oct. 2014 or later). */
2092 scope = &drhd->scope[0];
2093 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2094 scope->length = ioapic_scope_size;
2095 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2096 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2097 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2098 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2099
2100 if (iommu->dt_supported) {
2101 atsr = acpi_data_push(table_data, sizeof(*atsr));
2102 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2103 atsr->length = cpu_to_le16(sizeof(*atsr));
2104 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2105 atsr->pci_segment = cpu_to_le16(0);
2106 }
2107
2108 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2109 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2110 }
2111
2112 /*
2113 * Windows ACPI Emulated Devices Table
2114 * (Version 1.0 - April 6, 2009)
2115 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2116 *
2117 * Helpful to speedup Windows guests and ignored by others.
2118 */
2119 static void
2120 build_waet(GArray *table_data, BIOSLinker *linker)
2121 {
2122 int waet_start = table_data->len;
2123
2124 /* WAET header */
2125 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2126 /*
2127 * Set "ACPI PM timer good" flag.
2128 *
2129 * Tells Windows guests that our ACPI PM timer is reliable in the
2130 * sense that guest can read it only once to obtain a reliable value.
2131 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2132 */
2133 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2134
2135 build_header(linker, table_data, (void *)(table_data->data + waet_start),
2136 "WAET", table_data->len - waet_start, 1, NULL, NULL);
2137 }
2138
2139 /*
2140 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2141 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2142 */
2143 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2144
2145 /*
2146 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2147 * necessary for the PCI topology.
2148 */
2149 static void
2150 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2151 {
2152 GArray *table_data = opaque;
2153 uint32_t entry;
2154
2155 /* "Select" IVHD entry, type 0x2 */
2156 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2157 build_append_int_noprefix(table_data, entry, 4);
2158
2159 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2160 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2161 uint8_t sec = pci_bus_num(sec_bus);
2162 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2163
2164 if (pci_bus_is_express(sec_bus)) {
2165 /*
2166 * Walk the bus if there are subordinates, otherwise use a range
2167 * to cover an entire leaf bus. We could potentially also use a
2168 * range for traversed buses, but we'd need to take care not to
2169 * create both Select and Range entries covering the same device.
2170 * This is easier and potentially more compact.
2171 *
2172 * An example bare metal system seems to use Select entries for
2173 * root ports without a slot (ie. built-ins) and Range entries
2174 * when there is a slot. The same system also only hard-codes
2175 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2176 * making no effort to support nested bridges. We attempt to
2177 * be more thorough here.
2178 */
2179 if (sec == sub) { /* leaf bus */
2180 /* "Start of Range" IVHD entry, type 0x3 */
2181 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2182 build_append_int_noprefix(table_data, entry, 4);
2183 /* "End of Range" IVHD entry, type 0x4 */
2184 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2185 build_append_int_noprefix(table_data, entry, 4);
2186 } else {
2187 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2188 }
2189 } else {
2190 /*
2191 * If the secondary bus is conventional, then we need to create an
2192 * Alias range for everything downstream. The range covers the
2193 * first devfn on the secondary bus to the last devfn on the
2194 * subordinate bus. The alias target depends on legacy versus
2195 * express bridges, just as in pci_device_iommu_address_space().
2196 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2197 */
2198 uint16_t dev_id_a, dev_id_b;
2199
2200 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2201
2202 if (pci_is_express(dev) &&
2203 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2204 dev_id_b = dev_id_a;
2205 } else {
2206 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2207 }
2208
2209 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2210 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2211 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2212
2213 /* "End of Range" IVHD entry, type 0x4 */
2214 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2215 build_append_int_noprefix(table_data, entry, 4);
2216 }
2217 }
2218 }
2219
2220 /* For all PCI host bridges, walk and insert IVHD entries */
2221 static int
2222 ivrs_host_bridges(Object *obj, void *opaque)
2223 {
2224 GArray *ivhd_blob = opaque;
2225
2226 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2227 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2228
2229 if (bus) {
2230 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2231 }
2232 }
2233
2234 return 0;
2235 }
2236
2237 static void
2238 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2239 {
2240 int ivhd_table_len = 24;
2241 int iommu_start = table_data->len;
2242 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2243 GArray *ivhd_blob = g_array_new(false, true, 1);
2244
2245 /* IVRS header */
2246 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2247 /* IVinfo - IO virtualization information common to all
2248 * IOMMU units in a system
2249 */
2250 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2251 /* reserved */
2252 build_append_int_noprefix(table_data, 0, 8);
2253
2254 /* IVHD definition - type 10h */
2255 build_append_int_noprefix(table_data, 0x10, 1);
2256 /* virtualization flags */
2257 build_append_int_noprefix(table_data,
2258 (1UL << 0) | /* HtTunEn */
2259 (1UL << 4) | /* iotblSup */
2260 (1UL << 6) | /* PrefSup */
2261 (1UL << 7), /* PPRSup */
2262 1);
2263
2264 /*
2265 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2266 * complete set of IVHD entries. Do this into a separate blob so that we
2267 * can calculate the total IVRS table length here and then append the new
2268 * blob further below. Fall back to an entry covering all devices, which
2269 * is sufficient when no aliases are present.
2270 */
2271 object_child_foreach_recursive(object_get_root(),
2272 ivrs_host_bridges, ivhd_blob);
2273
2274 if (!ivhd_blob->len) {
2275 /*
2276 * Type 1 device entry reporting all devices
2277 * These are 4-byte device entries currently reporting the range of
2278 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2279 */
2280 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2281 }
2282
2283 ivhd_table_len += ivhd_blob->len;
2284
2285 /*
2286 * When interrupt remapping is supported, we add a special IVHD device
2287 * for type IO-APIC.
2288 */
2289 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2290 ivhd_table_len += 8;
2291 }
2292
2293 /* IVHD length */
2294 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2295 /* DeviceID */
2296 build_append_int_noprefix(table_data, s->devid, 2);
2297 /* Capability offset */
2298 build_append_int_noprefix(table_data, s->capab_offset, 2);
2299 /* IOMMU base address */
2300 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2301 /* PCI Segment Group */
2302 build_append_int_noprefix(table_data, 0, 2);
2303 /* IOMMU info */
2304 build_append_int_noprefix(table_data, 0, 2);
2305 /* IOMMU Feature Reporting */
2306 build_append_int_noprefix(table_data,
2307 (48UL << 30) | /* HATS */
2308 (48UL << 28) | /* GATS */
2309 (1UL << 2) | /* GTSup */
2310 (1UL << 6), /* GASup */
2311 4);
2312
2313 /* IVHD entries as found above */
2314 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2315 g_array_free(ivhd_blob, TRUE);
2316
2317 /*
2318 * Add a special IVHD device type.
2319 * Refer to spec - Table 95: IVHD device entry type codes
2320 *
2321 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2322 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2323 */
2324 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2325 build_append_int_noprefix(table_data,
2326 (0x1ull << 56) | /* type IOAPIC */
2327 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2328 0x48, /* special device */
2329 8);
2330 }
2331
2332 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2333 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2334 }
2335
2336 typedef
2337 struct AcpiBuildState {
2338 /* Copy of table in RAM (for patching). */
2339 MemoryRegion *table_mr;
2340 /* Is table patched? */
2341 uint8_t patched;
2342 void *rsdp;
2343 MemoryRegion *rsdp_mr;
2344 MemoryRegion *linker_mr;
2345 } AcpiBuildState;
2346
2347 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2348 {
2349 Object *pci_host;
2350 QObject *o;
2351
2352 pci_host = acpi_get_i386_pci_host();
2353 g_assert(pci_host);
2354
2355 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2356 if (!o) {
2357 return false;
2358 }
2359 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2360 qobject_unref(o);
2361 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2362 return false;
2363 }
2364
2365 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2366 assert(o);
2367 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2368 qobject_unref(o);
2369 return true;
2370 }
2371
2372 static
2373 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2374 {
2375 PCMachineState *pcms = PC_MACHINE(machine);
2376 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2377 X86MachineState *x86ms = X86_MACHINE(machine);
2378 GArray *table_offsets;
2379 unsigned facs, dsdt, rsdt, fadt;
2380 AcpiPmInfo pm;
2381 AcpiMiscInfo misc;
2382 AcpiMcfgInfo mcfg;
2383 Range pci_hole, pci_hole64;
2384 uint8_t *u;
2385 size_t aml_len = 0;
2386 GArray *tables_blob = tables->table_data;
2387 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2388 Object *vmgenid_dev;
2389
2390 acpi_get_pm_info(machine, &pm);
2391 acpi_get_misc_info(&misc);
2392 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2393 acpi_get_slic_oem(&slic_oem);
2394
2395 table_offsets = g_array_new(false, true /* clear */,
2396 sizeof(uint32_t));
2397 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2398
2399 bios_linker_loader_alloc(tables->linker,
2400 ACPI_BUILD_TABLE_FILE, tables_blob,
2401 64 /* Ensure FACS is aligned */,
2402 false /* high memory */);
2403
2404 /*
2405 * FACS is pointed to by FADT.
2406 * We place it first since it's the only table that has alignment
2407 * requirements.
2408 */
2409 facs = tables_blob->len;
2410 build_facs(tables_blob);
2411
2412 /* DSDT is pointed to by FADT */
2413 dsdt = tables_blob->len;
2414 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2415 &pci_hole, &pci_hole64, machine);
2416
2417 /* Count the size of the DSDT and SSDT, we will need it for legacy
2418 * sizing of ACPI tables.
2419 */
2420 aml_len += tables_blob->len - dsdt;
2421
2422 /* ACPI tables pointed to by RSDT */
2423 fadt = tables_blob->len;
2424 acpi_add_table(table_offsets, tables_blob);
2425 pm.fadt.facs_tbl_offset = &facs;
2426 pm.fadt.dsdt_tbl_offset = &dsdt;
2427 pm.fadt.xdsdt_tbl_offset = &dsdt;
2428 build_fadt(tables_blob, tables->linker, &pm.fadt,
2429 slic_oem.id, slic_oem.table_id);
2430 aml_len += tables_blob->len - fadt;
2431
2432 acpi_add_table(table_offsets, tables_blob);
2433 acpi_build_madt(tables_blob, tables->linker, x86ms,
2434 ACPI_DEVICE_IF(x86ms->acpi_dev), true);
2435
2436 vmgenid_dev = find_vmgenid_dev();
2437 if (vmgenid_dev) {
2438 acpi_add_table(table_offsets, tables_blob);
2439 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2440 tables->vmgenid, tables->linker);
2441 }
2442
2443 if (misc.has_hpet) {
2444 acpi_add_table(table_offsets, tables_blob);
2445 build_hpet(tables_blob, tables->linker);
2446 }
2447 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2448 if (misc.tpm_version == TPM_VERSION_1_2) {
2449 acpi_add_table(table_offsets, tables_blob);
2450 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2451 } else { /* TPM_VERSION_2_0 */
2452 acpi_add_table(table_offsets, tables_blob);
2453 build_tpm2(tables_blob, tables->linker, tables->tcpalog);
2454 }
2455 }
2456 if (pcms->numa_nodes) {
2457 acpi_add_table(table_offsets, tables_blob);
2458 build_srat(tables_blob, tables->linker, machine);
2459 if (machine->numa_state->have_numa_distance) {
2460 acpi_add_table(table_offsets, tables_blob);
2461 build_slit(tables_blob, tables->linker, machine);
2462 }
2463 if (machine->numa_state->hmat_enabled) {
2464 acpi_add_table(table_offsets, tables_blob);
2465 build_hmat(tables_blob, tables->linker, machine->numa_state);
2466 }
2467 }
2468 if (acpi_get_mcfg(&mcfg)) {
2469 acpi_add_table(table_offsets, tables_blob);
2470 build_mcfg(tables_blob, tables->linker, &mcfg);
2471 }
2472 if (x86_iommu_get_default()) {
2473 IommuType IOMMUType = x86_iommu_get_type();
2474 if (IOMMUType == TYPE_AMD) {
2475 acpi_add_table(table_offsets, tables_blob);
2476 build_amd_iommu(tables_blob, tables->linker);
2477 } else if (IOMMUType == TYPE_INTEL) {
2478 acpi_add_table(table_offsets, tables_blob);
2479 build_dmar_q35(tables_blob, tables->linker);
2480 }
2481 }
2482 if (machine->nvdimms_state->is_enabled) {
2483 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2484 machine->nvdimms_state, machine->ram_slots);
2485 }
2486
2487 acpi_add_table(table_offsets, tables_blob);
2488 build_waet(tables_blob, tables->linker);
2489
2490 /* Add tables supplied by user (if any) */
2491 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2492 unsigned len = acpi_table_len(u);
2493
2494 acpi_add_table(table_offsets, tables_blob);
2495 g_array_append_vals(tables_blob, u, len);
2496 }
2497
2498 /* RSDT is pointed to by RSDP */
2499 rsdt = tables_blob->len;
2500 build_rsdt(tables_blob, tables->linker, table_offsets,
2501 slic_oem.id, slic_oem.table_id);
2502
2503 /* RSDP is in FSEG memory, so allocate it separately */
2504 {
2505 AcpiRsdpData rsdp_data = {
2506 .revision = 0,
2507 .oem_id = ACPI_BUILD_APPNAME6,
2508 .xsdt_tbl_offset = NULL,
2509 .rsdt_tbl_offset = &rsdt,
2510 };
2511 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2512 if (!pcmc->rsdp_in_ram) {
2513 /* We used to allocate some extra space for RSDP revision 2 but
2514 * only used the RSDP revision 0 space. The extra bytes were
2515 * zeroed out and not used.
2516 * Here we continue wasting those extra 16 bytes to make sure we
2517 * don't break migration for machine types 2.2 and older due to
2518 * RSDP blob size mismatch.
2519 */
2520 build_append_int_noprefix(tables->rsdp, 0, 16);
2521 }
2522 }
2523
2524 /* We'll expose it all to Guest so we want to reduce
2525 * chance of size changes.
2526 *
2527 * We used to align the tables to 4k, but of course this would
2528 * too simple to be enough. 4k turned out to be too small an
2529 * alignment very soon, and in fact it is almost impossible to
2530 * keep the table size stable for all (max_cpus, max_memory_slots)
2531 * combinations. So the table size is always 64k for pc-i440fx-2.1
2532 * and we give an error if the table grows beyond that limit.
2533 *
2534 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2535 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2536 * than 2.0 and we can always pad the smaller tables with zeros. We can
2537 * then use the exact size of the 2.0 tables.
2538 *
2539 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2540 */
2541 if (pcmc->legacy_acpi_table_size) {
2542 /* Subtracting aml_len gives the size of fixed tables. Then add the
2543 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2544 */
2545 int legacy_aml_len =
2546 pcmc->legacy_acpi_table_size +
2547 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2548 int legacy_table_size =
2549 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2550 ACPI_BUILD_ALIGN_SIZE);
2551 if (tables_blob->len > legacy_table_size) {
2552 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2553 warn_report("ACPI table size %u exceeds %d bytes,"
2554 " migration may not work",
2555 tables_blob->len, legacy_table_size);
2556 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2557 " or PCI bridges.");
2558 }
2559 g_array_set_size(tables_blob, legacy_table_size);
2560 } else {
2561 /* Make sure we have a buffer in case we need to resize the tables. */
2562 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2563 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2564 warn_report("ACPI table size %u exceeds %d bytes,"
2565 " migration may not work",
2566 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2567 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2568 " or PCI bridges.");
2569 }
2570 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2571 }
2572
2573 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2574
2575 /* Cleanup memory that's no longer used. */
2576 g_array_free(table_offsets, true);
2577 }
2578
2579 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2580 {
2581 uint32_t size = acpi_data_len(data);
2582
2583 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2584 memory_region_ram_resize(mr, size, &error_abort);
2585
2586 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2587 memory_region_set_dirty(mr, 0, size);
2588 }
2589
2590 static void acpi_build_update(void *build_opaque)
2591 {
2592 AcpiBuildState *build_state = build_opaque;
2593 AcpiBuildTables tables;
2594
2595 /* No state to update or already patched? Nothing to do. */
2596 if (!build_state || build_state->patched) {
2597 return;
2598 }
2599 build_state->patched = 1;
2600
2601 acpi_build_tables_init(&tables);
2602
2603 acpi_build(&tables, MACHINE(qdev_get_machine()));
2604
2605 acpi_ram_update(build_state->table_mr, tables.table_data);
2606
2607 if (build_state->rsdp) {
2608 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2609 } else {
2610 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2611 }
2612
2613 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2614 acpi_build_tables_cleanup(&tables, true);
2615 }
2616
2617 static void acpi_build_reset(void *build_opaque)
2618 {
2619 AcpiBuildState *build_state = build_opaque;
2620 build_state->patched = 0;
2621 }
2622
2623 static const VMStateDescription vmstate_acpi_build = {
2624 .name = "acpi_build",
2625 .version_id = 1,
2626 .minimum_version_id = 1,
2627 .fields = (VMStateField[]) {
2628 VMSTATE_UINT8(patched, AcpiBuildState),
2629 VMSTATE_END_OF_LIST()
2630 },
2631 };
2632
2633 void acpi_setup(void)
2634 {
2635 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2636 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2637 X86MachineState *x86ms = X86_MACHINE(pcms);
2638 AcpiBuildTables tables;
2639 AcpiBuildState *build_state;
2640 Object *vmgenid_dev;
2641 TPMIf *tpm;
2642 static FwCfgTPMConfig tpm_config;
2643
2644 if (!x86ms->fw_cfg) {
2645 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2646 return;
2647 }
2648
2649 if (!pcms->acpi_build_enabled) {
2650 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2651 return;
2652 }
2653
2654 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2655 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2656 return;
2657 }
2658
2659 build_state = g_malloc0(sizeof *build_state);
2660
2661 acpi_build_tables_init(&tables);
2662 acpi_build(&tables, MACHINE(pcms));
2663
2664 /* Now expose it all to Guest */
2665 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2666 build_state, tables.table_data,
2667 ACPI_BUILD_TABLE_FILE,
2668 ACPI_BUILD_TABLE_MAX_SIZE);
2669 assert(build_state->table_mr != NULL);
2670
2671 build_state->linker_mr =
2672 acpi_add_rom_blob(acpi_build_update, build_state,
2673 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
2674
2675 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2676 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2677
2678 tpm = tpm_find();
2679 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2680 tpm_config = (FwCfgTPMConfig) {
2681 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2682 .tpm_version = tpm_get_version(tpm),
2683 .tpmppi_version = TPM_PPI_VERSION_1_30
2684 };
2685 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2686 &tpm_config, sizeof tpm_config);
2687 }
2688
2689 vmgenid_dev = find_vmgenid_dev();
2690 if (vmgenid_dev) {
2691 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2692 tables.vmgenid);
2693 }
2694
2695 if (!pcmc->rsdp_in_ram) {
2696 /*
2697 * Keep for compatibility with old machine types.
2698 * Though RSDP is small, its contents isn't immutable, so
2699 * we'll update it along with the rest of tables on guest access.
2700 */
2701 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2702
2703 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2704 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2705 acpi_build_update, NULL, build_state,
2706 build_state->rsdp, rsdp_size, true);
2707 build_state->rsdp_mr = NULL;
2708 } else {
2709 build_state->rsdp = NULL;
2710 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2711 build_state, tables.rsdp,
2712 ACPI_BUILD_RSDP_FILE, 0);
2713 }
2714
2715 qemu_register_reset(acpi_build_reset, build_state);
2716 acpi_build_reset(build_state);
2717 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2718
2719 /* Cleanup tables but don't free the memory: we track it
2720 * in build_state.
2721 */
2722 acpi_build_tables_cleanup(&tables, false);
2723 }
AR7 emulation for QEMU