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target/ppc: add external PID support
[qemu/ar7.git] / target / ppc / translate.c
blobc99983242608f7aecfaabfb2110ca1f9f6d5327a
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
35 #include "exec/log.h"
36 #include "qemu/atomic128.h"
37
38
39 #define CPU_SINGLE_STEP 0x1
40 #define CPU_BRANCH_STEP 0x2
41 #define GDBSTUB_SINGLE_STEP 0x4
42
43 /* Include definitions for instructions classes and implementations flags */
44 //#define PPC_DEBUG_DISAS
45 //#define DO_PPC_STATISTICS
46
47 #ifdef PPC_DEBUG_DISAS
48 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
49 #else
50 # define LOG_DISAS(...) do { } while (0)
51 #endif
52 /*****************************************************************************/
53 /* Code translation helpers */
54
55 /* global register indexes */
56 static char cpu_reg_names[10*3 + 22*4 /* GPR */
57 + 10*4 + 22*5 /* SPE GPRh */
58 + 10*4 + 22*5 /* FPR */
59 + 2*(10*6 + 22*7) /* AVRh, AVRl */
60 + 10*5 + 22*6 /* VSR */
61 + 8*5 /* CRF */];
62 static TCGv cpu_gpr[32];
63 static TCGv cpu_gprh[32];
64 static TCGv_i64 cpu_fpr[32];
65 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
66 static TCGv_i64 cpu_vsr[32];
67 static TCGv_i32 cpu_crf[8];
68 static TCGv cpu_nip;
69 static TCGv cpu_msr;
70 static TCGv cpu_ctr;
71 static TCGv cpu_lr;
72 #if defined(TARGET_PPC64)
73 static TCGv cpu_cfar;
74 #endif
75 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
76 static TCGv cpu_reserve;
77 static TCGv cpu_reserve_val;
78 static TCGv cpu_fpscr;
79 static TCGv_i32 cpu_access_type;
80
81 #include "exec/gen-icount.h"
82
83 void ppc_translate_init(void)
84 {
85 int i;
86 char* p;
87 size_t cpu_reg_names_size;
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(cpu_env,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(cpu_env,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(cpu_env,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(cpu_env,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(cpu_env,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, ca), "CA");
171 cpu_ov32 = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov32), "OV32");
173 cpu_ca32 = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca32), "CA32");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179 cpu_reserve_val = tcg_global_mem_new(cpu_env,
180 offsetof(CPUPPCState, reserve_val),
181 "reserve_val");
182
183 cpu_fpscr = tcg_global_mem_new(cpu_env,
184 offsetof(CPUPPCState, fpscr), "fpscr");
185
186 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
187 offsetof(CPUPPCState, access_type), "access_type");
188 }
189
190 /* internal defines */
191 struct DisasContext {
192 DisasContextBase base;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 bool gtse;
213 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
214 int singlestep_enabled;
215 uint32_t flags;
216 uint64_t insns_flags;
217 uint64_t insns_flags2;
218 };
219
220 /* Return true iff byteswap is needed in a scalar memop */
221 static inline bool need_byteswap(const DisasContext *ctx)
222 {
223 #if defined(TARGET_WORDS_BIGENDIAN)
224 return ctx->le_mode;
225 #else
226 return !ctx->le_mode;
227 #endif
228 }
229
230 /* True when active word size < size of target_long. */
231 #ifdef TARGET_PPC64
232 # define NARROW_MODE(C) (!(C)->sf_mode)
233 #else
234 # define NARROW_MODE(C) 0
235 #endif
236
237 struct opc_handler_t {
238 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
239 uint32_t inval1;
240 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
241 uint32_t inval2;
242 /* instruction type */
243 uint64_t type;
244 /* extended instruction type */
245 uint64_t type2;
246 /* handler */
247 void (*handler)(DisasContext *ctx);
248 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
249 const char *oname;
250 #endif
251 #if defined(DO_PPC_STATISTICS)
252 uint64_t count;
253 #endif
254 };
255
256 /* SPR load/store helpers */
257 static inline void gen_load_spr(TCGv t, int reg)
258 {
259 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
260 }
261
262 static inline void gen_store_spr(int reg, TCGv t)
263 {
264 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
265 }
266
267 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
268 {
269 if (ctx->need_access_type && ctx->access_type != access_type) {
270 tcg_gen_movi_i32(cpu_access_type, access_type);
271 ctx->access_type = access_type;
272 }
273 }
274
275 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
276 {
277 if (NARROW_MODE(ctx)) {
278 nip = (uint32_t)nip;
279 }
280 tcg_gen_movi_tl(cpu_nip, nip);
281 }
282
283 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
284 {
285 TCGv_i32 t0, t1;
286
287 /* These are all synchronous exceptions, we set the PC back to
288 * the faulting instruction
289 */
290 if (ctx->exception == POWERPC_EXCP_NONE) {
291 gen_update_nip(ctx, ctx->base.pc_next - 4);
292 }
293 t0 = tcg_const_i32(excp);
294 t1 = tcg_const_i32(error);
295 gen_helper_raise_exception_err(cpu_env, t0, t1);
296 tcg_temp_free_i32(t0);
297 tcg_temp_free_i32(t1);
298 ctx->exception = (excp);
299 }
300
301 static void gen_exception(DisasContext *ctx, uint32_t excp)
302 {
303 TCGv_i32 t0;
304
305 /* These are all synchronous exceptions, we set the PC back to
306 * the faulting instruction
307 */
308 if (ctx->exception == POWERPC_EXCP_NONE) {
309 gen_update_nip(ctx, ctx->base.pc_next - 4);
310 }
311 t0 = tcg_const_i32(excp);
312 gen_helper_raise_exception(cpu_env, t0);
313 tcg_temp_free_i32(t0);
314 ctx->exception = (excp);
315 }
316
317 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
318 target_ulong nip)
319 {
320 TCGv_i32 t0;
321
322 gen_update_nip(ctx, nip);
323 t0 = tcg_const_i32(excp);
324 gen_helper_raise_exception(cpu_env, t0);
325 tcg_temp_free_i32(t0);
326 ctx->exception = (excp);
327 }
328
329 /* Translates the EXCP_TRACE/BRANCH exceptions used on most PowerPCs to
330 * EXCP_DEBUG, if we are running on cores using the debug enable bit (e.g.
331 * BookE).
332 */
333 static uint32_t gen_prep_dbgex(DisasContext *ctx, uint32_t excp)
334 {
335 if ((ctx->singlestep_enabled & CPU_SINGLE_STEP)
336 && (excp == POWERPC_EXCP_BRANCH)) {
337 /* Trace excpt. has priority */
338 excp = POWERPC_EXCP_TRACE;
339 }
340 if (ctx->flags & POWERPC_FLAG_DE) {
341 target_ulong dbsr = 0;
342 switch (excp) {
343 case POWERPC_EXCP_TRACE:
344 dbsr = DBCR0_ICMP;
345 break;
346 case POWERPC_EXCP_BRANCH:
347 dbsr = DBCR0_BRT;
348 break;
349 }
350 TCGv t0 = tcg_temp_new();
351 gen_load_spr(t0, SPR_BOOKE_DBSR);
352 tcg_gen_ori_tl(t0, t0, dbsr);
353 gen_store_spr(SPR_BOOKE_DBSR, t0);
354 tcg_temp_free(t0);
355 return POWERPC_EXCP_DEBUG;
356 } else {
357 return excp;
358 }
359 }
360
361 static void gen_debug_exception(DisasContext *ctx)
362 {
363 TCGv_i32 t0;
364
365 /* These are all synchronous exceptions, we set the PC back to
366 * the faulting instruction
367 */
368 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
369 (ctx->exception != POWERPC_EXCP_SYNC)) {
370 gen_update_nip(ctx, ctx->base.pc_next);
371 }
372 t0 = tcg_const_i32(EXCP_DEBUG);
373 gen_helper_raise_exception(cpu_env, t0);
374 tcg_temp_free_i32(t0);
375 }
376
377 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
378 {
379 /* Will be converted to program check if needed */
380 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
381 }
382
383 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
384 {
385 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
386 }
387
388 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
389 {
390 /* Will be converted to program check if needed */
391 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
392 }
393
394 /* Stop translation */
395 static inline void gen_stop_exception(DisasContext *ctx)
396 {
397 gen_update_nip(ctx, ctx->base.pc_next);
398 ctx->exception = POWERPC_EXCP_STOP;
399 }
400
401 #ifndef CONFIG_USER_ONLY
402 /* No need to update nip here, as execution flow will change */
403 static inline void gen_sync_exception(DisasContext *ctx)
404 {
405 ctx->exception = POWERPC_EXCP_SYNC;
406 }
407 #endif
408
409 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
410 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
411
412 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
413 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
414
415 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
416 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
417
418 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
419 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
420
421 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
422 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
423
424 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
425 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
426
427 typedef struct opcode_t {
428 unsigned char opc1, opc2, opc3, opc4;
429 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
430 unsigned char pad[4];
431 #endif
432 opc_handler_t handler;
433 const char *oname;
434 } opcode_t;
435
436 /* Helpers for priv. check */
437 #define GEN_PRIV \
438 do { \
439 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
440 } while (0)
441
442 #if defined(CONFIG_USER_ONLY)
443 #define CHK_HV GEN_PRIV
444 #define CHK_SV GEN_PRIV
445 #define CHK_HVRM GEN_PRIV
446 #else
447 #define CHK_HV \
448 do { \
449 if (unlikely(ctx->pr || !ctx->hv)) { \
450 GEN_PRIV; \
451 } \
452 } while (0)
453 #define CHK_SV \
454 do { \
455 if (unlikely(ctx->pr)) { \
456 GEN_PRIV; \
457 } \
458 } while (0)
459 #define CHK_HVRM \
460 do { \
461 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
462 GEN_PRIV; \
463 } \
464 } while (0)
465 #endif
466
467 #define CHK_NONE
468
469 /*****************************************************************************/
470 /* PowerPC instructions table */
471
472 #if defined(DO_PPC_STATISTICS)
473 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
474 { \
475 .opc1 = op1, \
476 .opc2 = op2, \
477 .opc3 = op3, \
478 .opc4 = 0xff, \
479 .handler = { \
480 .inval1 = invl, \
481 .type = _typ, \
482 .type2 = _typ2, \
483 .handler = &gen_##name, \
484 .oname = stringify(name), \
485 }, \
486 .oname = stringify(name), \
487 }
488 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
489 { \
490 .opc1 = op1, \
491 .opc2 = op2, \
492 .opc3 = op3, \
493 .opc4 = 0xff, \
494 .handler = { \
495 .inval1 = invl1, \
496 .inval2 = invl2, \
497 .type = _typ, \
498 .type2 = _typ2, \
499 .handler = &gen_##name, \
500 .oname = stringify(name), \
501 }, \
502 .oname = stringify(name), \
503 }
504 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
505 { \
506 .opc1 = op1, \
507 .opc2 = op2, \
508 .opc3 = op3, \
509 .opc4 = 0xff, \
510 .handler = { \
511 .inval1 = invl, \
512 .type = _typ, \
513 .type2 = _typ2, \
514 .handler = &gen_##name, \
515 .oname = onam, \
516 }, \
517 .oname = onam, \
518 }
519 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .opc4 = op4, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 .oname = stringify(name), \
531 }, \
532 .oname = stringify(name), \
533 }
534 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
535 { \
536 .opc1 = op1, \
537 .opc2 = op2, \
538 .opc3 = op3, \
539 .opc4 = op4, \
540 .handler = { \
541 .inval1 = invl, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 .oname = onam, \
546 }, \
547 .oname = onam, \
548 }
549 #else
550 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
551 { \
552 .opc1 = op1, \
553 .opc2 = op2, \
554 .opc3 = op3, \
555 .opc4 = 0xff, \
556 .handler = { \
557 .inval1 = invl, \
558 .type = _typ, \
559 .type2 = _typ2, \
560 .handler = &gen_##name, \
561 }, \
562 .oname = stringify(name), \
563 }
564 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
565 { \
566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
569 .opc4 = 0xff, \
570 .handler = { \
571 .inval1 = invl1, \
572 .inval2 = invl2, \
573 .type = _typ, \
574 .type2 = _typ2, \
575 .handler = &gen_##name, \
576 }, \
577 .oname = stringify(name), \
578 }
579 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
580 { \
581 .opc1 = op1, \
582 .opc2 = op2, \
583 .opc3 = op3, \
584 .opc4 = 0xff, \
585 .handler = { \
586 .inval1 = invl, \
587 .type = _typ, \
588 .type2 = _typ2, \
589 .handler = &gen_##name, \
590 }, \
591 .oname = onam, \
592 }
593 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
594 { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .opc4 = op4, \
599 .handler = { \
600 .inval1 = invl, \
601 .type = _typ, \
602 .type2 = _typ2, \
603 .handler = &gen_##name, \
604 }, \
605 .oname = stringify(name), \
606 }
607 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
608 { \
609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
612 .opc4 = op4, \
613 .handler = { \
614 .inval1 = invl, \
615 .type = _typ, \
616 .type2 = _typ2, \
617 .handler = &gen_##name, \
618 }, \
619 .oname = onam, \
620 }
621 #endif
622
623 /* Invalid instruction */
624 static void gen_invalid(DisasContext *ctx)
625 {
626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
627 }
628
629 static opc_handler_t invalid_handler = {
630 .inval1 = 0xFFFFFFFF,
631 .inval2 = 0xFFFFFFFF,
632 .type = PPC_NONE,
633 .type2 = PPC_NONE,
634 .handler = gen_invalid,
635 };
636
637 /*** Integer comparison ***/
638
639 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
640 {
641 TCGv t0 = tcg_temp_new();
642 TCGv t1 = tcg_temp_new();
643 TCGv_i32 t = tcg_temp_new_i32();
644
645 tcg_gen_movi_tl(t0, CRF_EQ);
646 tcg_gen_movi_tl(t1, CRF_LT);
647 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
648 tcg_gen_movi_tl(t1, CRF_GT);
649 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
650
651 tcg_gen_trunc_tl_i32(t, t0);
652 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
653 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
654
655 tcg_temp_free(t0);
656 tcg_temp_free(t1);
657 tcg_temp_free_i32(t);
658 }
659
660 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
661 {
662 TCGv t0 = tcg_const_tl(arg1);
663 gen_op_cmp(arg0, t0, s, crf);
664 tcg_temp_free(t0);
665 }
666
667 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
668 {
669 TCGv t0, t1;
670 t0 = tcg_temp_new();
671 t1 = tcg_temp_new();
672 if (s) {
673 tcg_gen_ext32s_tl(t0, arg0);
674 tcg_gen_ext32s_tl(t1, arg1);
675 } else {
676 tcg_gen_ext32u_tl(t0, arg0);
677 tcg_gen_ext32u_tl(t1, arg1);
678 }
679 gen_op_cmp(t0, t1, s, crf);
680 tcg_temp_free(t1);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
685 {
686 TCGv t0 = tcg_const_tl(arg1);
687 gen_op_cmp32(arg0, t0, s, crf);
688 tcg_temp_free(t0);
689 }
690
691 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
692 {
693 if (NARROW_MODE(ctx)) {
694 gen_op_cmpi32(reg, 0, 1, 0);
695 } else {
696 gen_op_cmpi(reg, 0, 1, 0);
697 }
698 }
699
700 /* cmp */
701 static void gen_cmp(DisasContext *ctx)
702 {
703 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
704 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
705 1, crfD(ctx->opcode));
706 } else {
707 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
708 1, crfD(ctx->opcode));
709 }
710 }
711
712 /* cmpi */
713 static void gen_cmpi(DisasContext *ctx)
714 {
715 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
716 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
717 1, crfD(ctx->opcode));
718 } else {
719 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
720 1, crfD(ctx->opcode));
721 }
722 }
723
724 /* cmpl */
725 static void gen_cmpl(DisasContext *ctx)
726 {
727 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
728 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
729 0, crfD(ctx->opcode));
730 } else {
731 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
732 0, crfD(ctx->opcode));
733 }
734 }
735
736 /* cmpli */
737 static void gen_cmpli(DisasContext *ctx)
738 {
739 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
740 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
741 0, crfD(ctx->opcode));
742 } else {
743 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
744 0, crfD(ctx->opcode));
745 }
746 }
747
748 /* cmprb - range comparison: isupper, isaplha, islower*/
749 static void gen_cmprb(DisasContext *ctx)
750 {
751 TCGv_i32 src1 = tcg_temp_new_i32();
752 TCGv_i32 src2 = tcg_temp_new_i32();
753 TCGv_i32 src2lo = tcg_temp_new_i32();
754 TCGv_i32 src2hi = tcg_temp_new_i32();
755 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
756
757 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
758 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
759
760 tcg_gen_andi_i32(src1, src1, 0xFF);
761 tcg_gen_ext8u_i32(src2lo, src2);
762 tcg_gen_shri_i32(src2, src2, 8);
763 tcg_gen_ext8u_i32(src2hi, src2);
764
765 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
766 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
767 tcg_gen_and_i32(crf, src2lo, src2hi);
768
769 if (ctx->opcode & 0x00200000) {
770 tcg_gen_shri_i32(src2, src2, 8);
771 tcg_gen_ext8u_i32(src2lo, src2);
772 tcg_gen_shri_i32(src2, src2, 8);
773 tcg_gen_ext8u_i32(src2hi, src2);
774 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
775 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
776 tcg_gen_and_i32(src2lo, src2lo, src2hi);
777 tcg_gen_or_i32(crf, crf, src2lo);
778 }
779 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
780 tcg_temp_free_i32(src1);
781 tcg_temp_free_i32(src2);
782 tcg_temp_free_i32(src2lo);
783 tcg_temp_free_i32(src2hi);
784 }
785
786 #if defined(TARGET_PPC64)
787 /* cmpeqb */
788 static void gen_cmpeqb(DisasContext *ctx)
789 {
790 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
791 cpu_gpr[rB(ctx->opcode)]);
792 }
793 #endif
794
795 /* isel (PowerPC 2.03 specification) */
796 static void gen_isel(DisasContext *ctx)
797 {
798 uint32_t bi = rC(ctx->opcode);
799 uint32_t mask = 0x08 >> (bi & 0x03);
800 TCGv t0 = tcg_temp_new();
801 TCGv zr;
802
803 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
804 tcg_gen_andi_tl(t0, t0, mask);
805
806 zr = tcg_const_tl(0);
807 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
808 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
809 cpu_gpr[rB(ctx->opcode)]);
810 tcg_temp_free(zr);
811 tcg_temp_free(t0);
812 }
813
814 /* cmpb: PowerPC 2.05 specification */
815 static void gen_cmpb(DisasContext *ctx)
816 {
817 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
818 cpu_gpr[rB(ctx->opcode)]);
819 }
820
821 /*** Integer arithmetic ***/
822
823 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
824 TCGv arg1, TCGv arg2, int sub)
825 {
826 TCGv t0 = tcg_temp_new();
827
828 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
829 tcg_gen_xor_tl(t0, arg1, arg2);
830 if (sub) {
831 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
832 } else {
833 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
834 }
835 tcg_temp_free(t0);
836 if (NARROW_MODE(ctx)) {
837 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
838 if (is_isa300(ctx)) {
839 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
840 }
841 } else {
842 if (is_isa300(ctx)) {
843 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
844 }
845 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
846 }
847 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
848 }
849
850 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
851 TCGv res, TCGv arg0, TCGv arg1,
852 int sub)
853 {
854 TCGv t0;
855
856 if (!is_isa300(ctx)) {
857 return;
858 }
859
860 t0 = tcg_temp_new();
861 if (sub) {
862 tcg_gen_eqv_tl(t0, arg0, arg1);
863 } else {
864 tcg_gen_xor_tl(t0, arg0, arg1);
865 }
866 tcg_gen_xor_tl(t0, t0, res);
867 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
868 tcg_temp_free(t0);
869 }
870
871 /* Common add function */
872 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
873 TCGv arg2, bool add_ca, bool compute_ca,
874 bool compute_ov, bool compute_rc0)
875 {
876 TCGv t0 = ret;
877
878 if (compute_ca || compute_ov) {
879 t0 = tcg_temp_new();
880 }
881
882 if (compute_ca) {
883 if (NARROW_MODE(ctx)) {
884 /* Caution: a non-obvious corner case of the spec is that we
885 must produce the *entire* 64-bit addition, but produce the
886 carry into bit 32. */
887 TCGv t1 = tcg_temp_new();
888 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
889 tcg_gen_add_tl(t0, arg1, arg2);
890 if (add_ca) {
891 tcg_gen_add_tl(t0, t0, cpu_ca);
892 }
893 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
894 tcg_temp_free(t1);
895 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
896 if (is_isa300(ctx)) {
897 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
898 }
899 } else {
900 TCGv zero = tcg_const_tl(0);
901 if (add_ca) {
902 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
903 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
904 } else {
905 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
906 }
907 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
908 tcg_temp_free(zero);
909 }
910 } else {
911 tcg_gen_add_tl(t0, arg1, arg2);
912 if (add_ca) {
913 tcg_gen_add_tl(t0, t0, cpu_ca);
914 }
915 }
916
917 if (compute_ov) {
918 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
919 }
920 if (unlikely(compute_rc0)) {
921 gen_set_Rc0(ctx, t0);
922 }
923
924 if (t0 != ret) {
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 }
928 }
929 /* Add functions with two operands */
930 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
931 static void glue(gen_, name)(DisasContext *ctx) \
932 { \
933 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
934 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
935 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
936 }
937 /* Add functions with one operand and one immediate */
938 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
939 add_ca, compute_ca, compute_ov) \
940 static void glue(gen_, name)(DisasContext *ctx) \
941 { \
942 TCGv t0 = tcg_const_tl(const_val); \
943 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
944 cpu_gpr[rA(ctx->opcode)], t0, \
945 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
946 tcg_temp_free(t0); \
947 }
948
949 /* add add. addo addo. */
950 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
951 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
952 /* addc addc. addco addco. */
953 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
954 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
955 /* adde adde. addeo addeo. */
956 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
957 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
958 /* addme addme. addmeo addmeo. */
959 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
960 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
961 /* addze addze. addzeo addzeo.*/
962 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
963 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
964 /* addi */
965 static void gen_addi(DisasContext *ctx)
966 {
967 target_long simm = SIMM(ctx->opcode);
968
969 if (rA(ctx->opcode) == 0) {
970 /* li case */
971 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
972 } else {
973 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
974 cpu_gpr[rA(ctx->opcode)], simm);
975 }
976 }
977 /* addic addic.*/
978 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
979 {
980 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
981 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
982 c, 0, 1, 0, compute_rc0);
983 tcg_temp_free(c);
984 }
985
986 static void gen_addic(DisasContext *ctx)
987 {
988 gen_op_addic(ctx, 0);
989 }
990
991 static void gen_addic_(DisasContext *ctx)
992 {
993 gen_op_addic(ctx, 1);
994 }
995
996 /* addis */
997 static void gen_addis(DisasContext *ctx)
998 {
999 target_long simm = SIMM(ctx->opcode);
1000
1001 if (rA(ctx->opcode) == 0) {
1002 /* lis case */
1003 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1004 } else {
1005 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1006 cpu_gpr[rA(ctx->opcode)], simm << 16);
1007 }
1008 }
1009
1010 /* addpcis */
1011 static void gen_addpcis(DisasContext *ctx)
1012 {
1013 target_long d = DX(ctx->opcode);
1014
1015 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
1016 }
1017
1018 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1019 TCGv arg2, int sign, int compute_ov)
1020 {
1021 TCGv_i32 t0 = tcg_temp_new_i32();
1022 TCGv_i32 t1 = tcg_temp_new_i32();
1023 TCGv_i32 t2 = tcg_temp_new_i32();
1024 TCGv_i32 t3 = tcg_temp_new_i32();
1025
1026 tcg_gen_trunc_tl_i32(t0, arg1);
1027 tcg_gen_trunc_tl_i32(t1, arg2);
1028 if (sign) {
1029 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1030 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1031 tcg_gen_and_i32(t2, t2, t3);
1032 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1033 tcg_gen_or_i32(t2, t2, t3);
1034 tcg_gen_movi_i32(t3, 0);
1035 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1036 tcg_gen_div_i32(t3, t0, t1);
1037 tcg_gen_extu_i32_tl(ret, t3);
1038 } else {
1039 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1040 tcg_gen_movi_i32(t3, 0);
1041 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1042 tcg_gen_divu_i32(t3, t0, t1);
1043 tcg_gen_extu_i32_tl(ret, t3);
1044 }
1045 if (compute_ov) {
1046 tcg_gen_extu_i32_tl(cpu_ov, t2);
1047 if (is_isa300(ctx)) {
1048 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1049 }
1050 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1051 }
1052 tcg_temp_free_i32(t0);
1053 tcg_temp_free_i32(t1);
1054 tcg_temp_free_i32(t2);
1055 tcg_temp_free_i32(t3);
1056
1057 if (unlikely(Rc(ctx->opcode) != 0))
1058 gen_set_Rc0(ctx, ret);
1059 }
1060 /* Div functions */
1061 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1062 static void glue(gen_, name)(DisasContext *ctx) \
1063 { \
1064 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1065 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1066 sign, compute_ov); \
1067 }
1068 /* divwu divwu. divwuo divwuo. */
1069 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1070 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1071 /* divw divw. divwo divwo. */
1072 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1073 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1074
1075 /* div[wd]eu[o][.] */
1076 #define GEN_DIVE(name, hlpr, compute_ov) \
1077 static void gen_##name(DisasContext *ctx) \
1078 { \
1079 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1080 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1081 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1082 tcg_temp_free_i32(t0); \
1083 if (unlikely(Rc(ctx->opcode) != 0)) { \
1084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1085 } \
1086 }
1087
1088 GEN_DIVE(divweu, divweu, 0);
1089 GEN_DIVE(divweuo, divweu, 1);
1090 GEN_DIVE(divwe, divwe, 0);
1091 GEN_DIVE(divweo, divwe, 1);
1092
1093 #if defined(TARGET_PPC64)
1094 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1095 TCGv arg2, int sign, int compute_ov)
1096 {
1097 TCGv_i64 t0 = tcg_temp_new_i64();
1098 TCGv_i64 t1 = tcg_temp_new_i64();
1099 TCGv_i64 t2 = tcg_temp_new_i64();
1100 TCGv_i64 t3 = tcg_temp_new_i64();
1101
1102 tcg_gen_mov_i64(t0, arg1);
1103 tcg_gen_mov_i64(t1, arg2);
1104 if (sign) {
1105 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1106 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1107 tcg_gen_and_i64(t2, t2, t3);
1108 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1109 tcg_gen_or_i64(t2, t2, t3);
1110 tcg_gen_movi_i64(t3, 0);
1111 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1112 tcg_gen_div_i64(ret, t0, t1);
1113 } else {
1114 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1115 tcg_gen_movi_i64(t3, 0);
1116 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1117 tcg_gen_divu_i64(ret, t0, t1);
1118 }
1119 if (compute_ov) {
1120 tcg_gen_mov_tl(cpu_ov, t2);
1121 if (is_isa300(ctx)) {
1122 tcg_gen_mov_tl(cpu_ov32, t2);
1123 }
1124 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1125 }
1126 tcg_temp_free_i64(t0);
1127 tcg_temp_free_i64(t1);
1128 tcg_temp_free_i64(t2);
1129 tcg_temp_free_i64(t3);
1130
1131 if (unlikely(Rc(ctx->opcode) != 0))
1132 gen_set_Rc0(ctx, ret);
1133 }
1134
1135 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1136 static void glue(gen_, name)(DisasContext *ctx) \
1137 { \
1138 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1139 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1140 sign, compute_ov); \
1141 }
1142 /* divdu divdu. divduo divduo. */
1143 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1144 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1145 /* divd divd. divdo divdo. */
1146 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1147 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1148
1149 GEN_DIVE(divdeu, divdeu, 0);
1150 GEN_DIVE(divdeuo, divdeu, 1);
1151 GEN_DIVE(divde, divde, 0);
1152 GEN_DIVE(divdeo, divde, 1);
1153 #endif
1154
1155 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1156 TCGv arg2, int sign)
1157 {
1158 TCGv_i32 t0 = tcg_temp_new_i32();
1159 TCGv_i32 t1 = tcg_temp_new_i32();
1160
1161 tcg_gen_trunc_tl_i32(t0, arg1);
1162 tcg_gen_trunc_tl_i32(t1, arg2);
1163 if (sign) {
1164 TCGv_i32 t2 = tcg_temp_new_i32();
1165 TCGv_i32 t3 = tcg_temp_new_i32();
1166 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1167 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1168 tcg_gen_and_i32(t2, t2, t3);
1169 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1170 tcg_gen_or_i32(t2, t2, t3);
1171 tcg_gen_movi_i32(t3, 0);
1172 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1173 tcg_gen_rem_i32(t3, t0, t1);
1174 tcg_gen_ext_i32_tl(ret, t3);
1175 tcg_temp_free_i32(t2);
1176 tcg_temp_free_i32(t3);
1177 } else {
1178 TCGv_i32 t2 = tcg_const_i32(1);
1179 TCGv_i32 t3 = tcg_const_i32(0);
1180 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1181 tcg_gen_remu_i32(t3, t0, t1);
1182 tcg_gen_extu_i32_tl(ret, t3);
1183 tcg_temp_free_i32(t2);
1184 tcg_temp_free_i32(t3);
1185 }
1186 tcg_temp_free_i32(t0);
1187 tcg_temp_free_i32(t1);
1188 }
1189
1190 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1191 static void glue(gen_, name)(DisasContext *ctx) \
1192 { \
1193 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1194 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1195 sign); \
1196 }
1197
1198 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1199 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1200
1201 #if defined(TARGET_PPC64)
1202 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1203 TCGv arg2, int sign)
1204 {
1205 TCGv_i64 t0 = tcg_temp_new_i64();
1206 TCGv_i64 t1 = tcg_temp_new_i64();
1207
1208 tcg_gen_mov_i64(t0, arg1);
1209 tcg_gen_mov_i64(t1, arg2);
1210 if (sign) {
1211 TCGv_i64 t2 = tcg_temp_new_i64();
1212 TCGv_i64 t3 = tcg_temp_new_i64();
1213 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1214 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1215 tcg_gen_and_i64(t2, t2, t3);
1216 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1217 tcg_gen_or_i64(t2, t2, t3);
1218 tcg_gen_movi_i64(t3, 0);
1219 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1220 tcg_gen_rem_i64(ret, t0, t1);
1221 tcg_temp_free_i64(t2);
1222 tcg_temp_free_i64(t3);
1223 } else {
1224 TCGv_i64 t2 = tcg_const_i64(1);
1225 TCGv_i64 t3 = tcg_const_i64(0);
1226 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1227 tcg_gen_remu_i64(ret, t0, t1);
1228 tcg_temp_free_i64(t2);
1229 tcg_temp_free_i64(t3);
1230 }
1231 tcg_temp_free_i64(t0);
1232 tcg_temp_free_i64(t1);
1233 }
1234
1235 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1236 static void glue(gen_, name)(DisasContext *ctx) \
1237 { \
1238 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1239 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1240 sign); \
1241 }
1242
1243 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1244 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1245 #endif
1246
1247 /* mulhw mulhw. */
1248 static void gen_mulhw(DisasContext *ctx)
1249 {
1250 TCGv_i32 t0 = tcg_temp_new_i32();
1251 TCGv_i32 t1 = tcg_temp_new_i32();
1252
1253 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1254 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1255 tcg_gen_muls2_i32(t0, t1, t0, t1);
1256 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1257 tcg_temp_free_i32(t0);
1258 tcg_temp_free_i32(t1);
1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1261 }
1262
1263 /* mulhwu mulhwu. */
1264 static void gen_mulhwu(DisasContext *ctx)
1265 {
1266 TCGv_i32 t0 = tcg_temp_new_i32();
1267 TCGv_i32 t1 = tcg_temp_new_i32();
1268
1269 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1270 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1271 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1272 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1273 tcg_temp_free_i32(t0);
1274 tcg_temp_free_i32(t1);
1275 if (unlikely(Rc(ctx->opcode) != 0))
1276 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1277 }
1278
1279 /* mullw mullw. */
1280 static void gen_mullw(DisasContext *ctx)
1281 {
1282 #if defined(TARGET_PPC64)
1283 TCGv_i64 t0, t1;
1284 t0 = tcg_temp_new_i64();
1285 t1 = tcg_temp_new_i64();
1286 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1287 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1288 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1289 tcg_temp_free(t0);
1290 tcg_temp_free(t1);
1291 #else
1292 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1293 cpu_gpr[rB(ctx->opcode)]);
1294 #endif
1295 if (unlikely(Rc(ctx->opcode) != 0))
1296 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1297 }
1298
1299 /* mullwo mullwo. */
1300 static void gen_mullwo(DisasContext *ctx)
1301 {
1302 TCGv_i32 t0 = tcg_temp_new_i32();
1303 TCGv_i32 t1 = tcg_temp_new_i32();
1304
1305 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1306 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1307 tcg_gen_muls2_i32(t0, t1, t0, t1);
1308 #if defined(TARGET_PPC64)
1309 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1310 #else
1311 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1312 #endif
1313
1314 tcg_gen_sari_i32(t0, t0, 31);
1315 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1316 tcg_gen_extu_i32_tl(cpu_ov, t0);
1317 if (is_isa300(ctx)) {
1318 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1319 }
1320 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1321
1322 tcg_temp_free_i32(t0);
1323 tcg_temp_free_i32(t1);
1324 if (unlikely(Rc(ctx->opcode) != 0))
1325 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1326 }
1327
1328 /* mulli */
1329 static void gen_mulli(DisasContext *ctx)
1330 {
1331 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1332 SIMM(ctx->opcode));
1333 }
1334
1335 #if defined(TARGET_PPC64)
1336 /* mulhd mulhd. */
1337 static void gen_mulhd(DisasContext *ctx)
1338 {
1339 TCGv lo = tcg_temp_new();
1340 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1341 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1342 tcg_temp_free(lo);
1343 if (unlikely(Rc(ctx->opcode) != 0)) {
1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1345 }
1346 }
1347
1348 /* mulhdu mulhdu. */
1349 static void gen_mulhdu(DisasContext *ctx)
1350 {
1351 TCGv lo = tcg_temp_new();
1352 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1353 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1354 tcg_temp_free(lo);
1355 if (unlikely(Rc(ctx->opcode) != 0)) {
1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1357 }
1358 }
1359
1360 /* mulld mulld. */
1361 static void gen_mulld(DisasContext *ctx)
1362 {
1363 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 cpu_gpr[rB(ctx->opcode)]);
1365 if (unlikely(Rc(ctx->opcode) != 0))
1366 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1367 }
1368
1369 /* mulldo mulldo. */
1370 static void gen_mulldo(DisasContext *ctx)
1371 {
1372 TCGv_i64 t0 = tcg_temp_new_i64();
1373 TCGv_i64 t1 = tcg_temp_new_i64();
1374
1375 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1376 cpu_gpr[rB(ctx->opcode)]);
1377 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1378
1379 tcg_gen_sari_i64(t0, t0, 63);
1380 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1381 if (is_isa300(ctx)) {
1382 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1383 }
1384 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1385
1386 tcg_temp_free_i64(t0);
1387 tcg_temp_free_i64(t1);
1388
1389 if (unlikely(Rc(ctx->opcode) != 0)) {
1390 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1391 }
1392 }
1393 #endif
1394
1395 /* Common subf function */
1396 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1397 TCGv arg2, bool add_ca, bool compute_ca,
1398 bool compute_ov, bool compute_rc0)
1399 {
1400 TCGv t0 = ret;
1401
1402 if (compute_ca || compute_ov) {
1403 t0 = tcg_temp_new();
1404 }
1405
1406 if (compute_ca) {
1407 /* dest = ~arg1 + arg2 [+ ca]. */
1408 if (NARROW_MODE(ctx)) {
1409 /* Caution: a non-obvious corner case of the spec is that we
1410 must produce the *entire* 64-bit addition, but produce the
1411 carry into bit 32. */
1412 TCGv inv1 = tcg_temp_new();
1413 TCGv t1 = tcg_temp_new();
1414 tcg_gen_not_tl(inv1, arg1);
1415 if (add_ca) {
1416 tcg_gen_add_tl(t0, arg2, cpu_ca);
1417 } else {
1418 tcg_gen_addi_tl(t0, arg2, 1);
1419 }
1420 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1421 tcg_gen_add_tl(t0, t0, inv1);
1422 tcg_temp_free(inv1);
1423 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1424 tcg_temp_free(t1);
1425 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1426 if (is_isa300(ctx)) {
1427 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1428 }
1429 } else if (add_ca) {
1430 TCGv zero, inv1 = tcg_temp_new();
1431 tcg_gen_not_tl(inv1, arg1);
1432 zero = tcg_const_tl(0);
1433 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1434 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1435 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1436 tcg_temp_free(zero);
1437 tcg_temp_free(inv1);
1438 } else {
1439 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1440 tcg_gen_sub_tl(t0, arg2, arg1);
1441 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1442 }
1443 } else if (add_ca) {
1444 /* Since we're ignoring carry-out, we can simplify the
1445 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1446 tcg_gen_sub_tl(t0, arg2, arg1);
1447 tcg_gen_add_tl(t0, t0, cpu_ca);
1448 tcg_gen_subi_tl(t0, t0, 1);
1449 } else {
1450 tcg_gen_sub_tl(t0, arg2, arg1);
1451 }
1452
1453 if (compute_ov) {
1454 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1455 }
1456 if (unlikely(compute_rc0)) {
1457 gen_set_Rc0(ctx, t0);
1458 }
1459
1460 if (t0 != ret) {
1461 tcg_gen_mov_tl(ret, t0);
1462 tcg_temp_free(t0);
1463 }
1464 }
1465 /* Sub functions with Two operands functions */
1466 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1467 static void glue(gen_, name)(DisasContext *ctx) \
1468 { \
1469 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1470 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1471 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1472 }
1473 /* Sub functions with one operand and one immediate */
1474 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1475 add_ca, compute_ca, compute_ov) \
1476 static void glue(gen_, name)(DisasContext *ctx) \
1477 { \
1478 TCGv t0 = tcg_const_tl(const_val); \
1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1480 cpu_gpr[rA(ctx->opcode)], t0, \
1481 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1482 tcg_temp_free(t0); \
1483 }
1484 /* subf subf. subfo subfo. */
1485 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1486 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1487 /* subfc subfc. subfco subfco. */
1488 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1489 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1490 /* subfe subfe. subfeo subfo. */
1491 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1492 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1493 /* subfme subfme. subfmeo subfmeo. */
1494 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1495 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1496 /* subfze subfze. subfzeo subfzeo.*/
1497 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1498 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1499
1500 /* subfic */
1501 static void gen_subfic(DisasContext *ctx)
1502 {
1503 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1504 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1505 c, 0, 1, 0, 0);
1506 tcg_temp_free(c);
1507 }
1508
1509 /* neg neg. nego nego. */
1510 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1511 {
1512 TCGv zero = tcg_const_tl(0);
1513 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1514 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1515 tcg_temp_free(zero);
1516 }
1517
1518 static void gen_neg(DisasContext *ctx)
1519 {
1520 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1521 if (unlikely(Rc(ctx->opcode))) {
1522 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1523 }
1524 }
1525
1526 static void gen_nego(DisasContext *ctx)
1527 {
1528 gen_op_arith_neg(ctx, 1);
1529 }
1530
1531 /*** Integer logical ***/
1532 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1533 static void glue(gen_, name)(DisasContext *ctx) \
1534 { \
1535 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1536 cpu_gpr[rB(ctx->opcode)]); \
1537 if (unlikely(Rc(ctx->opcode) != 0)) \
1538 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1539 }
1540
1541 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1542 static void glue(gen_, name)(DisasContext *ctx) \
1543 { \
1544 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1545 if (unlikely(Rc(ctx->opcode) != 0)) \
1546 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1547 }
1548
1549 /* and & and. */
1550 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1551 /* andc & andc. */
1552 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1553
1554 /* andi. */
1555 static void gen_andi_(DisasContext *ctx)
1556 {
1557 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1558 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1559 }
1560
1561 /* andis. */
1562 static void gen_andis_(DisasContext *ctx)
1563 {
1564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1566 }
1567
1568 /* cntlzw */
1569 static void gen_cntlzw(DisasContext *ctx)
1570 {
1571 TCGv_i32 t = tcg_temp_new_i32();
1572
1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1574 tcg_gen_clzi_i32(t, t, 32);
1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1576 tcg_temp_free_i32(t);
1577
1578 if (unlikely(Rc(ctx->opcode) != 0))
1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1580 }
1581
1582 /* cnttzw */
1583 static void gen_cnttzw(DisasContext *ctx)
1584 {
1585 TCGv_i32 t = tcg_temp_new_i32();
1586
1587 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1588 tcg_gen_ctzi_i32(t, t, 32);
1589 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1590 tcg_temp_free_i32(t);
1591
1592 if (unlikely(Rc(ctx->opcode) != 0)) {
1593 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1594 }
1595 }
1596
1597 /* eqv & eqv. */
1598 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1599 /* extsb & extsb. */
1600 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1601 /* extsh & extsh. */
1602 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1603 /* nand & nand. */
1604 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1605 /* nor & nor. */
1606 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1607
1608 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1609 static void gen_pause(DisasContext *ctx)
1610 {
1611 TCGv_i32 t0 = tcg_const_i32(0);
1612 tcg_gen_st_i32(t0, cpu_env,
1613 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1614 tcg_temp_free_i32(t0);
1615
1616 /* Stop translation, this gives other CPUs a chance to run */
1617 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1618 }
1619 #endif /* defined(TARGET_PPC64) */
1620
1621 /* or & or. */
1622 static void gen_or(DisasContext *ctx)
1623 {
1624 int rs, ra, rb;
1625
1626 rs = rS(ctx->opcode);
1627 ra = rA(ctx->opcode);
1628 rb = rB(ctx->opcode);
1629 /* Optimisation for mr. ri case */
1630 if (rs != ra || rs != rb) {
1631 if (rs != rb)
1632 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1633 else
1634 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1635 if (unlikely(Rc(ctx->opcode) != 0))
1636 gen_set_Rc0(ctx, cpu_gpr[ra]);
1637 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1638 gen_set_Rc0(ctx, cpu_gpr[rs]);
1639 #if defined(TARGET_PPC64)
1640 } else if (rs != 0) { /* 0 is nop */
1641 int prio = 0;
1642
1643 switch (rs) {
1644 case 1:
1645 /* Set process priority to low */
1646 prio = 2;
1647 break;
1648 case 6:
1649 /* Set process priority to medium-low */
1650 prio = 3;
1651 break;
1652 case 2:
1653 /* Set process priority to normal */
1654 prio = 4;
1655 break;
1656 #if !defined(CONFIG_USER_ONLY)
1657 case 31:
1658 if (!ctx->pr) {
1659 /* Set process priority to very low */
1660 prio = 1;
1661 }
1662 break;
1663 case 5:
1664 if (!ctx->pr) {
1665 /* Set process priority to medium-hight */
1666 prio = 5;
1667 }
1668 break;
1669 case 3:
1670 if (!ctx->pr) {
1671 /* Set process priority to high */
1672 prio = 6;
1673 }
1674 break;
1675 case 7:
1676 if (ctx->hv && !ctx->pr) {
1677 /* Set process priority to very high */
1678 prio = 7;
1679 }
1680 break;
1681 #endif
1682 default:
1683 break;
1684 }
1685 if (prio) {
1686 TCGv t0 = tcg_temp_new();
1687 gen_load_spr(t0, SPR_PPR);
1688 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1689 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1690 gen_store_spr(SPR_PPR, t0);
1691 tcg_temp_free(t0);
1692 }
1693 #if !defined(CONFIG_USER_ONLY)
1694 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1695 * CPU and the kernel hangs. This applies to all encodings other
1696 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1697 * and all currently undefined.
1698 */
1699 gen_pause(ctx);
1700 #endif
1701 #endif
1702 }
1703 }
1704 /* orc & orc. */
1705 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1706
1707 /* xor & xor. */
1708 static void gen_xor(DisasContext *ctx)
1709 {
1710 /* Optimisation for "set to zero" case */
1711 if (rS(ctx->opcode) != rB(ctx->opcode))
1712 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1713 else
1714 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1715 if (unlikely(Rc(ctx->opcode) != 0))
1716 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1717 }
1718
1719 /* ori */
1720 static void gen_ori(DisasContext *ctx)
1721 {
1722 target_ulong uimm = UIMM(ctx->opcode);
1723
1724 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1725 return;
1726 }
1727 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1728 }
1729
1730 /* oris */
1731 static void gen_oris(DisasContext *ctx)
1732 {
1733 target_ulong uimm = UIMM(ctx->opcode);
1734
1735 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1736 /* NOP */
1737 return;
1738 }
1739 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1740 }
1741
1742 /* xori */
1743 static void gen_xori(DisasContext *ctx)
1744 {
1745 target_ulong uimm = UIMM(ctx->opcode);
1746
1747 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1748 /* NOP */
1749 return;
1750 }
1751 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1752 }
1753
1754 /* xoris */
1755 static void gen_xoris(DisasContext *ctx)
1756 {
1757 target_ulong uimm = UIMM(ctx->opcode);
1758
1759 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1760 /* NOP */
1761 return;
1762 }
1763 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1764 }
1765
1766 /* popcntb : PowerPC 2.03 specification */
1767 static void gen_popcntb(DisasContext *ctx)
1768 {
1769 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1770 }
1771
1772 static void gen_popcntw(DisasContext *ctx)
1773 {
1774 #if defined(TARGET_PPC64)
1775 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1776 #else
1777 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1778 #endif
1779 }
1780
1781 #if defined(TARGET_PPC64)
1782 /* popcntd: PowerPC 2.06 specification */
1783 static void gen_popcntd(DisasContext *ctx)
1784 {
1785 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1786 }
1787 #endif
1788
1789 /* prtyw: PowerPC 2.05 specification */
1790 static void gen_prtyw(DisasContext *ctx)
1791 {
1792 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1793 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1794 TCGv t0 = tcg_temp_new();
1795 tcg_gen_shri_tl(t0, rs, 16);
1796 tcg_gen_xor_tl(ra, rs, t0);
1797 tcg_gen_shri_tl(t0, ra, 8);
1798 tcg_gen_xor_tl(ra, ra, t0);
1799 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1800 tcg_temp_free(t0);
1801 }
1802
1803 #if defined(TARGET_PPC64)
1804 /* prtyd: PowerPC 2.05 specification */
1805 static void gen_prtyd(DisasContext *ctx)
1806 {
1807 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1808 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1809 TCGv t0 = tcg_temp_new();
1810 tcg_gen_shri_tl(t0, rs, 32);
1811 tcg_gen_xor_tl(ra, rs, t0);
1812 tcg_gen_shri_tl(t0, ra, 16);
1813 tcg_gen_xor_tl(ra, ra, t0);
1814 tcg_gen_shri_tl(t0, ra, 8);
1815 tcg_gen_xor_tl(ra, ra, t0);
1816 tcg_gen_andi_tl(ra, ra, 1);
1817 tcg_temp_free(t0);
1818 }
1819 #endif
1820
1821 #if defined(TARGET_PPC64)
1822 /* bpermd */
1823 static void gen_bpermd(DisasContext *ctx)
1824 {
1825 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1826 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1827 }
1828 #endif
1829
1830 #if defined(TARGET_PPC64)
1831 /* extsw & extsw. */
1832 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1833
1834 /* cntlzd */
1835 static void gen_cntlzd(DisasContext *ctx)
1836 {
1837 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1838 if (unlikely(Rc(ctx->opcode) != 0))
1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1840 }
1841
1842 /* cnttzd */
1843 static void gen_cnttzd(DisasContext *ctx)
1844 {
1845 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1846 if (unlikely(Rc(ctx->opcode) != 0)) {
1847 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1848 }
1849 }
1850
1851 /* darn */
1852 static void gen_darn(DisasContext *ctx)
1853 {
1854 int l = L(ctx->opcode);
1855
1856 if (l == 0) {
1857 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1858 } else if (l <= 2) {
1859 /* Return 64-bit random for both CRN and RRN */
1860 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1861 } else {
1862 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1863 }
1864 }
1865 #endif
1866
1867 /*** Integer rotate ***/
1868
1869 /* rlwimi & rlwimi. */
1870 static void gen_rlwimi(DisasContext *ctx)
1871 {
1872 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1873 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1874 uint32_t sh = SH(ctx->opcode);
1875 uint32_t mb = MB(ctx->opcode);
1876 uint32_t me = ME(ctx->opcode);
1877
1878 if (sh == (31-me) && mb <= me) {
1879 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1880 } else {
1881 target_ulong mask;
1882 TCGv t1;
1883
1884 #if defined(TARGET_PPC64)
1885 mb += 32;
1886 me += 32;
1887 #endif
1888 mask = MASK(mb, me);
1889
1890 t1 = tcg_temp_new();
1891 if (mask <= 0xffffffffu) {
1892 TCGv_i32 t0 = tcg_temp_new_i32();
1893 tcg_gen_trunc_tl_i32(t0, t_rs);
1894 tcg_gen_rotli_i32(t0, t0, sh);
1895 tcg_gen_extu_i32_tl(t1, t0);
1896 tcg_temp_free_i32(t0);
1897 } else {
1898 #if defined(TARGET_PPC64)
1899 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1900 tcg_gen_rotli_i64(t1, t1, sh);
1901 #else
1902 g_assert_not_reached();
1903 #endif
1904 }
1905
1906 tcg_gen_andi_tl(t1, t1, mask);
1907 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1908 tcg_gen_or_tl(t_ra, t_ra, t1);
1909 tcg_temp_free(t1);
1910 }
1911 if (unlikely(Rc(ctx->opcode) != 0)) {
1912 gen_set_Rc0(ctx, t_ra);
1913 }
1914 }
1915
1916 /* rlwinm & rlwinm. */
1917 static void gen_rlwinm(DisasContext *ctx)
1918 {
1919 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1920 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1921 int sh = SH(ctx->opcode);
1922 int mb = MB(ctx->opcode);
1923 int me = ME(ctx->opcode);
1924 int len = me - mb + 1;
1925 int rsh = (32 - sh) & 31;
1926
1927 if (sh != 0 && len > 0 && me == (31 - sh)) {
1928 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1929 } else if (me == 31 && rsh + len <= 32) {
1930 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1931 } else {
1932 target_ulong mask;
1933 #if defined(TARGET_PPC64)
1934 mb += 32;
1935 me += 32;
1936 #endif
1937 mask = MASK(mb, me);
1938 if (sh == 0) {
1939 tcg_gen_andi_tl(t_ra, t_rs, mask);
1940 } else if (mask <= 0xffffffffu) {
1941 TCGv_i32 t0 = tcg_temp_new_i32();
1942 tcg_gen_trunc_tl_i32(t0, t_rs);
1943 tcg_gen_rotli_i32(t0, t0, sh);
1944 tcg_gen_andi_i32(t0, t0, mask);
1945 tcg_gen_extu_i32_tl(t_ra, t0);
1946 tcg_temp_free_i32(t0);
1947 } else {
1948 #if defined(TARGET_PPC64)
1949 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1950 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1951 tcg_gen_andi_i64(t_ra, t_ra, mask);
1952 #else
1953 g_assert_not_reached();
1954 #endif
1955 }
1956 }
1957 if (unlikely(Rc(ctx->opcode) != 0)) {
1958 gen_set_Rc0(ctx, t_ra);
1959 }
1960 }
1961
1962 /* rlwnm & rlwnm. */
1963 static void gen_rlwnm(DisasContext *ctx)
1964 {
1965 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1966 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1967 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1968 uint32_t mb = MB(ctx->opcode);
1969 uint32_t me = ME(ctx->opcode);
1970 target_ulong mask;
1971
1972 #if defined(TARGET_PPC64)
1973 mb += 32;
1974 me += 32;
1975 #endif
1976 mask = MASK(mb, me);
1977
1978 if (mask <= 0xffffffffu) {
1979 TCGv_i32 t0 = tcg_temp_new_i32();
1980 TCGv_i32 t1 = tcg_temp_new_i32();
1981 tcg_gen_trunc_tl_i32(t0, t_rb);
1982 tcg_gen_trunc_tl_i32(t1, t_rs);
1983 tcg_gen_andi_i32(t0, t0, 0x1f);
1984 tcg_gen_rotl_i32(t1, t1, t0);
1985 tcg_gen_extu_i32_tl(t_ra, t1);
1986 tcg_temp_free_i32(t0);
1987 tcg_temp_free_i32(t1);
1988 } else {
1989 #if defined(TARGET_PPC64)
1990 TCGv_i64 t0 = tcg_temp_new_i64();
1991 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1992 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1993 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1994 tcg_temp_free_i64(t0);
1995 #else
1996 g_assert_not_reached();
1997 #endif
1998 }
1999
2000 tcg_gen_andi_tl(t_ra, t_ra, mask);
2001
2002 if (unlikely(Rc(ctx->opcode) != 0)) {
2003 gen_set_Rc0(ctx, t_ra);
2004 }
2005 }
2006
2007 #if defined(TARGET_PPC64)
2008 #define GEN_PPC64_R2(name, opc1, opc2) \
2009 static void glue(gen_, name##0)(DisasContext *ctx) \
2010 { \
2011 gen_##name(ctx, 0); \
2012 } \
2013 \
2014 static void glue(gen_, name##1)(DisasContext *ctx) \
2015 { \
2016 gen_##name(ctx, 1); \
2017 }
2018 #define GEN_PPC64_R4(name, opc1, opc2) \
2019 static void glue(gen_, name##0)(DisasContext *ctx) \
2020 { \
2021 gen_##name(ctx, 0, 0); \
2022 } \
2023 \
2024 static void glue(gen_, name##1)(DisasContext *ctx) \
2025 { \
2026 gen_##name(ctx, 0, 1); \
2027 } \
2028 \
2029 static void glue(gen_, name##2)(DisasContext *ctx) \
2030 { \
2031 gen_##name(ctx, 1, 0); \
2032 } \
2033 \
2034 static void glue(gen_, name##3)(DisasContext *ctx) \
2035 { \
2036 gen_##name(ctx, 1, 1); \
2037 }
2038
2039 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2040 {
2041 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2042 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2043 int len = me - mb + 1;
2044 int rsh = (64 - sh) & 63;
2045
2046 if (sh != 0 && len > 0 && me == (63 - sh)) {
2047 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2048 } else if (me == 63 && rsh + len <= 64) {
2049 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2050 } else {
2051 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2052 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2053 }
2054 if (unlikely(Rc(ctx->opcode) != 0)) {
2055 gen_set_Rc0(ctx, t_ra);
2056 }
2057 }
2058
2059 /* rldicl - rldicl. */
2060 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2061 {
2062 uint32_t sh, mb;
2063
2064 sh = SH(ctx->opcode) | (shn << 5);
2065 mb = MB(ctx->opcode) | (mbn << 5);
2066 gen_rldinm(ctx, mb, 63, sh);
2067 }
2068 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2069
2070 /* rldicr - rldicr. */
2071 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2072 {
2073 uint32_t sh, me;
2074
2075 sh = SH(ctx->opcode) | (shn << 5);
2076 me = MB(ctx->opcode) | (men << 5);
2077 gen_rldinm(ctx, 0, me, sh);
2078 }
2079 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2080
2081 /* rldic - rldic. */
2082 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2083 {
2084 uint32_t sh, mb;
2085
2086 sh = SH(ctx->opcode) | (shn << 5);
2087 mb = MB(ctx->opcode) | (mbn << 5);
2088 gen_rldinm(ctx, mb, 63 - sh, sh);
2089 }
2090 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2091
2092 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2093 {
2094 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2095 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2096 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2097 TCGv t0;
2098
2099 t0 = tcg_temp_new();
2100 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2101 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2102 tcg_temp_free(t0);
2103
2104 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2105 if (unlikely(Rc(ctx->opcode) != 0)) {
2106 gen_set_Rc0(ctx, t_ra);
2107 }
2108 }
2109
2110 /* rldcl - rldcl. */
2111 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2112 {
2113 uint32_t mb;
2114
2115 mb = MB(ctx->opcode) | (mbn << 5);
2116 gen_rldnm(ctx, mb, 63);
2117 }
2118 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2119
2120 /* rldcr - rldcr. */
2121 static inline void gen_rldcr(DisasContext *ctx, int men)
2122 {
2123 uint32_t me;
2124
2125 me = MB(ctx->opcode) | (men << 5);
2126 gen_rldnm(ctx, 0, me);
2127 }
2128 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2129
2130 /* rldimi - rldimi. */
2131 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2132 {
2133 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2134 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2135 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2136 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2137 uint32_t me = 63 - sh;
2138
2139 if (mb <= me) {
2140 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2141 } else {
2142 target_ulong mask = MASK(mb, me);
2143 TCGv t1 = tcg_temp_new();
2144
2145 tcg_gen_rotli_tl(t1, t_rs, sh);
2146 tcg_gen_andi_tl(t1, t1, mask);
2147 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2148 tcg_gen_or_tl(t_ra, t_ra, t1);
2149 tcg_temp_free(t1);
2150 }
2151 if (unlikely(Rc(ctx->opcode) != 0)) {
2152 gen_set_Rc0(ctx, t_ra);
2153 }
2154 }
2155 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2156 #endif
2157
2158 /*** Integer shift ***/
2159
2160 /* slw & slw. */
2161 static void gen_slw(DisasContext *ctx)
2162 {
2163 TCGv t0, t1;
2164
2165 t0 = tcg_temp_new();
2166 /* AND rS with a mask that is 0 when rB >= 0x20 */
2167 #if defined(TARGET_PPC64)
2168 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2169 tcg_gen_sari_tl(t0, t0, 0x3f);
2170 #else
2171 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2172 tcg_gen_sari_tl(t0, t0, 0x1f);
2173 #endif
2174 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2175 t1 = tcg_temp_new();
2176 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2177 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2178 tcg_temp_free(t1);
2179 tcg_temp_free(t0);
2180 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2181 if (unlikely(Rc(ctx->opcode) != 0))
2182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2183 }
2184
2185 /* sraw & sraw. */
2186 static void gen_sraw(DisasContext *ctx)
2187 {
2188 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2189 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2190 if (unlikely(Rc(ctx->opcode) != 0))
2191 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2192 }
2193
2194 /* srawi & srawi. */
2195 static void gen_srawi(DisasContext *ctx)
2196 {
2197 int sh = SH(ctx->opcode);
2198 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2199 TCGv src = cpu_gpr[rS(ctx->opcode)];
2200 if (sh == 0) {
2201 tcg_gen_ext32s_tl(dst, src);
2202 tcg_gen_movi_tl(cpu_ca, 0);
2203 if (is_isa300(ctx)) {
2204 tcg_gen_movi_tl(cpu_ca32, 0);
2205 }
2206 } else {
2207 TCGv t0;
2208 tcg_gen_ext32s_tl(dst, src);
2209 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2210 t0 = tcg_temp_new();
2211 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2212 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2213 tcg_temp_free(t0);
2214 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2215 if (is_isa300(ctx)) {
2216 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2217 }
2218 tcg_gen_sari_tl(dst, dst, sh);
2219 }
2220 if (unlikely(Rc(ctx->opcode) != 0)) {
2221 gen_set_Rc0(ctx, dst);
2222 }
2223 }
2224
2225 /* srw & srw. */
2226 static void gen_srw(DisasContext *ctx)
2227 {
2228 TCGv t0, t1;
2229
2230 t0 = tcg_temp_new();
2231 /* AND rS with a mask that is 0 when rB >= 0x20 */
2232 #if defined(TARGET_PPC64)
2233 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2234 tcg_gen_sari_tl(t0, t0, 0x3f);
2235 #else
2236 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2237 tcg_gen_sari_tl(t0, t0, 0x1f);
2238 #endif
2239 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2240 tcg_gen_ext32u_tl(t0, t0);
2241 t1 = tcg_temp_new();
2242 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2243 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2244 tcg_temp_free(t1);
2245 tcg_temp_free(t0);
2246 if (unlikely(Rc(ctx->opcode) != 0))
2247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2248 }
2249
2250 #if defined(TARGET_PPC64)
2251 /* sld & sld. */
2252 static void gen_sld(DisasContext *ctx)
2253 {
2254 TCGv t0, t1;
2255
2256 t0 = tcg_temp_new();
2257 /* AND rS with a mask that is 0 when rB >= 0x40 */
2258 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2259 tcg_gen_sari_tl(t0, t0, 0x3f);
2260 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2261 t1 = tcg_temp_new();
2262 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2263 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2264 tcg_temp_free(t1);
2265 tcg_temp_free(t0);
2266 if (unlikely(Rc(ctx->opcode) != 0))
2267 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2268 }
2269
2270 /* srad & srad. */
2271 static void gen_srad(DisasContext *ctx)
2272 {
2273 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2274 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2275 if (unlikely(Rc(ctx->opcode) != 0))
2276 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2277 }
2278 /* sradi & sradi. */
2279 static inline void gen_sradi(DisasContext *ctx, int n)
2280 {
2281 int sh = SH(ctx->opcode) + (n << 5);
2282 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2283 TCGv src = cpu_gpr[rS(ctx->opcode)];
2284 if (sh == 0) {
2285 tcg_gen_mov_tl(dst, src);
2286 tcg_gen_movi_tl(cpu_ca, 0);
2287 if (is_isa300(ctx)) {
2288 tcg_gen_movi_tl(cpu_ca32, 0);
2289 }
2290 } else {
2291 TCGv t0;
2292 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2293 t0 = tcg_temp_new();
2294 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2295 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2296 tcg_temp_free(t0);
2297 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2298 if (is_isa300(ctx)) {
2299 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2300 }
2301 tcg_gen_sari_tl(dst, src, sh);
2302 }
2303 if (unlikely(Rc(ctx->opcode) != 0)) {
2304 gen_set_Rc0(ctx, dst);
2305 }
2306 }
2307
2308 static void gen_sradi0(DisasContext *ctx)
2309 {
2310 gen_sradi(ctx, 0);
2311 }
2312
2313 static void gen_sradi1(DisasContext *ctx)
2314 {
2315 gen_sradi(ctx, 1);
2316 }
2317
2318 /* extswsli & extswsli. */
2319 static inline void gen_extswsli(DisasContext *ctx, int n)
2320 {
2321 int sh = SH(ctx->opcode) + (n << 5);
2322 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2323 TCGv src = cpu_gpr[rS(ctx->opcode)];
2324
2325 tcg_gen_ext32s_tl(dst, src);
2326 tcg_gen_shli_tl(dst, dst, sh);
2327 if (unlikely(Rc(ctx->opcode) != 0)) {
2328 gen_set_Rc0(ctx, dst);
2329 }
2330 }
2331
2332 static void gen_extswsli0(DisasContext *ctx)
2333 {
2334 gen_extswsli(ctx, 0);
2335 }
2336
2337 static void gen_extswsli1(DisasContext *ctx)
2338 {
2339 gen_extswsli(ctx, 1);
2340 }
2341
2342 /* srd & srd. */
2343 static void gen_srd(DisasContext *ctx)
2344 {
2345 TCGv t0, t1;
2346
2347 t0 = tcg_temp_new();
2348 /* AND rS with a mask that is 0 when rB >= 0x40 */
2349 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2350 tcg_gen_sari_tl(t0, t0, 0x3f);
2351 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2352 t1 = tcg_temp_new();
2353 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2354 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2355 tcg_temp_free(t1);
2356 tcg_temp_free(t0);
2357 if (unlikely(Rc(ctx->opcode) != 0))
2358 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2359 }
2360 #endif
2361
2362 /*** Addressing modes ***/
2363 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2364 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2365 target_long maskl)
2366 {
2367 target_long simm = SIMM(ctx->opcode);
2368
2369 simm &= ~maskl;
2370 if (rA(ctx->opcode) == 0) {
2371 if (NARROW_MODE(ctx)) {
2372 simm = (uint32_t)simm;
2373 }
2374 tcg_gen_movi_tl(EA, simm);
2375 } else if (likely(simm != 0)) {
2376 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2377 if (NARROW_MODE(ctx)) {
2378 tcg_gen_ext32u_tl(EA, EA);
2379 }
2380 } else {
2381 if (NARROW_MODE(ctx)) {
2382 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2383 } else {
2384 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2385 }
2386 }
2387 }
2388
2389 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2390 {
2391 if (rA(ctx->opcode) == 0) {
2392 if (NARROW_MODE(ctx)) {
2393 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2394 } else {
2395 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2396 }
2397 } else {
2398 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2399 if (NARROW_MODE(ctx)) {
2400 tcg_gen_ext32u_tl(EA, EA);
2401 }
2402 }
2403 }
2404
2405 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2406 {
2407 if (rA(ctx->opcode) == 0) {
2408 tcg_gen_movi_tl(EA, 0);
2409 } else if (NARROW_MODE(ctx)) {
2410 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2411 } else {
2412 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2413 }
2414 }
2415
2416 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2417 target_long val)
2418 {
2419 tcg_gen_addi_tl(ret, arg1, val);
2420 if (NARROW_MODE(ctx)) {
2421 tcg_gen_ext32u_tl(ret, ret);
2422 }
2423 }
2424
2425 static inline void gen_align_no_le(DisasContext *ctx)
2426 {
2427 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2428 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2429 }
2430
2431 /*** Integer load ***/
2432 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2433 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2434
2435 #define GEN_QEMU_LOAD_TL(ldop, op) \
2436 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2437 TCGv val, \
2438 TCGv addr) \
2439 { \
2440 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2441 }
2442
2443 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2444 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2445 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2446 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2447 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2448
2449 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2450 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2451
2452 #define GEN_QEMU_LOAD_64(ldop, op) \
2453 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2454 TCGv_i64 val, \
2455 TCGv addr) \
2456 { \
2457 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2458 }
2459
2460 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2461 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2462 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2463 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2464 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2465
2466 #if defined(TARGET_PPC64)
2467 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2468 #endif
2469
2470 #define GEN_QEMU_STORE_TL(stop, op) \
2471 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2472 TCGv val, \
2473 TCGv addr) \
2474 { \
2475 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2476 }
2477
2478 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2479 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2480 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2481
2482 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2483 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2484
2485 #define GEN_QEMU_STORE_64(stop, op) \
2486 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2487 TCGv_i64 val, \
2488 TCGv addr) \
2489 { \
2490 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2491 }
2492
2493 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2494 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2495 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2496 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2497
2498 #if defined(TARGET_PPC64)
2499 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2500 #endif
2501
2502 #define GEN_LD(name, ldop, opc, type) \
2503 static void glue(gen_, name)(DisasContext *ctx) \
2504 { \
2505 TCGv EA; \
2506 gen_set_access_type(ctx, ACCESS_INT); \
2507 EA = tcg_temp_new(); \
2508 gen_addr_imm_index(ctx, EA, 0); \
2509 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2510 tcg_temp_free(EA); \
2511 }
2512
2513 #define GEN_LDU(name, ldop, opc, type) \
2514 static void glue(gen_, name##u)(DisasContext *ctx) \
2515 { \
2516 TCGv EA; \
2517 if (unlikely(rA(ctx->opcode) == 0 || \
2518 rA(ctx->opcode) == rD(ctx->opcode))) { \
2519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2520 return; \
2521 } \
2522 gen_set_access_type(ctx, ACCESS_INT); \
2523 EA = tcg_temp_new(); \
2524 if (type == PPC_64B) \
2525 gen_addr_imm_index(ctx, EA, 0x03); \
2526 else \
2527 gen_addr_imm_index(ctx, EA, 0); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2530 tcg_temp_free(EA); \
2531 }
2532
2533 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2534 static void glue(gen_, name##ux)(DisasContext *ctx) \
2535 { \
2536 TCGv EA; \
2537 if (unlikely(rA(ctx->opcode) == 0 || \
2538 rA(ctx->opcode) == rD(ctx->opcode))) { \
2539 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2540 return; \
2541 } \
2542 gen_set_access_type(ctx, ACCESS_INT); \
2543 EA = tcg_temp_new(); \
2544 gen_addr_reg_index(ctx, EA); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2548 }
2549
2550 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2551 static void glue(gen_, name##x)(DisasContext *ctx) \
2552 { \
2553 TCGv EA; \
2554 chk; \
2555 gen_set_access_type(ctx, ACCESS_INT); \
2556 EA = tcg_temp_new(); \
2557 gen_addr_reg_index(ctx, EA); \
2558 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2559 tcg_temp_free(EA); \
2560 }
2561
2562 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2563 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2564
2565 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2566 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2567
2568 #define GEN_LDS(name, ldop, op, type) \
2569 GEN_LD(name, ldop, op | 0x20, type); \
2570 GEN_LDU(name, ldop, op | 0x21, type); \
2571 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2572 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2573
2574 /* lbz lbzu lbzux lbzx */
2575 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2576 /* lha lhau lhaux lhax */
2577 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2578 /* lhz lhzu lhzux lhzx */
2579 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2580 /* lwz lwzu lwzux lwzx */
2581 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2582
2583 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2584 static void glue(gen_, name##epx)(DisasContext *ctx) \
2585 { \
2586 TCGv EA; \
2587 CHK_SV; \
2588 gen_set_access_type(ctx, ACCESS_INT); \
2589 EA = tcg_temp_new(); \
2590 gen_addr_reg_index(ctx, EA); \
2591 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2592 tcg_temp_free(EA); \
2593 }
2594
2595 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
2596 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
2597 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
2598 #if defined(TARGET_PPC64)
2599 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
2600 #endif
2601
2602 #if defined(TARGET_PPC64)
2603 /* lwaux */
2604 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2605 /* lwax */
2606 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2607 /* ldux */
2608 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2609 /* ldx */
2610 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2611
2612 /* CI load/store variants */
2613 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2614 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2615 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2616 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2617
2618 static void gen_ld(DisasContext *ctx)
2619 {
2620 TCGv EA;
2621 if (Rc(ctx->opcode)) {
2622 if (unlikely(rA(ctx->opcode) == 0 ||
2623 rA(ctx->opcode) == rD(ctx->opcode))) {
2624 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2625 return;
2626 }
2627 }
2628 gen_set_access_type(ctx, ACCESS_INT);
2629 EA = tcg_temp_new();
2630 gen_addr_imm_index(ctx, EA, 0x03);
2631 if (ctx->opcode & 0x02) {
2632 /* lwa (lwau is undefined) */
2633 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2634 } else {
2635 /* ld - ldu */
2636 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2637 }
2638 if (Rc(ctx->opcode))
2639 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2640 tcg_temp_free(EA);
2641 }
2642
2643 /* lq */
2644 static void gen_lq(DisasContext *ctx)
2645 {
2646 int ra, rd;
2647 TCGv EA, hi, lo;
2648
2649 /* lq is a legal user mode instruction starting in ISA 2.07 */
2650 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2651 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2652
2653 if (!legal_in_user_mode && ctx->pr) {
2654 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2655 return;
2656 }
2657
2658 if (!le_is_supported && ctx->le_mode) {
2659 gen_align_no_le(ctx);
2660 return;
2661 }
2662 ra = rA(ctx->opcode);
2663 rd = rD(ctx->opcode);
2664 if (unlikely((rd & 1) || rd == ra)) {
2665 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2666 return;
2667 }
2668
2669 gen_set_access_type(ctx, ACCESS_INT);
2670 EA = tcg_temp_new();
2671 gen_addr_imm_index(ctx, EA, 0x0F);
2672
2673 /* Note that the low part is always in RD+1, even in LE mode. */
2674 lo = cpu_gpr[rd + 1];
2675 hi = cpu_gpr[rd];
2676
2677 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2678 if (HAVE_ATOMIC128) {
2679 TCGv_i32 oi = tcg_temp_new_i32();
2680 if (ctx->le_mode) {
2681 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2682 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2683 } else {
2684 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2685 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2686 }
2687 tcg_temp_free_i32(oi);
2688 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2689 } else {
2690 /* Restart with exclusive lock. */
2691 gen_helper_exit_atomic(cpu_env);
2692 ctx->base.is_jmp = DISAS_NORETURN;
2693 }
2694 } else if (ctx->le_mode) {
2695 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2696 gen_addr_add(ctx, EA, EA, 8);
2697 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2698 } else {
2699 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2700 gen_addr_add(ctx, EA, EA, 8);
2701 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2702 }
2703 tcg_temp_free(EA);
2704 }
2705 #endif
2706
2707 /*** Integer store ***/
2708 #define GEN_ST(name, stop, opc, type) \
2709 static void glue(gen_, name)(DisasContext *ctx) \
2710 { \
2711 TCGv EA; \
2712 gen_set_access_type(ctx, ACCESS_INT); \
2713 EA = tcg_temp_new(); \
2714 gen_addr_imm_index(ctx, EA, 0); \
2715 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2716 tcg_temp_free(EA); \
2717 }
2718
2719 #define GEN_STU(name, stop, opc, type) \
2720 static void glue(gen_, stop##u)(DisasContext *ctx) \
2721 { \
2722 TCGv EA; \
2723 if (unlikely(rA(ctx->opcode) == 0)) { \
2724 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2725 return; \
2726 } \
2727 gen_set_access_type(ctx, ACCESS_INT); \
2728 EA = tcg_temp_new(); \
2729 if (type == PPC_64B) \
2730 gen_addr_imm_index(ctx, EA, 0x03); \
2731 else \
2732 gen_addr_imm_index(ctx, EA, 0); \
2733 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2734 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2735 tcg_temp_free(EA); \
2736 }
2737
2738 #define GEN_STUX(name, stop, opc2, opc3, type) \
2739 static void glue(gen_, name##ux)(DisasContext *ctx) \
2740 { \
2741 TCGv EA; \
2742 if (unlikely(rA(ctx->opcode) == 0)) { \
2743 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2744 return; \
2745 } \
2746 gen_set_access_type(ctx, ACCESS_INT); \
2747 EA = tcg_temp_new(); \
2748 gen_addr_reg_index(ctx, EA); \
2749 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2750 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2751 tcg_temp_free(EA); \
2752 }
2753
2754 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2755 static void glue(gen_, name##x)(DisasContext *ctx) \
2756 { \
2757 TCGv EA; \
2758 chk; \
2759 gen_set_access_type(ctx, ACCESS_INT); \
2760 EA = tcg_temp_new(); \
2761 gen_addr_reg_index(ctx, EA); \
2762 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2763 tcg_temp_free(EA); \
2764 }
2765 #define GEN_STX(name, stop, opc2, opc3, type) \
2766 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2767
2768 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2769 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2770
2771 #define GEN_STS(name, stop, op, type) \
2772 GEN_ST(name, stop, op | 0x20, type); \
2773 GEN_STU(name, stop, op | 0x21, type); \
2774 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2775 GEN_STX(name, stop, 0x17, op | 0x00, type)
2776
2777 /* stb stbu stbux stbx */
2778 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2779 /* sth sthu sthux sthx */
2780 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2781 /* stw stwu stwux stwx */
2782 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2783
2784 #define GEN_STEPX(name, stop, opc2, opc3) \
2785 static void glue(gen_, name##epx)(DisasContext *ctx) \
2786 { \
2787 TCGv EA; \
2788 CHK_SV; \
2789 gen_set_access_type(ctx, ACCESS_INT); \
2790 EA = tcg_temp_new(); \
2791 gen_addr_reg_index(ctx, EA); \
2792 tcg_gen_qemu_st_tl( \
2793 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2794 tcg_temp_free(EA); \
2795 }
2796
2797 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
2798 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
2799 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2800 #if defined(TARGET_PPC64)
2801 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
2802 #endif
2803
2804 #if defined(TARGET_PPC64)
2805 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2806 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2807 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2808 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2809 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2810 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2811
2812 static void gen_std(DisasContext *ctx)
2813 {
2814 int rs;
2815 TCGv EA;
2816
2817 rs = rS(ctx->opcode);
2818 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2819 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2820 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2821 TCGv hi, lo;
2822
2823 if (!(ctx->insns_flags & PPC_64BX)) {
2824 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2825 }
2826
2827 if (!legal_in_user_mode && ctx->pr) {
2828 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2829 return;
2830 }
2831
2832 if (!le_is_supported && ctx->le_mode) {
2833 gen_align_no_le(ctx);
2834 return;
2835 }
2836
2837 if (unlikely(rs & 1)) {
2838 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2839 return;
2840 }
2841 gen_set_access_type(ctx, ACCESS_INT);
2842 EA = tcg_temp_new();
2843 gen_addr_imm_index(ctx, EA, 0x03);
2844
2845 /* Note that the low part is always in RS+1, even in LE mode. */
2846 lo = cpu_gpr[rs + 1];
2847 hi = cpu_gpr[rs];
2848
2849 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2850 if (HAVE_ATOMIC128) {
2851 TCGv_i32 oi = tcg_temp_new_i32();
2852 if (ctx->le_mode) {
2853 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2854 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2855 } else {
2856 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2857 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2858 }
2859 tcg_temp_free_i32(oi);
2860 } else {
2861 /* Restart with exclusive lock. */
2862 gen_helper_exit_atomic(cpu_env);
2863 ctx->base.is_jmp = DISAS_NORETURN;
2864 }
2865 } else if (ctx->le_mode) {
2866 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2867 gen_addr_add(ctx, EA, EA, 8);
2868 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2869 } else {
2870 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2871 gen_addr_add(ctx, EA, EA, 8);
2872 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2873 }
2874 tcg_temp_free(EA);
2875 } else {
2876 /* std / stdu */
2877 if (Rc(ctx->opcode)) {
2878 if (unlikely(rA(ctx->opcode) == 0)) {
2879 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2880 return;
2881 }
2882 }
2883 gen_set_access_type(ctx, ACCESS_INT);
2884 EA = tcg_temp_new();
2885 gen_addr_imm_index(ctx, EA, 0x03);
2886 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2887 if (Rc(ctx->opcode))
2888 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2889 tcg_temp_free(EA);
2890 }
2891 }
2892 #endif
2893 /*** Integer load and store with byte reverse ***/
2894
2895 /* lhbrx */
2896 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2897
2898 /* lwbrx */
2899 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2900
2901 #if defined(TARGET_PPC64)
2902 /* ldbrx */
2903 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2904 /* stdbrx */
2905 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2906 #endif /* TARGET_PPC64 */
2907
2908 /* sthbrx */
2909 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2910 /* stwbrx */
2911 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2912
2913 /*** Integer load and store multiple ***/
2914
2915 /* lmw */
2916 static void gen_lmw(DisasContext *ctx)
2917 {
2918 TCGv t0;
2919 TCGv_i32 t1;
2920
2921 if (ctx->le_mode) {
2922 gen_align_no_le(ctx);
2923 return;
2924 }
2925 gen_set_access_type(ctx, ACCESS_INT);
2926 t0 = tcg_temp_new();
2927 t1 = tcg_const_i32(rD(ctx->opcode));
2928 gen_addr_imm_index(ctx, t0, 0);
2929 gen_helper_lmw(cpu_env, t0, t1);
2930 tcg_temp_free(t0);
2931 tcg_temp_free_i32(t1);
2932 }
2933
2934 /* stmw */
2935 static void gen_stmw(DisasContext *ctx)
2936 {
2937 TCGv t0;
2938 TCGv_i32 t1;
2939
2940 if (ctx->le_mode) {
2941 gen_align_no_le(ctx);
2942 return;
2943 }
2944 gen_set_access_type(ctx, ACCESS_INT);
2945 t0 = tcg_temp_new();
2946 t1 = tcg_const_i32(rS(ctx->opcode));
2947 gen_addr_imm_index(ctx, t0, 0);
2948 gen_helper_stmw(cpu_env, t0, t1);
2949 tcg_temp_free(t0);
2950 tcg_temp_free_i32(t1);
2951 }
2952
2953 /*** Integer load and store strings ***/
2954
2955 /* lswi */
2956 /* PowerPC32 specification says we must generate an exception if
2957 * rA is in the range of registers to be loaded.
2958 * In an other hand, IBM says this is valid, but rA won't be loaded.
2959 * For now, I'll follow the spec...
2960 */
2961 static void gen_lswi(DisasContext *ctx)
2962 {
2963 TCGv t0;
2964 TCGv_i32 t1, t2;
2965 int nb = NB(ctx->opcode);
2966 int start = rD(ctx->opcode);
2967 int ra = rA(ctx->opcode);
2968 int nr;
2969
2970 if (ctx->le_mode) {
2971 gen_align_no_le(ctx);
2972 return;
2973 }
2974 if (nb == 0)
2975 nb = 32;
2976 nr = DIV_ROUND_UP(nb, 4);
2977 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2978 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2979 return;
2980 }
2981 gen_set_access_type(ctx, ACCESS_INT);
2982 t0 = tcg_temp_new();
2983 gen_addr_register(ctx, t0);
2984 t1 = tcg_const_i32(nb);
2985 t2 = tcg_const_i32(start);
2986 gen_helper_lsw(cpu_env, t0, t1, t2);
2987 tcg_temp_free(t0);
2988 tcg_temp_free_i32(t1);
2989 tcg_temp_free_i32(t2);
2990 }
2991
2992 /* lswx */
2993 static void gen_lswx(DisasContext *ctx)
2994 {
2995 TCGv t0;
2996 TCGv_i32 t1, t2, t3;
2997
2998 if (ctx->le_mode) {
2999 gen_align_no_le(ctx);
3000 return;
3001 }
3002 gen_set_access_type(ctx, ACCESS_INT);
3003 t0 = tcg_temp_new();
3004 gen_addr_reg_index(ctx, t0);
3005 t1 = tcg_const_i32(rD(ctx->opcode));
3006 t2 = tcg_const_i32(rA(ctx->opcode));
3007 t3 = tcg_const_i32(rB(ctx->opcode));
3008 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3009 tcg_temp_free(t0);
3010 tcg_temp_free_i32(t1);
3011 tcg_temp_free_i32(t2);
3012 tcg_temp_free_i32(t3);
3013 }
3014
3015 /* stswi */
3016 static void gen_stswi(DisasContext *ctx)
3017 {
3018 TCGv t0;
3019 TCGv_i32 t1, t2;
3020 int nb = NB(ctx->opcode);
3021
3022 if (ctx->le_mode) {
3023 gen_align_no_le(ctx);
3024 return;
3025 }
3026 gen_set_access_type(ctx, ACCESS_INT);
3027 t0 = tcg_temp_new();
3028 gen_addr_register(ctx, t0);
3029 if (nb == 0)
3030 nb = 32;
3031 t1 = tcg_const_i32(nb);
3032 t2 = tcg_const_i32(rS(ctx->opcode));
3033 gen_helper_stsw(cpu_env, t0, t1, t2);
3034 tcg_temp_free(t0);
3035 tcg_temp_free_i32(t1);
3036 tcg_temp_free_i32(t2);
3037 }
3038
3039 /* stswx */
3040 static void gen_stswx(DisasContext *ctx)
3041 {
3042 TCGv t0;
3043 TCGv_i32 t1, t2;
3044
3045 if (ctx->le_mode) {
3046 gen_align_no_le(ctx);
3047 return;
3048 }
3049 gen_set_access_type(ctx, ACCESS_INT);
3050 t0 = tcg_temp_new();
3051 gen_addr_reg_index(ctx, t0);
3052 t1 = tcg_temp_new_i32();
3053 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3054 tcg_gen_andi_i32(t1, t1, 0x7F);
3055 t2 = tcg_const_i32(rS(ctx->opcode));
3056 gen_helper_stsw(cpu_env, t0, t1, t2);
3057 tcg_temp_free(t0);
3058 tcg_temp_free_i32(t1);
3059 tcg_temp_free_i32(t2);
3060 }
3061
3062 /*** Memory synchronisation ***/
3063 /* eieio */
3064 static void gen_eieio(DisasContext *ctx)
3065 {
3066 TCGBar bar = TCG_MO_LD_ST;
3067
3068 /*
3069 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3070 * tell the CPU it is a store-forwarding barrier.
3071 */
3072 if (ctx->opcode & 0x2000000) {
3073 /*
3074 * ISA says that "Reserved fields in instructions are ignored
3075 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3076 * as this is not an instruction software should be using,
3077 * complain to the user.
3078 */
3079 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3080 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3081 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3082 } else {
3083 bar = TCG_MO_ST_LD;
3084 }
3085 }
3086
3087 tcg_gen_mb(bar | TCG_BAR_SC);
3088 }
3089
3090 #if !defined(CONFIG_USER_ONLY)
3091 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3092 {
3093 TCGv_i32 t;
3094 TCGLabel *l;
3095
3096 if (!ctx->lazy_tlb_flush) {
3097 return;
3098 }
3099 l = gen_new_label();
3100 t = tcg_temp_new_i32();
3101 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3102 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3103 if (global) {
3104 gen_helper_check_tlb_flush_global(cpu_env);
3105 } else {
3106 gen_helper_check_tlb_flush_local(cpu_env);
3107 }
3108 gen_set_label(l);
3109 tcg_temp_free_i32(t);
3110 }
3111 #else
3112 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3113 #endif
3114
3115 /* isync */
3116 static void gen_isync(DisasContext *ctx)
3117 {
3118 /*
3119 * We need to check for a pending TLB flush. This can only happen in
3120 * kernel mode however so check MSR_PR
3121 */
3122 if (!ctx->pr) {
3123 gen_check_tlb_flush(ctx, false);
3124 }
3125 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3126 gen_stop_exception(ctx);
3127 }
3128
3129 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3130
3131 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3132 {
3133 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3134 TCGv t0 = tcg_temp_new();
3135
3136 gen_set_access_type(ctx, ACCESS_RES);
3137 gen_addr_reg_index(ctx, t0);
3138 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3139 tcg_gen_mov_tl(cpu_reserve, t0);
3140 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3141 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3142 tcg_temp_free(t0);
3143 }
3144
3145 #define LARX(name, memop) \
3146 static void gen_##name(DisasContext *ctx) \
3147 { \
3148 gen_load_locked(ctx, memop); \
3149 }
3150
3151 /* lwarx */
3152 LARX(lbarx, DEF_MEMOP(MO_UB))
3153 LARX(lharx, DEF_MEMOP(MO_UW))
3154 LARX(lwarx, DEF_MEMOP(MO_UL))
3155
3156 static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
3157 TCGv EA, TCGCond cond, int addend)
3158 {
3159 TCGv t = tcg_temp_new();
3160 TCGv t2 = tcg_temp_new();
3161 TCGv u = tcg_temp_new();
3162
3163 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3164 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3165 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3166 tcg_gen_addi_tl(u, t, addend);
3167
3168 /* E.g. for fetch and increment bounded... */
3169 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3170 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3171 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3172
3173 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3174 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3175 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3176
3177 tcg_temp_free(t);
3178 tcg_temp_free(t2);
3179 tcg_temp_free(u);
3180 }
3181
3182 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3183 {
3184 uint32_t gpr_FC = FC(ctx->opcode);
3185 TCGv EA = tcg_temp_new();
3186 int rt = rD(ctx->opcode);
3187 bool need_serial;
3188 TCGv src, dst;
3189
3190 gen_addr_register(ctx, EA);
3191 dst = cpu_gpr[rt];
3192 src = cpu_gpr[(rt + 1) & 31];
3193
3194 need_serial = false;
3195 memop |= MO_ALIGN;
3196 switch (gpr_FC) {
3197 case 0: /* Fetch and add */
3198 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3199 break;
3200 case 1: /* Fetch and xor */
3201 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3202 break;
3203 case 2: /* Fetch and or */
3204 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3205 break;
3206 case 3: /* Fetch and 'and' */
3207 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3208 break;
3209 case 4: /* Fetch and max unsigned */
3210 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3211 break;
3212 case 5: /* Fetch and max signed */
3213 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3214 break;
3215 case 6: /* Fetch and min unsigned */
3216 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3217 break;
3218 case 7: /* Fetch and min signed */
3219 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3220 break;
3221 case 8: /* Swap */
3222 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3223 break;
3224
3225 case 16: /* Compare and swap not equal */
3226 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3227 need_serial = true;
3228 } else {
3229 TCGv t0 = tcg_temp_new();
3230 TCGv t1 = tcg_temp_new();
3231
3232 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3233 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3234 tcg_gen_mov_tl(t1, src);
3235 } else {
3236 tcg_gen_ext32u_tl(t1, src);
3237 }
3238 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3239 cpu_gpr[(rt + 2) & 31], t0);
3240 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3241 tcg_gen_mov_tl(dst, t0);
3242
3243 tcg_temp_free(t0);
3244 tcg_temp_free(t1);
3245 }
3246 break;
3247
3248 case 24: /* Fetch and increment bounded */
3249 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3250 need_serial = true;
3251 } else {
3252 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3253 }
3254 break;
3255 case 25: /* Fetch and increment equal */
3256 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3257 need_serial = true;
3258 } else {
3259 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3260 }
3261 break;
3262 case 28: /* Fetch and decrement bounded */
3263 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3264 need_serial = true;
3265 } else {
3266 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3267 }
3268 break;
3269
3270 default:
3271 /* invoke data storage error handler */
3272 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3273 }
3274 tcg_temp_free(EA);
3275
3276 if (need_serial) {
3277 /* Restart with exclusive lock. */
3278 gen_helper_exit_atomic(cpu_env);
3279 ctx->base.is_jmp = DISAS_NORETURN;
3280 }
3281 }
3282
3283 static void gen_lwat(DisasContext *ctx)
3284 {
3285 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3286 }
3287
3288 #ifdef TARGET_PPC64
3289 static void gen_ldat(DisasContext *ctx)
3290 {
3291 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3292 }
3293 #endif
3294
3295 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3296 {
3297 uint32_t gpr_FC = FC(ctx->opcode);
3298 TCGv EA = tcg_temp_new();
3299 TCGv src, discard;
3300
3301 gen_addr_register(ctx, EA);
3302 src = cpu_gpr[rD(ctx->opcode)];
3303 discard = tcg_temp_new();
3304
3305 memop |= MO_ALIGN;
3306 switch (gpr_FC) {
3307 case 0: /* add and Store */
3308 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3309 break;
3310 case 1: /* xor and Store */
3311 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3312 break;
3313 case 2: /* Or and Store */
3314 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3315 break;
3316 case 3: /* 'and' and Store */
3317 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3318 break;
3319 case 4: /* Store max unsigned */
3320 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3321 break;
3322 case 5: /* Store max signed */
3323 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3324 break;
3325 case 6: /* Store min unsigned */
3326 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3327 break;
3328 case 7: /* Store min signed */
3329 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3330 break;
3331 case 24: /* Store twin */
3332 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3333 /* Restart with exclusive lock. */
3334 gen_helper_exit_atomic(cpu_env);
3335 ctx->base.is_jmp = DISAS_NORETURN;
3336 } else {
3337 TCGv t = tcg_temp_new();
3338 TCGv t2 = tcg_temp_new();
3339 TCGv s = tcg_temp_new();
3340 TCGv s2 = tcg_temp_new();
3341 TCGv ea_plus_s = tcg_temp_new();
3342
3343 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3344 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3345 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3346 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3347 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3348 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3349 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3350
3351 tcg_temp_free(ea_plus_s);
3352 tcg_temp_free(s2);
3353 tcg_temp_free(s);
3354 tcg_temp_free(t2);
3355 tcg_temp_free(t);
3356 }
3357 break;
3358 default:
3359 /* invoke data storage error handler */
3360 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3361 }
3362 tcg_temp_free(discard);
3363 tcg_temp_free(EA);
3364 }
3365
3366 static void gen_stwat(DisasContext *ctx)
3367 {
3368 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3369 }
3370
3371 #ifdef TARGET_PPC64
3372 static void gen_stdat(DisasContext *ctx)
3373 {
3374 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3375 }
3376 #endif
3377
3378 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3379 {
3380 TCGLabel *l1 = gen_new_label();
3381 TCGLabel *l2 = gen_new_label();
3382 TCGv t0 = tcg_temp_new();
3383 int reg = rS(ctx->opcode);
3384
3385 gen_set_access_type(ctx, ACCESS_RES);
3386 gen_addr_reg_index(ctx, t0);
3387 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3388 tcg_temp_free(t0);
3389
3390 t0 = tcg_temp_new();
3391 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3392 cpu_gpr[reg], ctx->mem_idx,
3393 DEF_MEMOP(memop) | MO_ALIGN);
3394 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3395 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3396 tcg_gen_or_tl(t0, t0, cpu_so);
3397 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3398 tcg_temp_free(t0);
3399 tcg_gen_br(l2);
3400
3401 gen_set_label(l1);
3402
3403 /* Address mismatch implies failure. But we still need to provide the
3404 memory barrier semantics of the instruction. */
3405 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3406 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3407
3408 gen_set_label(l2);
3409 tcg_gen_movi_tl(cpu_reserve, -1);
3410 }
3411
3412 #define STCX(name, memop) \
3413 static void gen_##name(DisasContext *ctx) \
3414 { \
3415 gen_conditional_store(ctx, memop); \
3416 }
3417
3418 STCX(stbcx_, DEF_MEMOP(MO_UB))
3419 STCX(sthcx_, DEF_MEMOP(MO_UW))
3420 STCX(stwcx_, DEF_MEMOP(MO_UL))
3421
3422 #if defined(TARGET_PPC64)
3423 /* ldarx */
3424 LARX(ldarx, DEF_MEMOP(MO_Q))
3425 /* stdcx. */
3426 STCX(stdcx_, DEF_MEMOP(MO_Q))
3427
3428 /* lqarx */
3429 static void gen_lqarx(DisasContext *ctx)
3430 {
3431 int rd = rD(ctx->opcode);
3432 TCGv EA, hi, lo;
3433
3434 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3435 (rd == rB(ctx->opcode)))) {
3436 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3437 return;
3438 }
3439
3440 gen_set_access_type(ctx, ACCESS_RES);
3441 EA = tcg_temp_new();
3442 gen_addr_reg_index(ctx, EA);
3443
3444 /* Note that the low part is always in RD+1, even in LE mode. */
3445 lo = cpu_gpr[rd + 1];
3446 hi = cpu_gpr[rd];
3447
3448 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3449 if (HAVE_ATOMIC128) {
3450 TCGv_i32 oi = tcg_temp_new_i32();
3451 if (ctx->le_mode) {
3452 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3453 ctx->mem_idx));
3454 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3455 } else {
3456 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3457 ctx->mem_idx));
3458 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3459 }
3460 tcg_temp_free_i32(oi);
3461 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3462 } else {
3463 /* Restart with exclusive lock. */
3464 gen_helper_exit_atomic(cpu_env);
3465 ctx->base.is_jmp = DISAS_NORETURN;
3466 tcg_temp_free(EA);
3467 return;
3468 }
3469 } else if (ctx->le_mode) {
3470 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3471 tcg_gen_mov_tl(cpu_reserve, EA);
3472 gen_addr_add(ctx, EA, EA, 8);
3473 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3474 } else {
3475 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3476 tcg_gen_mov_tl(cpu_reserve, EA);
3477 gen_addr_add(ctx, EA, EA, 8);
3478 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3479 }
3480 tcg_temp_free(EA);
3481
3482 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3483 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3484 }
3485
3486 /* stqcx. */
3487 static void gen_stqcx_(DisasContext *ctx)
3488 {
3489 int rs = rS(ctx->opcode);
3490 TCGv EA, hi, lo;
3491
3492 if (unlikely(rs & 1)) {
3493 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3494 return;
3495 }
3496
3497 gen_set_access_type(ctx, ACCESS_RES);
3498 EA = tcg_temp_new();
3499 gen_addr_reg_index(ctx, EA);
3500
3501 /* Note that the low part is always in RS+1, even in LE mode. */
3502 lo = cpu_gpr[rs + 1];
3503 hi = cpu_gpr[rs];
3504
3505 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3506 if (HAVE_CMPXCHG128) {
3507 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3508 if (ctx->le_mode) {
3509 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
3510 EA, lo, hi, oi);
3511 } else {
3512 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
3513 EA, lo, hi, oi);
3514 }
3515 tcg_temp_free_i32(oi);
3516 } else {
3517 /* Restart with exclusive lock. */
3518 gen_helper_exit_atomic(cpu_env);
3519 ctx->base.is_jmp = DISAS_NORETURN;
3520 }
3521 tcg_temp_free(EA);
3522 } else {
3523 TCGLabel *lab_fail = gen_new_label();
3524 TCGLabel *lab_over = gen_new_label();
3525 TCGv_i64 t0 = tcg_temp_new_i64();
3526 TCGv_i64 t1 = tcg_temp_new_i64();
3527
3528 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3529 tcg_temp_free(EA);
3530
3531 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3532 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3533 ? offsetof(CPUPPCState, reserve_val2)
3534 : offsetof(CPUPPCState, reserve_val)));
3535 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3536
3537 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3538 gen_qemu_ld64_i64(ctx, t0, t0);
3539 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3540 ? offsetof(CPUPPCState, reserve_val)
3541 : offsetof(CPUPPCState, reserve_val2)));
3542 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3543
3544 /* Success */
3545 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3546 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3547 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3548
3549 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3550 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3551 tcg_gen_br(lab_over);
3552
3553 gen_set_label(lab_fail);
3554 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3555
3556 gen_set_label(lab_over);
3557 tcg_gen_movi_tl(cpu_reserve, -1);
3558 tcg_temp_free_i64(t0);
3559 tcg_temp_free_i64(t1);
3560 }
3561 }
3562 #endif /* defined(TARGET_PPC64) */
3563
3564 /* sync */
3565 static void gen_sync(DisasContext *ctx)
3566 {
3567 uint32_t l = (ctx->opcode >> 21) & 3;
3568
3569 /*
3570 * We may need to check for a pending TLB flush.
3571 *
3572 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3573 *
3574 * Additionally, this can only happen in kernel mode however so
3575 * check MSR_PR as well.
3576 */
3577 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3578 gen_check_tlb_flush(ctx, true);
3579 }
3580 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3581 }
3582
3583 /* wait */
3584 static void gen_wait(DisasContext *ctx)
3585 {
3586 TCGv_i32 t0 = tcg_const_i32(1);
3587 tcg_gen_st_i32(t0, cpu_env,
3588 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3589 tcg_temp_free_i32(t0);
3590 /* Stop translation, as the CPU is supposed to sleep from now */
3591 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3592 }
3593
3594 #if defined(TARGET_PPC64)
3595 static void gen_doze(DisasContext *ctx)
3596 {
3597 #if defined(CONFIG_USER_ONLY)
3598 GEN_PRIV;
3599 #else
3600 TCGv_i32 t;
3601
3602 CHK_HV;
3603 t = tcg_const_i32(PPC_PM_DOZE);
3604 gen_helper_pminsn(cpu_env, t);
3605 tcg_temp_free_i32(t);
3606 gen_stop_exception(ctx);
3607 #endif /* defined(CONFIG_USER_ONLY) */
3608 }
3609
3610 static void gen_nap(DisasContext *ctx)
3611 {
3612 #if defined(CONFIG_USER_ONLY)
3613 GEN_PRIV;
3614 #else
3615 TCGv_i32 t;
3616
3617 CHK_HV;
3618 t = tcg_const_i32(PPC_PM_NAP);
3619 gen_helper_pminsn(cpu_env, t);
3620 tcg_temp_free_i32(t);
3621 gen_stop_exception(ctx);
3622 #endif /* defined(CONFIG_USER_ONLY) */
3623 }
3624
3625 static void gen_stop(DisasContext *ctx)
3626 {
3627 gen_nap(ctx);
3628 }
3629
3630 static void gen_sleep(DisasContext *ctx)
3631 {
3632 #if defined(CONFIG_USER_ONLY)
3633 GEN_PRIV;
3634 #else
3635 TCGv_i32 t;
3636
3637 CHK_HV;
3638 t = tcg_const_i32(PPC_PM_SLEEP);
3639 gen_helper_pminsn(cpu_env, t);
3640 tcg_temp_free_i32(t);
3641 gen_stop_exception(ctx);
3642 #endif /* defined(CONFIG_USER_ONLY) */
3643 }
3644
3645 static void gen_rvwinkle(DisasContext *ctx)
3646 {
3647 #if defined(CONFIG_USER_ONLY)
3648 GEN_PRIV;
3649 #else
3650 TCGv_i32 t;
3651
3652 CHK_HV;
3653 t = tcg_const_i32(PPC_PM_RVWINKLE);
3654 gen_helper_pminsn(cpu_env, t);
3655 tcg_temp_free_i32(t);
3656 gen_stop_exception(ctx);
3657 #endif /* defined(CONFIG_USER_ONLY) */
3658 }
3659 #endif /* #if defined(TARGET_PPC64) */
3660
3661 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3662 {
3663 #if defined(TARGET_PPC64)
3664 if (ctx->has_cfar)
3665 tcg_gen_movi_tl(cpu_cfar, nip);
3666 #endif
3667 }
3668
3669 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3670 {
3671 if (unlikely(ctx->singlestep_enabled)) {
3672 return false;
3673 }
3674
3675 #ifndef CONFIG_USER_ONLY
3676 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3677 #else
3678 return true;
3679 #endif
3680 }
3681
3682 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
3683 {
3684 int sse = ctx->singlestep_enabled;
3685 if (unlikely(sse)) {
3686 if (sse & GDBSTUB_SINGLE_STEP) {
3687 gen_debug_exception(ctx);
3688 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
3689 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_BRANCH);
3690 if (excp != POWERPC_EXCP_NONE) {
3691 gen_exception(ctx, excp);
3692 }
3693 }
3694 tcg_gen_exit_tb(NULL, 0);
3695 } else {
3696 tcg_gen_lookup_and_goto_ptr();
3697 }
3698 }
3699
3700 /*** Branch ***/
3701 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3702 {
3703 if (NARROW_MODE(ctx)) {
3704 dest = (uint32_t) dest;
3705 }
3706 if (use_goto_tb(ctx, dest)) {
3707 tcg_gen_goto_tb(n);
3708 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3709 tcg_gen_exit_tb(ctx->base.tb, n);
3710 } else {
3711 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3712 gen_lookup_and_goto_ptr(ctx);
3713 }
3714 }
3715
3716 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3717 {
3718 if (NARROW_MODE(ctx)) {
3719 nip = (uint32_t)nip;
3720 }
3721 tcg_gen_movi_tl(cpu_lr, nip);
3722 }
3723
3724 /* b ba bl bla */
3725 static void gen_b(DisasContext *ctx)
3726 {
3727 target_ulong li, target;
3728
3729 ctx->exception = POWERPC_EXCP_BRANCH;
3730 /* sign extend LI */
3731 li = LI(ctx->opcode);
3732 li = (li ^ 0x02000000) - 0x02000000;
3733 if (likely(AA(ctx->opcode) == 0)) {
3734 target = ctx->base.pc_next + li - 4;
3735 } else {
3736 target = li;
3737 }
3738 if (LK(ctx->opcode)) {
3739 gen_setlr(ctx, ctx->base.pc_next);
3740 }
3741 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3742 gen_goto_tb(ctx, 0, target);
3743 }
3744
3745 #define BCOND_IM 0
3746 #define BCOND_LR 1
3747 #define BCOND_CTR 2
3748 #define BCOND_TAR 3
3749
3750 static void gen_bcond(DisasContext *ctx, int type)
3751 {
3752 uint32_t bo = BO(ctx->opcode);
3753 TCGLabel *l1;
3754 TCGv target;
3755 ctx->exception = POWERPC_EXCP_BRANCH;
3756
3757 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3758 target = tcg_temp_local_new();
3759 if (type == BCOND_CTR)
3760 tcg_gen_mov_tl(target, cpu_ctr);
3761 else if (type == BCOND_TAR)
3762 gen_load_spr(target, SPR_TAR);
3763 else
3764 tcg_gen_mov_tl(target, cpu_lr);
3765 } else {
3766 target = NULL;
3767 }
3768 if (LK(ctx->opcode))
3769 gen_setlr(ctx, ctx->base.pc_next);
3770 l1 = gen_new_label();
3771 if ((bo & 0x4) == 0) {
3772 /* Decrement and test CTR */
3773 TCGv temp = tcg_temp_new();
3774 if (unlikely(type == BCOND_CTR)) {
3775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3776 return;
3777 }
3778 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3779 if (NARROW_MODE(ctx)) {
3780 tcg_gen_ext32u_tl(temp, cpu_ctr);
3781 } else {
3782 tcg_gen_mov_tl(temp, cpu_ctr);
3783 }
3784 if (bo & 0x2) {
3785 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3786 } else {
3787 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3788 }
3789 tcg_temp_free(temp);
3790 }
3791 if ((bo & 0x10) == 0) {
3792 /* Test CR */
3793 uint32_t bi = BI(ctx->opcode);
3794 uint32_t mask = 0x08 >> (bi & 0x03);
3795 TCGv_i32 temp = tcg_temp_new_i32();
3796
3797 if (bo & 0x8) {
3798 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3799 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3800 } else {
3801 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3802 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3803 }
3804 tcg_temp_free_i32(temp);
3805 }
3806 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3807 if (type == BCOND_IM) {
3808 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3809 if (likely(AA(ctx->opcode) == 0)) {
3810 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3811 } else {
3812 gen_goto_tb(ctx, 0, li);
3813 }
3814 } else {
3815 if (NARROW_MODE(ctx)) {
3816 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3817 } else {
3818 tcg_gen_andi_tl(cpu_nip, target, ~3);
3819 }
3820 gen_lookup_and_goto_ptr(ctx);
3821 tcg_temp_free(target);
3822 }
3823 if ((bo & 0x14) != 0x14) {
3824 /* fallthrough case */
3825 gen_set_label(l1);
3826 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3827 }
3828 }
3829
3830 static void gen_bc(DisasContext *ctx)
3831 {
3832 gen_bcond(ctx, BCOND_IM);
3833 }
3834
3835 static void gen_bcctr(DisasContext *ctx)
3836 {
3837 gen_bcond(ctx, BCOND_CTR);
3838 }
3839
3840 static void gen_bclr(DisasContext *ctx)
3841 {
3842 gen_bcond(ctx, BCOND_LR);
3843 }
3844
3845 static void gen_bctar(DisasContext *ctx)
3846 {
3847 gen_bcond(ctx, BCOND_TAR);
3848 }
3849
3850 /*** Condition register logical ***/
3851 #define GEN_CRLOGIC(name, tcg_op, opc) \
3852 static void glue(gen_, name)(DisasContext *ctx) \
3853 { \
3854 uint8_t bitmask; \
3855 int sh; \
3856 TCGv_i32 t0, t1; \
3857 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3858 t0 = tcg_temp_new_i32(); \
3859 if (sh > 0) \
3860 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3861 else if (sh < 0) \
3862 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3863 else \
3864 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3865 t1 = tcg_temp_new_i32(); \
3866 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3867 if (sh > 0) \
3868 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3869 else if (sh < 0) \
3870 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3871 else \
3872 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3873 tcg_op(t0, t0, t1); \
3874 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3875 tcg_gen_andi_i32(t0, t0, bitmask); \
3876 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3877 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3878 tcg_temp_free_i32(t0); \
3879 tcg_temp_free_i32(t1); \
3880 }
3881
3882 /* crand */
3883 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3884 /* crandc */
3885 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3886 /* creqv */
3887 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3888 /* crnand */
3889 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3890 /* crnor */
3891 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3892 /* cror */
3893 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3894 /* crorc */
3895 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3896 /* crxor */
3897 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3898
3899 /* mcrf */
3900 static void gen_mcrf(DisasContext *ctx)
3901 {
3902 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3903 }
3904
3905 /*** System linkage ***/
3906
3907 /* rfi (supervisor only) */
3908 static void gen_rfi(DisasContext *ctx)
3909 {
3910 #if defined(CONFIG_USER_ONLY)
3911 GEN_PRIV;
3912 #else
3913 /* This instruction doesn't exist anymore on 64-bit server
3914 * processors compliant with arch 2.x
3915 */
3916 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3918 return;
3919 }
3920 /* Restore CPU state */
3921 CHK_SV;
3922 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3923 gen_helper_rfi(cpu_env);
3924 gen_sync_exception(ctx);
3925 #endif
3926 }
3927
3928 #if defined(TARGET_PPC64)
3929 static void gen_rfid(DisasContext *ctx)
3930 {
3931 #if defined(CONFIG_USER_ONLY)
3932 GEN_PRIV;
3933 #else
3934 /* Restore CPU state */
3935 CHK_SV;
3936 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3937 gen_helper_rfid(cpu_env);
3938 gen_sync_exception(ctx);
3939 #endif
3940 }
3941
3942 static void gen_hrfid(DisasContext *ctx)
3943 {
3944 #if defined(CONFIG_USER_ONLY)
3945 GEN_PRIV;
3946 #else
3947 /* Restore CPU state */
3948 CHK_HV;
3949 gen_helper_hrfid(cpu_env);
3950 gen_sync_exception(ctx);
3951 #endif
3952 }
3953 #endif
3954
3955 /* sc */
3956 #if defined(CONFIG_USER_ONLY)
3957 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3958 #else
3959 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3960 #endif
3961 static void gen_sc(DisasContext *ctx)
3962 {
3963 uint32_t lev;
3964
3965 lev = (ctx->opcode >> 5) & 0x7F;
3966 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3967 }
3968
3969 /*** Trap ***/
3970
3971 /* Check for unconditional traps (always or never) */
3972 static bool check_unconditional_trap(DisasContext *ctx)
3973 {
3974 /* Trap never */
3975 if (TO(ctx->opcode) == 0) {
3976 return true;
3977 }
3978 /* Trap always */
3979 if (TO(ctx->opcode) == 31) {
3980 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3981 return true;
3982 }
3983 return false;
3984 }
3985
3986 /* tw */
3987 static void gen_tw(DisasContext *ctx)
3988 {
3989 TCGv_i32 t0;
3990
3991 if (check_unconditional_trap(ctx)) {
3992 return;
3993 }
3994 t0 = tcg_const_i32(TO(ctx->opcode));
3995 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3996 t0);
3997 tcg_temp_free_i32(t0);
3998 }
3999
4000 /* twi */
4001 static void gen_twi(DisasContext *ctx)
4002 {
4003 TCGv t0;
4004 TCGv_i32 t1;
4005
4006 if (check_unconditional_trap(ctx)) {
4007 return;
4008 }
4009 t0 = tcg_const_tl(SIMM(ctx->opcode));
4010 t1 = tcg_const_i32(TO(ctx->opcode));
4011 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4012 tcg_temp_free(t0);
4013 tcg_temp_free_i32(t1);
4014 }
4015
4016 #if defined(TARGET_PPC64)
4017 /* td */
4018 static void gen_td(DisasContext *ctx)
4019 {
4020 TCGv_i32 t0;
4021
4022 if (check_unconditional_trap(ctx)) {
4023 return;
4024 }
4025 t0 = tcg_const_i32(TO(ctx->opcode));
4026 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4027 t0);
4028 tcg_temp_free_i32(t0);
4029 }
4030
4031 /* tdi */
4032 static void gen_tdi(DisasContext *ctx)
4033 {
4034 TCGv t0;
4035 TCGv_i32 t1;
4036
4037 if (check_unconditional_trap(ctx)) {
4038 return;
4039 }
4040 t0 = tcg_const_tl(SIMM(ctx->opcode));
4041 t1 = tcg_const_i32(TO(ctx->opcode));
4042 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4043 tcg_temp_free(t0);
4044 tcg_temp_free_i32(t1);
4045 }
4046 #endif
4047
4048 /*** Processor control ***/
4049
4050 static void gen_read_xer(DisasContext *ctx, TCGv dst)
4051 {
4052 TCGv t0 = tcg_temp_new();
4053 TCGv t1 = tcg_temp_new();
4054 TCGv t2 = tcg_temp_new();
4055 tcg_gen_mov_tl(dst, cpu_xer);
4056 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4057 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4058 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4059 tcg_gen_or_tl(t0, t0, t1);
4060 tcg_gen_or_tl(dst, dst, t2);
4061 tcg_gen_or_tl(dst, dst, t0);
4062 if (is_isa300(ctx)) {
4063 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
4064 tcg_gen_or_tl(dst, dst, t0);
4065 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
4066 tcg_gen_or_tl(dst, dst, t0);
4067 }
4068 tcg_temp_free(t0);
4069 tcg_temp_free(t1);
4070 tcg_temp_free(t2);
4071 }
4072
4073 static void gen_write_xer(TCGv src)
4074 {
4075 /* Write all flags, while reading back check for isa300 */
4076 tcg_gen_andi_tl(cpu_xer, src,
4077 ~((1u << XER_SO) |
4078 (1u << XER_OV) | (1u << XER_OV32) |
4079 (1u << XER_CA) | (1u << XER_CA32)));
4080 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
4081 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
4082 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
4083 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
4084 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
4085 }
4086
4087 /* mcrxr */
4088 static void gen_mcrxr(DisasContext *ctx)
4089 {
4090 TCGv_i32 t0 = tcg_temp_new_i32();
4091 TCGv_i32 t1 = tcg_temp_new_i32();
4092 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4093
4094 tcg_gen_trunc_tl_i32(t0, cpu_so);
4095 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4096 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4097 tcg_gen_shli_i32(t0, t0, 3);
4098 tcg_gen_shli_i32(t1, t1, 2);
4099 tcg_gen_shli_i32(dst, dst, 1);
4100 tcg_gen_or_i32(dst, dst, t0);
4101 tcg_gen_or_i32(dst, dst, t1);
4102 tcg_temp_free_i32(t0);
4103 tcg_temp_free_i32(t1);
4104
4105 tcg_gen_movi_tl(cpu_so, 0);
4106 tcg_gen_movi_tl(cpu_ov, 0);
4107 tcg_gen_movi_tl(cpu_ca, 0);
4108 }
4109
4110 #ifdef TARGET_PPC64
4111 /* mcrxrx */
4112 static void gen_mcrxrx(DisasContext *ctx)
4113 {
4114 TCGv t0 = tcg_temp_new();
4115 TCGv t1 = tcg_temp_new();
4116 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4117
4118 /* copy OV and OV32 */
4119 tcg_gen_shli_tl(t0, cpu_ov, 1);
4120 tcg_gen_or_tl(t0, t0, cpu_ov32);
4121 tcg_gen_shli_tl(t0, t0, 2);
4122 /* copy CA and CA32 */
4123 tcg_gen_shli_tl(t1, cpu_ca, 1);
4124 tcg_gen_or_tl(t1, t1, cpu_ca32);
4125 tcg_gen_or_tl(t0, t0, t1);
4126 tcg_gen_trunc_tl_i32(dst, t0);
4127 tcg_temp_free(t0);
4128 tcg_temp_free(t1);
4129 }
4130 #endif
4131
4132 /* mfcr mfocrf */
4133 static void gen_mfcr(DisasContext *ctx)
4134 {
4135 uint32_t crm, crn;
4136
4137 if (likely(ctx->opcode & 0x00100000)) {
4138 crm = CRM(ctx->opcode);
4139 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4140 crn = ctz32 (crm);
4141 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4142 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4143 cpu_gpr[rD(ctx->opcode)], crn * 4);
4144 }
4145 } else {
4146 TCGv_i32 t0 = tcg_temp_new_i32();
4147 tcg_gen_mov_i32(t0, cpu_crf[0]);
4148 tcg_gen_shli_i32(t0, t0, 4);
4149 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4150 tcg_gen_shli_i32(t0, t0, 4);
4151 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4152 tcg_gen_shli_i32(t0, t0, 4);
4153 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4154 tcg_gen_shli_i32(t0, t0, 4);
4155 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4156 tcg_gen_shli_i32(t0, t0, 4);
4157 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4158 tcg_gen_shli_i32(t0, t0, 4);
4159 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4160 tcg_gen_shli_i32(t0, t0, 4);
4161 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4162 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4163 tcg_temp_free_i32(t0);
4164 }
4165 }
4166
4167 /* mfmsr */
4168 static void gen_mfmsr(DisasContext *ctx)
4169 {
4170 CHK_SV;
4171 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4172 }
4173
4174 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4175 {
4176 #if 0
4177 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4178 printf("ERROR: try to access SPR %d !\n", sprn);
4179 #endif
4180 }
4181 #define SPR_NOACCESS (&spr_noaccess)
4182
4183 /* mfspr */
4184 static inline void gen_op_mfspr(DisasContext *ctx)
4185 {
4186 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4187 uint32_t sprn = SPR(ctx->opcode);
4188
4189 #if defined(CONFIG_USER_ONLY)
4190 read_cb = ctx->spr_cb[sprn].uea_read;
4191 #else
4192 if (ctx->pr) {
4193 read_cb = ctx->spr_cb[sprn].uea_read;
4194 } else if (ctx->hv) {
4195 read_cb = ctx->spr_cb[sprn].hea_read;
4196 } else {
4197 read_cb = ctx->spr_cb[sprn].oea_read;
4198 }
4199 #endif
4200 if (likely(read_cb != NULL)) {
4201 if (likely(read_cb != SPR_NOACCESS)) {
4202 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4203 } else {
4204 /* Privilege exception */
4205 /* This is a hack to avoid warnings when running Linux:
4206 * this OS breaks the PowerPC virtualisation model,
4207 * allowing userland application to read the PVR
4208 */
4209 if (sprn != SPR_PVR) {
4210 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4211 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4212 ctx->base.pc_next - 4);
4213 }
4214 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4215 }
4216 } else {
4217 /* ISA 2.07 defines these as no-ops */
4218 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4219 (sprn >= 808 && sprn <= 811)) {
4220 /* This is a nop */
4221 return;
4222 }
4223 /* Not defined */
4224 qemu_log_mask(LOG_GUEST_ERROR,
4225 "Trying to read invalid spr %d (0x%03x) at "
4226 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4227
4228 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4229 * it can generate a priv, a hv emu or a no-op
4230 */
4231 if (sprn & 0x10) {
4232 if (ctx->pr) {
4233 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4234 }
4235 } else {
4236 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4237 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4238 }
4239 }
4240 }
4241 }
4242
4243 static void gen_mfspr(DisasContext *ctx)
4244 {
4245 gen_op_mfspr(ctx);
4246 }
4247
4248 /* mftb */
4249 static void gen_mftb(DisasContext *ctx)
4250 {
4251 gen_op_mfspr(ctx);
4252 }
4253
4254 /* mtcrf mtocrf*/
4255 static void gen_mtcrf(DisasContext *ctx)
4256 {
4257 uint32_t crm, crn;
4258
4259 crm = CRM(ctx->opcode);
4260 if (likely((ctx->opcode & 0x00100000))) {
4261 if (crm && ((crm & (crm - 1)) == 0)) {
4262 TCGv_i32 temp = tcg_temp_new_i32();
4263 crn = ctz32 (crm);
4264 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4265 tcg_gen_shri_i32(temp, temp, crn * 4);
4266 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4267 tcg_temp_free_i32(temp);
4268 }
4269 } else {
4270 TCGv_i32 temp = tcg_temp_new_i32();
4271 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4272 for (crn = 0 ; crn < 8 ; crn++) {
4273 if (crm & (1 << crn)) {
4274 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4275 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4276 }
4277 }
4278 tcg_temp_free_i32(temp);
4279 }
4280 }
4281
4282 /* mtmsr */
4283 #if defined(TARGET_PPC64)
4284 static void gen_mtmsrd(DisasContext *ctx)
4285 {
4286 CHK_SV;
4287
4288 #if !defined(CONFIG_USER_ONLY)
4289 if (ctx->opcode & 0x00010000) {
4290 /* Special form that does not need any synchronisation */
4291 TCGv t0 = tcg_temp_new();
4292 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4293 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4294 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4295 tcg_temp_free(t0);
4296 } else {
4297 /* XXX: we need to update nip before the store
4298 * if we enter power saving mode, we will exit the loop
4299 * directly from ppc_store_msr
4300 */
4301 gen_update_nip(ctx, ctx->base.pc_next);
4302 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4303 /* Must stop the translation as machine state (may have) changed */
4304 /* Note that mtmsr is not always defined as context-synchronizing */
4305 gen_stop_exception(ctx);
4306 }
4307 #endif /* !defined(CONFIG_USER_ONLY) */
4308 }
4309 #endif /* defined(TARGET_PPC64) */
4310
4311 static void gen_mtmsr(DisasContext *ctx)
4312 {
4313 CHK_SV;
4314
4315 #if !defined(CONFIG_USER_ONLY)
4316 if (ctx->opcode & 0x00010000) {
4317 /* Special form that does not need any synchronisation */
4318 TCGv t0 = tcg_temp_new();
4319 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4320 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4321 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4322 tcg_temp_free(t0);
4323 } else {
4324 TCGv msr = tcg_temp_new();
4325
4326 /* XXX: we need to update nip before the store
4327 * if we enter power saving mode, we will exit the loop
4328 * directly from ppc_store_msr
4329 */
4330 gen_update_nip(ctx, ctx->base.pc_next);
4331 #if defined(TARGET_PPC64)
4332 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4333 #else
4334 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4335 #endif
4336 gen_helper_store_msr(cpu_env, msr);
4337 tcg_temp_free(msr);
4338 /* Must stop the translation as machine state (may have) changed */
4339 /* Note that mtmsr is not always defined as context-synchronizing */
4340 gen_stop_exception(ctx);
4341 }
4342 #endif
4343 }
4344
4345 /* mtspr */
4346 static void gen_mtspr(DisasContext *ctx)
4347 {
4348 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4349 uint32_t sprn = SPR(ctx->opcode);
4350
4351 #if defined(CONFIG_USER_ONLY)
4352 write_cb = ctx->spr_cb[sprn].uea_write;
4353 #else
4354 if (ctx->pr) {
4355 write_cb = ctx->spr_cb[sprn].uea_write;
4356 } else if (ctx->hv) {
4357 write_cb = ctx->spr_cb[sprn].hea_write;
4358 } else {
4359 write_cb = ctx->spr_cb[sprn].oea_write;
4360 }
4361 #endif
4362 if (likely(write_cb != NULL)) {
4363 if (likely(write_cb != SPR_NOACCESS)) {
4364 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4365 } else {
4366 /* Privilege exception */
4367 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4368 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4369 ctx->base.pc_next - 4);
4370 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4371 }
4372 } else {
4373 /* ISA 2.07 defines these as no-ops */
4374 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4375 (sprn >= 808 && sprn <= 811)) {
4376 /* This is a nop */
4377 return;
4378 }
4379
4380 /* Not defined */
4381 qemu_log_mask(LOG_GUEST_ERROR,
4382 "Trying to write invalid spr %d (0x%03x) at "
4383 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4384
4385
4386 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4387 * it can generate a priv, a hv emu or a no-op
4388 */
4389 if (sprn & 0x10) {
4390 if (ctx->pr) {
4391 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4392 }
4393 } else {
4394 if (ctx->pr || sprn == 0) {
4395 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4396 }
4397 }
4398 }
4399 }
4400
4401 #if defined(TARGET_PPC64)
4402 /* setb */
4403 static void gen_setb(DisasContext *ctx)
4404 {
4405 TCGv_i32 t0 = tcg_temp_new_i32();
4406 TCGv_i32 t8 = tcg_temp_new_i32();
4407 TCGv_i32 tm1 = tcg_temp_new_i32();
4408 int crf = crfS(ctx->opcode);
4409
4410 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4411 tcg_gen_movi_i32(t8, 8);
4412 tcg_gen_movi_i32(tm1, -1);
4413 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4414 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4415
4416 tcg_temp_free_i32(t0);
4417 tcg_temp_free_i32(t8);
4418 tcg_temp_free_i32(tm1);
4419 }
4420 #endif
4421
4422 /*** Cache management ***/
4423
4424 /* dcbf */
4425 static void gen_dcbf(DisasContext *ctx)
4426 {
4427 /* XXX: specification says this is treated as a load by the MMU */
4428 TCGv t0;
4429 gen_set_access_type(ctx, ACCESS_CACHE);
4430 t0 = tcg_temp_new();
4431 gen_addr_reg_index(ctx, t0);
4432 gen_qemu_ld8u(ctx, t0, t0);
4433 tcg_temp_free(t0);
4434 }
4435
4436 /* dcbfep (external PID dcbf) */
4437 static void gen_dcbfep(DisasContext *ctx)
4438 {
4439 /* XXX: specification says this is treated as a load by the MMU */
4440 TCGv t0;
4441 CHK_SV;
4442 gen_set_access_type(ctx, ACCESS_CACHE);
4443 t0 = tcg_temp_new();
4444 gen_addr_reg_index(ctx, t0);
4445 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4446 tcg_temp_free(t0);
4447 }
4448
4449 /* dcbi (Supervisor only) */
4450 static void gen_dcbi(DisasContext *ctx)
4451 {
4452 #if defined(CONFIG_USER_ONLY)
4453 GEN_PRIV;
4454 #else
4455 TCGv EA, val;
4456
4457 CHK_SV;
4458 EA = tcg_temp_new();
4459 gen_set_access_type(ctx, ACCESS_CACHE);
4460 gen_addr_reg_index(ctx, EA);
4461 val = tcg_temp_new();
4462 /* XXX: specification says this should be treated as a store by the MMU */
4463 gen_qemu_ld8u(ctx, val, EA);
4464 gen_qemu_st8(ctx, val, EA);
4465 tcg_temp_free(val);
4466 tcg_temp_free(EA);
4467 #endif /* defined(CONFIG_USER_ONLY) */
4468 }
4469
4470 /* dcdst */
4471 static void gen_dcbst(DisasContext *ctx)
4472 {
4473 /* XXX: specification say this is treated as a load by the MMU */
4474 TCGv t0;
4475 gen_set_access_type(ctx, ACCESS_CACHE);
4476 t0 = tcg_temp_new();
4477 gen_addr_reg_index(ctx, t0);
4478 gen_qemu_ld8u(ctx, t0, t0);
4479 tcg_temp_free(t0);
4480 }
4481
4482 /* dcbstep (dcbstep External PID version) */
4483 static void gen_dcbstep(DisasContext *ctx)
4484 {
4485 /* XXX: specification say this is treated as a load by the MMU */
4486 TCGv t0;
4487 gen_set_access_type(ctx, ACCESS_CACHE);
4488 t0 = tcg_temp_new();
4489 gen_addr_reg_index(ctx, t0);
4490 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4491 tcg_temp_free(t0);
4492 }
4493
4494 /* dcbt */
4495 static void gen_dcbt(DisasContext *ctx)
4496 {
4497 /* interpreted as no-op */
4498 /* XXX: specification say this is treated as a load by the MMU
4499 * but does not generate any exception
4500 */
4501 }
4502
4503 /* dcbtep */
4504 static void gen_dcbtep(DisasContext *ctx)
4505 {
4506 /* interpreted as no-op */
4507 /* XXX: specification say this is treated as a load by the MMU
4508 * but does not generate any exception
4509 */
4510 }
4511
4512 /* dcbtst */
4513 static void gen_dcbtst(DisasContext *ctx)
4514 {
4515 /* interpreted as no-op */
4516 /* XXX: specification say this is treated as a load by the MMU
4517 * but does not generate any exception
4518 */
4519 }
4520
4521 /* dcbtstep */
4522 static void gen_dcbtstep(DisasContext *ctx)
4523 {
4524 /* interpreted as no-op */
4525 /* XXX: specification say this is treated as a load by the MMU
4526 * but does not generate any exception
4527 */
4528 }
4529
4530 /* dcbtls */
4531 static void gen_dcbtls(DisasContext *ctx)
4532 {
4533 /* Always fails locking the cache */
4534 TCGv t0 = tcg_temp_new();
4535 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4536 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4537 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4538 tcg_temp_free(t0);
4539 }
4540
4541 /* dcbz */
4542 static void gen_dcbz(DisasContext *ctx)
4543 {
4544 TCGv tcgv_addr;
4545 TCGv_i32 tcgv_op;
4546
4547 gen_set_access_type(ctx, ACCESS_CACHE);
4548 tcgv_addr = tcg_temp_new();
4549 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4550 gen_addr_reg_index(ctx, tcgv_addr);
4551 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4552 tcg_temp_free(tcgv_addr);
4553 tcg_temp_free_i32(tcgv_op);
4554 }
4555
4556 /* dcbzep */
4557 static void gen_dcbzep(DisasContext *ctx)
4558 {
4559 TCGv tcgv_addr;
4560 TCGv_i32 tcgv_op;
4561
4562 gen_set_access_type(ctx, ACCESS_CACHE);
4563 tcgv_addr = tcg_temp_new();
4564 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4565 gen_addr_reg_index(ctx, tcgv_addr);
4566 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
4567 tcg_temp_free(tcgv_addr);
4568 tcg_temp_free_i32(tcgv_op);
4569 }
4570
4571 /* dst / dstt */
4572 static void gen_dst(DisasContext *ctx)
4573 {
4574 if (rA(ctx->opcode) == 0) {
4575 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4576 } else {
4577 /* interpreted as no-op */
4578 }
4579 }
4580
4581 /* dstst /dststt */
4582 static void gen_dstst(DisasContext *ctx)
4583 {
4584 if (rA(ctx->opcode) == 0) {
4585 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4586 } else {
4587 /* interpreted as no-op */
4588 }
4589
4590 }
4591
4592 /* dss / dssall */
4593 static void gen_dss(DisasContext *ctx)
4594 {
4595 /* interpreted as no-op */
4596 }
4597
4598 /* icbi */
4599 static void gen_icbi(DisasContext *ctx)
4600 {
4601 TCGv t0;
4602 gen_set_access_type(ctx, ACCESS_CACHE);
4603 t0 = tcg_temp_new();
4604 gen_addr_reg_index(ctx, t0);
4605 gen_helper_icbi(cpu_env, t0);
4606 tcg_temp_free(t0);
4607 }
4608
4609 /* icbiep */
4610 static void gen_icbiep(DisasContext *ctx)
4611 {
4612 TCGv t0;
4613 gen_set_access_type(ctx, ACCESS_CACHE);
4614 t0 = tcg_temp_new();
4615 gen_addr_reg_index(ctx, t0);
4616 gen_helper_icbiep(cpu_env, t0);
4617 tcg_temp_free(t0);
4618 }
4619
4620 /* Optional: */
4621 /* dcba */
4622 static void gen_dcba(DisasContext *ctx)
4623 {
4624 /* interpreted as no-op */
4625 /* XXX: specification say this is treated as a store by the MMU
4626 * but does not generate any exception
4627 */
4628 }
4629
4630 /*** Segment register manipulation ***/
4631 /* Supervisor only: */
4632
4633 /* mfsr */
4634 static void gen_mfsr(DisasContext *ctx)
4635 {
4636 #if defined(CONFIG_USER_ONLY)
4637 GEN_PRIV;
4638 #else
4639 TCGv t0;
4640
4641 CHK_SV;
4642 t0 = tcg_const_tl(SR(ctx->opcode));
4643 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4644 tcg_temp_free(t0);
4645 #endif /* defined(CONFIG_USER_ONLY) */
4646 }
4647
4648 /* mfsrin */
4649 static void gen_mfsrin(DisasContext *ctx)
4650 {
4651 #if defined(CONFIG_USER_ONLY)
4652 GEN_PRIV;
4653 #else
4654 TCGv t0;
4655
4656 CHK_SV;
4657 t0 = tcg_temp_new();
4658 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4659 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4660 tcg_temp_free(t0);
4661 #endif /* defined(CONFIG_USER_ONLY) */
4662 }
4663
4664 /* mtsr */
4665 static void gen_mtsr(DisasContext *ctx)
4666 {
4667 #if defined(CONFIG_USER_ONLY)
4668 GEN_PRIV;
4669 #else
4670 TCGv t0;
4671
4672 CHK_SV;
4673 t0 = tcg_const_tl(SR(ctx->opcode));
4674 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4675 tcg_temp_free(t0);
4676 #endif /* defined(CONFIG_USER_ONLY) */
4677 }
4678
4679 /* mtsrin */
4680 static void gen_mtsrin(DisasContext *ctx)
4681 {
4682 #if defined(CONFIG_USER_ONLY)
4683 GEN_PRIV;
4684 #else
4685 TCGv t0;
4686 CHK_SV;
4687
4688 t0 = tcg_temp_new();
4689 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4690 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4691 tcg_temp_free(t0);
4692 #endif /* defined(CONFIG_USER_ONLY) */
4693 }
4694
4695 #if defined(TARGET_PPC64)
4696 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4697
4698 /* mfsr */
4699 static void gen_mfsr_64b(DisasContext *ctx)
4700 {
4701 #if defined(CONFIG_USER_ONLY)
4702 GEN_PRIV;
4703 #else
4704 TCGv t0;
4705
4706 CHK_SV;
4707 t0 = tcg_const_tl(SR(ctx->opcode));
4708 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4709 tcg_temp_free(t0);
4710 #endif /* defined(CONFIG_USER_ONLY) */
4711 }
4712
4713 /* mfsrin */
4714 static void gen_mfsrin_64b(DisasContext *ctx)
4715 {
4716 #if defined(CONFIG_USER_ONLY)
4717 GEN_PRIV;
4718 #else
4719 TCGv t0;
4720
4721 CHK_SV;
4722 t0 = tcg_temp_new();
4723 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4724 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4725 tcg_temp_free(t0);
4726 #endif /* defined(CONFIG_USER_ONLY) */
4727 }
4728
4729 /* mtsr */
4730 static void gen_mtsr_64b(DisasContext *ctx)
4731 {
4732 #if defined(CONFIG_USER_ONLY)
4733 GEN_PRIV;
4734 #else
4735 TCGv t0;
4736
4737 CHK_SV;
4738 t0 = tcg_const_tl(SR(ctx->opcode));
4739 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4740 tcg_temp_free(t0);
4741 #endif /* defined(CONFIG_USER_ONLY) */
4742 }
4743
4744 /* mtsrin */
4745 static void gen_mtsrin_64b(DisasContext *ctx)
4746 {
4747 #if defined(CONFIG_USER_ONLY)
4748 GEN_PRIV;
4749 #else
4750 TCGv t0;
4751
4752 CHK_SV;
4753 t0 = tcg_temp_new();
4754 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4755 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4756 tcg_temp_free(t0);
4757 #endif /* defined(CONFIG_USER_ONLY) */
4758 }
4759
4760 /* slbmte */
4761 static void gen_slbmte(DisasContext *ctx)
4762 {
4763 #if defined(CONFIG_USER_ONLY)
4764 GEN_PRIV;
4765 #else
4766 CHK_SV;
4767
4768 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4769 cpu_gpr[rS(ctx->opcode)]);
4770 #endif /* defined(CONFIG_USER_ONLY) */
4771 }
4772
4773 static void gen_slbmfee(DisasContext *ctx)
4774 {
4775 #if defined(CONFIG_USER_ONLY)
4776 GEN_PRIV;
4777 #else
4778 CHK_SV;
4779
4780 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4781 cpu_gpr[rB(ctx->opcode)]);
4782 #endif /* defined(CONFIG_USER_ONLY) */
4783 }
4784
4785 static void gen_slbmfev(DisasContext *ctx)
4786 {
4787 #if defined(CONFIG_USER_ONLY)
4788 GEN_PRIV;
4789 #else
4790 CHK_SV;
4791
4792 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4793 cpu_gpr[rB(ctx->opcode)]);
4794 #endif /* defined(CONFIG_USER_ONLY) */
4795 }
4796
4797 static void gen_slbfee_(DisasContext *ctx)
4798 {
4799 #if defined(CONFIG_USER_ONLY)
4800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4801 #else
4802 TCGLabel *l1, *l2;
4803
4804 if (unlikely(ctx->pr)) {
4805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4806 return;
4807 }
4808 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4809 cpu_gpr[rB(ctx->opcode)]);
4810 l1 = gen_new_label();
4811 l2 = gen_new_label();
4812 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4813 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4814 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4815 tcg_gen_br(l2);
4816 gen_set_label(l1);
4817 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4818 gen_set_label(l2);
4819 #endif
4820 }
4821 #endif /* defined(TARGET_PPC64) */
4822
4823 /*** Lookaside buffer management ***/
4824 /* Optional & supervisor only: */
4825
4826 /* tlbia */
4827 static void gen_tlbia(DisasContext *ctx)
4828 {
4829 #if defined(CONFIG_USER_ONLY)
4830 GEN_PRIV;
4831 #else
4832 CHK_HV;
4833
4834 gen_helper_tlbia(cpu_env);
4835 #endif /* defined(CONFIG_USER_ONLY) */
4836 }
4837
4838 /* tlbiel */
4839 static void gen_tlbiel(DisasContext *ctx)
4840 {
4841 #if defined(CONFIG_USER_ONLY)
4842 GEN_PRIV;
4843 #else
4844 CHK_SV;
4845
4846 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4847 #endif /* defined(CONFIG_USER_ONLY) */
4848 }
4849
4850 /* tlbie */
4851 static void gen_tlbie(DisasContext *ctx)
4852 {
4853 #if defined(CONFIG_USER_ONLY)
4854 GEN_PRIV;
4855 #else
4856 TCGv_i32 t1;
4857
4858 if (ctx->gtse) {
4859 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4860 } else {
4861 CHK_HV; /* Else hypervisor privileged */
4862 }
4863
4864 if (NARROW_MODE(ctx)) {
4865 TCGv t0 = tcg_temp_new();
4866 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4867 gen_helper_tlbie(cpu_env, t0);
4868 tcg_temp_free(t0);
4869 } else {
4870 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4871 }
4872 t1 = tcg_temp_new_i32();
4873 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4874 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4875 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4876 tcg_temp_free_i32(t1);
4877 #endif /* defined(CONFIG_USER_ONLY) */
4878 }
4879
4880 /* tlbsync */
4881 static void gen_tlbsync(DisasContext *ctx)
4882 {
4883 #if defined(CONFIG_USER_ONLY)
4884 GEN_PRIV;
4885 #else
4886
4887 if (ctx->gtse) {
4888 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4889 } else {
4890 CHK_HV; /* Else hypervisor privileged */
4891 }
4892
4893 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4894 if (ctx->insns_flags & PPC_BOOKE) {
4895 gen_check_tlb_flush(ctx, true);
4896 }
4897 #endif /* defined(CONFIG_USER_ONLY) */
4898 }
4899
4900 #if defined(TARGET_PPC64)
4901 /* slbia */
4902 static void gen_slbia(DisasContext *ctx)
4903 {
4904 #if defined(CONFIG_USER_ONLY)
4905 GEN_PRIV;
4906 #else
4907 CHK_SV;
4908
4909 gen_helper_slbia(cpu_env);
4910 #endif /* defined(CONFIG_USER_ONLY) */
4911 }
4912
4913 /* slbie */
4914 static void gen_slbie(DisasContext *ctx)
4915 {
4916 #if defined(CONFIG_USER_ONLY)
4917 GEN_PRIV;
4918 #else
4919 CHK_SV;
4920
4921 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4922 #endif /* defined(CONFIG_USER_ONLY) */
4923 }
4924
4925 /* slbieg */
4926 static void gen_slbieg(DisasContext *ctx)
4927 {
4928 #if defined(CONFIG_USER_ONLY)
4929 GEN_PRIV;
4930 #else
4931 CHK_SV;
4932
4933 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4934 #endif /* defined(CONFIG_USER_ONLY) */
4935 }
4936
4937 /* slbsync */
4938 static void gen_slbsync(DisasContext *ctx)
4939 {
4940 #if defined(CONFIG_USER_ONLY)
4941 GEN_PRIV;
4942 #else
4943 CHK_SV;
4944 gen_check_tlb_flush(ctx, true);
4945 #endif /* defined(CONFIG_USER_ONLY) */
4946 }
4947
4948 #endif /* defined(TARGET_PPC64) */
4949
4950 /*** External control ***/
4951 /* Optional: */
4952
4953 /* eciwx */
4954 static void gen_eciwx(DisasContext *ctx)
4955 {
4956 TCGv t0;
4957 /* Should check EAR[E] ! */
4958 gen_set_access_type(ctx, ACCESS_EXT);
4959 t0 = tcg_temp_new();
4960 gen_addr_reg_index(ctx, t0);
4961 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4962 DEF_MEMOP(MO_UL | MO_ALIGN));
4963 tcg_temp_free(t0);
4964 }
4965
4966 /* ecowx */
4967 static void gen_ecowx(DisasContext *ctx)
4968 {
4969 TCGv t0;
4970 /* Should check EAR[E] ! */
4971 gen_set_access_type(ctx, ACCESS_EXT);
4972 t0 = tcg_temp_new();
4973 gen_addr_reg_index(ctx, t0);
4974 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
4975 DEF_MEMOP(MO_UL | MO_ALIGN));
4976 tcg_temp_free(t0);
4977 }
4978
4979 /* PowerPC 601 specific instructions */
4980
4981 /* abs - abs. */
4982 static void gen_abs(DisasContext *ctx)
4983 {
4984 TCGLabel *l1 = gen_new_label();
4985 TCGLabel *l2 = gen_new_label();
4986 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4987 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4988 tcg_gen_br(l2);
4989 gen_set_label(l1);
4990 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4991 gen_set_label(l2);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4994 }
4995
4996 /* abso - abso. */
4997 static void gen_abso(DisasContext *ctx)
4998 {
4999 TCGLabel *l1 = gen_new_label();
5000 TCGLabel *l2 = gen_new_label();
5001 TCGLabel *l3 = gen_new_label();
5002 /* Start with XER OV disabled, the most likely case */
5003 tcg_gen_movi_tl(cpu_ov, 0);
5004 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5005 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5006 tcg_gen_movi_tl(cpu_ov, 1);
5007 tcg_gen_movi_tl(cpu_so, 1);
5008 tcg_gen_br(l2);
5009 gen_set_label(l1);
5010 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5011 tcg_gen_br(l3);
5012 gen_set_label(l2);
5013 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5014 gen_set_label(l3);
5015 if (unlikely(Rc(ctx->opcode) != 0))
5016 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5017 }
5018
5019 /* clcs */
5020 static void gen_clcs(DisasContext *ctx)
5021 {
5022 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5023 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5024 tcg_temp_free_i32(t0);
5025 /* Rc=1 sets CR0 to an undefined state */
5026 }
5027
5028 /* div - div. */
5029 static void gen_div(DisasContext *ctx)
5030 {
5031 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5032 cpu_gpr[rB(ctx->opcode)]);
5033 if (unlikely(Rc(ctx->opcode) != 0))
5034 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5035 }
5036
5037 /* divo - divo. */
5038 static void gen_divo(DisasContext *ctx)
5039 {
5040 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5041 cpu_gpr[rB(ctx->opcode)]);
5042 if (unlikely(Rc(ctx->opcode) != 0))
5043 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5044 }
5045
5046 /* divs - divs. */
5047 static void gen_divs(DisasContext *ctx)
5048 {
5049 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5050 cpu_gpr[rB(ctx->opcode)]);
5051 if (unlikely(Rc(ctx->opcode) != 0))
5052 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5053 }
5054
5055 /* divso - divso. */
5056 static void gen_divso(DisasContext *ctx)
5057 {
5058 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5059 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5060 if (unlikely(Rc(ctx->opcode) != 0))
5061 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5062 }
5063
5064 /* doz - doz. */
5065 static void gen_doz(DisasContext *ctx)
5066 {
5067 TCGLabel *l1 = gen_new_label();
5068 TCGLabel *l2 = gen_new_label();
5069 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5070 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5071 tcg_gen_br(l2);
5072 gen_set_label(l1);
5073 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5074 gen_set_label(l2);
5075 if (unlikely(Rc(ctx->opcode) != 0))
5076 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5077 }
5078
5079 /* dozo - dozo. */
5080 static void gen_dozo(DisasContext *ctx)
5081 {
5082 TCGLabel *l1 = gen_new_label();
5083 TCGLabel *l2 = gen_new_label();
5084 TCGv t0 = tcg_temp_new();
5085 TCGv t1 = tcg_temp_new();
5086 TCGv t2 = tcg_temp_new();
5087 /* Start with XER OV disabled, the most likely case */
5088 tcg_gen_movi_tl(cpu_ov, 0);
5089 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5090 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5091 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5092 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5093 tcg_gen_andc_tl(t1, t1, t2);
5094 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5095 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5096 tcg_gen_movi_tl(cpu_ov, 1);
5097 tcg_gen_movi_tl(cpu_so, 1);
5098 tcg_gen_br(l2);
5099 gen_set_label(l1);
5100 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5101 gen_set_label(l2);
5102 tcg_temp_free(t0);
5103 tcg_temp_free(t1);
5104 tcg_temp_free(t2);
5105 if (unlikely(Rc(ctx->opcode) != 0))
5106 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5107 }
5108
5109 /* dozi */
5110 static void gen_dozi(DisasContext *ctx)
5111 {
5112 target_long simm = SIMM(ctx->opcode);
5113 TCGLabel *l1 = gen_new_label();
5114 TCGLabel *l2 = gen_new_label();
5115 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5116 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5117 tcg_gen_br(l2);
5118 gen_set_label(l1);
5119 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5120 gen_set_label(l2);
5121 if (unlikely(Rc(ctx->opcode) != 0))
5122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5123 }
5124
5125 /* lscbx - lscbx. */
5126 static void gen_lscbx(DisasContext *ctx)
5127 {
5128 TCGv t0 = tcg_temp_new();
5129 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5130 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5131 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5132
5133 gen_addr_reg_index(ctx, t0);
5134 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5135 tcg_temp_free_i32(t1);
5136 tcg_temp_free_i32(t2);
5137 tcg_temp_free_i32(t3);
5138 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5139 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5140 if (unlikely(Rc(ctx->opcode) != 0))
5141 gen_set_Rc0(ctx, t0);
5142 tcg_temp_free(t0);
5143 }
5144
5145 /* maskg - maskg. */
5146 static void gen_maskg(DisasContext *ctx)
5147 {
5148 TCGLabel *l1 = gen_new_label();
5149 TCGv t0 = tcg_temp_new();
5150 TCGv t1 = tcg_temp_new();
5151 TCGv t2 = tcg_temp_new();
5152 TCGv t3 = tcg_temp_new();
5153 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5154 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5155 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5156 tcg_gen_addi_tl(t2, t0, 1);
5157 tcg_gen_shr_tl(t2, t3, t2);
5158 tcg_gen_shr_tl(t3, t3, t1);
5159 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5160 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5161 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5162 gen_set_label(l1);
5163 tcg_temp_free(t0);
5164 tcg_temp_free(t1);
5165 tcg_temp_free(t2);
5166 tcg_temp_free(t3);
5167 if (unlikely(Rc(ctx->opcode) != 0))
5168 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5169 }
5170
5171 /* maskir - maskir. */
5172 static void gen_maskir(DisasContext *ctx)
5173 {
5174 TCGv t0 = tcg_temp_new();
5175 TCGv t1 = tcg_temp_new();
5176 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5177 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5178 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5179 tcg_temp_free(t0);
5180 tcg_temp_free(t1);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5183 }
5184
5185 /* mul - mul. */
5186 static void gen_mul(DisasContext *ctx)
5187 {
5188 TCGv_i64 t0 = tcg_temp_new_i64();
5189 TCGv_i64 t1 = tcg_temp_new_i64();
5190 TCGv t2 = tcg_temp_new();
5191 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5192 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5193 tcg_gen_mul_i64(t0, t0, t1);
5194 tcg_gen_trunc_i64_tl(t2, t0);
5195 gen_store_spr(SPR_MQ, t2);
5196 tcg_gen_shri_i64(t1, t0, 32);
5197 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5198 tcg_temp_free_i64(t0);
5199 tcg_temp_free_i64(t1);
5200 tcg_temp_free(t2);
5201 if (unlikely(Rc(ctx->opcode) != 0))
5202 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5203 }
5204
5205 /* mulo - mulo. */
5206 static void gen_mulo(DisasContext *ctx)
5207 {
5208 TCGLabel *l1 = gen_new_label();
5209 TCGv_i64 t0 = tcg_temp_new_i64();
5210 TCGv_i64 t1 = tcg_temp_new_i64();
5211 TCGv t2 = tcg_temp_new();
5212 /* Start with XER OV disabled, the most likely case */
5213 tcg_gen_movi_tl(cpu_ov, 0);
5214 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5215 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5216 tcg_gen_mul_i64(t0, t0, t1);
5217 tcg_gen_trunc_i64_tl(t2, t0);
5218 gen_store_spr(SPR_MQ, t2);
5219 tcg_gen_shri_i64(t1, t0, 32);
5220 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5221 tcg_gen_ext32s_i64(t1, t0);
5222 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5223 tcg_gen_movi_tl(cpu_ov, 1);
5224 tcg_gen_movi_tl(cpu_so, 1);
5225 gen_set_label(l1);
5226 tcg_temp_free_i64(t0);
5227 tcg_temp_free_i64(t1);
5228 tcg_temp_free(t2);
5229 if (unlikely(Rc(ctx->opcode) != 0))
5230 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5231 }
5232
5233 /* nabs - nabs. */
5234 static void gen_nabs(DisasContext *ctx)
5235 {
5236 TCGLabel *l1 = gen_new_label();
5237 TCGLabel *l2 = gen_new_label();
5238 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5239 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5240 tcg_gen_br(l2);
5241 gen_set_label(l1);
5242 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5243 gen_set_label(l2);
5244 if (unlikely(Rc(ctx->opcode) != 0))
5245 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5246 }
5247
5248 /* nabso - nabso. */
5249 static void gen_nabso(DisasContext *ctx)
5250 {
5251 TCGLabel *l1 = gen_new_label();
5252 TCGLabel *l2 = gen_new_label();
5253 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5254 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5255 tcg_gen_br(l2);
5256 gen_set_label(l1);
5257 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5258 gen_set_label(l2);
5259 /* nabs never overflows */
5260 tcg_gen_movi_tl(cpu_ov, 0);
5261 if (unlikely(Rc(ctx->opcode) != 0))
5262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5263 }
5264
5265 /* rlmi - rlmi. */
5266 static void gen_rlmi(DisasContext *ctx)
5267 {
5268 uint32_t mb = MB(ctx->opcode);
5269 uint32_t me = ME(ctx->opcode);
5270 TCGv t0 = tcg_temp_new();
5271 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5272 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5273 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5274 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5275 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5276 tcg_temp_free(t0);
5277 if (unlikely(Rc(ctx->opcode) != 0))
5278 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5279 }
5280
5281 /* rrib - rrib. */
5282 static void gen_rrib(DisasContext *ctx)
5283 {
5284 TCGv t0 = tcg_temp_new();
5285 TCGv t1 = tcg_temp_new();
5286 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5287 tcg_gen_movi_tl(t1, 0x80000000);
5288 tcg_gen_shr_tl(t1, t1, t0);
5289 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5290 tcg_gen_and_tl(t0, t0, t1);
5291 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5292 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
5295 if (unlikely(Rc(ctx->opcode) != 0))
5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5297 }
5298
5299 /* sle - sle. */
5300 static void gen_sle(DisasContext *ctx)
5301 {
5302 TCGv t0 = tcg_temp_new();
5303 TCGv t1 = tcg_temp_new();
5304 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5305 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5306 tcg_gen_subfi_tl(t1, 32, t1);
5307 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5308 tcg_gen_or_tl(t1, t0, t1);
5309 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5310 gen_store_spr(SPR_MQ, t1);
5311 tcg_temp_free(t0);
5312 tcg_temp_free(t1);
5313 if (unlikely(Rc(ctx->opcode) != 0))
5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5315 }
5316
5317 /* sleq - sleq. */
5318 static void gen_sleq(DisasContext *ctx)
5319 {
5320 TCGv t0 = tcg_temp_new();
5321 TCGv t1 = tcg_temp_new();
5322 TCGv t2 = tcg_temp_new();
5323 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5324 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5325 tcg_gen_shl_tl(t2, t2, t0);
5326 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5327 gen_load_spr(t1, SPR_MQ);
5328 gen_store_spr(SPR_MQ, t0);
5329 tcg_gen_and_tl(t0, t0, t2);
5330 tcg_gen_andc_tl(t1, t1, t2);
5331 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5332 tcg_temp_free(t0);
5333 tcg_temp_free(t1);
5334 tcg_temp_free(t2);
5335 if (unlikely(Rc(ctx->opcode) != 0))
5336 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5337 }
5338
5339 /* sliq - sliq. */
5340 static void gen_sliq(DisasContext *ctx)
5341 {
5342 int sh = SH(ctx->opcode);
5343 TCGv t0 = tcg_temp_new();
5344 TCGv t1 = tcg_temp_new();
5345 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5346 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5347 tcg_gen_or_tl(t1, t0, t1);
5348 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5349 gen_store_spr(SPR_MQ, t1);
5350 tcg_temp_free(t0);
5351 tcg_temp_free(t1);
5352 if (unlikely(Rc(ctx->opcode) != 0))
5353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5354 }
5355
5356 /* slliq - slliq. */
5357 static void gen_slliq(DisasContext *ctx)
5358 {
5359 int sh = SH(ctx->opcode);
5360 TCGv t0 = tcg_temp_new();
5361 TCGv t1 = tcg_temp_new();
5362 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5363 gen_load_spr(t1, SPR_MQ);
5364 gen_store_spr(SPR_MQ, t0);
5365 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5366 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5367 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5368 tcg_temp_free(t0);
5369 tcg_temp_free(t1);
5370 if (unlikely(Rc(ctx->opcode) != 0))
5371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5372 }
5373
5374 /* sllq - sllq. */
5375 static void gen_sllq(DisasContext *ctx)
5376 {
5377 TCGLabel *l1 = gen_new_label();
5378 TCGLabel *l2 = gen_new_label();
5379 TCGv t0 = tcg_temp_local_new();
5380 TCGv t1 = tcg_temp_local_new();
5381 TCGv t2 = tcg_temp_local_new();
5382 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5383 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5384 tcg_gen_shl_tl(t1, t1, t2);
5385 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5386 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5387 gen_load_spr(t0, SPR_MQ);
5388 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5389 tcg_gen_br(l2);
5390 gen_set_label(l1);
5391 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5392 gen_load_spr(t2, SPR_MQ);
5393 tcg_gen_andc_tl(t1, t2, t1);
5394 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5395 gen_set_label(l2);
5396 tcg_temp_free(t0);
5397 tcg_temp_free(t1);
5398 tcg_temp_free(t2);
5399 if (unlikely(Rc(ctx->opcode) != 0))
5400 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5401 }
5402
5403 /* slq - slq. */
5404 static void gen_slq(DisasContext *ctx)
5405 {
5406 TCGLabel *l1 = gen_new_label();
5407 TCGv t0 = tcg_temp_new();
5408 TCGv t1 = tcg_temp_new();
5409 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5410 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5411 tcg_gen_subfi_tl(t1, 32, t1);
5412 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5413 tcg_gen_or_tl(t1, t0, t1);
5414 gen_store_spr(SPR_MQ, t1);
5415 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5416 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5417 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5418 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5419 gen_set_label(l1);
5420 tcg_temp_free(t0);
5421 tcg_temp_free(t1);
5422 if (unlikely(Rc(ctx->opcode) != 0))
5423 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5424 }
5425
5426 /* sraiq - sraiq. */
5427 static void gen_sraiq(DisasContext *ctx)
5428 {
5429 int sh = SH(ctx->opcode);
5430 TCGLabel *l1 = gen_new_label();
5431 TCGv t0 = tcg_temp_new();
5432 TCGv t1 = tcg_temp_new();
5433 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5434 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5435 tcg_gen_or_tl(t0, t0, t1);
5436 gen_store_spr(SPR_MQ, t0);
5437 tcg_gen_movi_tl(cpu_ca, 0);
5438 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5439 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5440 tcg_gen_movi_tl(cpu_ca, 1);
5441 gen_set_label(l1);
5442 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5443 tcg_temp_free(t0);
5444 tcg_temp_free(t1);
5445 if (unlikely(Rc(ctx->opcode) != 0))
5446 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5447 }
5448
5449 /* sraq - sraq. */
5450 static void gen_sraq(DisasContext *ctx)
5451 {
5452 TCGLabel *l1 = gen_new_label();
5453 TCGLabel *l2 = gen_new_label();
5454 TCGv t0 = tcg_temp_new();
5455 TCGv t1 = tcg_temp_local_new();
5456 TCGv t2 = tcg_temp_local_new();
5457 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5458 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5459 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5460 tcg_gen_subfi_tl(t2, 32, t2);
5461 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5462 tcg_gen_or_tl(t0, t0, t2);
5463 gen_store_spr(SPR_MQ, t0);
5464 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5465 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5466 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5467 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5468 gen_set_label(l1);
5469 tcg_temp_free(t0);
5470 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5471 tcg_gen_movi_tl(cpu_ca, 0);
5472 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5473 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5474 tcg_gen_movi_tl(cpu_ca, 1);
5475 gen_set_label(l2);
5476 tcg_temp_free(t1);
5477 tcg_temp_free(t2);
5478 if (unlikely(Rc(ctx->opcode) != 0))
5479 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5480 }
5481
5482 /* sre - sre. */
5483 static void gen_sre(DisasContext *ctx)
5484 {
5485 TCGv t0 = tcg_temp_new();
5486 TCGv t1 = tcg_temp_new();
5487 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5488 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5489 tcg_gen_subfi_tl(t1, 32, t1);
5490 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5491 tcg_gen_or_tl(t1, t0, t1);
5492 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5493 gen_store_spr(SPR_MQ, t1);
5494 tcg_temp_free(t0);
5495 tcg_temp_free(t1);
5496 if (unlikely(Rc(ctx->opcode) != 0))
5497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5498 }
5499
5500 /* srea - srea. */
5501 static void gen_srea(DisasContext *ctx)
5502 {
5503 TCGv t0 = tcg_temp_new();
5504 TCGv t1 = tcg_temp_new();
5505 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5506 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5507 gen_store_spr(SPR_MQ, t0);
5508 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5509 tcg_temp_free(t0);
5510 tcg_temp_free(t1);
5511 if (unlikely(Rc(ctx->opcode) != 0))
5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5513 }
5514
5515 /* sreq */
5516 static void gen_sreq(DisasContext *ctx)
5517 {
5518 TCGv t0 = tcg_temp_new();
5519 TCGv t1 = tcg_temp_new();
5520 TCGv t2 = tcg_temp_new();
5521 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5522 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5523 tcg_gen_shr_tl(t1, t1, t0);
5524 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5525 gen_load_spr(t2, SPR_MQ);
5526 gen_store_spr(SPR_MQ, t0);
5527 tcg_gen_and_tl(t0, t0, t1);
5528 tcg_gen_andc_tl(t2, t2, t1);
5529 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5530 tcg_temp_free(t0);
5531 tcg_temp_free(t1);
5532 tcg_temp_free(t2);
5533 if (unlikely(Rc(ctx->opcode) != 0))
5534 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5535 }
5536
5537 /* sriq */
5538 static void gen_sriq(DisasContext *ctx)
5539 {
5540 int sh = SH(ctx->opcode);
5541 TCGv t0 = tcg_temp_new();
5542 TCGv t1 = tcg_temp_new();
5543 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5544 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5545 tcg_gen_or_tl(t1, t0, t1);
5546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5547 gen_store_spr(SPR_MQ, t1);
5548 tcg_temp_free(t0);
5549 tcg_temp_free(t1);
5550 if (unlikely(Rc(ctx->opcode) != 0))
5551 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5552 }
5553
5554 /* srliq */
5555 static void gen_srliq(DisasContext *ctx)
5556 {
5557 int sh = SH(ctx->opcode);
5558 TCGv t0 = tcg_temp_new();
5559 TCGv t1 = tcg_temp_new();
5560 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5561 gen_load_spr(t1, SPR_MQ);
5562 gen_store_spr(SPR_MQ, t0);
5563 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5564 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5565 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5566 tcg_temp_free(t0);
5567 tcg_temp_free(t1);
5568 if (unlikely(Rc(ctx->opcode) != 0))
5569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5570 }
5571
5572 /* srlq */
5573 static void gen_srlq(DisasContext *ctx)
5574 {
5575 TCGLabel *l1 = gen_new_label();
5576 TCGLabel *l2 = gen_new_label();
5577 TCGv t0 = tcg_temp_local_new();
5578 TCGv t1 = tcg_temp_local_new();
5579 TCGv t2 = tcg_temp_local_new();
5580 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5581 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5582 tcg_gen_shr_tl(t2, t1, t2);
5583 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5584 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5585 gen_load_spr(t0, SPR_MQ);
5586 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5587 tcg_gen_br(l2);
5588 gen_set_label(l1);
5589 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5590 tcg_gen_and_tl(t0, t0, t2);
5591 gen_load_spr(t1, SPR_MQ);
5592 tcg_gen_andc_tl(t1, t1, t2);
5593 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5594 gen_set_label(l2);
5595 tcg_temp_free(t0);
5596 tcg_temp_free(t1);
5597 tcg_temp_free(t2);
5598 if (unlikely(Rc(ctx->opcode) != 0))
5599 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5600 }
5601
5602 /* srq */
5603 static void gen_srq(DisasContext *ctx)
5604 {
5605 TCGLabel *l1 = gen_new_label();
5606 TCGv t0 = tcg_temp_new();
5607 TCGv t1 = tcg_temp_new();
5608 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5609 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5610 tcg_gen_subfi_tl(t1, 32, t1);
5611 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5612 tcg_gen_or_tl(t1, t0, t1);
5613 gen_store_spr(SPR_MQ, t1);
5614 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5615 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5616 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5617 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5618 gen_set_label(l1);
5619 tcg_temp_free(t0);
5620 tcg_temp_free(t1);
5621 if (unlikely(Rc(ctx->opcode) != 0))
5622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5623 }
5624
5625 /* PowerPC 602 specific instructions */
5626
5627 /* dsa */
5628 static void gen_dsa(DisasContext *ctx)
5629 {
5630 /* XXX: TODO */
5631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5632 }
5633
5634 /* esa */
5635 static void gen_esa(DisasContext *ctx)
5636 {
5637 /* XXX: TODO */
5638 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5639 }
5640
5641 /* mfrom */
5642 static void gen_mfrom(DisasContext *ctx)
5643 {
5644 #if defined(CONFIG_USER_ONLY)
5645 GEN_PRIV;
5646 #else
5647 CHK_SV;
5648 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5649 #endif /* defined(CONFIG_USER_ONLY) */
5650 }
5651
5652 /* 602 - 603 - G2 TLB management */
5653
5654 /* tlbld */
5655 static void gen_tlbld_6xx(DisasContext *ctx)
5656 {
5657 #if defined(CONFIG_USER_ONLY)
5658 GEN_PRIV;
5659 #else
5660 CHK_SV;
5661 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5662 #endif /* defined(CONFIG_USER_ONLY) */
5663 }
5664
5665 /* tlbli */
5666 static void gen_tlbli_6xx(DisasContext *ctx)
5667 {
5668 #if defined(CONFIG_USER_ONLY)
5669 GEN_PRIV;
5670 #else
5671 CHK_SV;
5672 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5673 #endif /* defined(CONFIG_USER_ONLY) */
5674 }
5675
5676 /* 74xx TLB management */
5677
5678 /* tlbld */
5679 static void gen_tlbld_74xx(DisasContext *ctx)
5680 {
5681 #if defined(CONFIG_USER_ONLY)
5682 GEN_PRIV;
5683 #else
5684 CHK_SV;
5685 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5686 #endif /* defined(CONFIG_USER_ONLY) */
5687 }
5688
5689 /* tlbli */
5690 static void gen_tlbli_74xx(DisasContext *ctx)
5691 {
5692 #if defined(CONFIG_USER_ONLY)
5693 GEN_PRIV;
5694 #else
5695 CHK_SV;
5696 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5697 #endif /* defined(CONFIG_USER_ONLY) */
5698 }
5699
5700 /* POWER instructions not in PowerPC 601 */
5701
5702 /* clf */
5703 static void gen_clf(DisasContext *ctx)
5704 {
5705 /* Cache line flush: implemented as no-op */
5706 }
5707
5708 /* cli */
5709 static void gen_cli(DisasContext *ctx)
5710 {
5711 #if defined(CONFIG_USER_ONLY)
5712 GEN_PRIV;
5713 #else
5714 /* Cache line invalidate: privileged and treated as no-op */
5715 CHK_SV;
5716 #endif /* defined(CONFIG_USER_ONLY) */
5717 }
5718
5719 /* dclst */
5720 static void gen_dclst(DisasContext *ctx)
5721 {
5722 /* Data cache line store: treated as no-op */
5723 }
5724
5725 static void gen_mfsri(DisasContext *ctx)
5726 {
5727 #if defined(CONFIG_USER_ONLY)
5728 GEN_PRIV;
5729 #else
5730 int ra = rA(ctx->opcode);
5731 int rd = rD(ctx->opcode);
5732 TCGv t0;
5733
5734 CHK_SV;
5735 t0 = tcg_temp_new();
5736 gen_addr_reg_index(ctx, t0);
5737 tcg_gen_extract_tl(t0, t0, 28, 4);
5738 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5739 tcg_temp_free(t0);
5740 if (ra != 0 && ra != rd)
5741 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5742 #endif /* defined(CONFIG_USER_ONLY) */
5743 }
5744
5745 static void gen_rac(DisasContext *ctx)
5746 {
5747 #if defined(CONFIG_USER_ONLY)
5748 GEN_PRIV;
5749 #else
5750 TCGv t0;
5751
5752 CHK_SV;
5753 t0 = tcg_temp_new();
5754 gen_addr_reg_index(ctx, t0);
5755 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5756 tcg_temp_free(t0);
5757 #endif /* defined(CONFIG_USER_ONLY) */
5758 }
5759
5760 static void gen_rfsvc(DisasContext *ctx)
5761 {
5762 #if defined(CONFIG_USER_ONLY)
5763 GEN_PRIV;
5764 #else
5765 CHK_SV;
5766
5767 gen_helper_rfsvc(cpu_env);
5768 gen_sync_exception(ctx);
5769 #endif /* defined(CONFIG_USER_ONLY) */
5770 }
5771
5772 /* svc is not implemented for now */
5773
5774 /* BookE specific instructions */
5775
5776 /* XXX: not implemented on 440 ? */
5777 static void gen_mfapidi(DisasContext *ctx)
5778 {
5779 /* XXX: TODO */
5780 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5781 }
5782
5783 /* XXX: not implemented on 440 ? */
5784 static void gen_tlbiva(DisasContext *ctx)
5785 {
5786 #if defined(CONFIG_USER_ONLY)
5787 GEN_PRIV;
5788 #else
5789 TCGv t0;
5790
5791 CHK_SV;
5792 t0 = tcg_temp_new();
5793 gen_addr_reg_index(ctx, t0);
5794 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5795 tcg_temp_free(t0);
5796 #endif /* defined(CONFIG_USER_ONLY) */
5797 }
5798
5799 /* All 405 MAC instructions are translated here */
5800 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5801 int ra, int rb, int rt, int Rc)
5802 {
5803 TCGv t0, t1;
5804
5805 t0 = tcg_temp_local_new();
5806 t1 = tcg_temp_local_new();
5807
5808 switch (opc3 & 0x0D) {
5809 case 0x05:
5810 /* macchw - macchw. - macchwo - macchwo. */
5811 /* macchws - macchws. - macchwso - macchwso. */
5812 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5813 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5814 /* mulchw - mulchw. */
5815 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5816 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5817 tcg_gen_ext16s_tl(t1, t1);
5818 break;
5819 case 0x04:
5820 /* macchwu - macchwu. - macchwuo - macchwuo. */
5821 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5822 /* mulchwu - mulchwu. */
5823 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5824 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5825 tcg_gen_ext16u_tl(t1, t1);
5826 break;
5827 case 0x01:
5828 /* machhw - machhw. - machhwo - machhwo. */
5829 /* machhws - machhws. - machhwso - machhwso. */
5830 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5831 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5832 /* mulhhw - mulhhw. */
5833 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5834 tcg_gen_ext16s_tl(t0, t0);
5835 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5836 tcg_gen_ext16s_tl(t1, t1);
5837 break;
5838 case 0x00:
5839 /* machhwu - machhwu. - machhwuo - machhwuo. */
5840 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5841 /* mulhhwu - mulhhwu. */
5842 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5843 tcg_gen_ext16u_tl(t0, t0);
5844 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5845 tcg_gen_ext16u_tl(t1, t1);
5846 break;
5847 case 0x0D:
5848 /* maclhw - maclhw. - maclhwo - maclhwo. */
5849 /* maclhws - maclhws. - maclhwso - maclhwso. */
5850 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5851 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5852 /* mullhw - mullhw. */
5853 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5854 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5855 break;
5856 case 0x0C:
5857 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5858 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5859 /* mullhwu - mullhwu. */
5860 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5861 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5862 break;
5863 }
5864 if (opc2 & 0x04) {
5865 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5866 tcg_gen_mul_tl(t1, t0, t1);
5867 if (opc2 & 0x02) {
5868 /* nmultiply-and-accumulate (0x0E) */
5869 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5870 } else {
5871 /* multiply-and-accumulate (0x0C) */
5872 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5873 }
5874
5875 if (opc3 & 0x12) {
5876 /* Check overflow and/or saturate */
5877 TCGLabel *l1 = gen_new_label();
5878
5879 if (opc3 & 0x10) {
5880 /* Start with XER OV disabled, the most likely case */
5881 tcg_gen_movi_tl(cpu_ov, 0);
5882 }
5883 if (opc3 & 0x01) {
5884 /* Signed */
5885 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5886 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5887 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5888 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5889 if (opc3 & 0x02) {
5890 /* Saturate */
5891 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5892 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5893 }
5894 } else {
5895 /* Unsigned */
5896 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5897 if (opc3 & 0x02) {
5898 /* Saturate */
5899 tcg_gen_movi_tl(t0, UINT32_MAX);
5900 }
5901 }
5902 if (opc3 & 0x10) {
5903 /* Check overflow */
5904 tcg_gen_movi_tl(cpu_ov, 1);
5905 tcg_gen_movi_tl(cpu_so, 1);
5906 }
5907 gen_set_label(l1);
5908 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5909 }
5910 } else {
5911 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5912 }
5913 tcg_temp_free(t0);
5914 tcg_temp_free(t1);
5915 if (unlikely(Rc) != 0) {
5916 /* Update Rc0 */
5917 gen_set_Rc0(ctx, cpu_gpr[rt]);
5918 }
5919 }
5920
5921 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5922 static void glue(gen_, name)(DisasContext *ctx) \
5923 { \
5924 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5925 rD(ctx->opcode), Rc(ctx->opcode)); \
5926 }
5927
5928 /* macchw - macchw. */
5929 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5930 /* macchwo - macchwo. */
5931 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5932 /* macchws - macchws. */
5933 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5934 /* macchwso - macchwso. */
5935 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5936 /* macchwsu - macchwsu. */
5937 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5938 /* macchwsuo - macchwsuo. */
5939 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5940 /* macchwu - macchwu. */
5941 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5942 /* macchwuo - macchwuo. */
5943 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5944 /* machhw - machhw. */
5945 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5946 /* machhwo - machhwo. */
5947 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5948 /* machhws - machhws. */
5949 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5950 /* machhwso - machhwso. */
5951 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5952 /* machhwsu - machhwsu. */
5953 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5954 /* machhwsuo - machhwsuo. */
5955 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5956 /* machhwu - machhwu. */
5957 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5958 /* machhwuo - machhwuo. */
5959 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5960 /* maclhw - maclhw. */
5961 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5962 /* maclhwo - maclhwo. */
5963 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5964 /* maclhws - maclhws. */
5965 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5966 /* maclhwso - maclhwso. */
5967 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5968 /* maclhwu - maclhwu. */
5969 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5970 /* maclhwuo - maclhwuo. */
5971 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5972 /* maclhwsu - maclhwsu. */
5973 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5974 /* maclhwsuo - maclhwsuo. */
5975 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5976 /* nmacchw - nmacchw. */
5977 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5978 /* nmacchwo - nmacchwo. */
5979 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5980 /* nmacchws - nmacchws. */
5981 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5982 /* nmacchwso - nmacchwso. */
5983 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5984 /* nmachhw - nmachhw. */
5985 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5986 /* nmachhwo - nmachhwo. */
5987 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5988 /* nmachhws - nmachhws. */
5989 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5990 /* nmachhwso - nmachhwso. */
5991 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5992 /* nmaclhw - nmaclhw. */
5993 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5994 /* nmaclhwo - nmaclhwo. */
5995 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5996 /* nmaclhws - nmaclhws. */
5997 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5998 /* nmaclhwso - nmaclhwso. */
5999 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6000
6001 /* mulchw - mulchw. */
6002 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6003 /* mulchwu - mulchwu. */
6004 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6005 /* mulhhw - mulhhw. */
6006 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6007 /* mulhhwu - mulhhwu. */
6008 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6009 /* mullhw - mullhw. */
6010 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6011 /* mullhwu - mullhwu. */
6012 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6013
6014 /* mfdcr */
6015 static void gen_mfdcr(DisasContext *ctx)
6016 {
6017 #if defined(CONFIG_USER_ONLY)
6018 GEN_PRIV;
6019 #else
6020 TCGv dcrn;
6021
6022 CHK_SV;
6023 dcrn = tcg_const_tl(SPR(ctx->opcode));
6024 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6025 tcg_temp_free(dcrn);
6026 #endif /* defined(CONFIG_USER_ONLY) */
6027 }
6028
6029 /* mtdcr */
6030 static void gen_mtdcr(DisasContext *ctx)
6031 {
6032 #if defined(CONFIG_USER_ONLY)
6033 GEN_PRIV;
6034 #else
6035 TCGv dcrn;
6036
6037 CHK_SV;
6038 dcrn = tcg_const_tl(SPR(ctx->opcode));
6039 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6040 tcg_temp_free(dcrn);
6041 #endif /* defined(CONFIG_USER_ONLY) */
6042 }
6043
6044 /* mfdcrx */
6045 /* XXX: not implemented on 440 ? */
6046 static void gen_mfdcrx(DisasContext *ctx)
6047 {
6048 #if defined(CONFIG_USER_ONLY)
6049 GEN_PRIV;
6050 #else
6051 CHK_SV;
6052 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6053 cpu_gpr[rA(ctx->opcode)]);
6054 /* Note: Rc update flag set leads to undefined state of Rc0 */
6055 #endif /* defined(CONFIG_USER_ONLY) */
6056 }
6057
6058 /* mtdcrx */
6059 /* XXX: not implemented on 440 ? */
6060 static void gen_mtdcrx(DisasContext *ctx)
6061 {
6062 #if defined(CONFIG_USER_ONLY)
6063 GEN_PRIV;
6064 #else
6065 CHK_SV;
6066 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6067 cpu_gpr[rS(ctx->opcode)]);
6068 /* Note: Rc update flag set leads to undefined state of Rc0 */
6069 #endif /* defined(CONFIG_USER_ONLY) */
6070 }
6071
6072 /* mfdcrux (PPC 460) : user-mode access to DCR */
6073 static void gen_mfdcrux(DisasContext *ctx)
6074 {
6075 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6076 cpu_gpr[rA(ctx->opcode)]);
6077 /* Note: Rc update flag set leads to undefined state of Rc0 */
6078 }
6079
6080 /* mtdcrux (PPC 460) : user-mode access to DCR */
6081 static void gen_mtdcrux(DisasContext *ctx)
6082 {
6083 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6084 cpu_gpr[rS(ctx->opcode)]);
6085 /* Note: Rc update flag set leads to undefined state of Rc0 */
6086 }
6087
6088 /* dccci */
6089 static void gen_dccci(DisasContext *ctx)
6090 {
6091 CHK_SV;
6092 /* interpreted as no-op */
6093 }
6094
6095 /* dcread */
6096 static void gen_dcread(DisasContext *ctx)
6097 {
6098 #if defined(CONFIG_USER_ONLY)
6099 GEN_PRIV;
6100 #else
6101 TCGv EA, val;
6102
6103 CHK_SV;
6104 gen_set_access_type(ctx, ACCESS_CACHE);
6105 EA = tcg_temp_new();
6106 gen_addr_reg_index(ctx, EA);
6107 val = tcg_temp_new();
6108 gen_qemu_ld32u(ctx, val, EA);
6109 tcg_temp_free(val);
6110 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6111 tcg_temp_free(EA);
6112 #endif /* defined(CONFIG_USER_ONLY) */
6113 }
6114
6115 /* icbt */
6116 static void gen_icbt_40x(DisasContext *ctx)
6117 {
6118 /* interpreted as no-op */
6119 /* XXX: specification say this is treated as a load by the MMU
6120 * but does not generate any exception
6121 */
6122 }
6123
6124 /* iccci */
6125 static void gen_iccci(DisasContext *ctx)
6126 {
6127 CHK_SV;
6128 /* interpreted as no-op */
6129 }
6130
6131 /* icread */
6132 static void gen_icread(DisasContext *ctx)
6133 {
6134 CHK_SV;
6135 /* interpreted as no-op */
6136 }
6137
6138 /* rfci (supervisor only) */
6139 static void gen_rfci_40x(DisasContext *ctx)
6140 {
6141 #if defined(CONFIG_USER_ONLY)
6142 GEN_PRIV;
6143 #else
6144 CHK_SV;
6145 /* Restore CPU state */
6146 gen_helper_40x_rfci(cpu_env);
6147 gen_sync_exception(ctx);
6148 #endif /* defined(CONFIG_USER_ONLY) */
6149 }
6150
6151 static void gen_rfci(DisasContext *ctx)
6152 {
6153 #if defined(CONFIG_USER_ONLY)
6154 GEN_PRIV;
6155 #else
6156 CHK_SV;
6157 /* Restore CPU state */
6158 gen_helper_rfci(cpu_env);
6159 gen_sync_exception(ctx);
6160 #endif /* defined(CONFIG_USER_ONLY) */
6161 }
6162
6163 /* BookE specific */
6164
6165 /* XXX: not implemented on 440 ? */
6166 static void gen_rfdi(DisasContext *ctx)
6167 {
6168 #if defined(CONFIG_USER_ONLY)
6169 GEN_PRIV;
6170 #else
6171 CHK_SV;
6172 /* Restore CPU state */
6173 gen_helper_rfdi(cpu_env);
6174 gen_sync_exception(ctx);
6175 #endif /* defined(CONFIG_USER_ONLY) */
6176 }
6177
6178 /* XXX: not implemented on 440 ? */
6179 static void gen_rfmci(DisasContext *ctx)
6180 {
6181 #if defined(CONFIG_USER_ONLY)
6182 GEN_PRIV;
6183 #else
6184 CHK_SV;
6185 /* Restore CPU state */
6186 gen_helper_rfmci(cpu_env);
6187 gen_sync_exception(ctx);
6188 #endif /* defined(CONFIG_USER_ONLY) */
6189 }
6190
6191 /* TLB management - PowerPC 405 implementation */
6192
6193 /* tlbre */
6194 static void gen_tlbre_40x(DisasContext *ctx)
6195 {
6196 #if defined(CONFIG_USER_ONLY)
6197 GEN_PRIV;
6198 #else
6199 CHK_SV;
6200 switch (rB(ctx->opcode)) {
6201 case 0:
6202 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6203 cpu_gpr[rA(ctx->opcode)]);
6204 break;
6205 case 1:
6206 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6207 cpu_gpr[rA(ctx->opcode)]);
6208 break;
6209 default:
6210 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6211 break;
6212 }
6213 #endif /* defined(CONFIG_USER_ONLY) */
6214 }
6215
6216 /* tlbsx - tlbsx. */
6217 static void gen_tlbsx_40x(DisasContext *ctx)
6218 {
6219 #if defined(CONFIG_USER_ONLY)
6220 GEN_PRIV;
6221 #else
6222 TCGv t0;
6223
6224 CHK_SV;
6225 t0 = tcg_temp_new();
6226 gen_addr_reg_index(ctx, t0);
6227 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6228 tcg_temp_free(t0);
6229 if (Rc(ctx->opcode)) {
6230 TCGLabel *l1 = gen_new_label();
6231 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6232 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6233 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6234 gen_set_label(l1);
6235 }
6236 #endif /* defined(CONFIG_USER_ONLY) */
6237 }
6238
6239 /* tlbwe */
6240 static void gen_tlbwe_40x(DisasContext *ctx)
6241 {
6242 #if defined(CONFIG_USER_ONLY)
6243 GEN_PRIV;
6244 #else
6245 CHK_SV;
6246
6247 switch (rB(ctx->opcode)) {
6248 case 0:
6249 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6250 cpu_gpr[rS(ctx->opcode)]);
6251 break;
6252 case 1:
6253 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6254 cpu_gpr[rS(ctx->opcode)]);
6255 break;
6256 default:
6257 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6258 break;
6259 }
6260 #endif /* defined(CONFIG_USER_ONLY) */
6261 }
6262
6263 /* TLB management - PowerPC 440 implementation */
6264
6265 /* tlbre */
6266 static void gen_tlbre_440(DisasContext *ctx)
6267 {
6268 #if defined(CONFIG_USER_ONLY)
6269 GEN_PRIV;
6270 #else
6271 CHK_SV;
6272
6273 switch (rB(ctx->opcode)) {
6274 case 0:
6275 case 1:
6276 case 2:
6277 {
6278 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6279 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6280 t0, cpu_gpr[rA(ctx->opcode)]);
6281 tcg_temp_free_i32(t0);
6282 }
6283 break;
6284 default:
6285 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6286 break;
6287 }
6288 #endif /* defined(CONFIG_USER_ONLY) */
6289 }
6290
6291 /* tlbsx - tlbsx. */
6292 static void gen_tlbsx_440(DisasContext *ctx)
6293 {
6294 #if defined(CONFIG_USER_ONLY)
6295 GEN_PRIV;
6296 #else
6297 TCGv t0;
6298
6299 CHK_SV;
6300 t0 = tcg_temp_new();
6301 gen_addr_reg_index(ctx, t0);
6302 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6303 tcg_temp_free(t0);
6304 if (Rc(ctx->opcode)) {
6305 TCGLabel *l1 = gen_new_label();
6306 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6307 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6308 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6309 gen_set_label(l1);
6310 }
6311 #endif /* defined(CONFIG_USER_ONLY) */
6312 }
6313
6314 /* tlbwe */
6315 static void gen_tlbwe_440(DisasContext *ctx)
6316 {
6317 #if defined(CONFIG_USER_ONLY)
6318 GEN_PRIV;
6319 #else
6320 CHK_SV;
6321 switch (rB(ctx->opcode)) {
6322 case 0:
6323 case 1:
6324 case 2:
6325 {
6326 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6327 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6328 cpu_gpr[rS(ctx->opcode)]);
6329 tcg_temp_free_i32(t0);
6330 }
6331 break;
6332 default:
6333 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6334 break;
6335 }
6336 #endif /* defined(CONFIG_USER_ONLY) */
6337 }
6338
6339 /* TLB management - PowerPC BookE 2.06 implementation */
6340
6341 /* tlbre */
6342 static void gen_tlbre_booke206(DisasContext *ctx)
6343 {
6344 #if defined(CONFIG_USER_ONLY)
6345 GEN_PRIV;
6346 #else
6347 CHK_SV;
6348 gen_helper_booke206_tlbre(cpu_env);
6349 #endif /* defined(CONFIG_USER_ONLY) */
6350 }
6351
6352 /* tlbsx - tlbsx. */
6353 static void gen_tlbsx_booke206(DisasContext *ctx)
6354 {
6355 #if defined(CONFIG_USER_ONLY)
6356 GEN_PRIV;
6357 #else
6358 TCGv t0;
6359
6360 CHK_SV;
6361 if (rA(ctx->opcode)) {
6362 t0 = tcg_temp_new();
6363 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6364 } else {
6365 t0 = tcg_const_tl(0);
6366 }
6367
6368 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6369 gen_helper_booke206_tlbsx(cpu_env, t0);
6370 tcg_temp_free(t0);
6371 #endif /* defined(CONFIG_USER_ONLY) */
6372 }
6373
6374 /* tlbwe */
6375 static void gen_tlbwe_booke206(DisasContext *ctx)
6376 {
6377 #if defined(CONFIG_USER_ONLY)
6378 GEN_PRIV;
6379 #else
6380 CHK_SV;
6381 gen_helper_booke206_tlbwe(cpu_env);
6382 #endif /* defined(CONFIG_USER_ONLY) */
6383 }
6384
6385 static void gen_tlbivax_booke206(DisasContext *ctx)
6386 {
6387 #if defined(CONFIG_USER_ONLY)
6388 GEN_PRIV;
6389 #else
6390 TCGv t0;
6391
6392 CHK_SV;
6393 t0 = tcg_temp_new();
6394 gen_addr_reg_index(ctx, t0);
6395 gen_helper_booke206_tlbivax(cpu_env, t0);
6396 tcg_temp_free(t0);
6397 #endif /* defined(CONFIG_USER_ONLY) */
6398 }
6399
6400 static void gen_tlbilx_booke206(DisasContext *ctx)
6401 {
6402 #if defined(CONFIG_USER_ONLY)
6403 GEN_PRIV;
6404 #else
6405 TCGv t0;
6406
6407 CHK_SV;
6408 t0 = tcg_temp_new();
6409 gen_addr_reg_index(ctx, t0);
6410
6411 switch((ctx->opcode >> 21) & 0x3) {
6412 case 0:
6413 gen_helper_booke206_tlbilx0(cpu_env, t0);
6414 break;
6415 case 1:
6416 gen_helper_booke206_tlbilx1(cpu_env, t0);
6417 break;
6418 case 3:
6419 gen_helper_booke206_tlbilx3(cpu_env, t0);
6420 break;
6421 default:
6422 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6423 break;
6424 }
6425
6426 tcg_temp_free(t0);
6427 #endif /* defined(CONFIG_USER_ONLY) */
6428 }
6429
6430
6431 /* wrtee */
6432 static void gen_wrtee(DisasContext *ctx)
6433 {
6434 #if defined(CONFIG_USER_ONLY)
6435 GEN_PRIV;
6436 #else
6437 TCGv t0;
6438
6439 CHK_SV;
6440 t0 = tcg_temp_new();
6441 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6442 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6443 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6444 tcg_temp_free(t0);
6445 /* Stop translation to have a chance to raise an exception
6446 * if we just set msr_ee to 1
6447 */
6448 gen_stop_exception(ctx);
6449 #endif /* defined(CONFIG_USER_ONLY) */
6450 }
6451
6452 /* wrteei */
6453 static void gen_wrteei(DisasContext *ctx)
6454 {
6455 #if defined(CONFIG_USER_ONLY)
6456 GEN_PRIV;
6457 #else
6458 CHK_SV;
6459 if (ctx->opcode & 0x00008000) {
6460 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6461 /* Stop translation to have a chance to raise an exception */
6462 gen_stop_exception(ctx);
6463 } else {
6464 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6465 }
6466 #endif /* defined(CONFIG_USER_ONLY) */
6467 }
6468
6469 /* PowerPC 440 specific instructions */
6470
6471 /* dlmzb */
6472 static void gen_dlmzb(DisasContext *ctx)
6473 {
6474 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6475 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6476 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6477 tcg_temp_free_i32(t0);
6478 }
6479
6480 /* mbar replaces eieio on 440 */
6481 static void gen_mbar(DisasContext *ctx)
6482 {
6483 /* interpreted as no-op */
6484 }
6485
6486 /* msync replaces sync on 440 */
6487 static void gen_msync_4xx(DisasContext *ctx)
6488 {
6489 /* interpreted as no-op */
6490 }
6491
6492 /* icbt */
6493 static void gen_icbt_440(DisasContext *ctx)
6494 {
6495 /* interpreted as no-op */
6496 /* XXX: specification say this is treated as a load by the MMU
6497 * but does not generate any exception
6498 */
6499 }
6500
6501 /* Embedded.Processor Control */
6502
6503 static void gen_msgclr(DisasContext *ctx)
6504 {
6505 #if defined(CONFIG_USER_ONLY)
6506 GEN_PRIV;
6507 #else
6508 CHK_HV;
6509 /* 64-bit server processors compliant with arch 2.x */
6510 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6511 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6512 } else {
6513 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6514 }
6515 #endif /* defined(CONFIG_USER_ONLY) */
6516 }
6517
6518 static void gen_msgsnd(DisasContext *ctx)
6519 {
6520 #if defined(CONFIG_USER_ONLY)
6521 GEN_PRIV;
6522 #else
6523 CHK_HV;
6524 /* 64-bit server processors compliant with arch 2.x */
6525 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6526 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6527 } else {
6528 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6529 }
6530 #endif /* defined(CONFIG_USER_ONLY) */
6531 }
6532
6533 static void gen_msgsync(DisasContext *ctx)
6534 {
6535 #if defined(CONFIG_USER_ONLY)
6536 GEN_PRIV;
6537 #else
6538 CHK_HV;
6539 #endif /* defined(CONFIG_USER_ONLY) */
6540 /* interpreted as no-op */
6541 }
6542
6543 #if defined(TARGET_PPC64)
6544 static void gen_maddld(DisasContext *ctx)
6545 {
6546 TCGv_i64 t1 = tcg_temp_new_i64();
6547
6548 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6549 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6550 tcg_temp_free_i64(t1);
6551 }
6552
6553 /* maddhd maddhdu */
6554 static void gen_maddhd_maddhdu(DisasContext *ctx)
6555 {
6556 TCGv_i64 lo = tcg_temp_new_i64();
6557 TCGv_i64 hi = tcg_temp_new_i64();
6558 TCGv_i64 t1 = tcg_temp_new_i64();
6559
6560 if (Rc(ctx->opcode)) {
6561 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6562 cpu_gpr[rB(ctx->opcode)]);
6563 tcg_gen_movi_i64(t1, 0);
6564 } else {
6565 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6566 cpu_gpr[rB(ctx->opcode)]);
6567 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6568 }
6569 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6570 cpu_gpr[rC(ctx->opcode)], t1);
6571 tcg_temp_free_i64(lo);
6572 tcg_temp_free_i64(hi);
6573 tcg_temp_free_i64(t1);
6574 }
6575 #endif /* defined(TARGET_PPC64) */
6576
6577 static void gen_tbegin(DisasContext *ctx)
6578 {
6579 if (unlikely(!ctx->tm_enabled)) {
6580 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6581 return;
6582 }
6583 gen_helper_tbegin(cpu_env);
6584 }
6585
6586 #define GEN_TM_NOOP(name) \
6587 static inline void gen_##name(DisasContext *ctx) \
6588 { \
6589 if (unlikely(!ctx->tm_enabled)) { \
6590 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6591 return; \
6592 } \
6593 /* Because tbegin always fails in QEMU, these user \
6594 * space instructions all have a simple implementation: \
6595 * \
6596 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6597 * = 0b0 || 0b00 || 0b0 \
6598 */ \
6599 tcg_gen_movi_i32(cpu_crf[0], 0); \
6600 }
6601
6602 GEN_TM_NOOP(tend);
6603 GEN_TM_NOOP(tabort);
6604 GEN_TM_NOOP(tabortwc);
6605 GEN_TM_NOOP(tabortwci);
6606 GEN_TM_NOOP(tabortdc);
6607 GEN_TM_NOOP(tabortdci);
6608 GEN_TM_NOOP(tsr);
6609 static inline void gen_cp_abort(DisasContext *ctx)
6610 {
6611 // Do Nothing
6612 }
6613
6614 #define GEN_CP_PASTE_NOOP(name) \
6615 static inline void gen_##name(DisasContext *ctx) \
6616 { \
6617 /* Generate invalid exception until \
6618 * we have an implementation of the copy \
6619 * paste facility \
6620 */ \
6621 gen_invalid(ctx); \
6622 }
6623
6624 GEN_CP_PASTE_NOOP(copy)
6625 GEN_CP_PASTE_NOOP(paste)
6626
6627 static void gen_tcheck(DisasContext *ctx)
6628 {
6629 if (unlikely(!ctx->tm_enabled)) {
6630 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6631 return;
6632 }
6633 /* Because tbegin always fails, the tcheck implementation
6634 * is simple:
6635 *
6636 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6637 * = 0b1 || 0b00 || 0b0
6638 */
6639 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6640 }
6641
6642 #if defined(CONFIG_USER_ONLY)
6643 #define GEN_TM_PRIV_NOOP(name) \
6644 static inline void gen_##name(DisasContext *ctx) \
6645 { \
6646 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6647 }
6648
6649 #else
6650
6651 #define GEN_TM_PRIV_NOOP(name) \
6652 static inline void gen_##name(DisasContext *ctx) \
6653 { \
6654 CHK_SV; \
6655 if (unlikely(!ctx->tm_enabled)) { \
6656 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6657 return; \
6658 } \
6659 /* Because tbegin always fails, the implementation is \
6660 * simple: \
6661 * \
6662 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6663 * = 0b0 || 0b00 | 0b0 \
6664 */ \
6665 tcg_gen_movi_i32(cpu_crf[0], 0); \
6666 }
6667
6668 #endif
6669
6670 GEN_TM_PRIV_NOOP(treclaim);
6671 GEN_TM_PRIV_NOOP(trechkpt);
6672
6673 #include "translate/fp-impl.inc.c"
6674
6675 #include "translate/vmx-impl.inc.c"
6676
6677 #include "translate/vsx-impl.inc.c"
6678
6679 #include "translate/dfp-impl.inc.c"
6680
6681 #include "translate/spe-impl.inc.c"
6682
6683 /* Handles lfdp, lxsd, lxssp */
6684 static void gen_dform39(DisasContext *ctx)
6685 {
6686 switch (ctx->opcode & 0x3) {
6687 case 0: /* lfdp */
6688 if (ctx->insns_flags2 & PPC2_ISA205) {
6689 return gen_lfdp(ctx);
6690 }
6691 break;
6692 case 2: /* lxsd */
6693 if (ctx->insns_flags2 & PPC2_ISA300) {
6694 return gen_lxsd(ctx);
6695 }
6696 break;
6697 case 3: /* lxssp */
6698 if (ctx->insns_flags2 & PPC2_ISA300) {
6699 return gen_lxssp(ctx);
6700 }
6701 break;
6702 }
6703 return gen_invalid(ctx);
6704 }
6705
6706 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6707 static void gen_dform3D(DisasContext *ctx)
6708 {
6709 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6710 switch (ctx->opcode & 0x7) {
6711 case 1: /* lxv */
6712 if (ctx->insns_flags2 & PPC2_ISA300) {
6713 return gen_lxv(ctx);
6714 }
6715 break;
6716 case 5: /* stxv */
6717 if (ctx->insns_flags2 & PPC2_ISA300) {
6718 return gen_stxv(ctx);
6719 }
6720 break;
6721 }
6722 } else { /* DS-FORM */
6723 switch (ctx->opcode & 0x3) {
6724 case 0: /* stfdp */
6725 if (ctx->insns_flags2 & PPC2_ISA205) {
6726 return gen_stfdp(ctx);
6727 }
6728 break;
6729 case 2: /* stxsd */
6730 if (ctx->insns_flags2 & PPC2_ISA300) {
6731 return gen_stxsd(ctx);
6732 }
6733 break;
6734 case 3: /* stxssp */
6735 if (ctx->insns_flags2 & PPC2_ISA300) {
6736 return gen_stxssp(ctx);
6737 }
6738 break;
6739 }
6740 }
6741 return gen_invalid(ctx);
6742 }
6743
6744 static opcode_t opcodes[] = {
6745 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6746 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6747 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6748 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6749 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6750 #if defined(TARGET_PPC64)
6751 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6752 #endif
6753 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6754 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6755 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6756 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6757 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6758 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6759 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6760 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6761 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6762 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6763 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6764 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6765 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6766 #if defined(TARGET_PPC64)
6767 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6768 #endif
6769 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6770 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6771 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6772 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6773 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6774 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6775 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6776 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6777 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6778 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6779 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6780 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6781 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6782 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6783 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6784 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6785 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6786 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6787 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6788 #if defined(TARGET_PPC64)
6789 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6790 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6791 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6792 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6793 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6794 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6795 #endif
6796 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6797 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6798 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6799 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6800 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6801 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6802 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6803 #if defined(TARGET_PPC64)
6804 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6805 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6806 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6807 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6808 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6809 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6810 PPC_NONE, PPC2_ISA300),
6811 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6812 PPC_NONE, PPC2_ISA300),
6813 #endif
6814 #if defined(TARGET_PPC64)
6815 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6816 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6817 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6818 #endif
6819 /* handles lfdp, lxsd, lxssp */
6820 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6821 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6822 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6823 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6824 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6825 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6826 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6827 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6828 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6829 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6830 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6831 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6832 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6833 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6834 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6835 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6836 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6837 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6838 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6839 #if defined(TARGET_PPC64)
6840 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6841 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6842 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6843 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6844 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6845 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6846 #endif
6847 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6848 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6849 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6850 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6851 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6852 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6853 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6854 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6855 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6856 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6857 #if defined(TARGET_PPC64)
6858 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6859 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6860 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6861 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6862 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6863 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6864 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6865 #endif
6866 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6867 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6868 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6869 #if defined(TARGET_PPC64)
6870 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6871 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6872 #endif
6873 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6874 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6875 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6876 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6877 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6878 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6879 #if defined(TARGET_PPC64)
6880 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6881 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6882 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6883 #endif
6884 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6885 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6886 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6887 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6888 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6889 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6890 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6891 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6892 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6893 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6894 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
6895 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6896 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6897 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
6898 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6899 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6900 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6901 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6902 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
6903 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6904 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6905 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6906 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6907 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6908 #if defined(TARGET_PPC64)
6909 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6910 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6911 PPC_SEGMENT_64B),
6912 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6913 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6914 PPC_SEGMENT_64B),
6915 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6916 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6917 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6918 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6919 #endif
6920 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6921 /* XXX Those instructions will need to be handled differently for
6922 * different ISA versions */
6923 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6924 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6925 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6926 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6927 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6928 #if defined(TARGET_PPC64)
6929 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6930 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6931 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6932 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6933 #endif
6934 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6935 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6936 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6937 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6938 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6939 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6940 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6941 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6942 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6943 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6944 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6945 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6946 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6947 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6948 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6949 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6950 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6951 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6952 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6953 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6954 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6955 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6956 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6957 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6958 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6959 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6960 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6961 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6962 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6963 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6964 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6965 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6966 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6967 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6968 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6969 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6970 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6971 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6972 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6973 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6974 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6975 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6976 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6977 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6978 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6979 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6980 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6981 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6982 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6983 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6984 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6985 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6986 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6987 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6988 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6989 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6990 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6991 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6992 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6993 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6994 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6995 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6996 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6997 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6998 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6999 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
7000 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
7001 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
7002 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
7003 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
7004 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
7005 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
7006 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
7007 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
7008 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
7009 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
7010 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
7011 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
7012 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
7013 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
7014 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7015 PPC_NONE, PPC2_BOOKE206),
7016 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7017 PPC_NONE, PPC2_BOOKE206),
7018 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7019 PPC_NONE, PPC2_BOOKE206),
7020 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7021 PPC_NONE, PPC2_BOOKE206),
7022 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7023 PPC_NONE, PPC2_BOOKE206),
7024 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7025 PPC_NONE, PPC2_PRCNTL),
7026 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7027 PPC_NONE, PPC2_PRCNTL),
7028 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7029 PPC_NONE, PPC2_PRCNTL),
7030 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
7031 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
7032 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
7033 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
7034 PPC_BOOKE, PPC2_BOOKE206),
7035 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
7036 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7037 PPC_BOOKE, PPC2_BOOKE206),
7038 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7039 PPC_440_SPEC),
7040 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7041 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7042 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7043 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
7044 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
7045 #if defined(TARGET_PPC64)
7046 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7047 PPC2_ISA300),
7048 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
7049 #endif
7050
7051 #undef GEN_INT_ARITH_ADD
7052 #undef GEN_INT_ARITH_ADD_CONST
7053 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7054 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7055 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7056 add_ca, compute_ca, compute_ov) \
7057 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7058 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7059 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7060 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7061 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7062 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7063 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7064 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7065 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
7066 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7067 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7068
7069 #undef GEN_INT_ARITH_DIVW
7070 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7071 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7072 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7073 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7074 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7075 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
7076 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7077 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7078 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7079 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7080 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7081 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7082
7083 #if defined(TARGET_PPC64)
7084 #undef GEN_INT_ARITH_DIVD
7085 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7086 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7087 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7088 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7089 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7090 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7091
7092 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7093 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7094 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7095 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7096 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7097 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7098
7099 #undef GEN_INT_ARITH_MUL_HELPER
7100 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7101 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7102 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7103 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7104 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7105 #endif
7106
7107 #undef GEN_INT_ARITH_SUBF
7108 #undef GEN_INT_ARITH_SUBF_CONST
7109 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7110 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7111 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7112 add_ca, compute_ca, compute_ov) \
7113 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7114 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7115 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7116 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7117 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7118 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7119 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7120 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7121 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7122 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7123 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7124
7125 #undef GEN_LOGICAL1
7126 #undef GEN_LOGICAL2
7127 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7128 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7129 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7130 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7131 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7132 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7133 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7134 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7135 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7136 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7137 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7138 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7139 #if defined(TARGET_PPC64)
7140 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7141 #endif
7142
7143 #if defined(TARGET_PPC64)
7144 #undef GEN_PPC64_R2
7145 #undef GEN_PPC64_R4
7146 #define GEN_PPC64_R2(name, opc1, opc2) \
7147 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7148 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7149 PPC_64B)
7150 #define GEN_PPC64_R4(name, opc1, opc2) \
7151 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7152 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7153 PPC_64B), \
7154 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7155 PPC_64B), \
7156 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7157 PPC_64B)
7158 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7159 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7160 GEN_PPC64_R4(rldic, 0x1E, 0x04),
7161 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7162 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7163 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7164 #endif
7165
7166 #undef GEN_LD
7167 #undef GEN_LDU
7168 #undef GEN_LDUX
7169 #undef GEN_LDX_E
7170 #undef GEN_LDS
7171 #define GEN_LD(name, ldop, opc, type) \
7172 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7173 #define GEN_LDU(name, ldop, opc, type) \
7174 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7175 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7176 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7177 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7178 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7179 #define GEN_LDS(name, ldop, op, type) \
7180 GEN_LD(name, ldop, op | 0x20, type) \
7181 GEN_LDU(name, ldop, op | 0x21, type) \
7182 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7183 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7184
7185 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
7186 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
7187 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
7188 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
7189 #if defined(TARGET_PPC64)
7190 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
7191 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
7192 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
7193 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
7194 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
7195
7196 /* HV/P7 and later only */
7197 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
7198 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7199 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7200 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
7201 #endif
7202 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
7203 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
7204
7205 /* External PID based load */
7206 #undef GEN_LDEPX
7207 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7208 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7209 0x00000001, PPC_NONE, PPC2_BOOKE206),
7210
7211 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
7212 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
7213 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
7214 #if defined(TARGET_PPC64)
7215 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
7216 #endif
7217
7218 #undef GEN_ST
7219 #undef GEN_STU
7220 #undef GEN_STUX
7221 #undef GEN_STX_E
7222 #undef GEN_STS
7223 #define GEN_ST(name, stop, opc, type) \
7224 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7225 #define GEN_STU(name, stop, opc, type) \
7226 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7227 #define GEN_STUX(name, stop, opc2, opc3, type) \
7228 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7229 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7230 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7231 #define GEN_STS(name, stop, op, type) \
7232 GEN_ST(name, stop, op | 0x20, type) \
7233 GEN_STU(name, stop, op | 0x21, type) \
7234 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7235 GEN_STX(name, stop, 0x17, op | 0x00, type)
7236
7237 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
7238 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
7239 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
7240 #if defined(TARGET_PPC64)
7241 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
7242 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
7243 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
7244 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
7245 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
7246 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
7247 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
7248 #endif
7249 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
7250 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
7251
7252 #undef GEN_STEPX
7253 #define GEN_STEPX(name, ldop, opc2, opc3) \
7254 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7255 0x00000001, PPC_NONE, PPC2_BOOKE206),
7256
7257 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
7258 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
7259 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
7260 #if defined(TARGET_PPC64)
7261 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
7262 #endif
7263
7264 #undef GEN_CRLOGIC
7265 #define GEN_CRLOGIC(name, tcg_op, opc) \
7266 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7267 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
7268 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
7269 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
7270 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
7271 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
7272 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
7273 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
7274 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
7275
7276 #undef GEN_MAC_HANDLER
7277 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7278 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7279 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
7280 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
7281 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
7282 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7283 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7284 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7285 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7286 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7287 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7288 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7289 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7290 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7291 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7292 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7293 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7294 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7295 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7296 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7297 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7298 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7299 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7300 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7301 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7302 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7303 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7304 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7305 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7306 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7307 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7308 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7309 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7310 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7311 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7312 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7313 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7314 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7315 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7316 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7317 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7318 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7319 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7320 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7321
7322 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7323 PPC_NONE, PPC2_TM),
7324 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7325 PPC_NONE, PPC2_TM),
7326 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7327 PPC_NONE, PPC2_TM),
7328 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7329 PPC_NONE, PPC2_TM),
7330 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7331 PPC_NONE, PPC2_TM),
7332 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7333 PPC_NONE, PPC2_TM),
7334 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7335 PPC_NONE, PPC2_TM),
7336 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7337 PPC_NONE, PPC2_TM),
7338 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7339 PPC_NONE, PPC2_TM),
7340 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7341 PPC_NONE, PPC2_TM),
7342 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7343 PPC_NONE, PPC2_TM),
7344
7345 #include "translate/fp-ops.inc.c"
7346
7347 #include "translate/vmx-ops.inc.c"
7348
7349 #include "translate/vsx-ops.inc.c"
7350
7351 #include "translate/dfp-ops.inc.c"
7352
7353 #include "translate/spe-ops.inc.c"
7354 };
7355
7356 #include "helper_regs.h"
7357 #include "translate_init.inc.c"
7358
7359 /*****************************************************************************/
7360 /* Misc PowerPC helpers */
7361 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
7362 int flags)
7363 {
7364 #define RGPL 4
7365 #define RFPL 4
7366
7367 PowerPCCPU *cpu = POWERPC_CPU(cs);
7368 CPUPPCState *env = &cpu->env;
7369 int i;
7370
7371 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7372 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7373 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7374 cs->cpu_index);
7375 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7376 TARGET_FMT_lx " iidx %d didx %d\n",
7377 env->msr, env->spr[SPR_HID0],
7378 env->hflags, env->immu_idx, env->dmmu_idx);
7379 #if !defined(NO_TIMER_DUMP)
7380 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7381 #if !defined(CONFIG_USER_ONLY)
7382 " DECR %08" PRIu32
7383 #endif
7384 "\n",
7385 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7386 #if !defined(CONFIG_USER_ONLY)
7387 , cpu_ppc_load_decr(env)
7388 #endif
7389 );
7390 #endif
7391 for (i = 0; i < 32; i++) {
7392 if ((i & (RGPL - 1)) == 0)
7393 cpu_fprintf(f, "GPR%02d", i);
7394 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7395 if ((i & (RGPL - 1)) == (RGPL - 1))
7396 cpu_fprintf(f, "\n");
7397 }
7398 cpu_fprintf(f, "CR ");
7399 for (i = 0; i < 8; i++)
7400 cpu_fprintf(f, "%01x", env->crf[i]);
7401 cpu_fprintf(f, " [");
7402 for (i = 0; i < 8; i++) {
7403 char a = '-';
7404 if (env->crf[i] & 0x08)
7405 a = 'L';
7406 else if (env->crf[i] & 0x04)
7407 a = 'G';
7408 else if (env->crf[i] & 0x02)
7409 a = 'E';
7410 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7411 }
7412 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7413 env->reserve_addr);
7414
7415 if (flags & CPU_DUMP_FPU) {
7416 for (i = 0; i < 32; i++) {
7417 if ((i & (RFPL - 1)) == 0) {
7418 cpu_fprintf(f, "FPR%02d", i);
7419 }
7420 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7421 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7422 cpu_fprintf(f, "\n");
7423 }
7424 }
7425 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7426 }
7427
7428 #if !defined(CONFIG_USER_ONLY)
7429 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7430 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7431 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7432 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7433
7434 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7435 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7436 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7437 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7438
7439 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7440 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7441 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7442 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7443
7444 #if defined(TARGET_PPC64)
7445 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7446 env->excp_model == POWERPC_EXCP_POWER8) {
7447 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7448 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7449 }
7450 #endif
7451 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7452 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7453 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7454 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7455 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7456
7457 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7458 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7459 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7460 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7461
7462 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7463 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7464 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7465 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7466
7467 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7468 " EPR " TARGET_FMT_lx "\n",
7469 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7470 env->spr[SPR_BOOKE_EPR]);
7471
7472 /* FSL-specific */
7473 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7474 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7475 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7476 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7477
7478 /*
7479 * IVORs are left out as they are large and do not change often --
7480 * they can be read with "p $ivor0", "p $ivor1", etc.
7481 */
7482 }
7483
7484 #if defined(TARGET_PPC64)
7485 if (env->flags & POWERPC_FLAG_CFAR) {
7486 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7487 }
7488 #endif
7489
7490 if (env->spr_cb[SPR_LPCR].name)
7491 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7492
7493 switch (env->mmu_model) {
7494 case POWERPC_MMU_32B:
7495 case POWERPC_MMU_601:
7496 case POWERPC_MMU_SOFT_6xx:
7497 case POWERPC_MMU_SOFT_74xx:
7498 #if defined(TARGET_PPC64)
7499 case POWERPC_MMU_64B:
7500 case POWERPC_MMU_2_03:
7501 case POWERPC_MMU_2_06:
7502 case POWERPC_MMU_2_07:
7503 case POWERPC_MMU_3_00:
7504 #endif
7505 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7506 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7507 }
7508 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7509 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7510 }
7511 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7512 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7513 break;
7514 case POWERPC_MMU_BOOKE206:
7515 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7516 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7517 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7518 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7519
7520 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7521 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7522 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7523 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7524
7525 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7526 " TLB1CFG " TARGET_FMT_lx "\n",
7527 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7528 env->spr[SPR_BOOKE_TLB1CFG]);
7529 break;
7530 default:
7531 break;
7532 }
7533 #endif
7534
7535 #undef RGPL
7536 #undef RFPL
7537 }
7538
7539 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7540 fprintf_function cpu_fprintf, int flags)
7541 {
7542 #if defined(DO_PPC_STATISTICS)
7543 PowerPCCPU *cpu = POWERPC_CPU(cs);
7544 opc_handler_t **t1, **t2, **t3, *handler;
7545 int op1, op2, op3;
7546
7547 t1 = cpu->env.opcodes;
7548 for (op1 = 0; op1 < 64; op1++) {
7549 handler = t1[op1];
7550 if (is_indirect_opcode(handler)) {
7551 t2 = ind_table(handler);
7552 for (op2 = 0; op2 < 32; op2++) {
7553 handler = t2[op2];
7554 if (is_indirect_opcode(handler)) {
7555 t3 = ind_table(handler);
7556 for (op3 = 0; op3 < 32; op3++) {
7557 handler = t3[op3];
7558 if (handler->count == 0)
7559 continue;
7560 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7561 "%016" PRIx64 " %" PRId64 "\n",
7562 op1, op2, op3, op1, (op3 << 5) | op2,
7563 handler->oname,
7564 handler->count, handler->count);
7565 }
7566 } else {
7567 if (handler->count == 0)
7568 continue;
7569 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7570 "%016" PRIx64 " %" PRId64 "\n",
7571 op1, op2, op1, op2, handler->oname,
7572 handler->count, handler->count);
7573 }
7574 }
7575 } else {
7576 if (handler->count == 0)
7577 continue;
7578 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7579 " %" PRId64 "\n",
7580 op1, op1, handler->oname,
7581 handler->count, handler->count);
7582 }
7583 }
7584 #endif
7585 }
7586
7587 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7588 {
7589 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7590 CPUPPCState *env = cs->env_ptr;
7591 int bound;
7592
7593 ctx->exception = POWERPC_EXCP_NONE;
7594 ctx->spr_cb = env->spr_cb;
7595 ctx->pr = msr_pr;
7596 ctx->mem_idx = env->dmmu_idx;
7597 ctx->dr = msr_dr;
7598 #if !defined(CONFIG_USER_ONLY)
7599 ctx->hv = msr_hv || !env->has_hv_mode;
7600 #endif
7601 ctx->insns_flags = env->insns_flags;
7602 ctx->insns_flags2 = env->insns_flags2;
7603 ctx->access_type = -1;
7604 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7605 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7606 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7607 ctx->flags = env->flags;
7608 #if defined(TARGET_PPC64)
7609 ctx->sf_mode = msr_is_64bit(env, env->msr);
7610 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7611 #endif
7612 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7613 || env->mmu_model == POWERPC_MMU_601
7614 || (env->mmu_model & POWERPC_MMU_64B);
7615
7616 ctx->fpu_enabled = !!msr_fp;
7617 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7618 ctx->spe_enabled = !!msr_spe;
7619 else
7620 ctx->spe_enabled = false;
7621 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7622 ctx->altivec_enabled = !!msr_vr;
7623 else
7624 ctx->altivec_enabled = false;
7625 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7626 ctx->vsx_enabled = !!msr_vsx;
7627 } else {
7628 ctx->vsx_enabled = false;
7629 }
7630 #if defined(TARGET_PPC64)
7631 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7632 ctx->tm_enabled = !!msr_tm;
7633 } else {
7634 ctx->tm_enabled = false;
7635 }
7636 #endif
7637 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7638 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7639 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7640 else
7641 ctx->singlestep_enabled = 0;
7642 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7643 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7644 if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
7645 ctx->singlestep_enabled = 0;
7646 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
7647 if (dbcr0 & DBCR0_ICMP) {
7648 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7649 }
7650 if (dbcr0 & DBCR0_BRT) {
7651 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7652 }
7653
7654 }
7655 if (unlikely(ctx->base.singlestep_enabled)) {
7656 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7657 }
7658 #if defined (DO_SINGLE_STEP) && 0
7659 /* Single step trace mode */
7660 msr_se = 1;
7661 #endif
7662
7663 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7664 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7665 }
7666
7667 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7668 {
7669 }
7670
7671 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7672 {
7673 tcg_gen_insn_start(dcbase->pc_next);
7674 }
7675
7676 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7677 const CPUBreakpoint *bp)
7678 {
7679 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7680
7681 gen_debug_exception(ctx);
7682 dcbase->is_jmp = DISAS_NORETURN;
7683 /* The address covered by the breakpoint must be included in
7684 [tb->pc, tb->pc + tb->size) in order to for it to be
7685 properly cleared -- thus we increment the PC here so that
7686 the logic setting tb->size below does the right thing. */
7687 ctx->base.pc_next += 4;
7688 return true;
7689 }
7690
7691 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7692 {
7693 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7694 CPUPPCState *env = cs->env_ptr;
7695 opc_handler_t **table, *handler;
7696
7697 LOG_DISAS("----------------\n");
7698 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7699 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7700
7701 if (unlikely(need_byteswap(ctx))) {
7702 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7703 } else {
7704 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7705 }
7706 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7707 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7708 opc3(ctx->opcode), opc4(ctx->opcode),
7709 ctx->le_mode ? "little" : "big");
7710 ctx->base.pc_next += 4;
7711 table = env->opcodes;
7712 handler = table[opc1(ctx->opcode)];
7713 if (is_indirect_opcode(handler)) {
7714 table = ind_table(handler);
7715 handler = table[opc2(ctx->opcode)];
7716 if (is_indirect_opcode(handler)) {
7717 table = ind_table(handler);
7718 handler = table[opc3(ctx->opcode)];
7719 if (is_indirect_opcode(handler)) {
7720 table = ind_table(handler);
7721 handler = table[opc4(ctx->opcode)];
7722 }
7723 }
7724 }
7725 /* Is opcode *REALLY* valid ? */
7726 if (unlikely(handler->handler == &gen_invalid)) {
7727 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7728 "%02x - %02x - %02x - %02x (%08x) "
7729 TARGET_FMT_lx " %d\n",
7730 opc1(ctx->opcode), opc2(ctx->opcode),
7731 opc3(ctx->opcode), opc4(ctx->opcode),
7732 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7733 } else {
7734 uint32_t inval;
7735
7736 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7737 && Rc(ctx->opcode))) {
7738 inval = handler->inval2;
7739 } else {
7740 inval = handler->inval1;
7741 }
7742
7743 if (unlikely((ctx->opcode & inval) != 0)) {
7744 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7745 "%02x - %02x - %02x - %02x (%08x) "
7746 TARGET_FMT_lx "\n", ctx->opcode & inval,
7747 opc1(ctx->opcode), opc2(ctx->opcode),
7748 opc3(ctx->opcode), opc4(ctx->opcode),
7749 ctx->opcode, ctx->base.pc_next - 4);
7750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7751 ctx->base.is_jmp = DISAS_NORETURN;
7752 return;
7753 }
7754 }
7755 (*(handler->handler))(ctx);
7756 #if defined(DO_PPC_STATISTICS)
7757 handler->count++;
7758 #endif
7759 /* Check trace mode exceptions */
7760 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7761 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7762 ctx->exception != POWERPC_SYSCALL &&
7763 ctx->exception != POWERPC_EXCP_TRAP &&
7764 ctx->exception != POWERPC_EXCP_BRANCH)) {
7765 uint32_t excp = gen_prep_dbgex(ctx, POWERPC_EXCP_TRACE);
7766 if (excp != POWERPC_EXCP_NONE)
7767 gen_exception_nip(ctx, excp, ctx->base.pc_next);
7768 }
7769
7770 if (tcg_check_temp_count()) {
7771 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7772 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7773 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7774 }
7775
7776 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7777 DISAS_NEXT : DISAS_NORETURN;
7778 }
7779
7780 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7781 {
7782 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7783
7784 if (ctx->exception == POWERPC_EXCP_NONE) {
7785 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7786 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7787 if (unlikely(ctx->base.singlestep_enabled)) {
7788 gen_debug_exception(ctx);
7789 }
7790 /* Generate the return instruction */
7791 tcg_gen_exit_tb(NULL, 0);
7792 }
7793 }
7794
7795 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7796 {
7797 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7798 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7799 }
7800
7801 static const TranslatorOps ppc_tr_ops = {
7802 .init_disas_context = ppc_tr_init_disas_context,
7803 .tb_start = ppc_tr_tb_start,
7804 .insn_start = ppc_tr_insn_start,
7805 .breakpoint_check = ppc_tr_breakpoint_check,
7806 .translate_insn = ppc_tr_translate_insn,
7807 .tb_stop = ppc_tr_tb_stop,
7808 .disas_log = ppc_tr_disas_log,
7809 };
7810
7811 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7812 {
7813 DisasContext ctx;
7814
7815 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
7816 }
7817
7818 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7819 target_ulong *data)
7820 {
7821 env->nip = data[0];
7822 }
AR7 emulation for QEMU