4 * Copyright (c) 2013 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "hw/loader.h"
28 #include "sysemu/kvm.h"
30 #include "qapi/visitor.h"
32 static inline void set_feature(CPUARMState
*env
, int feature
)
34 env
->features
|= 1ULL << feature
;
37 static inline void unset_feature(CPUARMState
*env
, int feature
)
39 env
->features
&= ~(1ULL << feature
);
42 #ifndef CONFIG_USER_ONLY
43 static uint64_t a57_a53_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
45 ARMCPU
*cpu
= env_archcpu(env
);
47 /* Number of cores is in [25:24]; otherwise we RAZ */
48 return (cpu
->core_count
- 1) << 24;
52 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo
[] = {
53 #ifndef CONFIG_USER_ONLY
54 { .name
= "L2CTLR_EL1", .state
= ARM_CP_STATE_AA64
,
55 .opc0
= 3, .opc1
= 1, .crn
= 11, .crm
= 0, .opc2
= 2,
56 .access
= PL1_RW
, .readfn
= a57_a53_l2ctlr_read
,
57 .writefn
= arm_cp_write_ignore
},
59 .cp
= 15, .opc1
= 1, .crn
= 9, .crm
= 0, .opc2
= 2,
60 .access
= PL1_RW
, .readfn
= a57_a53_l2ctlr_read
,
61 .writefn
= arm_cp_write_ignore
},
63 { .name
= "L2ECTLR_EL1", .state
= ARM_CP_STATE_AA64
,
64 .opc0
= 3, .opc1
= 1, .crn
= 11, .crm
= 0, .opc2
= 3,
65 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
67 .cp
= 15, .opc1
= 1, .crn
= 9, .crm
= 0, .opc2
= 3,
68 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
69 { .name
= "L2ACTLR", .state
= ARM_CP_STATE_BOTH
,
70 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 0, .opc2
= 0,
71 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
72 { .name
= "CPUACTLR_EL1", .state
= ARM_CP_STATE_AA64
,
73 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 2, .opc2
= 0,
74 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
76 .cp
= 15, .opc1
= 0, .crm
= 15,
77 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
78 { .name
= "CPUECTLR_EL1", .state
= ARM_CP_STATE_AA64
,
79 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 2, .opc2
= 1,
80 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
82 .cp
= 15, .opc1
= 1, .crm
= 15,
83 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
84 { .name
= "CPUMERRSR_EL1", .state
= ARM_CP_STATE_AA64
,
85 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 2, .opc2
= 2,
86 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
87 { .name
= "CPUMERRSR",
88 .cp
= 15, .opc1
= 2, .crm
= 15,
89 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
90 { .name
= "L2MERRSR_EL1", .state
= ARM_CP_STATE_AA64
,
91 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 2, .opc2
= 3,
92 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
94 .cp
= 15, .opc1
= 3, .crm
= 15,
95 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
99 static void aarch64_a57_initfn(Object
*obj
)
101 ARMCPU
*cpu
= ARM_CPU(obj
);
103 cpu
->dtb_compatible
= "arm,cortex-a57";
104 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
105 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
106 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
107 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
108 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
109 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
110 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
111 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
112 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A57
;
113 cpu
->midr
= 0x411fd070;
114 cpu
->revidr
= 0x00000000;
115 cpu
->reset_fpsid
= 0x41034070;
116 cpu
->isar
.mvfr0
= 0x10110222;
117 cpu
->isar
.mvfr1
= 0x12111111;
118 cpu
->isar
.mvfr2
= 0x00000043;
119 cpu
->ctr
= 0x8444c004;
120 cpu
->reset_sctlr
= 0x00c50838;
121 cpu
->id_pfr0
= 0x00000131;
122 cpu
->id_pfr1
= 0x00011011;
123 cpu
->isar
.id_dfr0
= 0x03010066;
124 cpu
->id_afr0
= 0x00000000;
125 cpu
->isar
.id_mmfr0
= 0x10101105;
126 cpu
->isar
.id_mmfr1
= 0x40000000;
127 cpu
->isar
.id_mmfr2
= 0x01260000;
128 cpu
->isar
.id_mmfr3
= 0x02102211;
129 cpu
->isar
.id_isar0
= 0x02101110;
130 cpu
->isar
.id_isar1
= 0x13112111;
131 cpu
->isar
.id_isar2
= 0x21232042;
132 cpu
->isar
.id_isar3
= 0x01112131;
133 cpu
->isar
.id_isar4
= 0x00011142;
134 cpu
->isar
.id_isar5
= 0x00011121;
135 cpu
->isar
.id_isar6
= 0;
136 cpu
->isar
.id_aa64pfr0
= 0x00002222;
137 cpu
->isar
.id_aa64dfr0
= 0x10305106;
138 cpu
->isar
.id_aa64isar0
= 0x00011120;
139 cpu
->isar
.id_aa64mmfr0
= 0x00001124;
140 cpu
->isar
.dbgdidr
= 0x3516d000;
141 cpu
->clidr
= 0x0a200023;
142 cpu
->ccsidr
[0] = 0x701fe00a; /* 32KB L1 dcache */
143 cpu
->ccsidr
[1] = 0x201fe012; /* 48KB L1 icache */
144 cpu
->ccsidr
[2] = 0x70ffe07a; /* 2048KB L2 cache */
145 cpu
->dcz_blocksize
= 4; /* 64 bytes */
146 cpu
->gic_num_lrs
= 4;
147 cpu
->gic_vpribits
= 5;
148 cpu
->gic_vprebits
= 5;
149 define_arm_cp_regs(cpu
, cortex_a72_a57_a53_cp_reginfo
);
152 static void aarch64_a53_initfn(Object
*obj
)
154 ARMCPU
*cpu
= ARM_CPU(obj
);
156 cpu
->dtb_compatible
= "arm,cortex-a53";
157 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
158 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
159 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
160 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
161 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
162 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
163 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
164 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
165 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A53
;
166 cpu
->midr
= 0x410fd034;
167 cpu
->revidr
= 0x00000000;
168 cpu
->reset_fpsid
= 0x41034070;
169 cpu
->isar
.mvfr0
= 0x10110222;
170 cpu
->isar
.mvfr1
= 0x12111111;
171 cpu
->isar
.mvfr2
= 0x00000043;
172 cpu
->ctr
= 0x84448004; /* L1Ip = VIPT */
173 cpu
->reset_sctlr
= 0x00c50838;
174 cpu
->id_pfr0
= 0x00000131;
175 cpu
->id_pfr1
= 0x00011011;
176 cpu
->isar
.id_dfr0
= 0x03010066;
177 cpu
->id_afr0
= 0x00000000;
178 cpu
->isar
.id_mmfr0
= 0x10101105;
179 cpu
->isar
.id_mmfr1
= 0x40000000;
180 cpu
->isar
.id_mmfr2
= 0x01260000;
181 cpu
->isar
.id_mmfr3
= 0x02102211;
182 cpu
->isar
.id_isar0
= 0x02101110;
183 cpu
->isar
.id_isar1
= 0x13112111;
184 cpu
->isar
.id_isar2
= 0x21232042;
185 cpu
->isar
.id_isar3
= 0x01112131;
186 cpu
->isar
.id_isar4
= 0x00011142;
187 cpu
->isar
.id_isar5
= 0x00011121;
188 cpu
->isar
.id_isar6
= 0;
189 cpu
->isar
.id_aa64pfr0
= 0x00002222;
190 cpu
->isar
.id_aa64dfr0
= 0x10305106;
191 cpu
->isar
.id_aa64isar0
= 0x00011120;
192 cpu
->isar
.id_aa64mmfr0
= 0x00001122; /* 40 bit physical addr */
193 cpu
->isar
.dbgdidr
= 0x3516d000;
194 cpu
->clidr
= 0x0a200023;
195 cpu
->ccsidr
[0] = 0x700fe01a; /* 32KB L1 dcache */
196 cpu
->ccsidr
[1] = 0x201fe00a; /* 32KB L1 icache */
197 cpu
->ccsidr
[2] = 0x707fe07a; /* 1024KB L2 cache */
198 cpu
->dcz_blocksize
= 4; /* 64 bytes */
199 cpu
->gic_num_lrs
= 4;
200 cpu
->gic_vpribits
= 5;
201 cpu
->gic_vprebits
= 5;
202 define_arm_cp_regs(cpu
, cortex_a72_a57_a53_cp_reginfo
);
205 static void aarch64_a72_initfn(Object
*obj
)
207 ARMCPU
*cpu
= ARM_CPU(obj
);
209 cpu
->dtb_compatible
= "arm,cortex-a72";
210 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
211 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
212 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
213 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
214 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
215 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
216 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
217 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
218 cpu
->midr
= 0x410fd083;
219 cpu
->revidr
= 0x00000000;
220 cpu
->reset_fpsid
= 0x41034080;
221 cpu
->isar
.mvfr0
= 0x10110222;
222 cpu
->isar
.mvfr1
= 0x12111111;
223 cpu
->isar
.mvfr2
= 0x00000043;
224 cpu
->ctr
= 0x8444c004;
225 cpu
->reset_sctlr
= 0x00c50838;
226 cpu
->id_pfr0
= 0x00000131;
227 cpu
->id_pfr1
= 0x00011011;
228 cpu
->isar
.id_dfr0
= 0x03010066;
229 cpu
->id_afr0
= 0x00000000;
230 cpu
->isar
.id_mmfr0
= 0x10201105;
231 cpu
->isar
.id_mmfr1
= 0x40000000;
232 cpu
->isar
.id_mmfr2
= 0x01260000;
233 cpu
->isar
.id_mmfr3
= 0x02102211;
234 cpu
->isar
.id_isar0
= 0x02101110;
235 cpu
->isar
.id_isar1
= 0x13112111;
236 cpu
->isar
.id_isar2
= 0x21232042;
237 cpu
->isar
.id_isar3
= 0x01112131;
238 cpu
->isar
.id_isar4
= 0x00011142;
239 cpu
->isar
.id_isar5
= 0x00011121;
240 cpu
->isar
.id_aa64pfr0
= 0x00002222;
241 cpu
->isar
.id_aa64dfr0
= 0x10305106;
242 cpu
->isar
.id_aa64isar0
= 0x00011120;
243 cpu
->isar
.id_aa64mmfr0
= 0x00001124;
244 cpu
->isar
.dbgdidr
= 0x3516d000;
245 cpu
->clidr
= 0x0a200023;
246 cpu
->ccsidr
[0] = 0x701fe00a; /* 32KB L1 dcache */
247 cpu
->ccsidr
[1] = 0x201fe012; /* 48KB L1 icache */
248 cpu
->ccsidr
[2] = 0x707fe07a; /* 1MB L2 cache */
249 cpu
->dcz_blocksize
= 4; /* 64 bytes */
250 cpu
->gic_num_lrs
= 4;
251 cpu
->gic_vpribits
= 5;
252 cpu
->gic_vprebits
= 5;
253 define_arm_cp_regs(cpu
, cortex_a72_a57_a53_cp_reginfo
);
256 void arm_cpu_sve_finalize(ARMCPU
*cpu
, Error
**errp
)
259 * If any vector lengths are explicitly enabled with sve<N> properties,
260 * then all other lengths are implicitly disabled. If sve-max-vq is
261 * specified then it is the same as explicitly enabling all lengths
262 * up to and including the specified maximum, which means all larger
263 * lengths will be implicitly disabled. If no sve<N> properties
264 * are enabled and sve-max-vq is not specified, then all lengths not
265 * explicitly disabled will be enabled. Additionally, all power-of-two
266 * vector lengths less than the maximum enabled length will be
267 * automatically enabled and all vector lengths larger than the largest
268 * disabled power-of-two vector length will be automatically disabled.
269 * Errors are generated if the user provided input that interferes with
270 * any of the above. Finally, if SVE is not disabled, then at least one
271 * vector length must be enabled.
273 DECLARE_BITMAP(kvm_supported
, ARM_MAX_VQ
);
274 DECLARE_BITMAP(tmp
, ARM_MAX_VQ
);
275 uint32_t vq
, max_vq
= 0;
277 /* Collect the set of vector lengths supported by KVM. */
278 bitmap_zero(kvm_supported
, ARM_MAX_VQ
);
279 if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu
))) {
280 kvm_arm_sve_get_vls(CPU(cpu
), kvm_supported
);
281 } else if (kvm_enabled()) {
282 assert(!cpu_isar_feature(aa64_sve
, cpu
));
286 * Process explicit sve<N> properties.
287 * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
288 * Check first for any sve<N> enabled.
290 if (!bitmap_empty(cpu
->sve_vq_map
, ARM_MAX_VQ
)) {
291 max_vq
= find_last_bit(cpu
->sve_vq_map
, ARM_MAX_VQ
) + 1;
293 if (cpu
->sve_max_vq
&& max_vq
> cpu
->sve_max_vq
) {
294 error_setg(errp
, "cannot enable sve%d", max_vq
* 128);
295 error_append_hint(errp
, "sve%d is larger than the maximum vector "
296 "length, sve-max-vq=%d (%d bits)\n",
297 max_vq
* 128, cpu
->sve_max_vq
,
298 cpu
->sve_max_vq
* 128);
304 * For KVM we have to automatically enable all supported unitialized
305 * lengths, even when the smaller lengths are not all powers-of-two.
307 bitmap_andnot(tmp
, kvm_supported
, cpu
->sve_vq_init
, max_vq
);
308 bitmap_or(cpu
->sve_vq_map
, cpu
->sve_vq_map
, tmp
, max_vq
);
310 /* Propagate enabled bits down through required powers-of-two. */
311 for (vq
= pow2floor(max_vq
); vq
>= 1; vq
>>= 1) {
312 if (!test_bit(vq
- 1, cpu
->sve_vq_init
)) {
313 set_bit(vq
- 1, cpu
->sve_vq_map
);
317 } else if (cpu
->sve_max_vq
== 0) {
319 * No explicit bits enabled, and no implicit bits from sve-max-vq.
321 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
322 /* SVE is disabled and so are all vector lengths. Good. */
327 /* Disabling a supported length disables all larger lengths. */
328 for (vq
= 1; vq
<= ARM_MAX_VQ
; ++vq
) {
329 if (test_bit(vq
- 1, cpu
->sve_vq_init
) &&
330 test_bit(vq
- 1, kvm_supported
)) {
334 max_vq
= vq
<= ARM_MAX_VQ
? vq
- 1 : ARM_MAX_VQ
;
335 bitmap_andnot(cpu
->sve_vq_map
, kvm_supported
,
336 cpu
->sve_vq_init
, max_vq
);
337 if (max_vq
== 0 || bitmap_empty(cpu
->sve_vq_map
, max_vq
)) {
338 error_setg(errp
, "cannot disable sve%d", vq
* 128);
339 error_append_hint(errp
, "Disabling sve%d results in all "
340 "vector lengths being disabled.\n",
342 error_append_hint(errp
, "With SVE enabled, at least one "
343 "vector length must be enabled.\n");
347 /* Disabling a power-of-two disables all larger lengths. */
348 if (test_bit(0, cpu
->sve_vq_init
)) {
349 error_setg(errp
, "cannot disable sve128");
350 error_append_hint(errp
, "Disabling sve128 results in all "
351 "vector lengths being disabled.\n");
352 error_append_hint(errp
, "With SVE enabled, at least one "
353 "vector length must be enabled.\n");
356 for (vq
= 2; vq
<= ARM_MAX_VQ
; vq
<<= 1) {
357 if (test_bit(vq
- 1, cpu
->sve_vq_init
)) {
361 max_vq
= vq
<= ARM_MAX_VQ
? vq
- 1 : ARM_MAX_VQ
;
362 bitmap_complement(cpu
->sve_vq_map
, cpu
->sve_vq_init
, max_vq
);
365 max_vq
= find_last_bit(cpu
->sve_vq_map
, max_vq
) + 1;
369 * Process the sve-max-vq property.
370 * Note that we know from the above that no bit above
371 * sve-max-vq is currently set.
373 if (cpu
->sve_max_vq
!= 0) {
374 max_vq
= cpu
->sve_max_vq
;
376 if (!test_bit(max_vq
- 1, cpu
->sve_vq_map
) &&
377 test_bit(max_vq
- 1, cpu
->sve_vq_init
)) {
378 error_setg(errp
, "cannot disable sve%d", max_vq
* 128);
379 error_append_hint(errp
, "The maximum vector length must be "
380 "enabled, sve-max-vq=%d (%d bits)\n",
381 max_vq
, max_vq
* 128);
385 /* Set all bits not explicitly set within sve-max-vq. */
386 bitmap_complement(tmp
, cpu
->sve_vq_init
, max_vq
);
387 bitmap_or(cpu
->sve_vq_map
, cpu
->sve_vq_map
, tmp
, max_vq
);
391 * We should know what max-vq is now. Also, as we're done
392 * manipulating sve-vq-map, we ensure any bits above max-vq
393 * are clear, just in case anybody looks.
396 bitmap_clear(cpu
->sve_vq_map
, max_vq
, ARM_MAX_VQ
- max_vq
);
399 /* Ensure the set of lengths matches what KVM supports. */
400 bitmap_xor(tmp
, cpu
->sve_vq_map
, kvm_supported
, max_vq
);
401 if (!bitmap_empty(tmp
, max_vq
)) {
402 vq
= find_last_bit(tmp
, max_vq
) + 1;
403 if (test_bit(vq
- 1, cpu
->sve_vq_map
)) {
404 if (cpu
->sve_max_vq
) {
405 error_setg(errp
, "cannot set sve-max-vq=%d",
407 error_append_hint(errp
, "This KVM host does not support "
408 "the vector length %d-bits.\n",
410 error_append_hint(errp
, "It may not be possible to use "
411 "sve-max-vq with this KVM host. Try "
412 "using only sve<N> properties.\n");
414 error_setg(errp
, "cannot enable sve%d", vq
* 128);
415 error_append_hint(errp
, "This KVM host does not support "
416 "the vector length %d-bits.\n",
420 error_setg(errp
, "cannot disable sve%d", vq
* 128);
421 error_append_hint(errp
, "The KVM host requires all "
422 "supported vector lengths smaller "
423 "than %d bits to also be enabled.\n",
429 /* Ensure all required powers-of-two are enabled. */
430 for (vq
= pow2floor(max_vq
); vq
>= 1; vq
>>= 1) {
431 if (!test_bit(vq
- 1, cpu
->sve_vq_map
)) {
432 error_setg(errp
, "cannot disable sve%d", vq
* 128);
433 error_append_hint(errp
, "sve%d is required as it "
434 "is a power-of-two length smaller than "
435 "the maximum, sve%d\n",
436 vq
* 128, max_vq
* 128);
443 * Now that we validated all our vector lengths, the only question
444 * left to answer is if we even want SVE at all.
446 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
447 error_setg(errp
, "cannot enable sve%d", max_vq
* 128);
448 error_append_hint(errp
, "SVE must be enabled to enable vector "
450 error_append_hint(errp
, "Add sve=on to the CPU property list.\n");
454 /* From now on sve_max_vq is the actual maximum supported length. */
455 cpu
->sve_max_vq
= max_vq
;
458 static void cpu_max_get_sve_max_vq(Object
*obj
, Visitor
*v
, const char *name
,
459 void *opaque
, Error
**errp
)
461 ARMCPU
*cpu
= ARM_CPU(obj
);
464 /* All vector lengths are disabled when SVE is off. */
465 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
468 value
= cpu
->sve_max_vq
;
470 visit_type_uint32(v
, name
, &value
, errp
);
473 static void cpu_max_set_sve_max_vq(Object
*obj
, Visitor
*v
, const char *name
,
474 void *opaque
, Error
**errp
)
476 ARMCPU
*cpu
= ARM_CPU(obj
);
480 visit_type_uint32(v
, name
, &max_vq
, &err
);
482 error_propagate(errp
, err
);
486 if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu
))) {
487 error_setg(errp
, "cannot set sve-max-vq");
488 error_append_hint(errp
, "SVE not supported by KVM on this host\n");
492 if (max_vq
== 0 || max_vq
> ARM_MAX_VQ
) {
493 error_setg(errp
, "unsupported SVE vector length");
494 error_append_hint(errp
, "Valid sve-max-vq in range [1-%d]\n",
499 cpu
->sve_max_vq
= max_vq
;
502 static void cpu_arm_get_sve_vq(Object
*obj
, Visitor
*v
, const char *name
,
503 void *opaque
, Error
**errp
)
505 ARMCPU
*cpu
= ARM_CPU(obj
);
506 uint32_t vq
= atoi(&name
[3]) / 128;
509 /* All vector lengths are disabled when SVE is off. */
510 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
513 value
= test_bit(vq
- 1, cpu
->sve_vq_map
);
515 visit_type_bool(v
, name
, &value
, errp
);
518 static void cpu_arm_set_sve_vq(Object
*obj
, Visitor
*v
, const char *name
,
519 void *opaque
, Error
**errp
)
521 ARMCPU
*cpu
= ARM_CPU(obj
);
522 uint32_t vq
= atoi(&name
[3]) / 128;
526 visit_type_bool(v
, name
, &value
, &err
);
528 error_propagate(errp
, err
);
532 if (value
&& kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu
))) {
533 error_setg(errp
, "cannot enable %s", name
);
534 error_append_hint(errp
, "SVE not supported by KVM on this host\n");
539 set_bit(vq
- 1, cpu
->sve_vq_map
);
541 clear_bit(vq
- 1, cpu
->sve_vq_map
);
543 set_bit(vq
- 1, cpu
->sve_vq_init
);
546 static void cpu_arm_get_sve(Object
*obj
, Visitor
*v
, const char *name
,
547 void *opaque
, Error
**errp
)
549 ARMCPU
*cpu
= ARM_CPU(obj
);
550 bool value
= cpu_isar_feature(aa64_sve
, cpu
);
552 visit_type_bool(v
, name
, &value
, errp
);
555 static void cpu_arm_set_sve(Object
*obj
, Visitor
*v
, const char *name
,
556 void *opaque
, Error
**errp
)
558 ARMCPU
*cpu
= ARM_CPU(obj
);
563 visit_type_bool(v
, name
, &value
, &err
);
565 error_propagate(errp
, err
);
569 if (value
&& kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu
))) {
570 error_setg(errp
, "'sve' feature not supported by KVM on this host");
574 t
= cpu
->isar
.id_aa64pfr0
;
575 t
= FIELD_DP64(t
, ID_AA64PFR0
, SVE
, value
);
576 cpu
->isar
.id_aa64pfr0
= t
;
579 void aarch64_add_sve_properties(Object
*obj
)
583 object_property_add(obj
, "sve", "bool", cpu_arm_get_sve
,
584 cpu_arm_set_sve
, NULL
, NULL
, &error_fatal
);
586 for (vq
= 1; vq
<= ARM_MAX_VQ
; ++vq
) {
588 sprintf(name
, "sve%d", vq
* 128);
589 object_property_add(obj
, name
, "bool", cpu_arm_get_sve_vq
,
590 cpu_arm_set_sve_vq
, NULL
, NULL
, &error_fatal
);
594 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
595 * otherwise, a CPU with as many features enabled as our emulation supports.
596 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
597 * this only needs to handle 64 bits.
599 static void aarch64_max_initfn(Object
*obj
)
601 ARMCPU
*cpu
= ARM_CPU(obj
);
604 kvm_arm_set_cpu_features_from_host(cpu
);
605 kvm_arm_add_vcpu_properties(obj
);
609 aarch64_a57_initfn(obj
);
612 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
613 * one and try to apply errata workarounds or use impdef features we
615 * An IMPLEMENTER field of 0 means "reserved for software use";
616 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
617 * to see which features are present";
618 * the VARIANT, PARTNUM and REVISION fields are all implementation
619 * defined and we choose to define PARTNUM just in case guest
620 * code needs to distinguish this QEMU CPU from other software
621 * implementations, though this shouldn't be needed.
623 t
= FIELD_DP64(0, MIDR_EL1
, IMPLEMENTER
, 0);
624 t
= FIELD_DP64(t
, MIDR_EL1
, ARCHITECTURE
, 0xf);
625 t
= FIELD_DP64(t
, MIDR_EL1
, PARTNUM
, 'Q');
626 t
= FIELD_DP64(t
, MIDR_EL1
, VARIANT
, 0);
627 t
= FIELD_DP64(t
, MIDR_EL1
, REVISION
, 0);
630 t
= cpu
->isar
.id_aa64isar0
;
631 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 2); /* AES + PMULL */
632 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 1);
633 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 2); /* SHA512 */
634 t
= FIELD_DP64(t
, ID_AA64ISAR0
, CRC32
, 1);
635 t
= FIELD_DP64(t
, ID_AA64ISAR0
, ATOMIC
, 2);
636 t
= FIELD_DP64(t
, ID_AA64ISAR0
, RDM
, 1);
637 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 1);
638 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 1);
639 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 1);
640 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 1);
641 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 1);
642 t
= FIELD_DP64(t
, ID_AA64ISAR0
, TS
, 2); /* v8.5-CondM */
643 t
= FIELD_DP64(t
, ID_AA64ISAR0
, RNDR
, 1);
644 cpu
->isar
.id_aa64isar0
= t
;
646 t
= cpu
->isar
.id_aa64isar1
;
647 t
= FIELD_DP64(t
, ID_AA64ISAR1
, DPB
, 2);
648 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 1);
649 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 1);
650 t
= FIELD_DP64(t
, ID_AA64ISAR1
, APA
, 1); /* PAuth, architected only */
651 t
= FIELD_DP64(t
, ID_AA64ISAR1
, API
, 0);
652 t
= FIELD_DP64(t
, ID_AA64ISAR1
, GPA
, 1);
653 t
= FIELD_DP64(t
, ID_AA64ISAR1
, GPI
, 0);
654 t
= FIELD_DP64(t
, ID_AA64ISAR1
, SB
, 1);
655 t
= FIELD_DP64(t
, ID_AA64ISAR1
, SPECRES
, 1);
656 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 1);
657 t
= FIELD_DP64(t
, ID_AA64ISAR1
, LRCPC
, 2); /* ARMv8.4-RCPC */
658 cpu
->isar
.id_aa64isar1
= t
;
660 t
= cpu
->isar
.id_aa64pfr0
;
661 t
= FIELD_DP64(t
, ID_AA64PFR0
, SVE
, 1);
662 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 1);
663 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 1);
664 cpu
->isar
.id_aa64pfr0
= t
;
666 t
= cpu
->isar
.id_aa64pfr1
;
667 t
= FIELD_DP64(t
, ID_AA64PFR1
, BT
, 1);
668 cpu
->isar
.id_aa64pfr1
= t
;
670 t
= cpu
->isar
.id_aa64mmfr1
;
671 t
= FIELD_DP64(t
, ID_AA64MMFR1
, HPDS
, 1); /* HPD */
672 t
= FIELD_DP64(t
, ID_AA64MMFR1
, LO
, 1);
673 t
= FIELD_DP64(t
, ID_AA64MMFR1
, VH
, 1);
674 t
= FIELD_DP64(t
, ID_AA64MMFR1
, PAN
, 2); /* ATS1E1 */
675 t
= FIELD_DP64(t
, ID_AA64MMFR1
, VMIDBITS
, 2); /* VMID16 */
676 t
= FIELD_DP64(t
, ID_AA64MMFR1
, XNX
, 1); /* TTS2UXN */
677 cpu
->isar
.id_aa64mmfr1
= t
;
679 t
= cpu
->isar
.id_aa64mmfr2
;
680 t
= FIELD_DP64(t
, ID_AA64MMFR2
, UAO
, 1);
681 t
= FIELD_DP64(t
, ID_AA64MMFR2
, CNP
, 1); /* TTCNP */
682 cpu
->isar
.id_aa64mmfr2
= t
;
684 /* Replicate the same data to the 32-bit id registers. */
685 u
= cpu
->isar
.id_isar5
;
686 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 2); /* AES + PMULL */
687 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 1);
688 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 1);
689 u
= FIELD_DP32(u
, ID_ISAR5
, CRC32
, 1);
690 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 1);
691 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 1);
692 cpu
->isar
.id_isar5
= u
;
694 u
= cpu
->isar
.id_isar6
;
695 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 1);
696 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 1);
697 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 1);
698 u
= FIELD_DP32(u
, ID_ISAR6
, SB
, 1);
699 u
= FIELD_DP32(u
, ID_ISAR6
, SPECRES
, 1);
700 cpu
->isar
.id_isar6
= u
;
702 u
= cpu
->isar
.id_mmfr3
;
703 u
= FIELD_DP32(u
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
704 cpu
->isar
.id_mmfr3
= u
;
706 u
= cpu
->isar
.id_mmfr4
;
707 u
= FIELD_DP32(u
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
708 u
= FIELD_DP32(u
, ID_MMFR4
, AC2
, 1); /* ACTLR2, HACTLR2 */
709 u
= FIELD_DP32(u
, ID_MMFR4
, CNP
, 1); /* TTCNP */
710 u
= FIELD_DP32(u
, ID_MMFR4
, XNX
, 1); /* TTS2UXN */
711 cpu
->isar
.id_mmfr4
= u
;
713 t
= cpu
->isar
.id_aa64dfr0
;
714 t
= FIELD_DP64(t
, ID_AA64DFR0
, PMUVER
, 5); /* v8.4-PMU */
715 cpu
->isar
.id_aa64dfr0
= t
;
717 u
= cpu
->isar
.id_dfr0
;
718 u
= FIELD_DP32(u
, ID_DFR0
, PERFMON
, 5); /* v8.4-PMU */
719 cpu
->isar
.id_dfr0
= u
;
722 * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
723 * so do not set MVFR1.FPHP. Strictly speaking this is not legal,
724 * but it is also not legal to enable SVE without support for FP16,
725 * and enabling SVE in system mode is more useful in the short term.
728 #ifdef CONFIG_USER_ONLY
729 /* For usermode -cpu max we can use a larger and more efficient DCZ
730 * blocksize since we don't have to follow what the hardware does.
732 cpu
->ctr
= 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
733 cpu
->dcz_blocksize
= 7; /* 512 bytes */
737 aarch64_add_sve_properties(obj
);
738 object_property_add(obj
, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq
,
739 cpu_max_set_sve_max_vq
, NULL
, NULL
, &error_fatal
);
742 static const ARMCPUInfo aarch64_cpus
[] = {
743 { .name
= "cortex-a57", .initfn
= aarch64_a57_initfn
},
744 { .name
= "cortex-a53", .initfn
= aarch64_a53_initfn
},
745 { .name
= "cortex-a72", .initfn
= aarch64_a72_initfn
},
746 { .name
= "max", .initfn
= aarch64_max_initfn
},
750 static bool aarch64_cpu_get_aarch64(Object
*obj
, Error
**errp
)
752 ARMCPU
*cpu
= ARM_CPU(obj
);
754 return arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
757 static void aarch64_cpu_set_aarch64(Object
*obj
, bool value
, Error
**errp
)
759 ARMCPU
*cpu
= ARM_CPU(obj
);
761 /* At this time, this property is only allowed if KVM is enabled. This
762 * restriction allows us to avoid fixing up functionality that assumes a
763 * uniform execution state like do_interrupt.
765 if (value
== false) {
766 if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu
))) {
767 error_setg(errp
, "'aarch64' feature cannot be disabled "
768 "unless KVM is enabled and 32-bit EL1 "
772 unset_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
774 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
778 static void aarch64_cpu_initfn(Object
*obj
)
780 object_property_add_bool(obj
, "aarch64", aarch64_cpu_get_aarch64
,
781 aarch64_cpu_set_aarch64
, NULL
);
782 object_property_set_description(obj
, "aarch64",
783 "Set on/off to enable/disable aarch64 "
788 static void aarch64_cpu_finalizefn(Object
*obj
)
792 static gchar
*aarch64_gdb_arch_name(CPUState
*cs
)
794 return g_strdup("aarch64");
797 static void aarch64_cpu_class_init(ObjectClass
*oc
, void *data
)
799 CPUClass
*cc
= CPU_CLASS(oc
);
801 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
802 cc
->gdb_read_register
= aarch64_cpu_gdb_read_register
;
803 cc
->gdb_write_register
= aarch64_cpu_gdb_write_register
;
804 cc
->gdb_num_core_regs
= 34;
805 cc
->gdb_core_xml_file
= "aarch64-core.xml";
806 cc
->gdb_arch_name
= aarch64_gdb_arch_name
;
809 static void aarch64_cpu_instance_init(Object
*obj
)
811 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
813 acc
->info
->initfn(obj
);
814 arm_cpu_post_init(obj
);
817 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
819 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
824 void aarch64_cpu_register(const ARMCPUInfo
*info
)
826 TypeInfo type_info
= {
827 .parent
= TYPE_AARCH64_CPU
,
828 .instance_size
= sizeof(ARMCPU
),
829 .instance_init
= aarch64_cpu_instance_init
,
830 .class_size
= sizeof(ARMCPUClass
),
831 .class_init
= info
->class_init
?: cpu_register_class_init
,
832 .class_data
= (void *)info
,
835 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
836 type_register(&type_info
);
837 g_free((void *)type_info
.name
);
840 static const TypeInfo aarch64_cpu_type_info
= {
841 .name
= TYPE_AARCH64_CPU
,
842 .parent
= TYPE_ARM_CPU
,
843 .instance_size
= sizeof(ARMCPU
),
844 .instance_init
= aarch64_cpu_initfn
,
845 .instance_finalize
= aarch64_cpu_finalizefn
,
847 .class_size
= sizeof(AArch64CPUClass
),
848 .class_init
= aarch64_cpu_class_init
,
851 static void aarch64_cpu_register_types(void)
853 const ARMCPUInfo
*info
= aarch64_cpus
;
855 type_register_static(&aarch64_cpu_type_info
);
858 aarch64_cpu_register(info
);
863 type_init(aarch64_cpu_register_types
)