2 * ARM V2M MPS2 board emulation, trustzone aware FPGA images
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 /* The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
13 * FPGA but is otherwise the same as the 2). Since the CPU itself
14 * and most of the devices are in the FPGA, the details of the board
15 * as seen by the guest depend significantly on the FPGA image.
16 * This source file covers the following FPGA images, for TrustZone cores:
17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
21 * Links to the TRM for the board itself and to the various Application
22 * Notes which document the FPGA images can be found here:
23 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
26 * https://developer.arm.com/documentation/100112/latest/
27 * Application Note AN505:
28 * https://developer.arm.com/documentation/dai0505/latest/
29 * Application Note AN521:
30 * https://developer.arm.com/documentation/dai0521/latest/
31 * Application Note AN524:
32 * https://developer.arm.com/documentation/dai0524/latest/
34 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
35 * (ARM ECM0601256) for the details of some of the device layout:
36 * https://developer.arm.com/documentation/ecm0601256/latest
37 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
38 * most of the device layout:
39 * https://developer.arm.com/documentation/101104/latest/
42 #include "qemu/osdep.h"
43 #include "qemu/units.h"
44 #include "qemu/cutils.h"
45 #include "qapi/error.h"
46 #include "qemu/error-report.h"
47 #include "hw/arm/boot.h"
48 #include "hw/arm/armv7m.h"
49 #include "hw/or-irq.h"
50 #include "hw/boards.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/sysemu.h"
53 #include "hw/misc/unimp.h"
54 #include "hw/char/cmsdk-apb-uart.h"
55 #include "hw/timer/cmsdk-apb-timer.h"
56 #include "hw/misc/mps2-scc.h"
57 #include "hw/misc/mps2-fpgaio.h"
58 #include "hw/misc/tz-mpc.h"
59 #include "hw/misc/tz-msc.h"
60 #include "hw/arm/armsse.h"
61 #include "hw/dma/pl080.h"
62 #include "hw/rtc/pl031.h"
63 #include "hw/ssi/pl022.h"
64 #include "hw/i2c/arm_sbcon_i2c.h"
65 #include "hw/net/lan9118.h"
67 #include "hw/core/split-irq.h"
68 #include "hw/qdev-clock.h"
69 #include "qom/object.h"
71 #define MPS2TZ_NUMIRQ_MAX 95
72 #define MPS2TZ_RAM_MAX 4
74 typedef enum MPS2TZFPGAType
{
81 * Define the layout of RAM in a board, including which parts are
83 * mrindex specifies the index into mms->ram[] to use for the backing RAM;
84 * -1 means "use the system RAM".
86 typedef struct RAMInfo
{
90 int mpc
; /* MPC number, -1 for "not behind an MPC" */
97 * IS_ALIAS: this RAM area is an alias to the upstream end of the
98 * MPC specified by its .mpc value
99 * IS_ROM: this RAM area is read-only
104 struct MPS2TZMachineClass
{
106 MPS2TZFPGAType fpga_type
;
108 uint32_t sysclk_frq
; /* Main SYSCLK frequency in Hz */
110 const uint32_t *oscclk
;
111 uint32_t fpgaio_num_leds
; /* Number of LEDs in FPGAIO LED0 register */
112 bool fpgaio_has_switches
; /* Does FPGAIO have SWITCH register? */
113 int numirq
; /* Number of external interrupts */
114 const RAMInfo
*raminfo
;
115 const char *armsse_type
;
118 struct MPS2TZMachineState
{
122 MemoryRegion ram
[MPS2TZ_RAM_MAX
];
123 MemoryRegion eth_usb_container
;
130 ArmSbconI2CState i2c
[5];
131 UnimplementedDeviceState i2s_audio
;
132 UnimplementedDeviceState gpio
[4];
133 UnimplementedDeviceState gfx
;
134 UnimplementedDeviceState cldc
;
135 UnimplementedDeviceState usb
;
139 CMSDKAPBUART uart
[6];
140 SplitIRQ sec_resp_splitter
;
141 qemu_or_irq uart_irq_orgate
;
142 DeviceState
*lan9118
;
143 SplitIRQ cpu_irq_splitter
[MPS2TZ_NUMIRQ_MAX
];
148 #define TYPE_MPS2TZ_MACHINE "mps2tz"
149 #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")
150 #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521")
151 #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524")
153 OBJECT_DECLARE_TYPE(MPS2TZMachineState
, MPS2TZMachineClass
, MPS2TZ_MACHINE
)
155 /* Slow 32Khz S32KCLK frequency in Hz */
156 #define S32KCLK_FRQ (32 * 1000)
159 * The MPS3 DDR is 2GiB, but on a 32-bit host QEMU doesn't permit
160 * emulation of that much guest RAM, so artificially make it smaller.
162 #if HOST_LONG_BITS == 32
163 #define MPS3_DDR_SIZE (1 * GiB)
165 #define MPS3_DDR_SIZE (2 * GiB)
168 static const uint32_t an505_oscclk
[] = {
174 static const uint32_t an524_oscclk
[] = {
183 static const RAMInfo an505_raminfo
[] = { {
202 .name
= "ssram-0-alias",
209 /* Use the largest bit of contiguous RAM as our "system memory" */
220 static const RAMInfo an524_raminfo
[] = { {
229 .size
= 32 * 4 * KiB
,
233 /* We don't model QSPI flash yet; for now expose it as simple ROM */
243 .size
= MPS3_DDR_SIZE
,
251 static const RAMInfo
*find_raminfo_for_mpc(MPS2TZMachineState
*mms
, int mpc
)
253 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
256 for (p
= mmc
->raminfo
; p
->name
; p
++) {
257 if (p
->mpc
== mpc
&& !(p
->flags
& IS_ALIAS
)) {
261 /* if raminfo array doesn't have an entry for each MPC this is a bug */
262 g_assert_not_reached();
265 static MemoryRegion
*mr_for_raminfo(MPS2TZMachineState
*mms
,
266 const RAMInfo
*raminfo
)
268 /* Return an initialized MemoryRegion for the RAMInfo. */
271 if (raminfo
->mrindex
< 0) {
272 /* Means this RAMInfo is for QEMU's "system memory" */
273 MachineState
*machine
= MACHINE(mms
);
274 assert(!(raminfo
->flags
& IS_ROM
));
278 assert(raminfo
->mrindex
< MPS2TZ_RAM_MAX
);
279 ram
= &mms
->ram
[raminfo
->mrindex
];
281 memory_region_init_ram(ram
, NULL
, raminfo
->name
,
282 raminfo
->size
, &error_fatal
);
283 if (raminfo
->flags
& IS_ROM
) {
284 memory_region_set_readonly(ram
, true);
289 /* Create an alias of an entire original MemoryRegion @orig
290 * located at @base in the memory map.
292 static void make_ram_alias(MemoryRegion
*mr
, const char *name
,
293 MemoryRegion
*orig
, hwaddr base
)
295 memory_region_init_alias(mr
, NULL
, name
, orig
, 0,
296 memory_region_size(orig
));
297 memory_region_add_subregion(get_system_memory(), base
, mr
);
300 static qemu_irq
get_sse_irq_in(MPS2TZMachineState
*mms
, int irqno
)
303 * Return a qemu_irq which will signal IRQ n to all CPUs in the
304 * SSE. The irqno should be as the CPU sees it, so the first
305 * external-to-the-SSE interrupt is 32.
307 MachineClass
*mc
= MACHINE_GET_CLASS(mms
);
308 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
310 assert(irqno
>= 32 && irqno
< (mmc
->numirq
+ 32));
313 * Convert from "CPU irq number" (as listed in the FPGA image
314 * documentation) to the SSE external-interrupt number.
318 if (mc
->max_cpus
> 1) {
319 return qdev_get_gpio_in(DEVICE(&mms
->cpu_irq_splitter
[irqno
]), 0);
321 return qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
), "EXP_IRQ", irqno
);
325 /* Most of the devices in the AN505 FPGA image sit behind
326 * Peripheral Protection Controllers. These data structures
327 * define the layout of which devices sit behind which PPCs.
328 * The devfn for each port is a function which creates, configures
329 * and initializes the device, returning the MemoryRegion which
330 * needs to be plugged into the downstream end of the PPC port.
332 typedef MemoryRegion
*MakeDevFn(MPS2TZMachineState
*mms
, void *opaque
,
333 const char *name
, hwaddr size
,
336 typedef struct PPCPortInfo
{
342 int irqs
[3]; /* currently no device needs more IRQ lines than this */
345 typedef struct PPCInfo
{
347 PPCPortInfo ports
[TZ_NUM_PORTS
];
350 static MemoryRegion
*make_unimp_dev(MPS2TZMachineState
*mms
,
352 const char *name
, hwaddr size
,
355 /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
356 * and return a pointer to its MemoryRegion.
358 UnimplementedDeviceState
*uds
= opaque
;
360 object_initialize_child(OBJECT(mms
), name
, uds
, TYPE_UNIMPLEMENTED_DEVICE
);
361 qdev_prop_set_string(DEVICE(uds
), "name", name
);
362 qdev_prop_set_uint64(DEVICE(uds
), "size", size
);
363 sysbus_realize(SYS_BUS_DEVICE(uds
), &error_fatal
);
364 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds
), 0);
367 static MemoryRegion
*make_uart(MPS2TZMachineState
*mms
, void *opaque
,
368 const char *name
, hwaddr size
,
371 /* The irq[] array is tx, rx, combined, in that order */
372 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
373 CMSDKAPBUART
*uart
= opaque
;
374 int i
= uart
- &mms
->uart
[0];
376 DeviceState
*orgate_dev
= DEVICE(&mms
->uart_irq_orgate
);
378 object_initialize_child(OBJECT(mms
), name
, uart
, TYPE_CMSDK_APB_UART
);
379 qdev_prop_set_chr(DEVICE(uart
), "chardev", serial_hd(i
));
380 qdev_prop_set_uint32(DEVICE(uart
), "pclk-frq", mmc
->sysclk_frq
);
381 sysbus_realize(SYS_BUS_DEVICE(uart
), &error_fatal
);
382 s
= SYS_BUS_DEVICE(uart
);
383 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
384 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
385 sysbus_connect_irq(s
, 2, qdev_get_gpio_in(orgate_dev
, i
* 2));
386 sysbus_connect_irq(s
, 3, qdev_get_gpio_in(orgate_dev
, i
* 2 + 1));
387 sysbus_connect_irq(s
, 4, get_sse_irq_in(mms
, irqs
[2]));
388 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart
), 0);
391 static MemoryRegion
*make_scc(MPS2TZMachineState
*mms
, void *opaque
,
392 const char *name
, hwaddr size
,
395 MPS2SCC
*scc
= opaque
;
397 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
400 object_initialize_child(OBJECT(mms
), "scc", scc
, TYPE_MPS2_SCC
);
401 sccdev
= DEVICE(scc
);
402 qdev_prop_set_uint32(sccdev
, "scc-cfg4", 0x2);
403 qdev_prop_set_uint32(sccdev
, "scc-aid", 0x00200008);
404 qdev_prop_set_uint32(sccdev
, "scc-id", mmc
->scc_id
);
405 qdev_prop_set_uint32(sccdev
, "len-oscclk", mmc
->len_oscclk
);
406 for (i
= 0; i
< mmc
->len_oscclk
; i
++) {
407 g_autofree
char *propname
= g_strdup_printf("oscclk[%u]", i
);
408 qdev_prop_set_uint32(sccdev
, propname
, mmc
->oscclk
[i
]);
410 sysbus_realize(SYS_BUS_DEVICE(scc
), &error_fatal
);
411 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev
), 0);
414 static MemoryRegion
*make_fpgaio(MPS2TZMachineState
*mms
, void *opaque
,
415 const char *name
, hwaddr size
,
418 MPS2FPGAIO
*fpgaio
= opaque
;
419 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
421 object_initialize_child(OBJECT(mms
), "fpgaio", fpgaio
, TYPE_MPS2_FPGAIO
);
422 qdev_prop_set_uint32(DEVICE(fpgaio
), "num-leds", mmc
->fpgaio_num_leds
);
423 qdev_prop_set_bit(DEVICE(fpgaio
), "has-switches", mmc
->fpgaio_has_switches
);
424 sysbus_realize(SYS_BUS_DEVICE(fpgaio
), &error_fatal
);
425 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio
), 0);
428 static MemoryRegion
*make_eth_dev(MPS2TZMachineState
*mms
, void *opaque
,
429 const char *name
, hwaddr size
,
433 NICInfo
*nd
= &nd_table
[0];
435 /* In hardware this is a LAN9220; the LAN9118 is software compatible
436 * except that it doesn't support the checksum-offload feature.
438 qemu_check_nic_model(nd
, "lan9118");
439 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
440 qdev_set_nic_properties(mms
->lan9118
, nd
);
442 s
= SYS_BUS_DEVICE(mms
->lan9118
);
443 sysbus_realize_and_unref(s
, &error_fatal
);
444 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
445 return sysbus_mmio_get_region(s
, 0);
448 static MemoryRegion
*make_eth_usb(MPS2TZMachineState
*mms
, void *opaque
,
449 const char *name
, hwaddr size
,
453 * The AN524 makes the ethernet and USB share a PPC port.
454 * irqs[] is the ethernet IRQ.
457 NICInfo
*nd
= &nd_table
[0];
459 memory_region_init(&mms
->eth_usb_container
, OBJECT(mms
),
460 "mps2-tz-eth-usb-container", 0x200000);
463 * In hardware this is a LAN9220; the LAN9118 is software compatible
464 * except that it doesn't support the checksum-offload feature.
466 qemu_check_nic_model(nd
, "lan9118");
467 mms
->lan9118
= qdev_new(TYPE_LAN9118
);
468 qdev_set_nic_properties(mms
->lan9118
, nd
);
470 s
= SYS_BUS_DEVICE(mms
->lan9118
);
471 sysbus_realize_and_unref(s
, &error_fatal
);
472 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
474 memory_region_add_subregion(&mms
->eth_usb_container
,
475 0, sysbus_mmio_get_region(s
, 0));
477 /* The USB OTG controller is an ISP1763; we don't have a model of it. */
478 object_initialize_child(OBJECT(mms
), "usb-otg",
479 &mms
->usb
, TYPE_UNIMPLEMENTED_DEVICE
);
480 qdev_prop_set_string(DEVICE(&mms
->usb
), "name", "usb-otg");
481 qdev_prop_set_uint64(DEVICE(&mms
->usb
), "size", 0x100000);
482 s
= SYS_BUS_DEVICE(&mms
->usb
);
483 sysbus_realize(s
, &error_fatal
);
485 memory_region_add_subregion(&mms
->eth_usb_container
,
486 0x100000, sysbus_mmio_get_region(s
, 0));
488 return &mms
->eth_usb_container
;
491 static MemoryRegion
*make_mpc(MPS2TZMachineState
*mms
, void *opaque
,
492 const char *name
, hwaddr size
,
496 int i
= mpc
- &mms
->mpc
[0];
497 MemoryRegion
*upstream
;
498 const RAMInfo
*raminfo
= find_raminfo_for_mpc(mms
, i
);
499 MemoryRegion
*ram
= mr_for_raminfo(mms
, raminfo
);
501 object_initialize_child(OBJECT(mms
), name
, mpc
, TYPE_TZ_MPC
);
502 object_property_set_link(OBJECT(mpc
), "downstream", OBJECT(ram
),
504 sysbus_realize(SYS_BUS_DEVICE(mpc
), &error_fatal
);
505 /* Map the upstream end of the MPC into system memory */
506 upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 1);
507 memory_region_add_subregion(get_system_memory(), raminfo
->base
, upstream
);
508 /* and connect its interrupt to the IoTKit */
509 qdev_connect_gpio_out_named(DEVICE(mpc
), "irq", 0,
510 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
511 "mpcexp_status", i
));
513 /* Return the register interface MR for our caller to map behind the PPC */
514 return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc
), 0);
517 static MemoryRegion
*make_dma(MPS2TZMachineState
*mms
, void *opaque
,
518 const char *name
, hwaddr size
,
521 /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */
522 PL080State
*dma
= opaque
;
523 int i
= dma
- &mms
->dma
[0];
525 char *mscname
= g_strdup_printf("%s-msc", name
);
526 TZMSC
*msc
= &mms
->msc
[i
];
527 DeviceState
*iotkitdev
= DEVICE(&mms
->iotkit
);
528 MemoryRegion
*msc_upstream
;
529 MemoryRegion
*msc_downstream
;
532 * Each DMA device is a PL081 whose transaction master interface
533 * is guarded by a Master Security Controller. The downstream end of
534 * the MSC connects to the IoTKit AHB Slave Expansion port, so the
535 * DMA devices can see all devices and memory that the CPU does.
537 object_initialize_child(OBJECT(mms
), mscname
, msc
, TYPE_TZ_MSC
);
538 msc_downstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms
->iotkit
), 0);
539 object_property_set_link(OBJECT(msc
), "downstream",
540 OBJECT(msc_downstream
), &error_fatal
);
541 object_property_set_link(OBJECT(msc
), "idau", OBJECT(mms
), &error_fatal
);
542 sysbus_realize(SYS_BUS_DEVICE(msc
), &error_fatal
);
544 qdev_connect_gpio_out_named(DEVICE(msc
), "irq", 0,
545 qdev_get_gpio_in_named(iotkitdev
,
546 "mscexp_status", i
));
547 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_clear", i
,
548 qdev_get_gpio_in_named(DEVICE(msc
),
550 qdev_connect_gpio_out_named(iotkitdev
, "mscexp_ns", i
,
551 qdev_get_gpio_in_named(DEVICE(msc
),
553 qdev_connect_gpio_out(DEVICE(&mms
->sec_resp_splitter
),
554 ARRAY_SIZE(mms
->ppc
) + i
,
555 qdev_get_gpio_in_named(DEVICE(msc
),
557 msc_upstream
= sysbus_mmio_get_region(SYS_BUS_DEVICE(msc
), 0);
559 object_initialize_child(OBJECT(mms
), name
, dma
, TYPE_PL081
);
560 object_property_set_link(OBJECT(dma
), "downstream", OBJECT(msc_upstream
),
562 sysbus_realize(SYS_BUS_DEVICE(dma
), &error_fatal
);
564 s
= SYS_BUS_DEVICE(dma
);
565 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */
566 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
567 sysbus_connect_irq(s
, 1, get_sse_irq_in(mms
, irqs
[1]));
568 sysbus_connect_irq(s
, 2, get_sse_irq_in(mms
, irqs
[2]));
571 return sysbus_mmio_get_region(s
, 0);
574 static MemoryRegion
*make_spi(MPS2TZMachineState
*mms
, void *opaque
,
575 const char *name
, hwaddr size
,
579 * The AN505 has five PL022 SPI controllers.
580 * One of these should have the LCD controller behind it; the others
581 * are connected only to the FPGA's "general purpose SPI connector"
582 * or "shield" expansion connectors.
583 * Note that if we do implement devices behind SPI, the chip select
584 * lines are set via the "MISC" register in the MPS2 FPGAIO device.
586 PL022State
*spi
= opaque
;
589 object_initialize_child(OBJECT(mms
), name
, spi
, TYPE_PL022
);
590 sysbus_realize(SYS_BUS_DEVICE(spi
), &error_fatal
);
591 s
= SYS_BUS_DEVICE(spi
);
592 sysbus_connect_irq(s
, 0, get_sse_irq_in(mms
, irqs
[0]));
593 return sysbus_mmio_get_region(s
, 0);
596 static MemoryRegion
*make_i2c(MPS2TZMachineState
*mms
, void *opaque
,
597 const char *name
, hwaddr size
,
600 ArmSbconI2CState
*i2c
= opaque
;
603 object_initialize_child(OBJECT(mms
), name
, i2c
, TYPE_ARM_SBCON_I2C
);
604 s
= SYS_BUS_DEVICE(i2c
);
605 sysbus_realize(s
, &error_fatal
);
606 return sysbus_mmio_get_region(s
, 0);
609 static MemoryRegion
*make_rtc(MPS2TZMachineState
*mms
, void *opaque
,
610 const char *name
, hwaddr size
,
613 PL031State
*pl031
= opaque
;
616 object_initialize_child(OBJECT(mms
), name
, pl031
, TYPE_PL031
);
617 s
= SYS_BUS_DEVICE(pl031
);
618 sysbus_realize(s
, &error_fatal
);
620 * The board docs don't give an IRQ number for the PL031, so
621 * presumably it is not connected.
623 return sysbus_mmio_get_region(s
, 0);
626 static void create_non_mpc_ram(MPS2TZMachineState
*mms
)
629 * Handle the RAMs which are either not behind MPCs or which are
630 * aliases to another MPC.
633 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
635 for (p
= mmc
->raminfo
; p
->name
; p
++) {
636 if (p
->flags
& IS_ALIAS
) {
637 SysBusDevice
*mpc_sbd
= SYS_BUS_DEVICE(&mms
->mpc
[p
->mpc
]);
638 MemoryRegion
*upstream
= sysbus_mmio_get_region(mpc_sbd
, 1);
639 make_ram_alias(&mms
->ram
[p
->mrindex
], p
->name
, upstream
, p
->base
);
640 } else if (p
->mpc
== -1) {
641 /* RAM not behind an MPC */
642 MemoryRegion
*mr
= mr_for_raminfo(mms
, p
);
643 memory_region_add_subregion(get_system_memory(), p
->base
, mr
);
648 static uint32_t boot_ram_size(MPS2TZMachineState
*mms
)
650 /* Return the size of the RAM block at guest address zero */
652 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
654 for (p
= mmc
->raminfo
; p
->name
; p
++) {
659 g_assert_not_reached();
662 static void mps2tz_common_init(MachineState
*machine
)
664 MPS2TZMachineState
*mms
= MPS2TZ_MACHINE(machine
);
665 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_GET_CLASS(mms
);
666 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
667 MemoryRegion
*system_memory
= get_system_memory();
668 DeviceState
*iotkitdev
;
669 DeviceState
*dev_splitter
;
674 if (strcmp(machine
->cpu_type
, mc
->default_cpu_type
) != 0) {
675 error_report("This board can only be used with CPU %s",
676 mc
->default_cpu_type
);
680 if (machine
->ram_size
!= mc
->default_ram_size
) {
681 char *sz
= size_to_str(mc
->default_ram_size
);
682 error_report("Invalid RAM size, should be %s", sz
);
687 /* These clocks don't need migration because they are fixed-frequency */
688 mms
->sysclk
= clock_new(OBJECT(machine
), "SYSCLK");
689 clock_set_hz(mms
->sysclk
, mmc
->sysclk_frq
);
690 mms
->s32kclk
= clock_new(OBJECT(machine
), "S32KCLK");
691 clock_set_hz(mms
->s32kclk
, S32KCLK_FRQ
);
693 object_initialize_child(OBJECT(machine
), TYPE_IOTKIT
, &mms
->iotkit
,
695 iotkitdev
= DEVICE(&mms
->iotkit
);
696 object_property_set_link(OBJECT(&mms
->iotkit
), "memory",
697 OBJECT(system_memory
), &error_abort
);
698 qdev_prop_set_uint32(iotkitdev
, "EXP_NUMIRQ", mmc
->numirq
);
699 qdev_connect_clock_in(iotkitdev
, "MAINCLK", mms
->sysclk
);
700 qdev_connect_clock_in(iotkitdev
, "S32KCLK", mms
->s32kclk
);
701 sysbus_realize(SYS_BUS_DEVICE(&mms
->iotkit
), &error_fatal
);
704 * If this board has more than one CPU, then we need to create splitters
705 * to feed the IRQ inputs for each CPU in the SSE from each device in the
706 * board. If there is only one CPU, we can just wire the device IRQ
707 * directly to the SSE's IRQ input.
709 assert(mmc
->numirq
<= MPS2TZ_NUMIRQ_MAX
);
710 if (mc
->max_cpus
> 1) {
711 for (i
= 0; i
< mmc
->numirq
; i
++) {
712 char *name
= g_strdup_printf("mps2-irq-splitter%d", i
);
713 SplitIRQ
*splitter
= &mms
->cpu_irq_splitter
[i
];
715 object_initialize_child_with_props(OBJECT(machine
), name
,
716 splitter
, sizeof(*splitter
),
717 TYPE_SPLIT_IRQ
, &error_fatal
,
721 object_property_set_int(OBJECT(splitter
), "num-lines", 2,
723 qdev_realize(DEVICE(splitter
), NULL
, &error_fatal
);
724 qdev_connect_gpio_out(DEVICE(splitter
), 0,
725 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
727 qdev_connect_gpio_out(DEVICE(splitter
), 1,
728 qdev_get_gpio_in_named(DEVICE(&mms
->iotkit
),
733 /* The sec_resp_cfg output from the IoTKit must be split into multiple
734 * lines, one for each of the PPCs we create here, plus one per MSC.
736 object_initialize_child(OBJECT(machine
), "sec-resp-splitter",
737 &mms
->sec_resp_splitter
, TYPE_SPLIT_IRQ
);
738 object_property_set_int(OBJECT(&mms
->sec_resp_splitter
), "num-lines",
739 ARRAY_SIZE(mms
->ppc
) + ARRAY_SIZE(mms
->msc
),
741 qdev_realize(DEVICE(&mms
->sec_resp_splitter
), NULL
, &error_fatal
);
742 dev_splitter
= DEVICE(&mms
->sec_resp_splitter
);
743 qdev_connect_gpio_out_named(iotkitdev
, "sec_resp_cfg", 0,
744 qdev_get_gpio_in(dev_splitter
, 0));
747 * The IoTKit sets up much of the memory layout, including
748 * the aliases between secure and non-secure regions in the
749 * address space, and also most of the devices in the system.
750 * The FPGA itself contains various RAMs and some additional devices.
751 * The FPGA images have an odd combination of different RAMs,
752 * because in hardware they are different implementations and
753 * connected to different buses, giving varying performance/size
754 * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
755 * call the largest lump our "system memory".
759 * The overflow IRQs for all UARTs are ORed together.
760 * Tx, Rx and "combined" IRQs are sent to the NVIC separately.
761 * Create the OR gate for this: it has one input for the TX overflow
762 * and one for the RX overflow for each UART we might have.
763 * (If the board has fewer than the maximum possible number of UARTs
764 * those inputs are never wired up and are treated as always-zero.)
766 object_initialize_child(OBJECT(mms
), "uart-irq-orgate",
767 &mms
->uart_irq_orgate
, TYPE_OR_IRQ
);
768 object_property_set_int(OBJECT(&mms
->uart_irq_orgate
), "num-lines",
769 2 * ARRAY_SIZE(mms
->uart
),
771 qdev_realize(DEVICE(&mms
->uart_irq_orgate
), NULL
, &error_fatal
);
772 qdev_connect_gpio_out(DEVICE(&mms
->uart_irq_orgate
), 0,
773 get_sse_irq_in(mms
, 47));
775 /* Most of the devices in the FPGA are behind Peripheral Protection
776 * Controllers. The required order for initializing things is:
777 * + initialize the PPC
778 * + initialize, configure and realize downstream devices
779 * + connect downstream device MemoryRegions to the PPC
781 * + map the PPC's MemoryRegions to the places in the address map
782 * where the downstream devices should appear
783 * + wire up the PPC's control lines to the IoTKit object
786 const PPCInfo an505_ppcs
[] = { {
787 .name
= "apb_ppcexp0",
789 { "ssram-0-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
790 { "ssram-1-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
791 { "ssram-2-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
794 .name
= "apb_ppcexp1",
796 { "spi0", make_spi
, &mms
->spi
[0], 0x40205000, 0x1000, { 51 } },
797 { "spi1", make_spi
, &mms
->spi
[1], 0x40206000, 0x1000, { 52 } },
798 { "spi2", make_spi
, &mms
->spi
[2], 0x40209000, 0x1000, { 53 } },
799 { "spi3", make_spi
, &mms
->spi
[3], 0x4020a000, 0x1000, { 54 } },
800 { "spi4", make_spi
, &mms
->spi
[4], 0x4020b000, 0x1000, { 55 } },
801 { "uart0", make_uart
, &mms
->uart
[0], 0x40200000, 0x1000, { 32, 33, 42 } },
802 { "uart1", make_uart
, &mms
->uart
[1], 0x40201000, 0x1000, { 34, 35, 43 } },
803 { "uart2", make_uart
, &mms
->uart
[2], 0x40202000, 0x1000, { 36, 37, 44 } },
804 { "uart3", make_uart
, &mms
->uart
[3], 0x40203000, 0x1000, { 38, 39, 45 } },
805 { "uart4", make_uart
, &mms
->uart
[4], 0x40204000, 0x1000, { 40, 41, 46 } },
806 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x40207000, 0x1000 },
807 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x40208000, 0x1000 },
808 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x4020c000, 0x1000 },
809 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x4020d000, 0x1000 },
812 .name
= "apb_ppcexp2",
814 { "scc", make_scc
, &mms
->scc
, 0x40300000, 0x1000 },
815 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
816 0x40301000, 0x1000 },
817 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x40302000, 0x1000 },
820 .name
= "ahb_ppcexp0",
822 { "gfx", make_unimp_dev
, &mms
->gfx
, 0x41000000, 0x140000 },
823 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x40100000, 0x1000 },
824 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x40101000, 0x1000 },
825 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x40102000, 0x1000 },
826 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x40103000, 0x1000 },
827 { "eth", make_eth_dev
, NULL
, 0x42000000, 0x100000, { 48 } },
830 .name
= "ahb_ppcexp1",
832 { "dma0", make_dma
, &mms
->dma
[0], 0x40110000, 0x1000, { 58, 56, 57 } },
833 { "dma1", make_dma
, &mms
->dma
[1], 0x40111000, 0x1000, { 61, 59, 60 } },
834 { "dma2", make_dma
, &mms
->dma
[2], 0x40112000, 0x1000, { 64, 62, 63 } },
835 { "dma3", make_dma
, &mms
->dma
[3], 0x40113000, 0x1000, { 67, 65, 66 } },
840 const PPCInfo an524_ppcs
[] = { {
841 .name
= "apb_ppcexp0",
843 { "bram-mpc", make_mpc
, &mms
->mpc
[0], 0x58007000, 0x1000 },
844 { "qspi-mpc", make_mpc
, &mms
->mpc
[1], 0x58008000, 0x1000 },
845 { "ddr-mpc", make_mpc
, &mms
->mpc
[2], 0x58009000, 0x1000 },
848 .name
= "apb_ppcexp1",
850 { "i2c0", make_i2c
, &mms
->i2c
[0], 0x41200000, 0x1000 },
851 { "i2c1", make_i2c
, &mms
->i2c
[1], 0x41201000, 0x1000 },
852 { "spi0", make_spi
, &mms
->spi
[0], 0x41202000, 0x1000, { 52 } },
853 { "spi1", make_spi
, &mms
->spi
[1], 0x41203000, 0x1000, { 53 } },
854 { "spi2", make_spi
, &mms
->spi
[2], 0x41204000, 0x1000, { 54 } },
855 { "i2c2", make_i2c
, &mms
->i2c
[2], 0x41205000, 0x1000 },
856 { "i2c3", make_i2c
, &mms
->i2c
[3], 0x41206000, 0x1000 },
857 { /* port 7 reserved */ },
858 { "i2c4", make_i2c
, &mms
->i2c
[4], 0x41208000, 0x1000 },
861 .name
= "apb_ppcexp2",
863 { "scc", make_scc
, &mms
->scc
, 0x41300000, 0x1000 },
864 { "i2s-audio", make_unimp_dev
, &mms
->i2s_audio
,
865 0x41301000, 0x1000 },
866 { "fpgaio", make_fpgaio
, &mms
->fpgaio
, 0x41302000, 0x1000 },
867 { "uart0", make_uart
, &mms
->uart
[0], 0x41303000, 0x1000, { 32, 33, 42 } },
868 { "uart1", make_uart
, &mms
->uart
[1], 0x41304000, 0x1000, { 34, 35, 43 } },
869 { "uart2", make_uart
, &mms
->uart
[2], 0x41305000, 0x1000, { 36, 37, 44 } },
870 { "uart3", make_uart
, &mms
->uart
[3], 0x41306000, 0x1000, { 38, 39, 45 } },
871 { "uart4", make_uart
, &mms
->uart
[4], 0x41307000, 0x1000, { 40, 41, 46 } },
872 { "uart5", make_uart
, &mms
->uart
[5], 0x41308000, 0x1000, { 124, 125, 126 } },
874 { /* port 9 reserved */ },
875 { "clcd", make_unimp_dev
, &mms
->cldc
, 0x4130a000, 0x1000 },
876 { "rtc", make_rtc
, &mms
->rtc
, 0x4130b000, 0x1000 },
879 .name
= "ahb_ppcexp0",
881 { "gpio0", make_unimp_dev
, &mms
->gpio
[0], 0x41100000, 0x1000 },
882 { "gpio1", make_unimp_dev
, &mms
->gpio
[1], 0x41101000, 0x1000 },
883 { "gpio2", make_unimp_dev
, &mms
->gpio
[2], 0x41102000, 0x1000 },
884 { "gpio3", make_unimp_dev
, &mms
->gpio
[3], 0x41103000, 0x1000 },
885 { "eth-usb", make_eth_usb
, NULL
, 0x41400000, 0x200000, { 48 } },
890 switch (mmc
->fpga_type
) {
894 num_ppcs
= ARRAY_SIZE(an505_ppcs
);
898 num_ppcs
= ARRAY_SIZE(an524_ppcs
);
901 g_assert_not_reached();
904 for (i
= 0; i
< num_ppcs
; i
++) {
905 const PPCInfo
*ppcinfo
= &ppcs
[i
];
906 TZPPC
*ppc
= &mms
->ppc
[i
];
911 object_initialize_child(OBJECT(machine
), ppcinfo
->name
, ppc
,
913 ppcdev
= DEVICE(ppc
);
915 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
916 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
924 mr
= pinfo
->devfn(mms
, pinfo
->opaque
, pinfo
->name
, pinfo
->size
,
926 portname
= g_strdup_printf("port[%d]", port
);
927 object_property_set_link(OBJECT(ppc
), portname
, OBJECT(mr
),
932 sysbus_realize(SYS_BUS_DEVICE(ppc
), &error_fatal
);
934 for (port
= 0; port
< TZ_NUM_PORTS
; port
++) {
935 const PPCPortInfo
*pinfo
= &ppcinfo
->ports
[port
];
940 sysbus_mmio_map(SYS_BUS_DEVICE(ppc
), port
, pinfo
->addr
);
942 gpioname
= g_strdup_printf("%s_nonsec", ppcinfo
->name
);
943 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
944 qdev_get_gpio_in_named(ppcdev
,
948 gpioname
= g_strdup_printf("%s_ap", ppcinfo
->name
);
949 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, port
,
950 qdev_get_gpio_in_named(ppcdev
,
955 gpioname
= g_strdup_printf("%s_irq_enable", ppcinfo
->name
);
956 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
957 qdev_get_gpio_in_named(ppcdev
,
960 gpioname
= g_strdup_printf("%s_irq_clear", ppcinfo
->name
);
961 qdev_connect_gpio_out_named(iotkitdev
, gpioname
, 0,
962 qdev_get_gpio_in_named(ppcdev
,
965 gpioname
= g_strdup_printf("%s_irq_status", ppcinfo
->name
);
966 qdev_connect_gpio_out_named(ppcdev
, "irq", 0,
967 qdev_get_gpio_in_named(iotkitdev
,
971 qdev_connect_gpio_out(dev_splitter
, i
,
972 qdev_get_gpio_in_named(ppcdev
,
976 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
978 create_non_mpc_ram(mms
);
980 armv7m_load_kernel(ARM_CPU(first_cpu
), machine
->kernel_filename
,
984 static void mps2_tz_idau_check(IDAUInterface
*ii
, uint32_t address
,
985 int *iregion
, bool *exempt
, bool *ns
, bool *nsc
)
988 * The MPS2 TZ FPGA images have IDAUs in them which are connected to
989 * the Master Security Controllers. Thes have the same logic as
990 * is used by the IoTKit for the IDAU connected to the CPU, except
991 * that MSCs don't care about the NSC attribute.
993 int region
= extract32(address
, 28, 4);
997 /* 0xe0000000..0xe00fffff and 0xf0000000..0xf00fffff are exempt */
998 *exempt
= (address
& 0xeff00000) == 0xe0000000;
1002 static void mps2tz_class_init(ObjectClass
*oc
, void *data
)
1004 MachineClass
*mc
= MACHINE_CLASS(oc
);
1005 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_CLASS(oc
);
1007 mc
->init
= mps2tz_common_init
;
1008 iic
->check
= mps2_tz_idau_check
;
1011 static void mps2tz_set_default_ram_info(MPS2TZMachineClass
*mmc
)
1014 * Set mc->default_ram_size and default_ram_id from the
1015 * information in mmc->raminfo.
1017 MachineClass
*mc
= MACHINE_CLASS(mmc
);
1020 for (p
= mmc
->raminfo
; p
->name
; p
++) {
1021 if (p
->mrindex
< 0) {
1022 /* Found the entry for "system memory" */
1023 mc
->default_ram_size
= p
->size
;
1024 mc
->default_ram_id
= p
->name
;
1028 g_assert_not_reached();
1031 static void mps2tz_an505_class_init(ObjectClass
*oc
, void *data
)
1033 MachineClass
*mc
= MACHINE_CLASS(oc
);
1034 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1036 mc
->desc
= "ARM MPS2 with AN505 FPGA image for Cortex-M33";
1037 mc
->default_cpus
= 1;
1038 mc
->min_cpus
= mc
->default_cpus
;
1039 mc
->max_cpus
= mc
->default_cpus
;
1040 mmc
->fpga_type
= FPGA_AN505
;
1041 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1042 mmc
->scc_id
= 0x41045050;
1043 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1044 mmc
->oscclk
= an505_oscclk
;
1045 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1046 mmc
->fpgaio_num_leds
= 2;
1047 mmc
->fpgaio_has_switches
= false;
1049 mmc
->raminfo
= an505_raminfo
;
1050 mmc
->armsse_type
= TYPE_IOTKIT
;
1051 mps2tz_set_default_ram_info(mmc
);
1054 static void mps2tz_an521_class_init(ObjectClass
*oc
, void *data
)
1056 MachineClass
*mc
= MACHINE_CLASS(oc
);
1057 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1059 mc
->desc
= "ARM MPS2 with AN521 FPGA image for dual Cortex-M33";
1060 mc
->default_cpus
= 2;
1061 mc
->min_cpus
= mc
->default_cpus
;
1062 mc
->max_cpus
= mc
->default_cpus
;
1063 mmc
->fpga_type
= FPGA_AN521
;
1064 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1065 mmc
->scc_id
= 0x41045210;
1066 mmc
->sysclk_frq
= 20 * 1000 * 1000; /* 20MHz */
1067 mmc
->oscclk
= an505_oscclk
; /* AN521 is the same as AN505 here */
1068 mmc
->len_oscclk
= ARRAY_SIZE(an505_oscclk
);
1069 mmc
->fpgaio_num_leds
= 2;
1070 mmc
->fpgaio_has_switches
= false;
1072 mmc
->raminfo
= an505_raminfo
; /* AN521 is the same as AN505 here */
1073 mmc
->armsse_type
= TYPE_SSE200
;
1074 mps2tz_set_default_ram_info(mmc
);
1077 static void mps3tz_an524_class_init(ObjectClass
*oc
, void *data
)
1079 MachineClass
*mc
= MACHINE_CLASS(oc
);
1080 MPS2TZMachineClass
*mmc
= MPS2TZ_MACHINE_CLASS(oc
);
1082 mc
->desc
= "ARM MPS3 with AN524 FPGA image for dual Cortex-M33";
1083 mc
->default_cpus
= 2;
1084 mc
->min_cpus
= mc
->default_cpus
;
1085 mc
->max_cpus
= mc
->default_cpus
;
1086 mmc
->fpga_type
= FPGA_AN524
;
1087 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("cortex-m33");
1088 mmc
->scc_id
= 0x41045240;
1089 mmc
->sysclk_frq
= 32 * 1000 * 1000; /* 32MHz */
1090 mmc
->oscclk
= an524_oscclk
;
1091 mmc
->len_oscclk
= ARRAY_SIZE(an524_oscclk
);
1092 mmc
->fpgaio_num_leds
= 10;
1093 mmc
->fpgaio_has_switches
= true;
1095 mmc
->raminfo
= an524_raminfo
;
1096 mmc
->armsse_type
= TYPE_SSE200
;
1097 mps2tz_set_default_ram_info(mmc
);
1100 static const TypeInfo mps2tz_info
= {
1101 .name
= TYPE_MPS2TZ_MACHINE
,
1102 .parent
= TYPE_MACHINE
,
1104 .instance_size
= sizeof(MPS2TZMachineState
),
1105 .class_size
= sizeof(MPS2TZMachineClass
),
1106 .class_init
= mps2tz_class_init
,
1107 .interfaces
= (InterfaceInfo
[]) {
1108 { TYPE_IDAU_INTERFACE
},
1113 static const TypeInfo mps2tz_an505_info
= {
1114 .name
= TYPE_MPS2TZ_AN505_MACHINE
,
1115 .parent
= TYPE_MPS2TZ_MACHINE
,
1116 .class_init
= mps2tz_an505_class_init
,
1119 static const TypeInfo mps2tz_an521_info
= {
1120 .name
= TYPE_MPS2TZ_AN521_MACHINE
,
1121 .parent
= TYPE_MPS2TZ_MACHINE
,
1122 .class_init
= mps2tz_an521_class_init
,
1125 static const TypeInfo mps3tz_an524_info
= {
1126 .name
= TYPE_MPS3TZ_AN524_MACHINE
,
1127 .parent
= TYPE_MPS2TZ_MACHINE
,
1128 .class_init
= mps3tz_an524_class_init
,
1131 static void mps2tz_machine_init(void)
1133 type_register_static(&mps2tz_info
);
1134 type_register_static(&mps2tz_an505_info
);
1135 type_register_static(&mps2tz_an521_info
);
1136 type_register_static(&mps3tz_an524_info
);
1139 type_init(mps2tz_machine_init
);