4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
15 #include "hw/arm/arm.h"
16 #include "hw/arm/linux-boot-if.h"
17 #include "sysemu/kvm.h"
18 #include "sysemu/sysemu.h"
19 #include "sysemu/numa.h"
20 #include "hw/boards.h"
21 #include "hw/loader.h"
23 #include "sysemu/device_tree.h"
24 #include "qemu/config-file.h"
25 #include "qemu/option.h"
26 #include "exec/address-spaces.h"
28 /* Kernel boot protocol is specified in the kernel docs
29 * Documentation/arm/Booting and Documentation/arm64/booting.txt
30 * They have different preferred image load offsets from system RAM base.
32 #define KERNEL_ARGS_ADDR 0x100
33 #define KERNEL_LOAD_ADDR 0x00010000
34 #define KERNEL64_LOAD_ADDR 0x00080000
36 #define ARM64_TEXT_OFFSET_OFFSET 8
37 #define ARM64_MAGIC_OFFSET 56
40 FIXUP_NONE
= 0, /* do nothing */
41 FIXUP_TERMINATOR
, /* end of insns */
42 FIXUP_BOARDID
, /* overwrite with board ID number */
43 FIXUP_BOARD_SETUP
, /* overwrite with board specific setup code address */
44 FIXUP_ARGPTR
, /* overwrite with pointer to kernel args */
45 FIXUP_ENTRYPOINT
, /* overwrite with kernel entry point */
46 FIXUP_GIC_CPU_IF
, /* overwrite with GIC CPU interface address */
47 FIXUP_BOOTREG
, /* overwrite with boot register address */
48 FIXUP_DSB
, /* overwrite with correct DSB insn for cpu */
52 typedef struct ARMInsnFixup
{
57 static const ARMInsnFixup bootloader_aarch64
[] = {
58 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
59 { 0xaa1f03e1 }, /* mov x1, xzr */
60 { 0xaa1f03e2 }, /* mov x2, xzr */
61 { 0xaa1f03e3 }, /* mov x3, xzr */
62 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
63 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
64 { 0, FIXUP_ARGPTR
}, /* arg: .word @DTB Lower 32-bits */
65 { 0 }, /* .word @DTB Higher 32-bits */
66 { 0, FIXUP_ENTRYPOINT
}, /* entry: .word @Kernel Entry Lower 32-bits */
67 { 0 }, /* .word @Kernel Entry Higher 32-bits */
68 { 0, FIXUP_TERMINATOR
}
71 /* A very small bootloader: call the board-setup code (if needed),
72 * set r0-r2, then jump to the kernel.
73 * If we're not calling boot setup code then we don't copy across
74 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.
77 static const ARMInsnFixup bootloader
[] = {
78 { 0xe28fe004 }, /* add lr, pc, #4 */
79 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */
80 { 0, FIXUP_BOARD_SETUP
},
81 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
82 { 0xe3a00000 }, /* mov r0, #0 */
83 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
84 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
85 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
88 { 0, FIXUP_ENTRYPOINT
},
89 { 0, FIXUP_TERMINATOR
}
92 /* Handling for secondary CPU boot in a multicore system.
93 * Unlike the uniprocessor/primary CPU boot, this is platform
94 * dependent. The default code here is based on the secondary
95 * CPU boot protocol used on realview/vexpress boards, with
96 * some parameterisation to increase its flexibility.
97 * QEMU platform models for which this code is not appropriate
98 * should override write_secondary_boot and secondary_cpu_reset_hook
101 * This code enables the interrupt controllers for the secondary
102 * CPUs and then puts all the secondary CPUs into a loop waiting
103 * for an interprocessor interrupt and polling a configurable
104 * location for the kernel secondary CPU entry point.
106 #define DSB_INSN 0xf57ff04f
107 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
109 static const ARMInsnFixup smpboot
[] = {
110 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
111 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
112 { 0xe3a01001 }, /* mov r1, #1 */
113 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
114 { 0xe3a010ff }, /* mov r1, #0xff */
115 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
116 { 0, FIXUP_DSB
}, /* dsb */
117 { 0xe320f003 }, /* wfi */
118 { 0xe5901000 }, /* ldr r1, [r0] */
119 { 0xe1110001 }, /* tst r1, r1 */
120 { 0x0afffffb }, /* beq <wfi> */
121 { 0xe12fff11 }, /* bx r1 */
122 { 0, FIXUP_GIC_CPU_IF
}, /* gic_cpu_if: .word 0x.... */
123 { 0, FIXUP_BOOTREG
}, /* bootreg_addr: .word 0x.... */
124 { 0, FIXUP_TERMINATOR
}
127 static void write_bootloader(const char *name
, hwaddr addr
,
128 const ARMInsnFixup
*insns
, uint32_t *fixupcontext
)
130 /* Fix up the specified bootloader fragment and write it into
131 * guest memory using rom_add_blob_fixed(). fixupcontext is
132 * an array giving the values to write in for the fixup types
133 * which write a value into the code array.
139 while (insns
[len
].fixup
!= FIXUP_TERMINATOR
) {
143 code
= g_new0(uint32_t, len
);
145 for (i
= 0; i
< len
; i
++) {
146 uint32_t insn
= insns
[i
].insn
;
147 FixupType fixup
= insns
[i
].fixup
;
153 case FIXUP_BOARD_SETUP
:
155 case FIXUP_ENTRYPOINT
:
156 case FIXUP_GIC_CPU_IF
:
159 insn
= fixupcontext
[fixup
];
164 code
[i
] = tswap32(insn
);
167 rom_add_blob_fixed(name
, code
, len
* sizeof(uint32_t), addr
);
172 static void default_write_secondary(ARMCPU
*cpu
,
173 const struct arm_boot_info
*info
)
175 uint32_t fixupcontext
[FIXUP_MAX
];
177 fixupcontext
[FIXUP_GIC_CPU_IF
] = info
->gic_cpu_if_addr
;
178 fixupcontext
[FIXUP_BOOTREG
] = info
->smp_bootreg_addr
;
179 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
180 fixupcontext
[FIXUP_DSB
] = DSB_INSN
;
182 fixupcontext
[FIXUP_DSB
] = CP15_DSB_INSN
;
185 write_bootloader("smpboot", info
->smp_loader_start
,
186 smpboot
, fixupcontext
);
189 void arm_write_secure_board_setup_dummy_smc(ARMCPU
*cpu
,
190 const struct arm_boot_info
*info
,
194 uint32_t mvbar_blob
[] = {
195 /* mvbar_addr: secure monitor vectors
196 * Default unimplemented and unused vectors to spin. Makes it
197 * easier to debug (as opposed to the CPU running away).
199 0xeafffffe, /* (spin) */
200 0xeafffffe, /* (spin) */
201 0xe1b0f00e, /* movs pc, lr ;SMC exception return */
202 0xeafffffe, /* (spin) */
203 0xeafffffe, /* (spin) */
204 0xeafffffe, /* (spin) */
205 0xeafffffe, /* (spin) */
206 0xeafffffe, /* (spin) */
208 uint32_t board_setup_blob
[] = {
209 /* board setup addr */
210 0xe3a00e00 + (mvbar_addr
>> 4), /* mov r0, #mvbar_addr */
211 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
212 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
213 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */
214 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */
215 0xe1a0100e, /* mov r1, lr ;save LR across SMC */
216 0xe1600070, /* smc #0 ;call monitor to flush SCR */
217 0xe1a0f001, /* mov pc, r1 ;return */
220 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */
221 assert((mvbar_addr
& 0x1f) == 0 && (mvbar_addr
>> 4) < 0x100);
223 /* check that these blobs don't overlap */
224 assert((mvbar_addr
+ sizeof(mvbar_blob
) <= info
->board_setup_addr
)
225 || (info
->board_setup_addr
+ sizeof(board_setup_blob
) <= mvbar_addr
));
227 for (n
= 0; n
< ARRAY_SIZE(mvbar_blob
); n
++) {
228 mvbar_blob
[n
] = tswap32(mvbar_blob
[n
]);
230 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob
, sizeof(mvbar_blob
),
233 for (n
= 0; n
< ARRAY_SIZE(board_setup_blob
); n
++) {
234 board_setup_blob
[n
] = tswap32(board_setup_blob
[n
]);
236 rom_add_blob_fixed("board-setup", board_setup_blob
,
237 sizeof(board_setup_blob
), info
->board_setup_addr
);
240 static void default_reset_secondary(ARMCPU
*cpu
,
241 const struct arm_boot_info
*info
)
243 CPUState
*cs
= CPU(cpu
);
245 address_space_stl_notdirty(&address_space_memory
, info
->smp_bootreg_addr
,
246 0, MEMTXATTRS_UNSPECIFIED
, NULL
);
247 cpu_set_pc(cs
, info
->smp_loader_start
);
250 static inline bool have_dtb(const struct arm_boot_info
*info
)
252 return info
->dtb_filename
|| info
->get_dtb
;
255 #define WRITE_WORD(p, value) do { \
256 address_space_stl_notdirty(&address_space_memory, p, value, \
257 MEMTXATTRS_UNSPECIFIED, NULL); \
261 static void set_kernel_args(const struct arm_boot_info
*info
)
263 int initrd_size
= info
->initrd_size
;
264 hwaddr base
= info
->loader_start
;
267 p
= base
+ KERNEL_ARGS_ADDR
;
270 WRITE_WORD(p
, 0x54410001);
272 WRITE_WORD(p
, 0x1000);
275 /* TODO: handle multiple chips on one ATAG list */
277 WRITE_WORD(p
, 0x54410002);
278 WRITE_WORD(p
, info
->ram_size
);
279 WRITE_WORD(p
, info
->loader_start
);
283 WRITE_WORD(p
, 0x54420005);
284 WRITE_WORD(p
, info
->initrd_start
);
285 WRITE_WORD(p
, initrd_size
);
287 if (info
->kernel_cmdline
&& *info
->kernel_cmdline
) {
291 cmdline_size
= strlen(info
->kernel_cmdline
);
292 cpu_physical_memory_write(p
+ 8, info
->kernel_cmdline
,
294 cmdline_size
= (cmdline_size
>> 2) + 1;
295 WRITE_WORD(p
, cmdline_size
+ 2);
296 WRITE_WORD(p
, 0x54410009);
297 p
+= cmdline_size
* 4;
299 if (info
->atag_board
) {
302 uint8_t atag_board_buf
[0x1000];
304 atag_board_len
= (info
->atag_board(info
, atag_board_buf
) + 3) & ~3;
305 WRITE_WORD(p
, (atag_board_len
+ 8) >> 2);
306 WRITE_WORD(p
, 0x414f4d50);
307 cpu_physical_memory_write(p
, atag_board_buf
, atag_board_len
);
315 static void set_kernel_args_old(const struct arm_boot_info
*info
)
319 int initrd_size
= info
->initrd_size
;
320 hwaddr base
= info
->loader_start
;
322 /* see linux/include/asm-arm/setup.h */
323 p
= base
+ KERNEL_ARGS_ADDR
;
327 WRITE_WORD(p
, info
->ram_size
/ 4096);
330 #define FLAG_READONLY 1
331 #define FLAG_RDLOAD 4
332 #define FLAG_RDPROMPT 8
334 WRITE_WORD(p
, FLAG_READONLY
| FLAG_RDLOAD
| FLAG_RDPROMPT
);
336 WRITE_WORD(p
, (31 << 8) | 0); /* /dev/mtdblock0 */
345 /* memc_control_reg */
347 /* unsigned char sounddefault */
348 /* unsigned char adfsdrives */
349 /* unsigned char bytes_per_char_h */
350 /* unsigned char bytes_per_char_v */
352 /* pages_in_bank[4] */
361 WRITE_WORD(p
, info
->initrd_start
);
366 WRITE_WORD(p
, initrd_size
);
371 /* system_serial_low */
373 /* system_serial_high */
377 /* zero unused fields */
378 while (p
< base
+ KERNEL_ARGS_ADDR
+ 256 + 1024) {
381 s
= info
->kernel_cmdline
;
383 cpu_physical_memory_write(p
, s
, strlen(s
) + 1);
389 static void fdt_add_psci_node(void *fdt
)
391 uint32_t cpu_suspend_fn
;
395 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
396 const char *psci_method
;
397 int64_t psci_conduit
;
399 psci_conduit
= object_property_get_int(OBJECT(armcpu
),
402 switch (psci_conduit
) {
403 case QEMU_PSCI_CONDUIT_DISABLED
:
405 case QEMU_PSCI_CONDUIT_HVC
:
408 case QEMU_PSCI_CONDUIT_SMC
:
412 g_assert_not_reached();
415 qemu_fdt_add_subnode(fdt
, "/psci");
416 if (armcpu
->psci_version
== 2) {
417 const char comp
[] = "arm,psci-0.2\0arm,psci";
418 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
420 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
421 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
422 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
423 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
424 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
426 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
427 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
428 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
431 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
433 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
434 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
435 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
436 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
439 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
440 * to the instruction that should be used to invoke PSCI functions.
441 * However, the device tree binding uses 'method' instead, so that is
442 * what we should use here.
444 qemu_fdt_setprop_string(fdt
, "/psci", "method", psci_method
);
446 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
447 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
448 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
449 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
453 * load_dtb() - load a device tree binary image into memory
454 * @addr: the address to load the image at
455 * @binfo: struct describing the boot environment
456 * @addr_limit: upper limit of the available memory area at @addr
458 * Load a device tree supplied by the machine or by the user with the
459 * '-dtb' command line option, and put it at offset @addr in target
462 * If @addr_limit contains a meaningful value (i.e., it is strictly greater
463 * than @addr), the device tree is only loaded if its size does not exceed
466 * Returns: the size of the device tree image on success,
467 * 0 if the image size exceeds the limit,
470 * Note: Must not be called unless have_dtb(binfo) is true.
472 static int load_dtb(hwaddr addr
, const struct arm_boot_info
*binfo
,
477 uint32_t acells
, scells
;
480 hwaddr mem_base
, mem_len
;
482 if (binfo
->dtb_filename
) {
484 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, binfo
->dtb_filename
);
486 fprintf(stderr
, "Couldn't open dtb file %s\n", binfo
->dtb_filename
);
490 fdt
= load_device_tree(filename
, &size
);
492 fprintf(stderr
, "Couldn't open dtb file %s\n", filename
);
498 fdt
= binfo
->get_dtb(binfo
, &size
);
500 fprintf(stderr
, "Board was unable to create a dtb blob\n");
505 if (addr_limit
> addr
&& size
> (addr_limit
- addr
)) {
506 /* Installing the device tree blob at addr would exceed addr_limit.
507 * Whether this constitutes failure is up to the caller to decide,
508 * so just return 0 as size, i.e., no error.
514 acells
= qemu_fdt_getprop_cell(fdt
, "/", "#address-cells",
516 scells
= qemu_fdt_getprop_cell(fdt
, "/", "#size-cells",
518 if (acells
== 0 || scells
== 0) {
519 fprintf(stderr
, "dtb file invalid (#address-cells or #size-cells 0)\n");
523 if (scells
< 2 && binfo
->ram_size
>= (1ULL << 32)) {
524 /* This is user error so deserves a friendlier error message
525 * than the failure of setprop_sized_cells would provide
527 fprintf(stderr
, "qemu: dtb file not compatible with "
532 if (nb_numa_nodes
> 0) {
534 * Turn the /memory node created before into a NOP node, then create
535 * /memory@addr nodes for all numa nodes respectively.
537 qemu_fdt_nop_node(fdt
, "/memory");
538 mem_base
= binfo
->loader_start
;
539 for (i
= 0; i
< nb_numa_nodes
; i
++) {
540 mem_len
= numa_info
[i
].node_mem
;
541 nodename
= g_strdup_printf("/memory@%" PRIx64
, mem_base
);
542 qemu_fdt_add_subnode(fdt
, nodename
);
543 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
544 rc
= qemu_fdt_setprop_sized_cells(fdt
, nodename
, "reg",
548 fprintf(stderr
, "couldn't set %s/reg for node %d\n", nodename
,
553 qemu_fdt_setprop_cell(fdt
, nodename
, "numa-node-id", i
);
560 rc
= fdt_path_offset(fdt
, "/memory");
562 qemu_fdt_add_subnode(fdt
, "/memory");
565 if (!qemu_fdt_getprop(fdt
, "/memory", "device_type", NULL
, &err
)) {
566 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
569 rc
= qemu_fdt_setprop_sized_cells(fdt
, "/memory", "reg",
570 acells
, binfo
->loader_start
,
571 scells
, binfo
->ram_size
);
573 fprintf(stderr
, "couldn't set /memory/reg\n");
578 rc
= fdt_path_offset(fdt
, "/chosen");
580 qemu_fdt_add_subnode(fdt
, "/chosen");
583 if (binfo
->kernel_cmdline
&& *binfo
->kernel_cmdline
) {
584 rc
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
585 binfo
->kernel_cmdline
);
587 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
592 if (binfo
->initrd_size
) {
593 rc
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
594 binfo
->initrd_start
);
596 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
600 rc
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
601 binfo
->initrd_start
+ binfo
->initrd_size
);
603 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
608 fdt_add_psci_node(fdt
);
610 if (binfo
->modify_dtb
) {
611 binfo
->modify_dtb(binfo
, fdt
);
614 qemu_fdt_dumpdtb(fdt
, size
);
616 /* Put the DTB into the memory map as a ROM image: this will ensure
617 * the DTB is copied again upon reset, even if addr points into RAM.
619 rom_add_blob_fixed("dtb", fdt
, size
, addr
);
630 static void do_cpu_reset(void *opaque
)
632 ARMCPU
*cpu
= opaque
;
633 CPUState
*cs
= CPU(cpu
);
634 CPUARMState
*env
= &cpu
->env
;
635 const struct arm_boot_info
*info
= env
->boot_info
;
639 if (!info
->is_linux
) {
641 /* Jump to the entry point. */
642 uint64_t entry
= info
->entry
;
644 switch (info
->endianness
) {
645 case ARM_ENDIANNESS_LE
:
646 env
->cp15
.sctlr_el
[1] &= ~SCTLR_E0E
;
647 for (i
= 1; i
< 4; ++i
) {
648 env
->cp15
.sctlr_el
[i
] &= ~SCTLR_EE
;
650 env
->uncached_cpsr
&= ~CPSR_E
;
652 case ARM_ENDIANNESS_BE8
:
653 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
654 for (i
= 1; i
< 4; ++i
) {
655 env
->cp15
.sctlr_el
[i
] |= SCTLR_EE
;
657 env
->uncached_cpsr
|= CPSR_E
;
659 case ARM_ENDIANNESS_BE32
:
660 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
662 case ARM_ENDIANNESS_UNKNOWN
:
663 break; /* Board's decision */
665 g_assert_not_reached();
669 env
->thumb
= info
->entry
& 1;
672 cpu_set_pc(cs
, entry
);
674 /* If we are booting Linux then we need to check whether we are
675 * booting into secure or non-secure state and adjust the state
676 * accordingly. Out of reset, ARM is defined to be in secure state
677 * (SCR.NS = 0), we change that here if non-secure boot has been
680 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
681 /* AArch64 is defined to come out of reset into EL3 if enabled.
682 * If we are booting Linux then we need to adjust our EL as
683 * Linux expects us to be in EL2 or EL1. AArch32 resets into
684 * SVC, which Linux expects, so no privilege/exception level to
688 env
->cp15
.scr_el3
|= SCR_RW
;
689 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
690 env
->cp15
.hcr_el2
|= HCR_RW
;
691 env
->pstate
= PSTATE_MODE_EL2h
;
693 env
->pstate
= PSTATE_MODE_EL1h
;
697 /* Set to non-secure if not a secure boot */
698 if (!info
->secure_boot
&&
699 (cs
!= first_cpu
|| !info
->secure_board_setup
)) {
700 /* Linux expects non-secure state */
701 env
->cp15
.scr_el3
|= SCR_NS
;
705 if (cs
== first_cpu
) {
706 cpu_set_pc(cs
, info
->loader_start
);
708 if (!have_dtb(info
)) {
710 set_kernel_args_old(info
);
712 set_kernel_args(info
);
716 info
->secondary_cpu_reset_hook(cpu
, info
);
723 * load_image_to_fw_cfg() - Load an image file into an fw_cfg entry identified
725 * @fw_cfg: The firmware config instance to store the data in.
726 * @size_key: The firmware config key to store the size of the loaded
727 * data under, with fw_cfg_add_i32().
728 * @data_key: The firmware config key to store the loaded data under,
729 * with fw_cfg_add_bytes().
730 * @image_name: The name of the image file to load. If it is NULL, the
731 * function returns without doing anything.
732 * @try_decompress: Whether the image should be decompressed (gunzipped) before
733 * adding it to fw_cfg. If decompression fails, the image is
736 * In case of failure, the function prints an error message to stderr and the
737 * process exits with status 1.
739 static void load_image_to_fw_cfg(FWCfgState
*fw_cfg
, uint16_t size_key
,
740 uint16_t data_key
, const char *image_name
,
746 if (image_name
== NULL
) {
750 if (try_decompress
) {
751 size
= load_image_gzipped_buffer(image_name
,
752 LOAD_IMAGE_MAX_GUNZIP_BYTES
, &data
);
755 if (size
== (size_t)-1) {
759 if (!g_file_get_contents(image_name
, &contents
, &length
, NULL
)) {
760 error_report("failed to load \"%s\"", image_name
);
764 data
= (uint8_t *)contents
;
767 fw_cfg_add_i32(fw_cfg
, size_key
, size
);
768 fw_cfg_add_bytes(fw_cfg
, data_key
, data
, size
);
771 static int do_arm_linux_init(Object
*obj
, void *opaque
)
773 if (object_dynamic_cast(obj
, TYPE_ARM_LINUX_BOOT_IF
)) {
774 ARMLinuxBootIf
*albif
= ARM_LINUX_BOOT_IF(obj
);
775 ARMLinuxBootIfClass
*albifc
= ARM_LINUX_BOOT_IF_GET_CLASS(obj
);
776 struct arm_boot_info
*info
= opaque
;
778 if (albifc
->arm_linux_init
) {
779 albifc
->arm_linux_init(albif
, info
->secure_boot
);
785 static uint64_t arm_load_elf(struct arm_boot_info
*info
, uint64_t *pentry
,
786 uint64_t *lowaddr
, uint64_t *highaddr
,
800 load_elf_hdr(info
->kernel_filename
, &elf_header
, &elf_is64
, &err
);
806 big_endian
= elf_header
.h64
.e_ident
[EI_DATA
] == ELFDATA2MSB
;
807 info
->endianness
= big_endian
? ARM_ENDIANNESS_BE8
810 big_endian
= elf_header
.h32
.e_ident
[EI_DATA
] == ELFDATA2MSB
;
812 if (bswap32(elf_header
.h32
.e_flags
) & EF_ARM_BE8
) {
813 info
->endianness
= ARM_ENDIANNESS_BE8
;
815 info
->endianness
= ARM_ENDIANNESS_BE32
;
816 /* In BE32, the CPU has a different view of the per-byte
817 * address map than the rest of the system. BE32 ELF files
818 * are organised such that they can be programmed through
819 * the CPU's per-word byte-reversed view of the world. QEMU
820 * however loads ELF files independently of the CPU. So
821 * tell the ELF loader to byte reverse the data for us.
826 info
->endianness
= ARM_ENDIANNESS_LE
;
830 ret
= load_elf(info
->kernel_filename
, NULL
, NULL
,
831 pentry
, lowaddr
, highaddr
, big_endian
, elf_machine
,
834 /* The header loaded but the image didn't */
841 static uint64_t load_aarch64_image(const char *filename
, hwaddr mem_base
,
844 hwaddr kernel_load_offset
= KERNEL64_LOAD_ADDR
;
848 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
849 size
= load_image_gzipped_buffer(filename
, LOAD_IMAGE_MAX_GUNZIP_BYTES
,
855 /* Load as raw file otherwise */
856 if (!g_file_get_contents(filename
, (char **)&buffer
, &len
, NULL
)) {
862 /* check the arm64 magic header value -- very old kernels may not have it */
863 if (memcmp(buffer
+ ARM64_MAGIC_OFFSET
, "ARM\x64", 4) == 0) {
866 /* The arm64 Image header has text_offset and image_size fields at 8 and
867 * 16 bytes into the Image header, respectively. The text_offset field
868 * is only valid if the image_size is non-zero.
870 memcpy(&hdrvals
, buffer
+ ARM64_TEXT_OFFSET_OFFSET
, sizeof(hdrvals
));
871 if (hdrvals
[1] != 0) {
872 kernel_load_offset
= le64_to_cpu(hdrvals
[0]);
876 *entry
= mem_base
+ kernel_load_offset
;
877 rom_add_blob_fixed(filename
, buffer
, size
, *entry
);
884 static void arm_load_kernel_notify(Notifier
*notifier
, void *data
)
890 uint64_t elf_entry
, elf_low_addr
, elf_high_addr
;
893 static const ARMInsnFixup
*primary_loader
;
894 ArmLoadKernelNotifier
*n
= DO_UPCAST(ArmLoadKernelNotifier
,
896 ARMCPU
*cpu
= n
->cpu
;
897 struct arm_boot_info
*info
=
898 container_of(n
, struct arm_boot_info
, load_kernel_notifier
);
900 /* The board code is not supposed to set secure_board_setup unless
901 * running its code in secure mode is actually possible, and KVM
902 * doesn't support secure.
904 assert(!(info
->secure_board_setup
&& kvm_enabled()));
906 info
->dtb_filename
= qemu_opt_get(qemu_get_machine_opts(), "dtb");
908 /* Load the kernel. */
909 if (!info
->kernel_filename
|| info
->firmware_loaded
) {
911 if (have_dtb(info
)) {
912 /* If we have a device tree blob, but no kernel to supply it to (or
913 * the kernel is supposed to be loaded by the bootloader), copy the
914 * DTB to the base of RAM for the bootloader to pick up.
916 if (load_dtb(info
->loader_start
, info
, 0) < 0) {
921 if (info
->kernel_filename
) {
923 bool try_decompressing_kernel
;
925 fw_cfg
= fw_cfg_find();
926 try_decompressing_kernel
= arm_feature(&cpu
->env
,
927 ARM_FEATURE_AARCH64
);
929 /* Expose the kernel, the command line, and the initrd in fw_cfg.
930 * We don't process them here at all, it's all left to the
933 load_image_to_fw_cfg(fw_cfg
,
934 FW_CFG_KERNEL_SIZE
, FW_CFG_KERNEL_DATA
,
935 info
->kernel_filename
,
936 try_decompressing_kernel
);
937 load_image_to_fw_cfg(fw_cfg
,
938 FW_CFG_INITRD_SIZE
, FW_CFG_INITRD_DATA
,
939 info
->initrd_filename
, false);
941 if (info
->kernel_cmdline
) {
942 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
943 strlen(info
->kernel_cmdline
) + 1);
944 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
,
945 info
->kernel_cmdline
);
949 /* We will start from address 0 (typically a boot ROM image) in the
950 * same way as hardware.
955 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
956 primary_loader
= bootloader_aarch64
;
957 elf_machine
= EM_AARCH64
;
959 primary_loader
= bootloader
;
960 if (!info
->write_board_setup
) {
961 primary_loader
+= BOOTLOADER_NO_BOARD_SETUP_OFFSET
;
963 elf_machine
= EM_ARM
;
966 if (!info
->secondary_cpu_reset_hook
) {
967 info
->secondary_cpu_reset_hook
= default_reset_secondary
;
969 if (!info
->write_secondary_boot
) {
970 info
->write_secondary_boot
= default_write_secondary
;
973 if (info
->nb_cpus
== 0)
976 /* We want to put the initrd far enough into RAM that when the
977 * kernel is uncompressed it will not clobber the initrd. However
978 * on boards without much RAM we must ensure that we still leave
979 * enough room for a decent sized initrd, and on boards with large
980 * amounts of RAM we must avoid the initrd being so far up in RAM
981 * that it is outside lowmem and inaccessible to the kernel.
982 * So for boards with less than 256MB of RAM we put the initrd
983 * halfway into RAM, and for boards with 256MB of RAM or more we put
984 * the initrd at 128MB.
986 info
->initrd_start
= info
->loader_start
+
987 MIN(info
->ram_size
/ 2, 128 * 1024 * 1024);
989 /* Assume that raw images are linux kernels, and ELF images are not. */
990 kernel_size
= arm_load_elf(info
, &elf_entry
, &elf_low_addr
,
991 &elf_high_addr
, elf_machine
);
992 if (kernel_size
> 0 && have_dtb(info
)) {
993 /* If there is still some room left at the base of RAM, try and put
994 * the DTB there like we do for images loaded with -bios or -pflash.
996 if (elf_low_addr
> info
->loader_start
997 || elf_high_addr
< info
->loader_start
) {
998 /* Pass elf_low_addr as address limit to load_dtb if it may be
999 * pointing into RAM, otherwise pass '0' (no limit)
1001 if (elf_low_addr
< info
->loader_start
) {
1004 if (load_dtb(info
->loader_start
, info
, elf_low_addr
) < 0) {
1010 if (kernel_size
< 0) {
1011 kernel_size
= load_uimage(info
->kernel_filename
, &entry
, NULL
,
1012 &is_linux
, NULL
, NULL
);
1014 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) && kernel_size
< 0) {
1015 kernel_size
= load_aarch64_image(info
->kernel_filename
,
1016 info
->loader_start
, &entry
);
1018 } else if (kernel_size
< 0) {
1020 entry
= info
->loader_start
+ KERNEL_LOAD_ADDR
;
1021 kernel_size
= load_image_targphys(info
->kernel_filename
, entry
,
1022 info
->ram_size
- KERNEL_LOAD_ADDR
);
1025 if (kernel_size
< 0) {
1026 error_report("could not load kernel '%s'", info
->kernel_filename
);
1029 info
->entry
= entry
;
1031 uint32_t fixupcontext
[FIXUP_MAX
];
1033 if (info
->initrd_filename
) {
1034 initrd_size
= load_ramdisk(info
->initrd_filename
,
1037 info
->initrd_start
);
1038 if (initrd_size
< 0) {
1039 initrd_size
= load_image_targphys(info
->initrd_filename
,
1042 info
->initrd_start
);
1044 if (initrd_size
< 0) {
1045 error_report("could not load initrd '%s'",
1046 info
->initrd_filename
);
1052 info
->initrd_size
= initrd_size
;
1054 fixupcontext
[FIXUP_BOARDID
] = info
->board_id
;
1055 fixupcontext
[FIXUP_BOARD_SETUP
] = info
->board_setup_addr
;
1057 /* for device tree boot, we pass the DTB directly in r2. Otherwise
1058 * we point to the kernel args.
1060 if (have_dtb(info
)) {
1064 if (elf_machine
== EM_AARCH64
) {
1066 * Some AArch64 kernels on early bootup map the fdt region as
1068 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
1070 * Let's play safe and prealign it to 2MB to give us some space.
1072 align
= 2 * 1024 * 1024;
1075 * Some 32bit kernels will trash anything in the 4K page the
1076 * initrd ends in, so make sure the DTB isn't caught up in that.
1081 /* Place the DTB after the initrd in memory with alignment. */
1082 dtb_start
= QEMU_ALIGN_UP(info
->initrd_start
+ initrd_size
, align
);
1083 if (load_dtb(dtb_start
, info
, 0) < 0) {
1086 fixupcontext
[FIXUP_ARGPTR
] = dtb_start
;
1088 fixupcontext
[FIXUP_ARGPTR
] = info
->loader_start
+ KERNEL_ARGS_ADDR
;
1089 if (info
->ram_size
>= (1ULL << 32)) {
1090 error_report("RAM size must be less than 4GB to boot"
1091 " Linux kernel using ATAGS (try passing a device tree"
1096 fixupcontext
[FIXUP_ENTRYPOINT
] = entry
;
1098 write_bootloader("bootloader", info
->loader_start
,
1099 primary_loader
, fixupcontext
);
1101 if (info
->nb_cpus
> 1) {
1102 info
->write_secondary_boot(cpu
, info
);
1104 if (info
->write_board_setup
) {
1105 info
->write_board_setup(cpu
, info
);
1108 /* Notify devices which need to fake up firmware initialization
1109 * that we're doing a direct kernel boot.
1111 object_child_foreach_recursive(object_get_root(),
1112 do_arm_linux_init
, info
);
1114 info
->is_linux
= is_linux
;
1116 for (cs
= CPU(cpu
); cs
; cs
= CPU_NEXT(cs
)) {
1117 ARM_CPU(cs
)->env
.boot_info
= info
;
1121 void arm_load_kernel(ARMCPU
*cpu
, struct arm_boot_info
*info
)
1125 info
->load_kernel_notifier
.cpu
= cpu
;
1126 info
->load_kernel_notifier
.notifier
.notify
= arm_load_kernel_notify
;
1127 qemu_add_machine_init_done_notifier(&info
->load_kernel_notifier
.notifier
);
1129 /* CPU objects (unlike devices) are not automatically reset on system
1130 * reset, so we must always register a handler to do so. If we're
1131 * actually loading a kernel, the handler is also responsible for
1132 * arranging that we start it correctly.
1134 for (cs
= CPU(cpu
); cs
; cs
= CPU_NEXT(cs
)) {
1135 qemu_register_reset(do_cpu_reset
, ARM_CPU(cs
));
1139 static const TypeInfo arm_linux_boot_if_info
= {
1140 .name
= TYPE_ARM_LINUX_BOOT_IF
,
1141 .parent
= TYPE_INTERFACE
,
1142 .class_size
= sizeof(ARMLinuxBootIfClass
),
1145 static void arm_linux_boot_register_types(void)
1147 type_register_static(&arm_linux_boot_if_info
);
1150 type_init(arm_linux_boot_register_types
)