2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
32 #include "qemu/timer.h"
33 #include "hw/ppc/xics.h"
34 #include "hw/qdev-properties.h"
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qapi/visitor.h"
38 #include "migration/vmstate.h"
39 #include "monitor/monitor.h"
40 #include "hw/intc/intc.h"
42 #include "sysemu/kvm.h"
43 #include "sysemu/reset.h"
45 void icp_pic_print_info(ICPState
*icp
, Monitor
*mon
)
49 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
50 * are hot plugged or unplugged.
56 cpu_index
= icp
->cs
? icp
->cs
->cpu_index
: -1;
62 if (kvm_irqchip_in_kernel()) {
63 icp_synchronize_state(icp
);
66 monitor_printf(mon
, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
67 cpu_index
, icp
->xirr
, icp
->xirr_owner
,
68 icp
->pending_priority
, icp
->mfrr
);
71 void ics_pic_print_info(ICSState
*ics
, Monitor
*mon
)
75 monitor_printf(mon
, "ICS %4x..%4x %p\n",
76 ics
->offset
, ics
->offset
+ ics
->nr_irqs
- 1, ics
);
82 if (kvm_irqchip_in_kernel()) {
83 ics_synchronize_state(ics
);
86 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
87 ICSIRQState
*irq
= ics
->irqs
+ i
;
89 if (!(irq
->flags
& XICS_FLAGS_IRQ_MASK
)) {
92 monitor_printf(mon
, " %4x %s %02x %02x\n",
94 (irq
->flags
& XICS_FLAGS_IRQ_LSI
) ?
96 irq
->priority
, irq
->status
);
101 * ICP: Presentation layer
104 #define XISR_MASK 0x00ffffff
105 #define CPPR_MASK 0xff000000
107 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
108 #define CPPR(icp) (((icp)->xirr) >> 24)
110 static void ics_reject(ICSState
*ics
, uint32_t nr
);
111 static void ics_eoi(ICSState
*ics
, uint32_t nr
);
113 static void icp_check_ipi(ICPState
*icp
)
115 if (XISR(icp
) && (icp
->pending_priority
<= icp
->mfrr
)) {
119 trace_xics_icp_check_ipi(icp
->cs
->cpu_index
, icp
->mfrr
);
121 if (XISR(icp
) && icp
->xirr_owner
) {
122 ics_reject(icp
->xirr_owner
, XISR(icp
));
125 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | XICS_IPI
;
126 icp
->pending_priority
= icp
->mfrr
;
127 icp
->xirr_owner
= NULL
;
128 qemu_irq_raise(icp
->output
);
131 void icp_resend(ICPState
*icp
)
133 XICSFabric
*xi
= icp
->xics
;
134 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
136 if (icp
->mfrr
< CPPR(icp
)) {
143 void icp_set_cppr(ICPState
*icp
, uint8_t cppr
)
148 old_cppr
= CPPR(icp
);
149 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (cppr
<< 24);
151 if (cppr
< old_cppr
) {
152 if (XISR(icp
) && (cppr
<= icp
->pending_priority
)) {
153 old_xisr
= XISR(icp
);
154 icp
->xirr
&= ~XISR_MASK
; /* Clear XISR */
155 icp
->pending_priority
= 0xff;
156 qemu_irq_lower(icp
->output
);
157 if (icp
->xirr_owner
) {
158 ics_reject(icp
->xirr_owner
, old_xisr
);
159 icp
->xirr_owner
= NULL
;
169 void icp_set_mfrr(ICPState
*icp
, uint8_t mfrr
)
172 if (mfrr
< CPPR(icp
)) {
177 uint32_t icp_accept(ICPState
*icp
)
179 uint32_t xirr
= icp
->xirr
;
181 qemu_irq_lower(icp
->output
);
182 icp
->xirr
= icp
->pending_priority
<< 24;
183 icp
->pending_priority
= 0xff;
184 icp
->xirr_owner
= NULL
;
186 trace_xics_icp_accept(xirr
, icp
->xirr
);
191 uint32_t icp_ipoll(ICPState
*icp
, uint32_t *mfrr
)
199 void icp_eoi(ICPState
*icp
, uint32_t xirr
)
201 XICSFabric
*xi
= icp
->xics
;
202 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
206 /* Send EOI -> ICS */
207 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (xirr
& CPPR_MASK
);
208 trace_xics_icp_eoi(icp
->cs
->cpu_index
, xirr
, icp
->xirr
);
209 irq
= xirr
& XISR_MASK
;
211 ics
= xic
->ics_get(xi
, irq
);
220 static void icp_irq(ICSState
*ics
, int server
, int nr
, uint8_t priority
)
222 ICPState
*icp
= xics_icp_get(ics
->xics
, server
);
224 trace_xics_icp_irq(server
, nr
, priority
);
226 if ((priority
>= CPPR(icp
))
227 || (XISR(icp
) && (icp
->pending_priority
<= priority
))) {
230 if (XISR(icp
) && icp
->xirr_owner
) {
231 ics_reject(icp
->xirr_owner
, XISR(icp
));
232 icp
->xirr_owner
= NULL
;
234 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | (nr
& XISR_MASK
);
235 icp
->xirr_owner
= ics
;
236 icp
->pending_priority
= priority
;
237 trace_xics_icp_raise(icp
->xirr
, icp
->pending_priority
);
238 qemu_irq_raise(icp
->output
);
242 static int icp_pre_save(void *opaque
)
244 ICPState
*icp
= opaque
;
246 if (kvm_irqchip_in_kernel()) {
247 icp_get_kvm_state(icp
);
253 static int icp_post_load(void *opaque
, int version_id
)
255 ICPState
*icp
= opaque
;
257 if (kvm_irqchip_in_kernel()) {
258 Error
*local_err
= NULL
;
261 ret
= icp_set_kvm_state(icp
, &local_err
);
263 error_report_err(local_err
);
271 static const VMStateDescription vmstate_icp_server
= {
272 .name
= "icp/server",
274 .minimum_version_id
= 1,
275 .pre_save
= icp_pre_save
,
276 .post_load
= icp_post_load
,
277 .fields
= (VMStateField
[]) {
279 VMSTATE_UINT32(xirr
, ICPState
),
280 VMSTATE_UINT8(pending_priority
, ICPState
),
281 VMSTATE_UINT8(mfrr
, ICPState
),
282 VMSTATE_END_OF_LIST()
286 void icp_reset(ICPState
*icp
)
289 icp
->pending_priority
= 0xff;
292 if (kvm_irqchip_in_kernel()) {
293 Error
*local_err
= NULL
;
295 icp_set_kvm_state(icp
, &local_err
);
297 error_report_err(local_err
);
302 static void icp_realize(DeviceState
*dev
, Error
**errp
)
304 ICPState
*icp
= ICP(dev
);
311 env
= &POWERPC_CPU(icp
->cs
)->env
;
312 switch (PPC_INPUT(env
)) {
313 case PPC_FLAGS_INPUT_POWER7
:
314 icp
->output
= env
->irq_inputs
[POWER7_INPUT_INT
];
316 case PPC_FLAGS_INPUT_POWER9
: /* For SPAPR xics emulation */
317 icp
->output
= env
->irq_inputs
[POWER9_INPUT_INT
];
320 case PPC_FLAGS_INPUT_970
:
321 icp
->output
= env
->irq_inputs
[PPC970_INPUT_INT
];
325 error_setg(errp
, "XICS interrupt controller does not support this CPU bus model");
329 /* Connect the presenter to the VCPU (required for CPU hotplug) */
330 if (kvm_irqchip_in_kernel()) {
331 icp_kvm_realize(dev
, &err
);
333 error_propagate(errp
, err
);
338 vmstate_register(NULL
, icp
->cs
->cpu_index
, &vmstate_icp_server
, icp
);
341 static void icp_unrealize(DeviceState
*dev
, Error
**errp
)
343 ICPState
*icp
= ICP(dev
);
345 vmstate_unregister(NULL
, &vmstate_icp_server
, icp
);
348 static Property icp_properties
[] = {
349 DEFINE_PROP_LINK(ICP_PROP_XICS
, ICPState
, xics
, TYPE_XICS_FABRIC
,
351 DEFINE_PROP_LINK(ICP_PROP_CPU
, ICPState
, cs
, TYPE_CPU
, CPUState
*),
352 DEFINE_PROP_END_OF_LIST(),
355 static void icp_class_init(ObjectClass
*klass
, void *data
)
357 DeviceClass
*dc
= DEVICE_CLASS(klass
);
359 dc
->realize
= icp_realize
;
360 dc
->unrealize
= icp_unrealize
;
361 dc
->props
= icp_properties
;
363 * Reason: part of XICS interrupt controller, needs to be wired up
366 dc
->user_creatable
= false;
369 static const TypeInfo icp_info
= {
371 .parent
= TYPE_DEVICE
,
372 .instance_size
= sizeof(ICPState
),
373 .class_init
= icp_class_init
,
374 .class_size
= sizeof(ICPStateClass
),
377 Object
*icp_create(Object
*cpu
, const char *type
, XICSFabric
*xi
, Error
**errp
)
379 Error
*local_err
= NULL
;
382 obj
= object_new(type
);
383 object_property_add_child(cpu
, type
, obj
, &error_abort
);
385 object_property_set_link(obj
, OBJECT(xi
), ICP_PROP_XICS
, &error_abort
);
386 object_property_set_link(obj
, cpu
, ICP_PROP_CPU
, &error_abort
);
387 object_property_set_bool(obj
, true, "realized", &local_err
);
389 object_unparent(obj
);
390 error_propagate(errp
, local_err
);
397 void icp_destroy(ICPState
*icp
)
399 Object
*obj
= OBJECT(icp
);
401 object_unparent(obj
);
407 static void ics_resend_msi(ICSState
*ics
, int srcno
)
409 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
411 /* FIXME: filter by server#? */
412 if (irq
->status
& XICS_STATUS_REJECTED
) {
413 irq
->status
&= ~XICS_STATUS_REJECTED
;
414 if (irq
->priority
!= 0xff) {
415 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
420 static void ics_resend_lsi(ICSState
*ics
, int srcno
)
422 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
424 if ((irq
->priority
!= 0xff)
425 && (irq
->status
& XICS_STATUS_ASSERTED
)
426 && !(irq
->status
& XICS_STATUS_SENT
)) {
427 irq
->status
|= XICS_STATUS_SENT
;
428 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
432 static void ics_set_irq_msi(ICSState
*ics
, int srcno
, int val
)
434 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
436 trace_xics_ics_set_irq_msi(srcno
, srcno
+ ics
->offset
);
439 if (irq
->priority
== 0xff) {
440 irq
->status
|= XICS_STATUS_MASKED_PENDING
;
441 trace_xics_masked_pending();
443 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
448 static void ics_set_irq_lsi(ICSState
*ics
, int srcno
, int val
)
450 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
452 trace_xics_ics_set_irq_lsi(srcno
, srcno
+ ics
->offset
);
454 irq
->status
|= XICS_STATUS_ASSERTED
;
456 irq
->status
&= ~XICS_STATUS_ASSERTED
;
458 ics_resend_lsi(ics
, srcno
);
461 void ics_set_irq(void *opaque
, int srcno
, int val
)
463 ICSState
*ics
= (ICSState
*)opaque
;
465 if (kvm_irqchip_in_kernel()) {
466 ics_kvm_set_irq(ics
, srcno
, val
);
470 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
471 ics_set_irq_lsi(ics
, srcno
, val
);
473 ics_set_irq_msi(ics
, srcno
, val
);
477 static void ics_write_xive_msi(ICSState
*ics
, int srcno
)
479 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
481 if (!(irq
->status
& XICS_STATUS_MASKED_PENDING
)
482 || (irq
->priority
== 0xff)) {
486 irq
->status
&= ~XICS_STATUS_MASKED_PENDING
;
487 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
490 static void ics_write_xive_lsi(ICSState
*ics
, int srcno
)
492 ics_resend_lsi(ics
, srcno
);
495 void ics_write_xive(ICSState
*ics
, int srcno
, int server
,
496 uint8_t priority
, uint8_t saved_priority
)
498 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
500 irq
->server
= server
;
501 irq
->priority
= priority
;
502 irq
->saved_priority
= saved_priority
;
504 trace_xics_ics_write_xive(ics
->offset
+ srcno
, srcno
, server
, priority
);
506 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
507 ics_write_xive_lsi(ics
, srcno
);
509 ics_write_xive_msi(ics
, srcno
);
513 static void ics_reject(ICSState
*ics
, uint32_t nr
)
515 ICSIRQState
*irq
= ics
->irqs
+ nr
- ics
->offset
;
517 trace_xics_ics_reject(nr
, nr
- ics
->offset
);
518 if (irq
->flags
& XICS_FLAGS_IRQ_MSI
) {
519 irq
->status
|= XICS_STATUS_REJECTED
;
520 } else if (irq
->flags
& XICS_FLAGS_IRQ_LSI
) {
521 irq
->status
&= ~XICS_STATUS_SENT
;
525 void ics_resend(ICSState
*ics
)
529 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
530 /* FIXME: filter by server#? */
531 if (ics
->irqs
[i
].flags
& XICS_FLAGS_IRQ_LSI
) {
532 ics_resend_lsi(ics
, i
);
534 ics_resend_msi(ics
, i
);
539 static void ics_eoi(ICSState
*ics
, uint32_t nr
)
541 int srcno
= nr
- ics
->offset
;
542 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
544 trace_xics_ics_eoi(nr
);
546 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
547 irq
->status
&= ~XICS_STATUS_SENT
;
551 static void ics_reset_irq(ICSIRQState
*irq
)
553 irq
->priority
= 0xff;
554 irq
->saved_priority
= 0xff;
557 static void ics_reset(DeviceState
*dev
)
559 ICSState
*ics
= ICS(dev
);
561 uint8_t flags
[ics
->nr_irqs
];
563 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
564 flags
[i
] = ics
->irqs
[i
].flags
;
567 memset(ics
->irqs
, 0, sizeof(ICSIRQState
) * ics
->nr_irqs
);
569 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
570 ics_reset_irq(ics
->irqs
+ i
);
571 ics
->irqs
[i
].flags
= flags
[i
];
574 if (kvm_irqchip_in_kernel()) {
575 Error
*local_err
= NULL
;
577 ics_set_kvm_state(ICS(dev
), &local_err
);
579 error_report_err(local_err
);
584 static void ics_reset_handler(void *dev
)
589 static void ics_realize(DeviceState
*dev
, Error
**errp
)
591 ICSState
*ics
= ICS(dev
);
596 error_setg(errp
, "Number of interrupts needs to be greater 0");
599 ics
->irqs
= g_malloc0(ics
->nr_irqs
* sizeof(ICSIRQState
));
601 qemu_register_reset(ics_reset_handler
, ics
);
604 static void ics_instance_init(Object
*obj
)
606 ICSState
*ics
= ICS(obj
);
608 ics
->offset
= XICS_IRQ_BASE
;
611 static int ics_pre_save(void *opaque
)
613 ICSState
*ics
= opaque
;
615 if (kvm_irqchip_in_kernel()) {
616 ics_get_kvm_state(ics
);
622 static int ics_post_load(void *opaque
, int version_id
)
624 ICSState
*ics
= opaque
;
626 if (kvm_irqchip_in_kernel()) {
627 Error
*local_err
= NULL
;
630 ret
= ics_set_kvm_state(ics
, &local_err
);
632 error_report_err(local_err
);
640 static const VMStateDescription vmstate_ics_irq
= {
643 .minimum_version_id
= 1,
644 .fields
= (VMStateField
[]) {
645 VMSTATE_UINT32(server
, ICSIRQState
),
646 VMSTATE_UINT8(priority
, ICSIRQState
),
647 VMSTATE_UINT8(saved_priority
, ICSIRQState
),
648 VMSTATE_UINT8(status
, ICSIRQState
),
649 VMSTATE_UINT8(flags
, ICSIRQState
),
650 VMSTATE_END_OF_LIST()
654 static const VMStateDescription vmstate_ics
= {
657 .minimum_version_id
= 1,
658 .pre_save
= ics_pre_save
,
659 .post_load
= ics_post_load
,
660 .fields
= (VMStateField
[]) {
662 VMSTATE_UINT32_EQUAL(nr_irqs
, ICSState
, NULL
),
664 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs
, ICSState
, nr_irqs
,
667 VMSTATE_END_OF_LIST()
671 static Property ics_properties
[] = {
672 DEFINE_PROP_UINT32("nr-irqs", ICSState
, nr_irqs
, 0),
673 DEFINE_PROP_LINK(ICS_PROP_XICS
, ICSState
, xics
, TYPE_XICS_FABRIC
,
675 DEFINE_PROP_END_OF_LIST(),
678 static void ics_class_init(ObjectClass
*klass
, void *data
)
680 DeviceClass
*dc
= DEVICE_CLASS(klass
);
682 dc
->realize
= ics_realize
;
683 dc
->props
= ics_properties
;
684 dc
->reset
= ics_reset
;
685 dc
->vmsd
= &vmstate_ics
;
687 * Reason: part of XICS interrupt controller, needs to be wired up,
688 * e.g. by spapr_irq_init().
690 dc
->user_creatable
= false;
693 static const TypeInfo ics_info
= {
695 .parent
= TYPE_DEVICE
,
696 .instance_size
= sizeof(ICSState
),
697 .instance_init
= ics_instance_init
,
698 .class_init
= ics_class_init
,
699 .class_size
= sizeof(ICSStateClass
),
702 static const TypeInfo xics_fabric_info
= {
703 .name
= TYPE_XICS_FABRIC
,
704 .parent
= TYPE_INTERFACE
,
705 .class_size
= sizeof(XICSFabricClass
),
711 ICPState
*xics_icp_get(XICSFabric
*xi
, int server
)
713 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
715 return xic
->icp_get(xi
, server
);
718 void ics_set_irq_type(ICSState
*ics
, int srcno
, bool lsi
)
720 assert(!(ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_MASK
));
722 ics
->irqs
[srcno
].flags
|=
723 lsi
? XICS_FLAGS_IRQ_LSI
: XICS_FLAGS_IRQ_MSI
;
725 if (kvm_irqchip_in_kernel()) {
726 Error
*local_err
= NULL
;
728 ics_reset_irq(ics
->irqs
+ srcno
);
729 ics_set_kvm_state_one(ics
, srcno
, &local_err
);
731 error_report_err(local_err
);
736 static void xics_register_types(void)
738 type_register_static(&ics_info
);
739 type_register_static(&icp_info
);
740 type_register_static(&xics_fabric_info
);
743 type_init(xics_register_types
)