target-ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "sysemu/kvm.h"
   8 #include "helper_regs.h"
   9 #include "mmu-hash64.h"
  10 #include "migration/cpu.h"
  11 #include "exec/exec-all.h"
  12
  13 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  14 {
  15     PowerPCCPU *cpu = opaque;
  16     CPUPPCState *env = &cpu->env;
  17     unsigned int i, j;
  18     target_ulong sdr1;
  19     uint32_t fpscr;
  20     target_ulong xer;
  21
  22     for (i = 0; i < 32; i++)
  23         qemu_get_betls(f, &env->gpr[i]);
  24 #if !defined(TARGET_PPC64)
  25     for (i = 0; i < 32; i++)
  26         qemu_get_betls(f, &env->gprh[i]);
  27 #endif
  28     qemu_get_betls(f, &env->lr);
  29     qemu_get_betls(f, &env->ctr);
  30     for (i = 0; i < 8; i++)
  31         qemu_get_be32s(f, &env->crf[i]);
  32     qemu_get_betls(f, &xer);
  33     cpu_write_xer(env, xer);
  34     qemu_get_betls(f, &env->reserve_addr);
  35     qemu_get_betls(f, &env->msr);
  36     for (i = 0; i < 4; i++)
  37         qemu_get_betls(f, &env->tgpr[i]);
  38     for (i = 0; i < 32; i++) {
  39         union {
  40             float64 d;
  41             uint64_t l;
  42         } u;
  43         u.l = qemu_get_be64(f);
  44         env->fpr[i] = u.d;
  45     }
  46     qemu_get_be32s(f, &fpscr);
  47     env->fpscr = fpscr;
  48     qemu_get_sbe32s(f, &env->access_type);
  49 #if defined(TARGET_PPC64)
  50     qemu_get_betls(f, &env->spr[SPR_ASR]);
  51     qemu_get_sbe32s(f, &env->slb_nr);
  52 #endif
  53     qemu_get_betls(f, &sdr1);
  54     for (i = 0; i < 32; i++)
  55         qemu_get_betls(f, &env->sr[i]);
  56     for (i = 0; i < 2; i++)
  57         for (j = 0; j < 8; j++)
  58             qemu_get_betls(f, &env->DBAT[i][j]);
  59     for (i = 0; i < 2; i++)
  60         for (j = 0; j < 8; j++)
  61             qemu_get_betls(f, &env->IBAT[i][j]);
  62     qemu_get_sbe32s(f, &env->nb_tlb);
  63     qemu_get_sbe32s(f, &env->tlb_per_way);
  64     qemu_get_sbe32s(f, &env->nb_ways);
  65     qemu_get_sbe32s(f, &env->last_way);
  66     qemu_get_sbe32s(f, &env->id_tlbs);
  67     qemu_get_sbe32s(f, &env->nb_pids);
  68     if (env->tlb.tlb6) {
  69         // XXX assumes 6xx
  70         for (i = 0; i < env->nb_tlb; i++) {
  71             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  72             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  73             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  74         }
  75     }
  76     for (i = 0; i < 4; i++)
  77         qemu_get_betls(f, &env->pb[i]);
  78     for (i = 0; i < 1024; i++)
  79         qemu_get_betls(f, &env->spr[i]);
  80     if (!env->external_htab) {
  81         ppc_store_sdr1(env, sdr1);
  82     }
  83     qemu_get_be32s(f, &env->vscr);
  84     qemu_get_be64s(f, &env->spe_acc);
  85     qemu_get_be32s(f, &env->spe_fscr);
  86     qemu_get_betls(f, &env->msr_mask);
  87     qemu_get_be32s(f, &env->flags);
  88     qemu_get_sbe32s(f, &env->error_code);
  89     qemu_get_be32s(f, &env->pending_interrupts);
  90     qemu_get_be32s(f, &env->irq_input_state);
  91     for (i = 0; i < POWERPC_EXCP_NB; i++)
  92         qemu_get_betls(f, &env->excp_vectors[i]);
  93     qemu_get_betls(f, &env->excp_prefix);
  94     qemu_get_betls(f, &env->ivor_mask);
  95     qemu_get_betls(f, &env->ivpr_mask);
  96     qemu_get_betls(f, &env->hreset_vector);
  97     qemu_get_betls(f, &env->nip);
  98     qemu_get_betls(f, &env->hflags);
  99     qemu_get_betls(f, &env->hflags_nmsr);
 100     qemu_get_sbe32s(f, &env->mmu_idx);
 101     qemu_get_sbe32(f); /* Discard unused power_mode */
 102
 103     return 0;
 104 }
 105
 106 static int get_avr(QEMUFile *f, void *pv, size_t size)
 107 {
 108     ppc_avr_t *v = pv;
 109
 110     v->u64[0] = qemu_get_be64(f);
 111     v->u64[1] = qemu_get_be64(f);
 112
 113     return 0;
 114 }
 115
 116 static void put_avr(QEMUFile *f, void *pv, size_t size)
 117 {
 118     ppc_avr_t *v = pv;
 119
 120     qemu_put_be64(f, v->u64[0]);
 121     qemu_put_be64(f, v->u64[1]);
 122 }
 123
 124 static const VMStateInfo vmstate_info_avr = {
 125     .name = "avr",
 126     .get  = get_avr,
 127     .put  = put_avr,
 128 };
 129
 130 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 131     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 132
 133 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 134     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 135
 136 static void cpu_pre_save(void *opaque)
 137 {
 138     PowerPCCPU *cpu = opaque;
 139     CPUPPCState *env = &cpu->env;
 140     int i;
 141
 142     env->spr[SPR_LR] = env->lr;
 143     env->spr[SPR_CTR] = env->ctr;
 144     env->spr[SPR_XER] = cpu_read_xer(env);
 145 #if defined(TARGET_PPC64)
 146     env->spr[SPR_CFAR] = env->cfar;
 147 #endif
 148     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 149
 150     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 151         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 152         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 153         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 154         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 155     }
 156     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 157         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 158         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 159         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 160         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 161     }
 162 }
 163
 164 static int cpu_post_load(void *opaque, int version_id)
 165 {
 166     PowerPCCPU *cpu = opaque;
 167     CPUPPCState *env = &cpu->env;
 168     int i;
 169     target_ulong msr;
 170
 171     /*
 172      * We always ignore the source PVR. The user or management
 173      * software has to take care of running QEMU in a compatible mode.
 174      */
 175     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 176     env->lr = env->spr[SPR_LR];
 177     env->ctr = env->spr[SPR_CTR];
 178     cpu_write_xer(env, env->spr[SPR_XER]);
 179 #if defined(TARGET_PPC64)
 180     env->cfar = env->spr[SPR_CFAR];
 181 #endif
 182     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 183
 184     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 185         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 186         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 187         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 188         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 189     }
 190     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 191         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 192         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 193         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 194         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 195     }
 196
 197     if (!env->external_htab) {
 198         /* Restore htab_base and htab_mask variables */
 199         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 200     }
 201
 202     /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
 203     msr = env->msr;
 204     env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
 205     ppc_store_msr(env, msr);
 206
 207     hreg_compute_mem_idx(env);
 208
 209     return 0;
 210 }
 211
 212 static bool fpu_needed(void *opaque)
 213 {
 214     PowerPCCPU *cpu = opaque;
 215
 216     return (cpu->env.insns_flags & PPC_FLOAT);
 217 }
 218
 219 static const VMStateDescription vmstate_fpu = {
 220     .name = "cpu/fpu",
 221     .version_id = 1,
 222     .minimum_version_id = 1,
 223     .needed = fpu_needed,
 224     .fields = (VMStateField[]) {
 225         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 226         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 227         VMSTATE_END_OF_LIST()
 228     },
 229 };
 230
 231 static bool altivec_needed(void *opaque)
 232 {
 233     PowerPCCPU *cpu = opaque;
 234
 235     return (cpu->env.insns_flags & PPC_ALTIVEC);
 236 }
 237
 238 static const VMStateDescription vmstate_altivec = {
 239     .name = "cpu/altivec",
 240     .version_id = 1,
 241     .minimum_version_id = 1,
 242     .needed = altivec_needed,
 243     .fields = (VMStateField[]) {
 244         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 245         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 246         VMSTATE_END_OF_LIST()
 247     },
 248 };
 249
 250 static bool vsx_needed(void *opaque)
 251 {
 252     PowerPCCPU *cpu = opaque;
 253
 254     return (cpu->env.insns_flags2 & PPC2_VSX);
 255 }
 256
 257 static const VMStateDescription vmstate_vsx = {
 258     .name = "cpu/vsx",
 259     .version_id = 1,
 260     .minimum_version_id = 1,
 261     .needed = vsx_needed,
 262     .fields = (VMStateField[]) {
 263         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 264         VMSTATE_END_OF_LIST()
 265     },
 266 };
 267
 268 #ifdef TARGET_PPC64
 269 /* Transactional memory state */
 270 static bool tm_needed(void *opaque)
 271 {
 272     PowerPCCPU *cpu = opaque;
 273     CPUPPCState *env = &cpu->env;
 274     return msr_ts;
 275 }
 276
 277 static const VMStateDescription vmstate_tm = {
 278     .name = "cpu/tm",
 279     .version_id = 1,
 280     .minimum_version_id = 1,
 281     .minimum_version_id_old = 1,
 282     .needed = tm_needed,
 283     .fields      = (VMStateField []) {
 284         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 285         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 286         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 287         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 288         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 289         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 290         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 291         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 292         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 293         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 294         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 295         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 296         VMSTATE_END_OF_LIST()
 297     },
 298 };
 299 #endif
 300
 301 static bool sr_needed(void *opaque)
 302 {
 303 #ifdef TARGET_PPC64
 304     PowerPCCPU *cpu = opaque;
 305
 306     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 307 #else
 308     return true;
 309 #endif
 310 }
 311
 312 static const VMStateDescription vmstate_sr = {
 313     .name = "cpu/sr",
 314     .version_id = 1,
 315     .minimum_version_id = 1,
 316     .needed = sr_needed,
 317     .fields = (VMStateField[]) {
 318         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 319         VMSTATE_END_OF_LIST()
 320     },
 321 };
 322
 323 #ifdef TARGET_PPC64
 324 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 325 {
 326     ppc_slb_t *v = pv;
 327
 328     v->esid = qemu_get_be64(f);
 329     v->vsid = qemu_get_be64(f);
 330
 331     return 0;
 332 }
 333
 334 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 335 {
 336     ppc_slb_t *v = pv;
 337
 338     qemu_put_be64(f, v->esid);
 339     qemu_put_be64(f, v->vsid);
 340 }
 341
 342 static const VMStateInfo vmstate_info_slbe = {
 343     .name = "slbe",
 344     .get  = get_slbe,
 345     .put  = put_slbe,
 346 };
 347
 348 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 349     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 350
 351 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 352     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 353
 354 static bool slb_needed(void *opaque)
 355 {
 356     PowerPCCPU *cpu = opaque;
 357
 358     /* We don't support any of the old segment table based 64-bit CPUs */
 359     return (cpu->env.mmu_model & POWERPC_MMU_64);
 360 }
 361
 362 static int slb_post_load(void *opaque, int version_id)
 363 {
 364     PowerPCCPU *cpu = opaque;
 365     CPUPPCState *env = &cpu->env;
 366     int i;
 367
 368     /* We've pulled in the raw esid and vsid values from the migration
 369      * stream, but we need to recompute the page size pointers */
 370     for (i = 0; i < env->slb_nr; i++) {
 371         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 372             /* Migration source had bad values in its SLB */
 373             return -1;
 374         }
 375     }
 376
 377     return 0;
 378 }
 379
 380 static const VMStateDescription vmstate_slb = {
 381     .name = "cpu/slb",
 382     .version_id = 1,
 383     .minimum_version_id = 1,
 384     .needed = slb_needed,
 385     .post_load = slb_post_load,
 386     .fields = (VMStateField[]) {
 387         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 388         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 389         VMSTATE_END_OF_LIST()
 390     }
 391 };
 392 #endif /* TARGET_PPC64 */
 393
 394 static const VMStateDescription vmstate_tlb6xx_entry = {
 395     .name = "cpu/tlb6xx_entry",
 396     .version_id = 1,
 397     .minimum_version_id = 1,
 398     .fields = (VMStateField[]) {
 399         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 400         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 401         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 402         VMSTATE_END_OF_LIST()
 403     },
 404 };
 405
 406 static bool tlb6xx_needed(void *opaque)
 407 {
 408     PowerPCCPU *cpu = opaque;
 409     CPUPPCState *env = &cpu->env;
 410
 411     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 412 }
 413
 414 static const VMStateDescription vmstate_tlb6xx = {
 415     .name = "cpu/tlb6xx",
 416     .version_id = 1,
 417     .minimum_version_id = 1,
 418     .needed = tlb6xx_needed,
 419     .fields = (VMStateField[]) {
 420         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 421         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 422                                             env.nb_tlb,
 423                                             vmstate_tlb6xx_entry,
 424                                             ppc6xx_tlb_t),
 425         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 426         VMSTATE_END_OF_LIST()
 427     }
 428 };
 429
 430 static const VMStateDescription vmstate_tlbemb_entry = {
 431     .name = "cpu/tlbemb_entry",
 432     .version_id = 1,
 433     .minimum_version_id = 1,
 434     .fields = (VMStateField[]) {
 435         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 436         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 437         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 438         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 439         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 440         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 441         VMSTATE_END_OF_LIST()
 442     },
 443 };
 444
 445 static bool tlbemb_needed(void *opaque)
 446 {
 447     PowerPCCPU *cpu = opaque;
 448     CPUPPCState *env = &cpu->env;
 449
 450     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 451 }
 452
 453 static bool pbr403_needed(void *opaque)
 454 {
 455     PowerPCCPU *cpu = opaque;
 456     uint32_t pvr = cpu->env.spr[SPR_PVR];
 457
 458     return (pvr & 0xffff0000) == 0x00200000;
 459 }
 460
 461 static const VMStateDescription vmstate_pbr403 = {
 462     .name = "cpu/pbr403",
 463     .version_id = 1,
 464     .minimum_version_id = 1,
 465     .needed = pbr403_needed,
 466     .fields = (VMStateField[]) {
 467         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 468         VMSTATE_END_OF_LIST()
 469     },
 470 };
 471
 472 static const VMStateDescription vmstate_tlbemb = {
 473     .name = "cpu/tlb6xx",
 474     .version_id = 1,
 475     .minimum_version_id = 1,
 476     .needed = tlbemb_needed,
 477     .fields = (VMStateField[]) {
 478         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 479         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 480                                             env.nb_tlb,
 481                                             vmstate_tlbemb_entry,
 482                                             ppcemb_tlb_t),
 483         /* 403 protection registers */
 484         VMSTATE_END_OF_LIST()
 485     },
 486     .subsections = (const VMStateDescription*[]) {
 487         &vmstate_pbr403,
 488         NULL
 489     }
 490 };
 491
 492 static const VMStateDescription vmstate_tlbmas_entry = {
 493     .name = "cpu/tlbmas_entry",
 494     .version_id = 1,
 495     .minimum_version_id = 1,
 496     .fields = (VMStateField[]) {
 497         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 498         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 499         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 500         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 501         VMSTATE_END_OF_LIST()
 502     },
 503 };
 504
 505 static bool tlbmas_needed(void *opaque)
 506 {
 507     PowerPCCPU *cpu = opaque;
 508     CPUPPCState *env = &cpu->env;
 509
 510     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 511 }
 512
 513 static const VMStateDescription vmstate_tlbmas = {
 514     .name = "cpu/tlbmas",
 515     .version_id = 1,
 516     .minimum_version_id = 1,
 517     .needed = tlbmas_needed,
 518     .fields = (VMStateField[]) {
 519         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 520         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 521                                             env.nb_tlb,
 522                                             vmstate_tlbmas_entry,
 523                                             ppcmas_tlb_t),
 524         VMSTATE_END_OF_LIST()
 525     }
 526 };
 527
 528 const VMStateDescription vmstate_ppc_cpu = {
 529     .name = "cpu",
 530     .version_id = 5,
 531     .minimum_version_id = 5,
 532     .minimum_version_id_old = 4,
 533     .load_state_old = cpu_load_old,
 534     .pre_save = cpu_pre_save,
 535     .post_load = cpu_post_load,
 536     .fields = (VMStateField[]) {
 537         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 538
 539         /* User mode architected state */
 540         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 541 #if !defined(TARGET_PPC64)
 542         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 543 #endif
 544         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 545         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 546
 547         /* SPRs */
 548         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 549         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 550
 551         /* Reservation */
 552         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 553
 554         /* Supervisor mode architected state */
 555         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 556
 557         /* Internal state */
 558         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 559         /* FIXME: access_type? */
 560
 561         /* Sanity checking */
 562         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 563         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 564         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 565         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 566         VMSTATE_END_OF_LIST()
 567     },
 568     .subsections = (const VMStateDescription*[]) {
 569         &vmstate_fpu,
 570         &vmstate_altivec,
 571         &vmstate_vsx,
 572         &vmstate_sr,
 573 #ifdef TARGET_PPC64
 574         &vmstate_tm,
 575         &vmstate_slb,
 576 #endif /* TARGET_PPC64 */
 577         &vmstate_tlb6xx,
 578         &vmstate_tlbemb,
 579         &vmstate_tlbmas,
 580         NULL
 581     }
 582 };