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target-i386: Move TCG initialization check to tcg_x86_init()
[qemu/ar7.git] / target-i386 / kvm.c
blob084183510a88764865e1907ce00b5aca34190b7c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/mman.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include <linux/kvm_para.h>
23
24 #include "qemu-common.h"
25 #include "cpu.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39
40 #include "exec/ioport.h"
41 #include "standard-headers/asm-x86/hyperv.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "migration/migration.h"
45 #include "exec/memattrs.h"
46
47 //#define DEBUG_KVM
48
49 #ifdef DEBUG_KVM
50 #define DPRINTF(fmt, ...) \
51 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF(fmt, ...) \
54 do { } while (0)
55 #endif
56
57 #define MSR_KVM_WALL_CLOCK 0x11
58 #define MSR_KVM_SYSTEM_TIME 0x12
59
60 #ifndef BUS_MCEERR_AR
61 #define BUS_MCEERR_AR 4
62 #endif
63 #ifndef BUS_MCEERR_AO
64 #define BUS_MCEERR_AO 5
65 #endif
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_async_pf_en;
81 static bool has_msr_pv_eoi_en;
82 static bool has_msr_misc_enable;
83 static bool has_msr_smbase;
84 static bool has_msr_bndcfgs;
85 static bool has_msr_kvm_steal_time;
86 static int lm_capable_kernel;
87 static bool has_msr_hv_hypercall;
88 static bool has_msr_hv_vapic;
89 static bool has_msr_hv_tsc;
90 static bool has_msr_hv_crash;
91 static bool has_msr_hv_reset;
92 static bool has_msr_hv_vpindex;
93 static bool has_msr_hv_runtime;
94 static bool has_msr_hv_synic;
95 static bool has_msr_hv_stimer;
96 static bool has_msr_mtrr;
97 static bool has_msr_xss;
98
99 static bool has_msr_architectural_pmu;
100 static uint32_t num_architectural_pmu_counters;
101
102 static int has_xsave;
103 static int has_xcrs;
104 static int has_pit_state2;
105
106 int kvm_has_pit_state2(void)
107 {
108 return has_pit_state2;
109 }
110
111 bool kvm_has_smm(void)
112 {
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114 }
115
116 bool kvm_allows_irq0_override(void)
117 {
118 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
119 }
120
121 static int kvm_get_tsc(CPUState *cs)
122 {
123 X86CPU *cpu = X86_CPU(cs);
124 CPUX86State *env = &cpu->env;
125 struct {
126 struct kvm_msrs info;
127 struct kvm_msr_entry entries[1];
128 } msr_data;
129 int ret;
130
131 if (env->tsc_valid) {
132 return 0;
133 }
134
135 msr_data.info.nmsrs = 1;
136 msr_data.entries[0].index = MSR_IA32_TSC;
137 env->tsc_valid = !runstate_is_running();
138
139 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
140 if (ret < 0) {
141 return ret;
142 }
143
144 assert(ret == 1);
145 env->tsc = msr_data.entries[0].data;
146 return 0;
147 }
148
149 static inline void do_kvm_synchronize_tsc(void *arg)
150 {
151 CPUState *cpu = arg;
152
153 kvm_get_tsc(cpu);
154 }
155
156 void kvm_synchronize_all_tsc(void)
157 {
158 CPUState *cpu;
159
160 if (kvm_enabled()) {
161 CPU_FOREACH(cpu) {
162 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
163 }
164 }
165 }
166
167 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
168 {
169 struct kvm_cpuid2 *cpuid;
170 int r, size;
171
172 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
173 cpuid = g_malloc0(size);
174 cpuid->nent = max;
175 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
176 if (r == 0 && cpuid->nent >= max) {
177 r = -E2BIG;
178 }
179 if (r < 0) {
180 if (r == -E2BIG) {
181 g_free(cpuid);
182 return NULL;
183 } else {
184 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
185 strerror(-r));
186 exit(1);
187 }
188 }
189 return cpuid;
190 }
191
192 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
193 * for all entries.
194 */
195 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
196 {
197 struct kvm_cpuid2 *cpuid;
198 int max = 1;
199 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
200 max *= 2;
201 }
202 return cpuid;
203 }
204
205 static const struct kvm_para_features {
206 int cap;
207 int feature;
208 } para_features[] = {
209 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
210 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
211 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
212 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
213 };
214
215 static int get_para_features(KVMState *s)
216 {
217 int i, features = 0;
218
219 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
220 if (kvm_check_extension(s, para_features[i].cap)) {
221 features |= (1 << para_features[i].feature);
222 }
223 }
224
225 return features;
226 }
227
228
229 /* Returns the value for a specific register on the cpuid entry
230 */
231 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
232 {
233 uint32_t ret = 0;
234 switch (reg) {
235 case R_EAX:
236 ret = entry->eax;
237 break;
238 case R_EBX:
239 ret = entry->ebx;
240 break;
241 case R_ECX:
242 ret = entry->ecx;
243 break;
244 case R_EDX:
245 ret = entry->edx;
246 break;
247 }
248 return ret;
249 }
250
251 /* Find matching entry for function/index on kvm_cpuid2 struct
252 */
253 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
254 uint32_t function,
255 uint32_t index)
256 {
257 int i;
258 for (i = 0; i < cpuid->nent; ++i) {
259 if (cpuid->entries[i].function == function &&
260 cpuid->entries[i].index == index) {
261 return &cpuid->entries[i];
262 }
263 }
264 /* not found: */
265 return NULL;
266 }
267
268 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
269 uint32_t index, int reg)
270 {
271 struct kvm_cpuid2 *cpuid;
272 uint32_t ret = 0;
273 uint32_t cpuid_1_edx;
274 bool found = false;
275
276 cpuid = get_supported_cpuid(s);
277
278 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
279 if (entry) {
280 found = true;
281 ret = cpuid_entry_get_reg(entry, reg);
282 }
283
284 /* Fixups for the data returned by KVM, below */
285
286 if (function == 1 && reg == R_EDX) {
287 /* KVM before 2.6.30 misreports the following features */
288 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
289 } else if (function == 1 && reg == R_ECX) {
290 /* We can set the hypervisor flag, even if KVM does not return it on
291 * GET_SUPPORTED_CPUID
292 */
293 ret |= CPUID_EXT_HYPERVISOR;
294 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
295 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
296 * and the irqchip is in the kernel.
297 */
298 if (kvm_irqchip_in_kernel() &&
299 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
300 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
301 }
302
303 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
304 * without the in-kernel irqchip
305 */
306 if (!kvm_irqchip_in_kernel()) {
307 ret &= ~CPUID_EXT_X2APIC;
308 }
309 } else if (function == 6 && reg == R_EAX) {
310 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
311 } else if (function == 0x80000001 && reg == R_EDX) {
312 /* On Intel, kvm returns cpuid according to the Intel spec,
313 * so add missing bits according to the AMD spec:
314 */
315 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
316 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
317 }
318
319 g_free(cpuid);
320
321 /* fallback for older kernels */
322 if ((function == KVM_CPUID_FEATURES) && !found) {
323 ret = get_para_features(s);
324 }
325
326 return ret;
327 }
328
329 typedef struct HWPoisonPage {
330 ram_addr_t ram_addr;
331 QLIST_ENTRY(HWPoisonPage) list;
332 } HWPoisonPage;
333
334 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
335 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
336
337 static void kvm_unpoison_all(void *param)
338 {
339 HWPoisonPage *page, *next_page;
340
341 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
342 QLIST_REMOVE(page, list);
343 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
344 g_free(page);
345 }
346 }
347
348 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
349 {
350 HWPoisonPage *page;
351
352 QLIST_FOREACH(page, &hwpoison_page_list, list) {
353 if (page->ram_addr == ram_addr) {
354 return;
355 }
356 }
357 page = g_new(HWPoisonPage, 1);
358 page->ram_addr = ram_addr;
359 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
360 }
361
362 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
363 int *max_banks)
364 {
365 int r;
366
367 r = kvm_check_extension(s, KVM_CAP_MCE);
368 if (r > 0) {
369 *max_banks = r;
370 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
371 }
372 return -ENOSYS;
373 }
374
375 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
376 {
377 CPUX86State *env = &cpu->env;
378 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
379 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
380 uint64_t mcg_status = MCG_STATUS_MCIP;
381
382 if (code == BUS_MCEERR_AR) {
383 status |= MCI_STATUS_AR | 0x134;
384 mcg_status |= MCG_STATUS_EIPV;
385 } else {
386 status |= 0xc0;
387 mcg_status |= MCG_STATUS_RIPV;
388 }
389 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
390 (MCM_ADDR_PHYS << 6) | 0xc,
391 cpu_x86_support_mca_broadcast(env) ?
392 MCE_INJECT_BROADCAST : 0);
393 }
394
395 static void hardware_memory_error(void)
396 {
397 fprintf(stderr, "Hardware memory error!\n");
398 exit(1);
399 }
400
401 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
402 {
403 X86CPU *cpu = X86_CPU(c);
404 CPUX86State *env = &cpu->env;
405 ram_addr_t ram_addr;
406 hwaddr paddr;
407
408 if ((env->mcg_cap & MCG_SER_P) && addr
409 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
410 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
411 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
412 fprintf(stderr, "Hardware memory error for memory used by "
413 "QEMU itself instead of guest system!\n");
414 /* Hope we are lucky for AO MCE */
415 if (code == BUS_MCEERR_AO) {
416 return 0;
417 } else {
418 hardware_memory_error();
419 }
420 }
421 kvm_hwpoison_page_add(ram_addr);
422 kvm_mce_inject(cpu, paddr, code);
423 } else {
424 if (code == BUS_MCEERR_AO) {
425 return 0;
426 } else if (code == BUS_MCEERR_AR) {
427 hardware_memory_error();
428 } else {
429 return 1;
430 }
431 }
432 return 0;
433 }
434
435 int kvm_arch_on_sigbus(int code, void *addr)
436 {
437 X86CPU *cpu = X86_CPU(first_cpu);
438
439 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
440 ram_addr_t ram_addr;
441 hwaddr paddr;
442
443 /* Hope we are lucky for AO MCE */
444 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
445 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
446 addr, &paddr)) {
447 fprintf(stderr, "Hardware memory error for memory used by "
448 "QEMU itself instead of guest system!: %p\n", addr);
449 return 0;
450 }
451 kvm_hwpoison_page_add(ram_addr);
452 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
453 } else {
454 if (code == BUS_MCEERR_AO) {
455 return 0;
456 } else if (code == BUS_MCEERR_AR) {
457 hardware_memory_error();
458 } else {
459 return 1;
460 }
461 }
462 return 0;
463 }
464
465 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
466 {
467 CPUX86State *env = &cpu->env;
468
469 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
470 unsigned int bank, bank_num = env->mcg_cap & 0xff;
471 struct kvm_x86_mce mce;
472
473 env->exception_injected = -1;
474
475 /*
476 * There must be at least one bank in use if an MCE is pending.
477 * Find it and use its values for the event injection.
478 */
479 for (bank = 0; bank < bank_num; bank++) {
480 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
481 break;
482 }
483 }
484 assert(bank < bank_num);
485
486 mce.bank = bank;
487 mce.status = env->mce_banks[bank * 4 + 1];
488 mce.mcg_status = env->mcg_status;
489 mce.addr = env->mce_banks[bank * 4 + 2];
490 mce.misc = env->mce_banks[bank * 4 + 3];
491
492 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
493 }
494 return 0;
495 }
496
497 static void cpu_update_state(void *opaque, int running, RunState state)
498 {
499 CPUX86State *env = opaque;
500
501 if (running) {
502 env->tsc_valid = false;
503 }
504 }
505
506 unsigned long kvm_arch_vcpu_id(CPUState *cs)
507 {
508 X86CPU *cpu = X86_CPU(cs);
509 return cpu->apic_id;
510 }
511
512 #ifndef KVM_CPUID_SIGNATURE_NEXT
513 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
514 #endif
515
516 static bool hyperv_hypercall_available(X86CPU *cpu)
517 {
518 return cpu->hyperv_vapic ||
519 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
520 }
521
522 static bool hyperv_enabled(X86CPU *cpu)
523 {
524 CPUState *cs = CPU(cpu);
525 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
526 (hyperv_hypercall_available(cpu) ||
527 cpu->hyperv_time ||
528 cpu->hyperv_relaxed_timing ||
529 cpu->hyperv_crash ||
530 cpu->hyperv_reset ||
531 cpu->hyperv_vpindex ||
532 cpu->hyperv_runtime ||
533 cpu->hyperv_synic ||
534 cpu->hyperv_stimer);
535 }
536
537 static int kvm_arch_set_tsc_khz(CPUState *cs)
538 {
539 X86CPU *cpu = X86_CPU(cs);
540 CPUX86State *env = &cpu->env;
541 int r;
542
543 if (!env->tsc_khz) {
544 return 0;
545 }
546
547 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
548 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
549 -ENOTSUP;
550 if (r < 0) {
551 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
552 * TSC frequency doesn't match the one we want.
553 */
554 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
555 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
556 -ENOTSUP;
557 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
558 error_report("warning: TSC frequency mismatch between "
559 "VM and host, and TSC scaling unavailable");
560 return r;
561 }
562 }
563
564 return 0;
565 }
566
567 static Error *invtsc_mig_blocker;
568
569 #define KVM_MAX_CPUID_ENTRIES 100
570
571 int kvm_arch_init_vcpu(CPUState *cs)
572 {
573 struct {
574 struct kvm_cpuid2 cpuid;
575 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
576 } QEMU_PACKED cpuid_data;
577 X86CPU *cpu = X86_CPU(cs);
578 CPUX86State *env = &cpu->env;
579 uint32_t limit, i, j, cpuid_i;
580 uint32_t unused;
581 struct kvm_cpuid_entry2 *c;
582 uint32_t signature[3];
583 int kvm_base = KVM_CPUID_SIGNATURE;
584 int r;
585
586 memset(&cpuid_data, 0, sizeof(cpuid_data));
587
588 cpuid_i = 0;
589
590 /* Paravirtualization CPUIDs */
591 if (hyperv_enabled(cpu)) {
592 c = &cpuid_data.entries[cpuid_i++];
593 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
594 if (!cpu->hyperv_vendor_id) {
595 memcpy(signature, "Microsoft Hv", 12);
596 } else {
597 size_t len = strlen(cpu->hyperv_vendor_id);
598
599 if (len > 12) {
600 error_report("hv-vendor-id truncated to 12 characters");
601 len = 12;
602 }
603 memset(signature, 0, 12);
604 memcpy(signature, cpu->hyperv_vendor_id, len);
605 }
606 c->eax = HYPERV_CPUID_MIN;
607 c->ebx = signature[0];
608 c->ecx = signature[1];
609 c->edx = signature[2];
610
611 c = &cpuid_data.entries[cpuid_i++];
612 c->function = HYPERV_CPUID_INTERFACE;
613 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
614 c->eax = signature[0];
615 c->ebx = 0;
616 c->ecx = 0;
617 c->edx = 0;
618
619 c = &cpuid_data.entries[cpuid_i++];
620 c->function = HYPERV_CPUID_VERSION;
621 c->eax = 0x00001bbc;
622 c->ebx = 0x00060001;
623
624 c = &cpuid_data.entries[cpuid_i++];
625 c->function = HYPERV_CPUID_FEATURES;
626 if (cpu->hyperv_relaxed_timing) {
627 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
628 }
629 if (cpu->hyperv_vapic) {
630 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
631 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
632 has_msr_hv_vapic = true;
633 }
634 if (cpu->hyperv_time &&
635 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
636 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
637 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
638 c->eax |= 0x200;
639 has_msr_hv_tsc = true;
640 }
641 if (cpu->hyperv_crash && has_msr_hv_crash) {
642 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
643 }
644 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
645 if (cpu->hyperv_reset && has_msr_hv_reset) {
646 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
647 }
648 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
649 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
650 }
651 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
652 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
653 }
654 if (cpu->hyperv_synic) {
655 int sint;
656
657 if (!has_msr_hv_synic ||
658 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
659 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
660 return -ENOSYS;
661 }
662
663 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
664 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
665 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
666 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
667 }
668 }
669 if (cpu->hyperv_stimer) {
670 if (!has_msr_hv_stimer) {
671 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
672 return -ENOSYS;
673 }
674 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
675 }
676 c = &cpuid_data.entries[cpuid_i++];
677 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
678 if (cpu->hyperv_relaxed_timing) {
679 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
680 }
681 if (has_msr_hv_vapic) {
682 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
683 }
684 c->ebx = cpu->hyperv_spinlock_attempts;
685
686 c = &cpuid_data.entries[cpuid_i++];
687 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
688 c->eax = 0x40;
689 c->ebx = 0x40;
690
691 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
692 has_msr_hv_hypercall = true;
693 }
694
695 if (cpu->expose_kvm) {
696 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
697 c = &cpuid_data.entries[cpuid_i++];
698 c->function = KVM_CPUID_SIGNATURE | kvm_base;
699 c->eax = KVM_CPUID_FEATURES | kvm_base;
700 c->ebx = signature[0];
701 c->ecx = signature[1];
702 c->edx = signature[2];
703
704 c = &cpuid_data.entries[cpuid_i++];
705 c->function = KVM_CPUID_FEATURES | kvm_base;
706 c->eax = env->features[FEAT_KVM];
707
708 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
709
710 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
711
712 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
713 }
714
715 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
716
717 for (i = 0; i <= limit; i++) {
718 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
719 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
720 abort();
721 }
722 c = &cpuid_data.entries[cpuid_i++];
723
724 switch (i) {
725 case 2: {
726 /* Keep reading function 2 till all the input is received */
727 int times;
728
729 c->function = i;
730 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
731 KVM_CPUID_FLAG_STATE_READ_NEXT;
732 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
733 times = c->eax & 0xff;
734
735 for (j = 1; j < times; ++j) {
736 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
737 fprintf(stderr, "cpuid_data is full, no space for "
738 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
739 abort();
740 }
741 c = &cpuid_data.entries[cpuid_i++];
742 c->function = i;
743 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
744 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
745 }
746 break;
747 }
748 case 4:
749 case 0xb:
750 case 0xd:
751 for (j = 0; ; j++) {
752 if (i == 0xd && j == 64) {
753 break;
754 }
755 c->function = i;
756 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
757 c->index = j;
758 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
759
760 if (i == 4 && c->eax == 0) {
761 break;
762 }
763 if (i == 0xb && !(c->ecx & 0xff00)) {
764 break;
765 }
766 if (i == 0xd && c->eax == 0) {
767 continue;
768 }
769 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
770 fprintf(stderr, "cpuid_data is full, no space for "
771 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
772 abort();
773 }
774 c = &cpuid_data.entries[cpuid_i++];
775 }
776 break;
777 default:
778 c->function = i;
779 c->flags = 0;
780 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
781 break;
782 }
783 }
784
785 if (limit >= 0x0a) {
786 uint32_t ver;
787
788 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
789 if ((ver & 0xff) > 0) {
790 has_msr_architectural_pmu = true;
791 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
792
793 /* Shouldn't be more than 32, since that's the number of bits
794 * available in EBX to tell us _which_ counters are available.
795 * Play it safe.
796 */
797 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
798 num_architectural_pmu_counters = MAX_GP_COUNTERS;
799 }
800 }
801 }
802
803 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
804
805 for (i = 0x80000000; i <= limit; i++) {
806 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
807 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
808 abort();
809 }
810 c = &cpuid_data.entries[cpuid_i++];
811
812 c->function = i;
813 c->flags = 0;
814 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
815 }
816
817 /* Call Centaur's CPUID instructions they are supported. */
818 if (env->cpuid_xlevel2 > 0) {
819 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
820
821 for (i = 0xC0000000; i <= limit; i++) {
822 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
823 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
824 abort();
825 }
826 c = &cpuid_data.entries[cpuid_i++];
827
828 c->function = i;
829 c->flags = 0;
830 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
831 }
832 }
833
834 cpuid_data.cpuid.nent = cpuid_i;
835
836 if (((env->cpuid_version >> 8)&0xF) >= 6
837 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
838 (CPUID_MCE | CPUID_MCA)
839 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
840 uint64_t mcg_cap, unsupported_caps;
841 int banks;
842 int ret;
843
844 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
845 if (ret < 0) {
846 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
847 return ret;
848 }
849
850 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
851 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
852 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
853 return -ENOTSUP;
854 }
855
856 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
857 if (unsupported_caps) {
858 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
859 unsupported_caps);
860 }
861
862 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
863 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
864 if (ret < 0) {
865 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
866 return ret;
867 }
868 }
869
870 qemu_add_vm_change_state_handler(cpu_update_state, env);
871
872 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
873 if (c) {
874 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
875 !!(c->ecx & CPUID_EXT_SMX);
876 }
877
878 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
879 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
880 /* for migration */
881 error_setg(&invtsc_mig_blocker,
882 "State blocked by non-migratable CPU device"
883 " (invtsc flag)");
884 migrate_add_blocker(invtsc_mig_blocker);
885 /* for savevm */
886 vmstate_x86_cpu.unmigratable = 1;
887 }
888
889 cpuid_data.cpuid.padding = 0;
890 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
891 if (r) {
892 return r;
893 }
894
895 r = kvm_arch_set_tsc_khz(cs);
896 if (r < 0) {
897 return r;
898 }
899
900 /* vcpu's TSC frequency is either specified by user, or following
901 * the value used by KVM if the former is not present. In the
902 * latter case, we query it from KVM and record in env->tsc_khz,
903 * so that vcpu's TSC frequency can be migrated later via this field.
904 */
905 if (!env->tsc_khz) {
906 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
907 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
908 -ENOTSUP;
909 if (r > 0) {
910 env->tsc_khz = r;
911 }
912 }
913
914 if (has_xsave) {
915 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
916 }
917
918 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
919 has_msr_mtrr = true;
920 }
921 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
922 has_msr_tsc_aux = false;
923 }
924
925 return 0;
926 }
927
928 void kvm_arch_reset_vcpu(X86CPU *cpu)
929 {
930 CPUX86State *env = &cpu->env;
931
932 env->exception_injected = -1;
933 env->interrupt_injected = -1;
934 env->xcr0 = 1;
935 if (kvm_irqchip_in_kernel()) {
936 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
937 KVM_MP_STATE_UNINITIALIZED;
938 } else {
939 env->mp_state = KVM_MP_STATE_RUNNABLE;
940 }
941 }
942
943 void kvm_arch_do_init_vcpu(X86CPU *cpu)
944 {
945 CPUX86State *env = &cpu->env;
946
947 /* APs get directly into wait-for-SIPI state. */
948 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
949 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
950 }
951 }
952
953 static int kvm_get_supported_msrs(KVMState *s)
954 {
955 static int kvm_supported_msrs;
956 int ret = 0;
957
958 /* first time */
959 if (kvm_supported_msrs == 0) {
960 struct kvm_msr_list msr_list, *kvm_msr_list;
961
962 kvm_supported_msrs = -1;
963
964 /* Obtain MSR list from KVM. These are the MSRs that we must
965 * save/restore */
966 msr_list.nmsrs = 0;
967 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
968 if (ret < 0 && ret != -E2BIG) {
969 return ret;
970 }
971 /* Old kernel modules had a bug and could write beyond the provided
972 memory. Allocate at least a safe amount of 1K. */
973 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
974 msr_list.nmsrs *
975 sizeof(msr_list.indices[0])));
976
977 kvm_msr_list->nmsrs = msr_list.nmsrs;
978 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
979 if (ret >= 0) {
980 int i;
981
982 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
983 if (kvm_msr_list->indices[i] == MSR_STAR) {
984 has_msr_star = true;
985 continue;
986 }
987 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
988 has_msr_hsave_pa = true;
989 continue;
990 }
991 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
992 has_msr_tsc_aux = true;
993 continue;
994 }
995 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
996 has_msr_tsc_adjust = true;
997 continue;
998 }
999 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1000 has_msr_tsc_deadline = true;
1001 continue;
1002 }
1003 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1004 has_msr_smbase = true;
1005 continue;
1006 }
1007 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1008 has_msr_misc_enable = true;
1009 continue;
1010 }
1011 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1012 has_msr_bndcfgs = true;
1013 continue;
1014 }
1015 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1016 has_msr_xss = true;
1017 continue;
1018 }
1019 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1020 has_msr_hv_crash = true;
1021 continue;
1022 }
1023 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1024 has_msr_hv_reset = true;
1025 continue;
1026 }
1027 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1028 has_msr_hv_vpindex = true;
1029 continue;
1030 }
1031 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1032 has_msr_hv_runtime = true;
1033 continue;
1034 }
1035 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1036 has_msr_hv_synic = true;
1037 continue;
1038 }
1039 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1040 has_msr_hv_stimer = true;
1041 continue;
1042 }
1043 }
1044 }
1045
1046 g_free(kvm_msr_list);
1047 }
1048
1049 return ret;
1050 }
1051
1052 static Notifier smram_machine_done;
1053 static KVMMemoryListener smram_listener;
1054 static AddressSpace smram_address_space;
1055 static MemoryRegion smram_as_root;
1056 static MemoryRegion smram_as_mem;
1057
1058 static void register_smram_listener(Notifier *n, void *unused)
1059 {
1060 MemoryRegion *smram =
1061 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1062
1063 /* Outer container... */
1064 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1065 memory_region_set_enabled(&smram_as_root, true);
1066
1067 /* ... with two regions inside: normal system memory with low
1068 * priority, and...
1069 */
1070 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1071 get_system_memory(), 0, ~0ull);
1072 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1073 memory_region_set_enabled(&smram_as_mem, true);
1074
1075 if (smram) {
1076 /* ... SMRAM with higher priority */
1077 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1078 memory_region_set_enabled(smram, true);
1079 }
1080
1081 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1082 kvm_memory_listener_register(kvm_state, &smram_listener,
1083 &smram_address_space, 1);
1084 }
1085
1086 int kvm_arch_init(MachineState *ms, KVMState *s)
1087 {
1088 uint64_t identity_base = 0xfffbc000;
1089 uint64_t shadow_mem;
1090 int ret;
1091 struct utsname utsname;
1092
1093 #ifdef KVM_CAP_XSAVE
1094 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1095 #endif
1096
1097 #ifdef KVM_CAP_XCRS
1098 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1099 #endif
1100
1101 #ifdef KVM_CAP_PIT_STATE2
1102 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1103 #endif
1104
1105 ret = kvm_get_supported_msrs(s);
1106 if (ret < 0) {
1107 return ret;
1108 }
1109
1110 uname(&utsname);
1111 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1112
1113 /*
1114 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1115 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1116 * Since these must be part of guest physical memory, we need to allocate
1117 * them, both by setting their start addresses in the kernel and by
1118 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1119 *
1120 * Older KVM versions may not support setting the identity map base. In
1121 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1122 * size.
1123 */
1124 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1125 /* Allows up to 16M BIOSes. */
1126 identity_base = 0xfeffc000;
1127
1128 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1129 if (ret < 0) {
1130 return ret;
1131 }
1132 }
1133
1134 /* Set TSS base one page after EPT identity map. */
1135 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1136 if (ret < 0) {
1137 return ret;
1138 }
1139
1140 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1141 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1142 if (ret < 0) {
1143 fprintf(stderr, "e820_add_entry() table is full\n");
1144 return ret;
1145 }
1146 qemu_register_reset(kvm_unpoison_all, NULL);
1147
1148 shadow_mem = machine_kvm_shadow_mem(ms);
1149 if (shadow_mem != -1) {
1150 shadow_mem /= 4096;
1151 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1152 if (ret < 0) {
1153 return ret;
1154 }
1155 }
1156
1157 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1158 smram_machine_done.notify = register_smram_listener;
1159 qemu_add_machine_init_done_notifier(&smram_machine_done);
1160 }
1161 return 0;
1162 }
1163
1164 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1165 {
1166 lhs->selector = rhs->selector;
1167 lhs->base = rhs->base;
1168 lhs->limit = rhs->limit;
1169 lhs->type = 3;
1170 lhs->present = 1;
1171 lhs->dpl = 3;
1172 lhs->db = 0;
1173 lhs->s = 1;
1174 lhs->l = 0;
1175 lhs->g = 0;
1176 lhs->avl = 0;
1177 lhs->unusable = 0;
1178 }
1179
1180 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1181 {
1182 unsigned flags = rhs->flags;
1183 lhs->selector = rhs->selector;
1184 lhs->base = rhs->base;
1185 lhs->limit = rhs->limit;
1186 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1187 lhs->present = (flags & DESC_P_MASK) != 0;
1188 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1189 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1190 lhs->s = (flags & DESC_S_MASK) != 0;
1191 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1192 lhs->g = (flags & DESC_G_MASK) != 0;
1193 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1194 lhs->unusable = !lhs->present;
1195 lhs->padding = 0;
1196 }
1197
1198 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1199 {
1200 lhs->selector = rhs->selector;
1201 lhs->base = rhs->base;
1202 lhs->limit = rhs->limit;
1203 if (rhs->unusable) {
1204 lhs->flags = 0;
1205 } else {
1206 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1207 (rhs->present * DESC_P_MASK) |
1208 (rhs->dpl << DESC_DPL_SHIFT) |
1209 (rhs->db << DESC_B_SHIFT) |
1210 (rhs->s * DESC_S_MASK) |
1211 (rhs->l << DESC_L_SHIFT) |
1212 (rhs->g * DESC_G_MASK) |
1213 (rhs->avl * DESC_AVL_MASK);
1214 }
1215 }
1216
1217 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1218 {
1219 if (set) {
1220 *kvm_reg = *qemu_reg;
1221 } else {
1222 *qemu_reg = *kvm_reg;
1223 }
1224 }
1225
1226 static int kvm_getput_regs(X86CPU *cpu, int set)
1227 {
1228 CPUX86State *env = &cpu->env;
1229 struct kvm_regs regs;
1230 int ret = 0;
1231
1232 if (!set) {
1233 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1234 if (ret < 0) {
1235 return ret;
1236 }
1237 }
1238
1239 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1240 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1241 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1242 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1243 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1244 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1245 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1246 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1247 #ifdef TARGET_X86_64
1248 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1249 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1250 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1251 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1252 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1253 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1254 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1255 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1256 #endif
1257
1258 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1259 kvm_getput_reg(&regs.rip, &env->eip, set);
1260
1261 if (set) {
1262 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1263 }
1264
1265 return ret;
1266 }
1267
1268 static int kvm_put_fpu(X86CPU *cpu)
1269 {
1270 CPUX86State *env = &cpu->env;
1271 struct kvm_fpu fpu;
1272 int i;
1273
1274 memset(&fpu, 0, sizeof fpu);
1275 fpu.fsw = env->fpus & ~(7 << 11);
1276 fpu.fsw |= (env->fpstt & 7) << 11;
1277 fpu.fcw = env->fpuc;
1278 fpu.last_opcode = env->fpop;
1279 fpu.last_ip = env->fpip;
1280 fpu.last_dp = env->fpdp;
1281 for (i = 0; i < 8; ++i) {
1282 fpu.ftwx |= (!env->fptags[i]) << i;
1283 }
1284 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1285 for (i = 0; i < CPU_NB_REGS; i++) {
1286 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1287 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1288 }
1289 fpu.mxcsr = env->mxcsr;
1290
1291 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1292 }
1293
1294 #define XSAVE_FCW_FSW 0
1295 #define XSAVE_FTW_FOP 1
1296 #define XSAVE_CWD_RIP 2
1297 #define XSAVE_CWD_RDP 4
1298 #define XSAVE_MXCSR 6
1299 #define XSAVE_ST_SPACE 8
1300 #define XSAVE_XMM_SPACE 40
1301 #define XSAVE_XSTATE_BV 128
1302 #define XSAVE_YMMH_SPACE 144
1303 #define XSAVE_BNDREGS 240
1304 #define XSAVE_BNDCSR 256
1305 #define XSAVE_OPMASK 272
1306 #define XSAVE_ZMM_Hi256 288
1307 #define XSAVE_Hi16_ZMM 416
1308 #define XSAVE_PKRU 672
1309
1310 #define XSAVE_BYTE_OFFSET(word_offset) \
1311 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1312
1313 #define ASSERT_OFFSET(word_offset, field) \
1314 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1315 offsetof(X86XSaveArea, field))
1316
1317 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1318 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1319 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1320 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1321 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1322 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1323 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1324 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1325 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1326 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1327 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1328 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1329 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1330 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1331 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1332
1333 static int kvm_put_xsave(X86CPU *cpu)
1334 {
1335 CPUX86State *env = &cpu->env;
1336 X86XSaveArea *xsave = env->kvm_xsave_buf;
1337 uint16_t cwd, swd, twd;
1338 int i, r;
1339
1340 if (!has_xsave) {
1341 return kvm_put_fpu(cpu);
1342 }
1343
1344 memset(xsave, 0, sizeof(struct kvm_xsave));
1345 twd = 0;
1346 swd = env->fpus & ~(7 << 11);
1347 swd |= (env->fpstt & 7) << 11;
1348 cwd = env->fpuc;
1349 for (i = 0; i < 8; ++i) {
1350 twd |= (!env->fptags[i]) << i;
1351 }
1352 xsave->legacy.fcw = cwd;
1353 xsave->legacy.fsw = swd;
1354 xsave->legacy.ftw = twd;
1355 xsave->legacy.fpop = env->fpop;
1356 xsave->legacy.fpip = env->fpip;
1357 xsave->legacy.fpdp = env->fpdp;
1358 memcpy(&xsave->legacy.fpregs, env->fpregs,
1359 sizeof env->fpregs);
1360 xsave->legacy.mxcsr = env->mxcsr;
1361 xsave->header.xstate_bv = env->xstate_bv;
1362 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1363 sizeof env->bnd_regs);
1364 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1365 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1366 sizeof env->opmask_regs);
1367
1368 for (i = 0; i < CPU_NB_REGS; i++) {
1369 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1370 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1371 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1372 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1373 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1374 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1375 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1376 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1377 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1378 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1379 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1380 }
1381
1382 #ifdef TARGET_X86_64
1383 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1384 16 * sizeof env->xmm_regs[16]);
1385 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1386 #endif
1387 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1388 return r;
1389 }
1390
1391 static int kvm_put_xcrs(X86CPU *cpu)
1392 {
1393 CPUX86State *env = &cpu->env;
1394 struct kvm_xcrs xcrs = {};
1395
1396 if (!has_xcrs) {
1397 return 0;
1398 }
1399
1400 xcrs.nr_xcrs = 1;
1401 xcrs.flags = 0;
1402 xcrs.xcrs[0].xcr = 0;
1403 xcrs.xcrs[0].value = env->xcr0;
1404 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1405 }
1406
1407 static int kvm_put_sregs(X86CPU *cpu)
1408 {
1409 CPUX86State *env = &cpu->env;
1410 struct kvm_sregs sregs;
1411
1412 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1413 if (env->interrupt_injected >= 0) {
1414 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1415 (uint64_t)1 << (env->interrupt_injected % 64);
1416 }
1417
1418 if ((env->eflags & VM_MASK)) {
1419 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1420 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1421 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1422 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1423 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1424 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1425 } else {
1426 set_seg(&sregs.cs, &env->segs[R_CS]);
1427 set_seg(&sregs.ds, &env->segs[R_DS]);
1428 set_seg(&sregs.es, &env->segs[R_ES]);
1429 set_seg(&sregs.fs, &env->segs[R_FS]);
1430 set_seg(&sregs.gs, &env->segs[R_GS]);
1431 set_seg(&sregs.ss, &env->segs[R_SS]);
1432 }
1433
1434 set_seg(&sregs.tr, &env->tr);
1435 set_seg(&sregs.ldt, &env->ldt);
1436
1437 sregs.idt.limit = env->idt.limit;
1438 sregs.idt.base = env->idt.base;
1439 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1440 sregs.gdt.limit = env->gdt.limit;
1441 sregs.gdt.base = env->gdt.base;
1442 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1443
1444 sregs.cr0 = env->cr[0];
1445 sregs.cr2 = env->cr[2];
1446 sregs.cr3 = env->cr[3];
1447 sregs.cr4 = env->cr[4];
1448
1449 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1450 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1451
1452 sregs.efer = env->efer;
1453
1454 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1455 }
1456
1457 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1458 uint32_t index, uint64_t value)
1459 {
1460 entry->index = index;
1461 entry->reserved = 0;
1462 entry->data = value;
1463 }
1464
1465 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1466 {
1467 CPUX86State *env = &cpu->env;
1468 struct {
1469 struct kvm_msrs info;
1470 struct kvm_msr_entry entries[1];
1471 } msr_data;
1472 struct kvm_msr_entry *msrs = msr_data.entries;
1473 int ret;
1474
1475 if (!has_msr_tsc_deadline) {
1476 return 0;
1477 }
1478
1479 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1480
1481 msr_data.info = (struct kvm_msrs) {
1482 .nmsrs = 1,
1483 };
1484
1485 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1486 if (ret < 0) {
1487 return ret;
1488 }
1489
1490 assert(ret == 1);
1491 return 0;
1492 }
1493
1494 /*
1495 * Provide a separate write service for the feature control MSR in order to
1496 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1497 * before writing any other state because forcibly leaving nested mode
1498 * invalidates the VCPU state.
1499 */
1500 static int kvm_put_msr_feature_control(X86CPU *cpu)
1501 {
1502 struct {
1503 struct kvm_msrs info;
1504 struct kvm_msr_entry entry;
1505 } msr_data;
1506 int ret;
1507
1508 if (!has_msr_feature_control) {
1509 return 0;
1510 }
1511
1512 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1513 cpu->env.msr_ia32_feature_control);
1514
1515 msr_data.info = (struct kvm_msrs) {
1516 .nmsrs = 1,
1517 };
1518
1519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1520 if (ret < 0) {
1521 return ret;
1522 }
1523
1524 assert(ret == 1);
1525 return 0;
1526 }
1527
1528 static int kvm_put_msrs(X86CPU *cpu, int level)
1529 {
1530 CPUX86State *env = &cpu->env;
1531 struct {
1532 struct kvm_msrs info;
1533 struct kvm_msr_entry entries[150];
1534 } msr_data;
1535 struct kvm_msr_entry *msrs = msr_data.entries;
1536 int n = 0, i;
1537 int ret;
1538
1539 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1540 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1541 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1542 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1543 if (has_msr_star) {
1544 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1545 }
1546 if (has_msr_hsave_pa) {
1547 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1548 }
1549 if (has_msr_tsc_aux) {
1550 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1551 }
1552 if (has_msr_tsc_adjust) {
1553 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1554 }
1555 if (has_msr_misc_enable) {
1556 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1557 env->msr_ia32_misc_enable);
1558 }
1559 if (has_msr_smbase) {
1560 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1561 }
1562 if (has_msr_bndcfgs) {
1563 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1564 }
1565 if (has_msr_xss) {
1566 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1567 }
1568 #ifdef TARGET_X86_64
1569 if (lm_capable_kernel) {
1570 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1571 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1572 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1573 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1574 }
1575 #endif
1576 /*
1577 * The following MSRs have side effects on the guest or are too heavy
1578 * for normal writeback. Limit them to reset or full state updates.
1579 */
1580 if (level >= KVM_PUT_RESET_STATE) {
1581 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1582 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1583 env->system_time_msr);
1584 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1585 if (has_msr_async_pf_en) {
1586 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1587 env->async_pf_en_msr);
1588 }
1589 if (has_msr_pv_eoi_en) {
1590 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1591 env->pv_eoi_en_msr);
1592 }
1593 if (has_msr_kvm_steal_time) {
1594 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1595 env->steal_time_msr);
1596 }
1597 if (has_msr_architectural_pmu) {
1598 /* Stop the counter. */
1599 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1600 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1601
1602 /* Set the counter values. */
1603 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1604 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1605 env->msr_fixed_counters[i]);
1606 }
1607 for (i = 0; i < num_architectural_pmu_counters; i++) {
1608 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1609 env->msr_gp_counters[i]);
1610 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1611 env->msr_gp_evtsel[i]);
1612 }
1613 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1614 env->msr_global_status);
1615 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1616 env->msr_global_ovf_ctrl);
1617
1618 /* Now start the PMU. */
1619 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1620 env->msr_fixed_ctr_ctrl);
1621 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1622 env->msr_global_ctrl);
1623 }
1624 if (has_msr_hv_hypercall) {
1625 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1626 env->msr_hv_guest_os_id);
1627 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1628 env->msr_hv_hypercall);
1629 }
1630 if (has_msr_hv_vapic) {
1631 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1632 env->msr_hv_vapic);
1633 }
1634 if (has_msr_hv_tsc) {
1635 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1636 env->msr_hv_tsc);
1637 }
1638 if (has_msr_hv_crash) {
1639 int j;
1640
1641 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1642 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1643 env->msr_hv_crash_params[j]);
1644
1645 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1646 HV_X64_MSR_CRASH_CTL_NOTIFY);
1647 }
1648 if (has_msr_hv_runtime) {
1649 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1650 env->msr_hv_runtime);
1651 }
1652 if (cpu->hyperv_synic) {
1653 int j;
1654
1655 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1656 env->msr_hv_synic_control);
1657 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1658 env->msr_hv_synic_version);
1659 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1660 env->msr_hv_synic_evt_page);
1661 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1662 env->msr_hv_synic_msg_page);
1663
1664 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1665 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1666 env->msr_hv_synic_sint[j]);
1667 }
1668 }
1669 if (has_msr_hv_stimer) {
1670 int j;
1671
1672 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1673 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1674 env->msr_hv_stimer_config[j]);
1675 }
1676
1677 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1678 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1679 env->msr_hv_stimer_count[j]);
1680 }
1681 }
1682 if (has_msr_mtrr) {
1683 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1684 kvm_msr_entry_set(&msrs[n++],
1685 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1686 kvm_msr_entry_set(&msrs[n++],
1687 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1688 kvm_msr_entry_set(&msrs[n++],
1689 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1690 kvm_msr_entry_set(&msrs[n++],
1691 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1692 kvm_msr_entry_set(&msrs[n++],
1693 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1694 kvm_msr_entry_set(&msrs[n++],
1695 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1696 kvm_msr_entry_set(&msrs[n++],
1697 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1698 kvm_msr_entry_set(&msrs[n++],
1699 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1700 kvm_msr_entry_set(&msrs[n++],
1701 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1702 kvm_msr_entry_set(&msrs[n++],
1703 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1704 kvm_msr_entry_set(&msrs[n++],
1705 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1706 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1707 kvm_msr_entry_set(&msrs[n++],
1708 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1709 kvm_msr_entry_set(&msrs[n++],
1710 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1711 }
1712 }
1713
1714 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1715 * kvm_put_msr_feature_control. */
1716 }
1717 if (env->mcg_cap) {
1718 int i;
1719
1720 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1721 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1722 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1723 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1724 }
1725 }
1726
1727 msr_data.info = (struct kvm_msrs) {
1728 .nmsrs = n,
1729 };
1730
1731 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1732 if (ret < 0) {
1733 return ret;
1734 }
1735
1736 assert(ret == n);
1737 return 0;
1738 }
1739
1740
1741 static int kvm_get_fpu(X86CPU *cpu)
1742 {
1743 CPUX86State *env = &cpu->env;
1744 struct kvm_fpu fpu;
1745 int i, ret;
1746
1747 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1748 if (ret < 0) {
1749 return ret;
1750 }
1751
1752 env->fpstt = (fpu.fsw >> 11) & 7;
1753 env->fpus = fpu.fsw;
1754 env->fpuc = fpu.fcw;
1755 env->fpop = fpu.last_opcode;
1756 env->fpip = fpu.last_ip;
1757 env->fpdp = fpu.last_dp;
1758 for (i = 0; i < 8; ++i) {
1759 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1760 }
1761 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1762 for (i = 0; i < CPU_NB_REGS; i++) {
1763 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1764 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1765 }
1766 env->mxcsr = fpu.mxcsr;
1767
1768 return 0;
1769 }
1770
1771 static int kvm_get_xsave(X86CPU *cpu)
1772 {
1773 CPUX86State *env = &cpu->env;
1774 X86XSaveArea *xsave = env->kvm_xsave_buf;
1775 int ret, i;
1776 uint16_t cwd, swd, twd;
1777
1778 if (!has_xsave) {
1779 return kvm_get_fpu(cpu);
1780 }
1781
1782 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1783 if (ret < 0) {
1784 return ret;
1785 }
1786
1787 cwd = xsave->legacy.fcw;
1788 swd = xsave->legacy.fsw;
1789 twd = xsave->legacy.ftw;
1790 env->fpop = xsave->legacy.fpop;
1791 env->fpstt = (swd >> 11) & 7;
1792 env->fpus = swd;
1793 env->fpuc = cwd;
1794 for (i = 0; i < 8; ++i) {
1795 env->fptags[i] = !((twd >> i) & 1);
1796 }
1797 env->fpip = xsave->legacy.fpip;
1798 env->fpdp = xsave->legacy.fpdp;
1799 env->mxcsr = xsave->legacy.mxcsr;
1800 memcpy(env->fpregs, &xsave->legacy.fpregs,
1801 sizeof env->fpregs);
1802 env->xstate_bv = xsave->header.xstate_bv;
1803 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1804 sizeof env->bnd_regs);
1805 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1806 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1807 sizeof env->opmask_regs);
1808
1809 for (i = 0; i < CPU_NB_REGS; i++) {
1810 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1811 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1812 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1813 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1814 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1815 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1816 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1817 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1818 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1819 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1820 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1821 }
1822
1823 #ifdef TARGET_X86_64
1824 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1825 16 * sizeof env->xmm_regs[16]);
1826 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1827 #endif
1828 return 0;
1829 }
1830
1831 static int kvm_get_xcrs(X86CPU *cpu)
1832 {
1833 CPUX86State *env = &cpu->env;
1834 int i, ret;
1835 struct kvm_xcrs xcrs;
1836
1837 if (!has_xcrs) {
1838 return 0;
1839 }
1840
1841 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1842 if (ret < 0) {
1843 return ret;
1844 }
1845
1846 for (i = 0; i < xcrs.nr_xcrs; i++) {
1847 /* Only support xcr0 now */
1848 if (xcrs.xcrs[i].xcr == 0) {
1849 env->xcr0 = xcrs.xcrs[i].value;
1850 break;
1851 }
1852 }
1853 return 0;
1854 }
1855
1856 static int kvm_get_sregs(X86CPU *cpu)
1857 {
1858 CPUX86State *env = &cpu->env;
1859 struct kvm_sregs sregs;
1860 uint32_t hflags;
1861 int bit, i, ret;
1862
1863 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1864 if (ret < 0) {
1865 return ret;
1866 }
1867
1868 /* There can only be one pending IRQ set in the bitmap at a time, so try
1869 to find it and save its number instead (-1 for none). */
1870 env->interrupt_injected = -1;
1871 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1872 if (sregs.interrupt_bitmap[i]) {
1873 bit = ctz64(sregs.interrupt_bitmap[i]);
1874 env->interrupt_injected = i * 64 + bit;
1875 break;
1876 }
1877 }
1878
1879 get_seg(&env->segs[R_CS], &sregs.cs);
1880 get_seg(&env->segs[R_DS], &sregs.ds);
1881 get_seg(&env->segs[R_ES], &sregs.es);
1882 get_seg(&env->segs[R_FS], &sregs.fs);
1883 get_seg(&env->segs[R_GS], &sregs.gs);
1884 get_seg(&env->segs[R_SS], &sregs.ss);
1885
1886 get_seg(&env->tr, &sregs.tr);
1887 get_seg(&env->ldt, &sregs.ldt);
1888
1889 env->idt.limit = sregs.idt.limit;
1890 env->idt.base = sregs.idt.base;
1891 env->gdt.limit = sregs.gdt.limit;
1892 env->gdt.base = sregs.gdt.base;
1893
1894 env->cr[0] = sregs.cr0;
1895 env->cr[2] = sregs.cr2;
1896 env->cr[3] = sregs.cr3;
1897 env->cr[4] = sregs.cr4;
1898
1899 env->efer = sregs.efer;
1900
1901 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1902
1903 #define HFLAG_COPY_MASK \
1904 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1905 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1906 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1907 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1908
1909 hflags = env->hflags & HFLAG_COPY_MASK;
1910 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1911 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1912 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1913 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1914 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1915
1916 if (env->cr[4] & CR4_OSFXSR_MASK) {
1917 hflags |= HF_OSFXSR_MASK;
1918 }
1919
1920 if (env->efer & MSR_EFER_LMA) {
1921 hflags |= HF_LMA_MASK;
1922 }
1923
1924 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1925 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1926 } else {
1927 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1928 (DESC_B_SHIFT - HF_CS32_SHIFT);
1929 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1930 (DESC_B_SHIFT - HF_SS32_SHIFT);
1931 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1932 !(hflags & HF_CS32_MASK)) {
1933 hflags |= HF_ADDSEG_MASK;
1934 } else {
1935 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1936 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1937 }
1938 }
1939 env->hflags = hflags;
1940
1941 return 0;
1942 }
1943
1944 static int kvm_get_msrs(X86CPU *cpu)
1945 {
1946 CPUX86State *env = &cpu->env;
1947 struct {
1948 struct kvm_msrs info;
1949 struct kvm_msr_entry entries[150];
1950 } msr_data;
1951 struct kvm_msr_entry *msrs = msr_data.entries;
1952 int ret, i, n;
1953
1954 n = 0;
1955 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1956 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1957 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1958 msrs[n++].index = MSR_PAT;
1959 if (has_msr_star) {
1960 msrs[n++].index = MSR_STAR;
1961 }
1962 if (has_msr_hsave_pa) {
1963 msrs[n++].index = MSR_VM_HSAVE_PA;
1964 }
1965 if (has_msr_tsc_aux) {
1966 msrs[n++].index = MSR_TSC_AUX;
1967 }
1968 if (has_msr_tsc_adjust) {
1969 msrs[n++].index = MSR_TSC_ADJUST;
1970 }
1971 if (has_msr_tsc_deadline) {
1972 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1973 }
1974 if (has_msr_misc_enable) {
1975 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1976 }
1977 if (has_msr_smbase) {
1978 msrs[n++].index = MSR_IA32_SMBASE;
1979 }
1980 if (has_msr_feature_control) {
1981 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1982 }
1983 if (has_msr_bndcfgs) {
1984 msrs[n++].index = MSR_IA32_BNDCFGS;
1985 }
1986 if (has_msr_xss) {
1987 msrs[n++].index = MSR_IA32_XSS;
1988 }
1989
1990
1991 if (!env->tsc_valid) {
1992 msrs[n++].index = MSR_IA32_TSC;
1993 env->tsc_valid = !runstate_is_running();
1994 }
1995
1996 #ifdef TARGET_X86_64
1997 if (lm_capable_kernel) {
1998 msrs[n++].index = MSR_CSTAR;
1999 msrs[n++].index = MSR_KERNELGSBASE;
2000 msrs[n++].index = MSR_FMASK;
2001 msrs[n++].index = MSR_LSTAR;
2002 }
2003 #endif
2004 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
2005 msrs[n++].index = MSR_KVM_WALL_CLOCK;
2006 if (has_msr_async_pf_en) {
2007 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
2008 }
2009 if (has_msr_pv_eoi_en) {
2010 msrs[n++].index = MSR_KVM_PV_EOI_EN;
2011 }
2012 if (has_msr_kvm_steal_time) {
2013 msrs[n++].index = MSR_KVM_STEAL_TIME;
2014 }
2015 if (has_msr_architectural_pmu) {
2016 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
2017 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
2018 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
2019 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
2020 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2021 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
2022 }
2023 for (i = 0; i < num_architectural_pmu_counters; i++) {
2024 msrs[n++].index = MSR_P6_PERFCTR0 + i;
2025 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
2026 }
2027 }
2028
2029 if (env->mcg_cap) {
2030 msrs[n++].index = MSR_MCG_STATUS;
2031 msrs[n++].index = MSR_MCG_CTL;
2032 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2033 msrs[n++].index = MSR_MC0_CTL + i;
2034 }
2035 }
2036
2037 if (has_msr_hv_hypercall) {
2038 msrs[n++].index = HV_X64_MSR_HYPERCALL;
2039 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
2040 }
2041 if (has_msr_hv_vapic) {
2042 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
2043 }
2044 if (has_msr_hv_tsc) {
2045 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
2046 }
2047 if (has_msr_hv_crash) {
2048 int j;
2049
2050 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2051 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
2052 }
2053 }
2054 if (has_msr_hv_runtime) {
2055 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
2056 }
2057 if (cpu->hyperv_synic) {
2058 uint32_t msr;
2059
2060 msrs[n++].index = HV_X64_MSR_SCONTROL;
2061 msrs[n++].index = HV_X64_MSR_SVERSION;
2062 msrs[n++].index = HV_X64_MSR_SIEFP;
2063 msrs[n++].index = HV_X64_MSR_SIMP;
2064 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2065 msrs[n++].index = msr;
2066 }
2067 }
2068 if (has_msr_hv_stimer) {
2069 uint32_t msr;
2070
2071 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2072 msr++) {
2073 msrs[n++].index = msr;
2074 }
2075 }
2076 if (has_msr_mtrr) {
2077 msrs[n++].index = MSR_MTRRdefType;
2078 msrs[n++].index = MSR_MTRRfix64K_00000;
2079 msrs[n++].index = MSR_MTRRfix16K_80000;
2080 msrs[n++].index = MSR_MTRRfix16K_A0000;
2081 msrs[n++].index = MSR_MTRRfix4K_C0000;
2082 msrs[n++].index = MSR_MTRRfix4K_C8000;
2083 msrs[n++].index = MSR_MTRRfix4K_D0000;
2084 msrs[n++].index = MSR_MTRRfix4K_D8000;
2085 msrs[n++].index = MSR_MTRRfix4K_E0000;
2086 msrs[n++].index = MSR_MTRRfix4K_E8000;
2087 msrs[n++].index = MSR_MTRRfix4K_F0000;
2088 msrs[n++].index = MSR_MTRRfix4K_F8000;
2089 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2090 msrs[n++].index = MSR_MTRRphysBase(i);
2091 msrs[n++].index = MSR_MTRRphysMask(i);
2092 }
2093 }
2094
2095 msr_data.info = (struct kvm_msrs) {
2096 .nmsrs = n,
2097 };
2098
2099 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2100 if (ret < 0) {
2101 return ret;
2102 }
2103
2104 assert(ret == n);
2105 for (i = 0; i < ret; i++) {
2106 uint32_t index = msrs[i].index;
2107 switch (index) {
2108 case MSR_IA32_SYSENTER_CS:
2109 env->sysenter_cs = msrs[i].data;
2110 break;
2111 case MSR_IA32_SYSENTER_ESP:
2112 env->sysenter_esp = msrs[i].data;
2113 break;
2114 case MSR_IA32_SYSENTER_EIP:
2115 env->sysenter_eip = msrs[i].data;
2116 break;
2117 case MSR_PAT:
2118 env->pat = msrs[i].data;
2119 break;
2120 case MSR_STAR:
2121 env->star = msrs[i].data;
2122 break;
2123 #ifdef TARGET_X86_64
2124 case MSR_CSTAR:
2125 env->cstar = msrs[i].data;
2126 break;
2127 case MSR_KERNELGSBASE:
2128 env->kernelgsbase = msrs[i].data;
2129 break;
2130 case MSR_FMASK:
2131 env->fmask = msrs[i].data;
2132 break;
2133 case MSR_LSTAR:
2134 env->lstar = msrs[i].data;
2135 break;
2136 #endif
2137 case MSR_IA32_TSC:
2138 env->tsc = msrs[i].data;
2139 break;
2140 case MSR_TSC_AUX:
2141 env->tsc_aux = msrs[i].data;
2142 break;
2143 case MSR_TSC_ADJUST:
2144 env->tsc_adjust = msrs[i].data;
2145 break;
2146 case MSR_IA32_TSCDEADLINE:
2147 env->tsc_deadline = msrs[i].data;
2148 break;
2149 case MSR_VM_HSAVE_PA:
2150 env->vm_hsave = msrs[i].data;
2151 break;
2152 case MSR_KVM_SYSTEM_TIME:
2153 env->system_time_msr = msrs[i].data;
2154 break;
2155 case MSR_KVM_WALL_CLOCK:
2156 env->wall_clock_msr = msrs[i].data;
2157 break;
2158 case MSR_MCG_STATUS:
2159 env->mcg_status = msrs[i].data;
2160 break;
2161 case MSR_MCG_CTL:
2162 env->mcg_ctl = msrs[i].data;
2163 break;
2164 case MSR_IA32_MISC_ENABLE:
2165 env->msr_ia32_misc_enable = msrs[i].data;
2166 break;
2167 case MSR_IA32_SMBASE:
2168 env->smbase = msrs[i].data;
2169 break;
2170 case MSR_IA32_FEATURE_CONTROL:
2171 env->msr_ia32_feature_control = msrs[i].data;
2172 break;
2173 case MSR_IA32_BNDCFGS:
2174 env->msr_bndcfgs = msrs[i].data;
2175 break;
2176 case MSR_IA32_XSS:
2177 env->xss = msrs[i].data;
2178 break;
2179 default:
2180 if (msrs[i].index >= MSR_MC0_CTL &&
2181 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2182 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2183 }
2184 break;
2185 case MSR_KVM_ASYNC_PF_EN:
2186 env->async_pf_en_msr = msrs[i].data;
2187 break;
2188 case MSR_KVM_PV_EOI_EN:
2189 env->pv_eoi_en_msr = msrs[i].data;
2190 break;
2191 case MSR_KVM_STEAL_TIME:
2192 env->steal_time_msr = msrs[i].data;
2193 break;
2194 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2195 env->msr_fixed_ctr_ctrl = msrs[i].data;
2196 break;
2197 case MSR_CORE_PERF_GLOBAL_CTRL:
2198 env->msr_global_ctrl = msrs[i].data;
2199 break;
2200 case MSR_CORE_PERF_GLOBAL_STATUS:
2201 env->msr_global_status = msrs[i].data;
2202 break;
2203 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2204 env->msr_global_ovf_ctrl = msrs[i].data;
2205 break;
2206 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2207 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2208 break;
2209 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2210 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2211 break;
2212 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2213 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2214 break;
2215 case HV_X64_MSR_HYPERCALL:
2216 env->msr_hv_hypercall = msrs[i].data;
2217 break;
2218 case HV_X64_MSR_GUEST_OS_ID:
2219 env->msr_hv_guest_os_id = msrs[i].data;
2220 break;
2221 case HV_X64_MSR_APIC_ASSIST_PAGE:
2222 env->msr_hv_vapic = msrs[i].data;
2223 break;
2224 case HV_X64_MSR_REFERENCE_TSC:
2225 env->msr_hv_tsc = msrs[i].data;
2226 break;
2227 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2228 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2229 break;
2230 case HV_X64_MSR_VP_RUNTIME:
2231 env->msr_hv_runtime = msrs[i].data;
2232 break;
2233 case HV_X64_MSR_SCONTROL:
2234 env->msr_hv_synic_control = msrs[i].data;
2235 break;
2236 case HV_X64_MSR_SVERSION:
2237 env->msr_hv_synic_version = msrs[i].data;
2238 break;
2239 case HV_X64_MSR_SIEFP:
2240 env->msr_hv_synic_evt_page = msrs[i].data;
2241 break;
2242 case HV_X64_MSR_SIMP:
2243 env->msr_hv_synic_msg_page = msrs[i].data;
2244 break;
2245 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2246 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2247 break;
2248 case HV_X64_MSR_STIMER0_CONFIG:
2249 case HV_X64_MSR_STIMER1_CONFIG:
2250 case HV_X64_MSR_STIMER2_CONFIG:
2251 case HV_X64_MSR_STIMER3_CONFIG:
2252 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2253 msrs[i].data;
2254 break;
2255 case HV_X64_MSR_STIMER0_COUNT:
2256 case HV_X64_MSR_STIMER1_COUNT:
2257 case HV_X64_MSR_STIMER2_COUNT:
2258 case HV_X64_MSR_STIMER3_COUNT:
2259 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2260 msrs[i].data;
2261 break;
2262 case MSR_MTRRdefType:
2263 env->mtrr_deftype = msrs[i].data;
2264 break;
2265 case MSR_MTRRfix64K_00000:
2266 env->mtrr_fixed[0] = msrs[i].data;
2267 break;
2268 case MSR_MTRRfix16K_80000:
2269 env->mtrr_fixed[1] = msrs[i].data;
2270 break;
2271 case MSR_MTRRfix16K_A0000:
2272 env->mtrr_fixed[2] = msrs[i].data;
2273 break;
2274 case MSR_MTRRfix4K_C0000:
2275 env->mtrr_fixed[3] = msrs[i].data;
2276 break;
2277 case MSR_MTRRfix4K_C8000:
2278 env->mtrr_fixed[4] = msrs[i].data;
2279 break;
2280 case MSR_MTRRfix4K_D0000:
2281 env->mtrr_fixed[5] = msrs[i].data;
2282 break;
2283 case MSR_MTRRfix4K_D8000:
2284 env->mtrr_fixed[6] = msrs[i].data;
2285 break;
2286 case MSR_MTRRfix4K_E0000:
2287 env->mtrr_fixed[7] = msrs[i].data;
2288 break;
2289 case MSR_MTRRfix4K_E8000:
2290 env->mtrr_fixed[8] = msrs[i].data;
2291 break;
2292 case MSR_MTRRfix4K_F0000:
2293 env->mtrr_fixed[9] = msrs[i].data;
2294 break;
2295 case MSR_MTRRfix4K_F8000:
2296 env->mtrr_fixed[10] = msrs[i].data;
2297 break;
2298 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2299 if (index & 1) {
2300 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2301 } else {
2302 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2303 }
2304 break;
2305 }
2306 }
2307
2308 return 0;
2309 }
2310
2311 static int kvm_put_mp_state(X86CPU *cpu)
2312 {
2313 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2314
2315 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2316 }
2317
2318 static int kvm_get_mp_state(X86CPU *cpu)
2319 {
2320 CPUState *cs = CPU(cpu);
2321 CPUX86State *env = &cpu->env;
2322 struct kvm_mp_state mp_state;
2323 int ret;
2324
2325 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2326 if (ret < 0) {
2327 return ret;
2328 }
2329 env->mp_state = mp_state.mp_state;
2330 if (kvm_irqchip_in_kernel()) {
2331 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2332 }
2333 return 0;
2334 }
2335
2336 static int kvm_get_apic(X86CPU *cpu)
2337 {
2338 DeviceState *apic = cpu->apic_state;
2339 struct kvm_lapic_state kapic;
2340 int ret;
2341
2342 if (apic && kvm_irqchip_in_kernel()) {
2343 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2344 if (ret < 0) {
2345 return ret;
2346 }
2347
2348 kvm_get_apic_state(apic, &kapic);
2349 }
2350 return 0;
2351 }
2352
2353 static int kvm_put_apic(X86CPU *cpu)
2354 {
2355 DeviceState *apic = cpu->apic_state;
2356 struct kvm_lapic_state kapic;
2357
2358 if (apic && kvm_irqchip_in_kernel()) {
2359 kvm_put_apic_state(apic, &kapic);
2360
2361 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2362 }
2363 return 0;
2364 }
2365
2366 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2367 {
2368 CPUState *cs = CPU(cpu);
2369 CPUX86State *env = &cpu->env;
2370 struct kvm_vcpu_events events = {};
2371
2372 if (!kvm_has_vcpu_events()) {
2373 return 0;
2374 }
2375
2376 events.exception.injected = (env->exception_injected >= 0);
2377 events.exception.nr = env->exception_injected;
2378 events.exception.has_error_code = env->has_error_code;
2379 events.exception.error_code = env->error_code;
2380 events.exception.pad = 0;
2381
2382 events.interrupt.injected = (env->interrupt_injected >= 0);
2383 events.interrupt.nr = env->interrupt_injected;
2384 events.interrupt.soft = env->soft_interrupt;
2385
2386 events.nmi.injected = env->nmi_injected;
2387 events.nmi.pending = env->nmi_pending;
2388 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2389 events.nmi.pad = 0;
2390
2391 events.sipi_vector = env->sipi_vector;
2392
2393 if (has_msr_smbase) {
2394 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2395 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2396 if (kvm_irqchip_in_kernel()) {
2397 /* As soon as these are moved to the kernel, remove them
2398 * from cs->interrupt_request.
2399 */
2400 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2401 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2402 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2403 } else {
2404 /* Keep these in cs->interrupt_request. */
2405 events.smi.pending = 0;
2406 events.smi.latched_init = 0;
2407 }
2408 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2409 }
2410
2411 events.flags = 0;
2412 if (level >= KVM_PUT_RESET_STATE) {
2413 events.flags |=
2414 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2415 }
2416
2417 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2418 }
2419
2420 static int kvm_get_vcpu_events(X86CPU *cpu)
2421 {
2422 CPUX86State *env = &cpu->env;
2423 struct kvm_vcpu_events events;
2424 int ret;
2425
2426 if (!kvm_has_vcpu_events()) {
2427 return 0;
2428 }
2429
2430 memset(&events, 0, sizeof(events));
2431 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2432 if (ret < 0) {
2433 return ret;
2434 }
2435 env->exception_injected =
2436 events.exception.injected ? events.exception.nr : -1;
2437 env->has_error_code = events.exception.has_error_code;
2438 env->error_code = events.exception.error_code;
2439
2440 env->interrupt_injected =
2441 events.interrupt.injected ? events.interrupt.nr : -1;
2442 env->soft_interrupt = events.interrupt.soft;
2443
2444 env->nmi_injected = events.nmi.injected;
2445 env->nmi_pending = events.nmi.pending;
2446 if (events.nmi.masked) {
2447 env->hflags2 |= HF2_NMI_MASK;
2448 } else {
2449 env->hflags2 &= ~HF2_NMI_MASK;
2450 }
2451
2452 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2453 if (events.smi.smm) {
2454 env->hflags |= HF_SMM_MASK;
2455 } else {
2456 env->hflags &= ~HF_SMM_MASK;
2457 }
2458 if (events.smi.pending) {
2459 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2460 } else {
2461 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2462 }
2463 if (events.smi.smm_inside_nmi) {
2464 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2465 } else {
2466 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2467 }
2468 if (events.smi.latched_init) {
2469 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2470 } else {
2471 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2472 }
2473 }
2474
2475 env->sipi_vector = events.sipi_vector;
2476
2477 return 0;
2478 }
2479
2480 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2481 {
2482 CPUState *cs = CPU(cpu);
2483 CPUX86State *env = &cpu->env;
2484 int ret = 0;
2485 unsigned long reinject_trap = 0;
2486
2487 if (!kvm_has_vcpu_events()) {
2488 if (env->exception_injected == 1) {
2489 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2490 } else if (env->exception_injected == 3) {
2491 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2492 }
2493 env->exception_injected = -1;
2494 }
2495
2496 /*
2497 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2498 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2499 * by updating the debug state once again if single-stepping is on.
2500 * Another reason to call kvm_update_guest_debug here is a pending debug
2501 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2502 * reinject them via SET_GUEST_DEBUG.
2503 */
2504 if (reinject_trap ||
2505 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2506 ret = kvm_update_guest_debug(cs, reinject_trap);
2507 }
2508 return ret;
2509 }
2510
2511 static int kvm_put_debugregs(X86CPU *cpu)
2512 {
2513 CPUX86State *env = &cpu->env;
2514 struct kvm_debugregs dbgregs;
2515 int i;
2516
2517 if (!kvm_has_debugregs()) {
2518 return 0;
2519 }
2520
2521 for (i = 0; i < 4; i++) {
2522 dbgregs.db[i] = env->dr[i];
2523 }
2524 dbgregs.dr6 = env->dr[6];
2525 dbgregs.dr7 = env->dr[7];
2526 dbgregs.flags = 0;
2527
2528 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2529 }
2530
2531 static int kvm_get_debugregs(X86CPU *cpu)
2532 {
2533 CPUX86State *env = &cpu->env;
2534 struct kvm_debugregs dbgregs;
2535 int i, ret;
2536
2537 if (!kvm_has_debugregs()) {
2538 return 0;
2539 }
2540
2541 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2542 if (ret < 0) {
2543 return ret;
2544 }
2545 for (i = 0; i < 4; i++) {
2546 env->dr[i] = dbgregs.db[i];
2547 }
2548 env->dr[4] = env->dr[6] = dbgregs.dr6;
2549 env->dr[5] = env->dr[7] = dbgregs.dr7;
2550
2551 return 0;
2552 }
2553
2554 int kvm_arch_put_registers(CPUState *cpu, int level)
2555 {
2556 X86CPU *x86_cpu = X86_CPU(cpu);
2557 int ret;
2558
2559 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2560
2561 if (level >= KVM_PUT_RESET_STATE) {
2562 ret = kvm_put_msr_feature_control(x86_cpu);
2563 if (ret < 0) {
2564 return ret;
2565 }
2566 }
2567
2568 if (level == KVM_PUT_FULL_STATE) {
2569 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2570 * because TSC frequency mismatch shouldn't abort migration,
2571 * unless the user explicitly asked for a more strict TSC
2572 * setting (e.g. using an explicit "tsc-freq" option).
2573 */
2574 kvm_arch_set_tsc_khz(cpu);
2575 }
2576
2577 ret = kvm_getput_regs(x86_cpu, 1);
2578 if (ret < 0) {
2579 return ret;
2580 }
2581 ret = kvm_put_xsave(x86_cpu);
2582 if (ret < 0) {
2583 return ret;
2584 }
2585 ret = kvm_put_xcrs(x86_cpu);
2586 if (ret < 0) {
2587 return ret;
2588 }
2589 ret = kvm_put_sregs(x86_cpu);
2590 if (ret < 0) {
2591 return ret;
2592 }
2593 /* must be before kvm_put_msrs */
2594 ret = kvm_inject_mce_oldstyle(x86_cpu);
2595 if (ret < 0) {
2596 return ret;
2597 }
2598 ret = kvm_put_msrs(x86_cpu, level);
2599 if (ret < 0) {
2600 return ret;
2601 }
2602 if (level >= KVM_PUT_RESET_STATE) {
2603 ret = kvm_put_mp_state(x86_cpu);
2604 if (ret < 0) {
2605 return ret;
2606 }
2607 ret = kvm_put_apic(x86_cpu);
2608 if (ret < 0) {
2609 return ret;
2610 }
2611 }
2612
2613 ret = kvm_put_tscdeadline_msr(x86_cpu);
2614 if (ret < 0) {
2615 return ret;
2616 }
2617
2618 ret = kvm_put_vcpu_events(x86_cpu, level);
2619 if (ret < 0) {
2620 return ret;
2621 }
2622 ret = kvm_put_debugregs(x86_cpu);
2623 if (ret < 0) {
2624 return ret;
2625 }
2626 /* must be last */
2627 ret = kvm_guest_debug_workarounds(x86_cpu);
2628 if (ret < 0) {
2629 return ret;
2630 }
2631 return 0;
2632 }
2633
2634 int kvm_arch_get_registers(CPUState *cs)
2635 {
2636 X86CPU *cpu = X86_CPU(cs);
2637 int ret;
2638
2639 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2640
2641 ret = kvm_getput_regs(cpu, 0);
2642 if (ret < 0) {
2643 goto out;
2644 }
2645 ret = kvm_get_xsave(cpu);
2646 if (ret < 0) {
2647 goto out;
2648 }
2649 ret = kvm_get_xcrs(cpu);
2650 if (ret < 0) {
2651 goto out;
2652 }
2653 ret = kvm_get_sregs(cpu);
2654 if (ret < 0) {
2655 goto out;
2656 }
2657 ret = kvm_get_msrs(cpu);
2658 if (ret < 0) {
2659 goto out;
2660 }
2661 ret = kvm_get_mp_state(cpu);
2662 if (ret < 0) {
2663 goto out;
2664 }
2665 ret = kvm_get_apic(cpu);
2666 if (ret < 0) {
2667 goto out;
2668 }
2669 ret = kvm_get_vcpu_events(cpu);
2670 if (ret < 0) {
2671 goto out;
2672 }
2673 ret = kvm_get_debugregs(cpu);
2674 if (ret < 0) {
2675 goto out;
2676 }
2677 ret = 0;
2678 out:
2679 cpu_sync_bndcs_hflags(&cpu->env);
2680 return ret;
2681 }
2682
2683 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2684 {
2685 X86CPU *x86_cpu = X86_CPU(cpu);
2686 CPUX86State *env = &x86_cpu->env;
2687 int ret;
2688
2689 /* Inject NMI */
2690 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2691 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2692 qemu_mutex_lock_iothread();
2693 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2694 qemu_mutex_unlock_iothread();
2695 DPRINTF("injected NMI\n");
2696 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2697 if (ret < 0) {
2698 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2699 strerror(-ret));
2700 }
2701 }
2702 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2703 qemu_mutex_lock_iothread();
2704 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2705 qemu_mutex_unlock_iothread();
2706 DPRINTF("injected SMI\n");
2707 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2708 if (ret < 0) {
2709 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2710 strerror(-ret));
2711 }
2712 }
2713 }
2714
2715 if (!kvm_pic_in_kernel()) {
2716 qemu_mutex_lock_iothread();
2717 }
2718
2719 /* Force the VCPU out of its inner loop to process any INIT requests
2720 * or (for userspace APIC, but it is cheap to combine the checks here)
2721 * pending TPR access reports.
2722 */
2723 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2724 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2725 !(env->hflags & HF_SMM_MASK)) {
2726 cpu->exit_request = 1;
2727 }
2728 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2729 cpu->exit_request = 1;
2730 }
2731 }
2732
2733 if (!kvm_pic_in_kernel()) {
2734 /* Try to inject an interrupt if the guest can accept it */
2735 if (run->ready_for_interrupt_injection &&
2736 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2737 (env->eflags & IF_MASK)) {
2738 int irq;
2739
2740 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2741 irq = cpu_get_pic_interrupt(env);
2742 if (irq >= 0) {
2743 struct kvm_interrupt intr;
2744
2745 intr.irq = irq;
2746 DPRINTF("injected interrupt %d\n", irq);
2747 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2748 if (ret < 0) {
2749 fprintf(stderr,
2750 "KVM: injection failed, interrupt lost (%s)\n",
2751 strerror(-ret));
2752 }
2753 }
2754 }
2755
2756 /* If we have an interrupt but the guest is not ready to receive an
2757 * interrupt, request an interrupt window exit. This will
2758 * cause a return to userspace as soon as the guest is ready to
2759 * receive interrupts. */
2760 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2761 run->request_interrupt_window = 1;
2762 } else {
2763 run->request_interrupt_window = 0;
2764 }
2765
2766 DPRINTF("setting tpr\n");
2767 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2768
2769 qemu_mutex_unlock_iothread();
2770 }
2771 }
2772
2773 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2774 {
2775 X86CPU *x86_cpu = X86_CPU(cpu);
2776 CPUX86State *env = &x86_cpu->env;
2777
2778 if (run->flags & KVM_RUN_X86_SMM) {
2779 env->hflags |= HF_SMM_MASK;
2780 } else {
2781 env->hflags &= HF_SMM_MASK;
2782 }
2783 if (run->if_flag) {
2784 env->eflags |= IF_MASK;
2785 } else {
2786 env->eflags &= ~IF_MASK;
2787 }
2788
2789 /* We need to protect the apic state against concurrent accesses from
2790 * different threads in case the userspace irqchip is used. */
2791 if (!kvm_irqchip_in_kernel()) {
2792 qemu_mutex_lock_iothread();
2793 }
2794 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2795 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2796 if (!kvm_irqchip_in_kernel()) {
2797 qemu_mutex_unlock_iothread();
2798 }
2799 return cpu_get_mem_attrs(env);
2800 }
2801
2802 int kvm_arch_process_async_events(CPUState *cs)
2803 {
2804 X86CPU *cpu = X86_CPU(cs);
2805 CPUX86State *env = &cpu->env;
2806
2807 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2808 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2809 assert(env->mcg_cap);
2810
2811 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2812
2813 kvm_cpu_synchronize_state(cs);
2814
2815 if (env->exception_injected == EXCP08_DBLE) {
2816 /* this means triple fault */
2817 qemu_system_reset_request();
2818 cs->exit_request = 1;
2819 return 0;
2820 }
2821 env->exception_injected = EXCP12_MCHK;
2822 env->has_error_code = 0;
2823
2824 cs->halted = 0;
2825 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2826 env->mp_state = KVM_MP_STATE_RUNNABLE;
2827 }
2828 }
2829
2830 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2831 !(env->hflags & HF_SMM_MASK)) {
2832 kvm_cpu_synchronize_state(cs);
2833 do_cpu_init(cpu);
2834 }
2835
2836 if (kvm_irqchip_in_kernel()) {
2837 return 0;
2838 }
2839
2840 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2841 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2842 apic_poll_irq(cpu->apic_state);
2843 }
2844 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2845 (env->eflags & IF_MASK)) ||
2846 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2847 cs->halted = 0;
2848 }
2849 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2850 kvm_cpu_synchronize_state(cs);
2851 do_cpu_sipi(cpu);
2852 }
2853 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2854 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2855 kvm_cpu_synchronize_state(cs);
2856 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2857 env->tpr_access_type);
2858 }
2859
2860 return cs->halted;
2861 }
2862
2863 static int kvm_handle_halt(X86CPU *cpu)
2864 {
2865 CPUState *cs = CPU(cpu);
2866 CPUX86State *env = &cpu->env;
2867
2868 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2869 (env->eflags & IF_MASK)) &&
2870 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2871 cs->halted = 1;
2872 return EXCP_HLT;
2873 }
2874
2875 return 0;
2876 }
2877
2878 static int kvm_handle_tpr_access(X86CPU *cpu)
2879 {
2880 CPUState *cs = CPU(cpu);
2881 struct kvm_run *run = cs->kvm_run;
2882
2883 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2884 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2885 : TPR_ACCESS_READ);
2886 return 1;
2887 }
2888
2889 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2890 {
2891 static const uint8_t int3 = 0xcc;
2892
2893 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2894 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2895 return -EINVAL;
2896 }
2897 return 0;
2898 }
2899
2900 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2901 {
2902 uint8_t int3;
2903
2904 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2905 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2906 return -EINVAL;
2907 }
2908 return 0;
2909 }
2910
2911 static struct {
2912 target_ulong addr;
2913 int len;
2914 int type;
2915 } hw_breakpoint[4];
2916
2917 static int nb_hw_breakpoint;
2918
2919 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2920 {
2921 int n;
2922
2923 for (n = 0; n < nb_hw_breakpoint; n++) {
2924 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2925 (hw_breakpoint[n].len == len || len == -1)) {
2926 return n;
2927 }
2928 }
2929 return -1;
2930 }
2931
2932 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2933 target_ulong len, int type)
2934 {
2935 switch (type) {
2936 case GDB_BREAKPOINT_HW:
2937 len = 1;
2938 break;
2939 case GDB_WATCHPOINT_WRITE:
2940 case GDB_WATCHPOINT_ACCESS:
2941 switch (len) {
2942 case 1:
2943 break;
2944 case 2:
2945 case 4:
2946 case 8:
2947 if (addr & (len - 1)) {
2948 return -EINVAL;
2949 }
2950 break;
2951 default:
2952 return -EINVAL;
2953 }
2954 break;
2955 default:
2956 return -ENOSYS;
2957 }
2958
2959 if (nb_hw_breakpoint == 4) {
2960 return -ENOBUFS;
2961 }
2962 if (find_hw_breakpoint(addr, len, type) >= 0) {
2963 return -EEXIST;
2964 }
2965 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2966 hw_breakpoint[nb_hw_breakpoint].len = len;
2967 hw_breakpoint[nb_hw_breakpoint].type = type;
2968 nb_hw_breakpoint++;
2969
2970 return 0;
2971 }
2972
2973 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2974 target_ulong len, int type)
2975 {
2976 int n;
2977
2978 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2979 if (n < 0) {
2980 return -ENOENT;
2981 }
2982 nb_hw_breakpoint--;
2983 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2984
2985 return 0;
2986 }
2987
2988 void kvm_arch_remove_all_hw_breakpoints(void)
2989 {
2990 nb_hw_breakpoint = 0;
2991 }
2992
2993 static CPUWatchpoint hw_watchpoint;
2994
2995 static int kvm_handle_debug(X86CPU *cpu,
2996 struct kvm_debug_exit_arch *arch_info)
2997 {
2998 CPUState *cs = CPU(cpu);
2999 CPUX86State *env = &cpu->env;
3000 int ret = 0;
3001 int n;
3002
3003 if (arch_info->exception == 1) {
3004 if (arch_info->dr6 & (1 << 14)) {
3005 if (cs->singlestep_enabled) {
3006 ret = EXCP_DEBUG;
3007 }
3008 } else {
3009 for (n = 0; n < 4; n++) {
3010 if (arch_info->dr6 & (1 << n)) {
3011 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3012 case 0x0:
3013 ret = EXCP_DEBUG;
3014 break;
3015 case 0x1:
3016 ret = EXCP_DEBUG;
3017 cs->watchpoint_hit = &hw_watchpoint;
3018 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3019 hw_watchpoint.flags = BP_MEM_WRITE;
3020 break;
3021 case 0x3:
3022 ret = EXCP_DEBUG;
3023 cs->watchpoint_hit = &hw_watchpoint;
3024 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3025 hw_watchpoint.flags = BP_MEM_ACCESS;
3026 break;
3027 }
3028 }
3029 }
3030 }
3031 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3032 ret = EXCP_DEBUG;
3033 }
3034 if (ret == 0) {
3035 cpu_synchronize_state(cs);
3036 assert(env->exception_injected == -1);
3037
3038 /* pass to guest */
3039 env->exception_injected = arch_info->exception;
3040 env->has_error_code = 0;
3041 }
3042
3043 return ret;
3044 }
3045
3046 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3047 {
3048 const uint8_t type_code[] = {
3049 [GDB_BREAKPOINT_HW] = 0x0,
3050 [GDB_WATCHPOINT_WRITE] = 0x1,
3051 [GDB_WATCHPOINT_ACCESS] = 0x3
3052 };
3053 const uint8_t len_code[] = {
3054 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3055 };
3056 int n;
3057
3058 if (kvm_sw_breakpoints_active(cpu)) {
3059 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3060 }
3061 if (nb_hw_breakpoint > 0) {
3062 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3063 dbg->arch.debugreg[7] = 0x0600;
3064 for (n = 0; n < nb_hw_breakpoint; n++) {
3065 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3066 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3067 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3068 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3069 }
3070 }
3071 }
3072
3073 static bool host_supports_vmx(void)
3074 {
3075 uint32_t ecx, unused;
3076
3077 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3078 return ecx & CPUID_EXT_VMX;
3079 }
3080
3081 #define VMX_INVALID_GUEST_STATE 0x80000021
3082
3083 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3084 {
3085 X86CPU *cpu = X86_CPU(cs);
3086 uint64_t code;
3087 int ret;
3088
3089 switch (run->exit_reason) {
3090 case KVM_EXIT_HLT:
3091 DPRINTF("handle_hlt\n");
3092 qemu_mutex_lock_iothread();
3093 ret = kvm_handle_halt(cpu);
3094 qemu_mutex_unlock_iothread();
3095 break;
3096 case KVM_EXIT_SET_TPR:
3097 ret = 0;
3098 break;
3099 case KVM_EXIT_TPR_ACCESS:
3100 qemu_mutex_lock_iothread();
3101 ret = kvm_handle_tpr_access(cpu);
3102 qemu_mutex_unlock_iothread();
3103 break;
3104 case KVM_EXIT_FAIL_ENTRY:
3105 code = run->fail_entry.hardware_entry_failure_reason;
3106 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3107 code);
3108 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3109 fprintf(stderr,
3110 "\nIf you're running a guest on an Intel machine without "
3111 "unrestricted mode\n"
3112 "support, the failure can be most likely due to the guest "
3113 "entering an invalid\n"
3114 "state for Intel VT. For example, the guest maybe running "
3115 "in big real mode\n"
3116 "which is not supported on less recent Intel processors."
3117 "\n\n");
3118 }
3119 ret = -1;
3120 break;
3121 case KVM_EXIT_EXCEPTION:
3122 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3123 run->ex.exception, run->ex.error_code);
3124 ret = -1;
3125 break;
3126 case KVM_EXIT_DEBUG:
3127 DPRINTF("kvm_exit_debug\n");
3128 qemu_mutex_lock_iothread();
3129 ret = kvm_handle_debug(cpu, &run->debug.arch);
3130 qemu_mutex_unlock_iothread();
3131 break;
3132 case KVM_EXIT_HYPERV:
3133 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3134 break;
3135 case KVM_EXIT_IOAPIC_EOI:
3136 ioapic_eoi_broadcast(run->eoi.vector);
3137 ret = 0;
3138 break;
3139 default:
3140 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3141 ret = -1;
3142 break;
3143 }
3144
3145 return ret;
3146 }
3147
3148 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3149 {
3150 X86CPU *cpu = X86_CPU(cs);
3151 CPUX86State *env = &cpu->env;
3152
3153 kvm_cpu_synchronize_state(cs);
3154 return !(env->cr[0] & CR0_PE_MASK) ||
3155 ((env->segs[R_CS].selector & 3) != 3);
3156 }
3157
3158 void kvm_arch_init_irq_routing(KVMState *s)
3159 {
3160 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3161 /* If kernel can't do irq routing, interrupt source
3162 * override 0->2 cannot be set up as required by HPET.
3163 * So we have to disable it.
3164 */
3165 no_hpet = 1;
3166 }
3167 /* We know at this point that we're using the in-kernel
3168 * irqchip, so we can use irqfds, and on x86 we know
3169 * we can use msi via irqfd and GSI routing.
3170 */
3171 kvm_msi_via_irqfd_allowed = true;
3172 kvm_gsi_routing_allowed = true;
3173
3174 if (kvm_irqchip_is_split()) {
3175 int i;
3176
3177 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3178 MSI routes for signaling interrupts to the local apics. */
3179 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3180 struct MSIMessage msg = { 0x0, 0x0 };
3181 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3182 error_report("Could not enable split IRQ mode.");
3183 exit(1);
3184 }
3185 }
3186 }
3187 }
3188
3189 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3190 {
3191 int ret;
3192 if (machine_kernel_irqchip_split(ms)) {
3193 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3194 if (ret) {
3195 error_report("Could not enable split irqchip mode: %s\n",
3196 strerror(-ret));
3197 exit(1);
3198 } else {
3199 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3200 kvm_split_irqchip = true;
3201 return 1;
3202 }
3203 } else {
3204 return 0;
3205 }
3206 }
3207
3208 /* Classic KVM device assignment interface. Will remain x86 only. */
3209 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3210 uint32_t flags, uint32_t *dev_id)
3211 {
3212 struct kvm_assigned_pci_dev dev_data = {
3213 .segnr = dev_addr->domain,
3214 .busnr = dev_addr->bus,
3215 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3216 .flags = flags,
3217 };
3218 int ret;
3219
3220 dev_data.assigned_dev_id =
3221 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3222
3223 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3224 if (ret < 0) {
3225 return ret;
3226 }
3227
3228 *dev_id = dev_data.assigned_dev_id;
3229
3230 return 0;
3231 }
3232
3233 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3234 {
3235 struct kvm_assigned_pci_dev dev_data = {
3236 .assigned_dev_id = dev_id,
3237 };
3238
3239 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3240 }
3241
3242 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3243 uint32_t irq_type, uint32_t guest_irq)
3244 {
3245 struct kvm_assigned_irq assigned_irq = {
3246 .assigned_dev_id = dev_id,
3247 .guest_irq = guest_irq,
3248 .flags = irq_type,
3249 };
3250
3251 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3252 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3253 } else {
3254 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3255 }
3256 }
3257
3258 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3259 uint32_t guest_irq)
3260 {
3261 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3262 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3263
3264 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3265 }
3266
3267 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3268 {
3269 struct kvm_assigned_pci_dev dev_data = {
3270 .assigned_dev_id = dev_id,
3271 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3272 };
3273
3274 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3275 }
3276
3277 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3278 uint32_t type)
3279 {
3280 struct kvm_assigned_irq assigned_irq = {
3281 .assigned_dev_id = dev_id,
3282 .flags = type,
3283 };
3284
3285 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3286 }
3287
3288 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3289 {
3290 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3291 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3292 }
3293
3294 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3295 {
3296 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3297 KVM_DEV_IRQ_GUEST_MSI, virq);
3298 }
3299
3300 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3301 {
3302 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3303 KVM_DEV_IRQ_HOST_MSI);
3304 }
3305
3306 bool kvm_device_msix_supported(KVMState *s)
3307 {
3308 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3309 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3310 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3311 }
3312
3313 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3314 uint32_t nr_vectors)
3315 {
3316 struct kvm_assigned_msix_nr msix_nr = {
3317 .assigned_dev_id = dev_id,
3318 .entry_nr = nr_vectors,
3319 };
3320
3321 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3322 }
3323
3324 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3325 int virq)
3326 {
3327 struct kvm_assigned_msix_entry msix_entry = {
3328 .assigned_dev_id = dev_id,
3329 .gsi = virq,
3330 .entry = vector,
3331 };
3332
3333 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3334 }
3335
3336 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3337 {
3338 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3339 KVM_DEV_IRQ_GUEST_MSIX, 0);
3340 }
3341
3342 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3343 {
3344 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3345 KVM_DEV_IRQ_HOST_MSIX);
3346 }
3347
3348 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3349 uint64_t address, uint32_t data, PCIDevice *dev)
3350 {
3351 return 0;
3352 }
3353
3354 int kvm_arch_msi_data_to_gsi(uint32_t data)
3355 {
3356 abort();
3357 }
AR7 emulation for QEMU