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linux-user: sync syscall numbers upto 3.13
[qemu/ar7.git] / target-arm / helper.c
blob5ae08c9ad1fd68bde35d7894a2b64242fd9499f9
1 #include "cpu.h"
2 #include "exec/gdbstub.h"
3 #include "helper.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/arch_init.h"
6 #include "sysemu/sysemu.h"
7 #include "qemu/bitops.h"
8
9 #ifndef CONFIG_USER_ONLY
10 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
11 int access_type, int is_user,
12 hwaddr *phys_ptr, int *prot,
13 target_ulong *page_size);
14 #endif
15
16 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
17 {
18 int nregs;
19
20 /* VFP data registers are always little-endian. */
21 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
22 if (reg < nregs) {
23 stfq_le_p(buf, env->vfp.regs[reg]);
24 return 8;
25 }
26 if (arm_feature(env, ARM_FEATURE_NEON)) {
27 /* Aliases for Q regs. */
28 nregs += 16;
29 if (reg < nregs) {
30 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
31 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
32 return 16;
33 }
34 }
35 switch (reg - nregs) {
36 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
37 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
38 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
39 }
40 return 0;
41 }
42
43 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
44 {
45 int nregs;
46
47 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
48 if (reg < nregs) {
49 env->vfp.regs[reg] = ldfq_le_p(buf);
50 return 8;
51 }
52 if (arm_feature(env, ARM_FEATURE_NEON)) {
53 nregs += 16;
54 if (reg < nregs) {
55 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
56 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
57 return 16;
58 }
59 }
60 switch (reg - nregs) {
61 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
62 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
63 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
64 }
65 return 0;
66 }
67
68 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
69 {
70 switch (reg) {
71 case 0 ... 31:
72 /* 128 bit FP register */
73 stfq_le_p(buf, env->vfp.regs[reg * 2]);
74 stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
75 return 16;
76 case 32:
77 /* FPSR */
78 stl_p(buf, vfp_get_fpsr(env));
79 return 4;
80 case 33:
81 /* FPCR */
82 stl_p(buf, vfp_get_fpcr(env));
83 return 4;
84 default:
85 return 0;
86 }
87 }
88
89 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
90 {
91 switch (reg) {
92 case 0 ... 31:
93 /* 128 bit FP register */
94 env->vfp.regs[reg * 2] = ldfq_le_p(buf);
95 env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
96 return 16;
97 case 32:
98 /* FPSR */
99 vfp_set_fpsr(env, ldl_p(buf));
100 return 4;
101 case 33:
102 /* FPCR */
103 vfp_set_fpcr(env, ldl_p(buf));
104 return 4;
105 default:
106 return 0;
107 }
108 }
109
110 static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
111 uint64_t *value)
112 {
113 if (ri->type & ARM_CP_64BIT) {
114 *value = CPREG_FIELD64(env, ri);
115 } else {
116 *value = CPREG_FIELD32(env, ri);
117 }
118 return 0;
119 }
120
121 static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
122 uint64_t value)
123 {
124 if (ri->type & ARM_CP_64BIT) {
125 CPREG_FIELD64(env, ri) = value;
126 } else {
127 CPREG_FIELD32(env, ri) = value;
128 }
129 return 0;
130 }
131
132 static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
133 uint64_t *v)
134 {
135 /* Raw read of a coprocessor register (as needed for migration, etc)
136 * return true on success, false if the read is impossible for some reason.
137 */
138 if (ri->type & ARM_CP_CONST) {
139 *v = ri->resetvalue;
140 } else if (ri->raw_readfn) {
141 return (ri->raw_readfn(env, ri, v) == 0);
142 } else if (ri->readfn) {
143 return (ri->readfn(env, ri, v) == 0);
144 } else {
145 raw_read(env, ri, v);
146 }
147 return true;
148 }
149
150 static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
151 int64_t v)
152 {
153 /* Raw write of a coprocessor register (as needed for migration, etc).
154 * Return true on success, false if the write is impossible for some reason.
155 * Note that constant registers are treated as write-ignored; the
156 * caller should check for success by whether a readback gives the
157 * value written.
158 */
159 if (ri->type & ARM_CP_CONST) {
160 return true;
161 } else if (ri->raw_writefn) {
162 return (ri->raw_writefn(env, ri, v) == 0);
163 } else if (ri->writefn) {
164 return (ri->writefn(env, ri, v) == 0);
165 } else {
166 raw_write(env, ri, v);
167 }
168 return true;
169 }
170
171 bool write_cpustate_to_list(ARMCPU *cpu)
172 {
173 /* Write the coprocessor state from cpu->env to the (index,value) list. */
174 int i;
175 bool ok = true;
176
177 for (i = 0; i < cpu->cpreg_array_len; i++) {
178 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
179 const ARMCPRegInfo *ri;
180 uint64_t v;
181 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
182 if (!ri) {
183 ok = false;
184 continue;
185 }
186 if (ri->type & ARM_CP_NO_MIGRATE) {
187 continue;
188 }
189 if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
190 ok = false;
191 continue;
192 }
193 cpu->cpreg_values[i] = v;
194 }
195 return ok;
196 }
197
198 bool write_list_to_cpustate(ARMCPU *cpu)
199 {
200 int i;
201 bool ok = true;
202
203 for (i = 0; i < cpu->cpreg_array_len; i++) {
204 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
205 uint64_t v = cpu->cpreg_values[i];
206 uint64_t readback;
207 const ARMCPRegInfo *ri;
208
209 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
210 if (!ri) {
211 ok = false;
212 continue;
213 }
214 if (ri->type & ARM_CP_NO_MIGRATE) {
215 continue;
216 }
217 /* Write value and confirm it reads back as written
218 * (to catch read-only registers and partially read-only
219 * registers where the incoming migration value doesn't match)
220 */
221 if (!write_raw_cp_reg(&cpu->env, ri, v) ||
222 !read_raw_cp_reg(&cpu->env, ri, &readback) ||
223 readback != v) {
224 ok = false;
225 }
226 }
227 return ok;
228 }
229
230 static void add_cpreg_to_list(gpointer key, gpointer opaque)
231 {
232 ARMCPU *cpu = opaque;
233 uint64_t regidx;
234 const ARMCPRegInfo *ri;
235
236 regidx = *(uint32_t *)key;
237 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
238
239 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
240 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
241 /* The value array need not be initialized at this point */
242 cpu->cpreg_array_len++;
243 }
244 }
245
246 static void count_cpreg(gpointer key, gpointer opaque)
247 {
248 ARMCPU *cpu = opaque;
249 uint64_t regidx;
250 const ARMCPRegInfo *ri;
251
252 regidx = *(uint32_t *)key;
253 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
254
255 if (!(ri->type & ARM_CP_NO_MIGRATE)) {
256 cpu->cpreg_array_len++;
257 }
258 }
259
260 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
261 {
262 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
263 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
264
265 if (aidx > bidx) {
266 return 1;
267 }
268 if (aidx < bidx) {
269 return -1;
270 }
271 return 0;
272 }
273
274 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
275 {
276 GList **plist = udata;
277
278 *plist = g_list_prepend(*plist, key);
279 }
280
281 void init_cpreg_list(ARMCPU *cpu)
282 {
283 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
284 * Note that we require cpreg_tuples[] to be sorted by key ID.
285 */
286 GList *keys = NULL;
287 int arraylen;
288
289 g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
290
291 keys = g_list_sort(keys, cpreg_key_compare);
292
293 cpu->cpreg_array_len = 0;
294
295 g_list_foreach(keys, count_cpreg, cpu);
296
297 arraylen = cpu->cpreg_array_len;
298 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
299 cpu->cpreg_values = g_new(uint64_t, arraylen);
300 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
301 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
302 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
303 cpu->cpreg_array_len = 0;
304
305 g_list_foreach(keys, add_cpreg_to_list, cpu);
306
307 assert(cpu->cpreg_array_len == arraylen);
308
309 g_list_free(keys);
310 }
311
312 static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
313 {
314 env->cp15.c3 = value;
315 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
316 return 0;
317 }
318
319 static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
320 {
321 if (env->cp15.c13_fcse != value) {
322 /* Unlike real hardware the qemu TLB uses virtual addresses,
323 * not modified virtual addresses, so this causes a TLB flush.
324 */
325 tlb_flush(env, 1);
326 env->cp15.c13_fcse = value;
327 }
328 return 0;
329 }
330 static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
331 uint64_t value)
332 {
333 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
334 /* For VMSA (when not using the LPAE long descriptor page table
335 * format) this register includes the ASID, so do a TLB flush.
336 * For PMSA it is purely a process ID and no action is needed.
337 */
338 tlb_flush(env, 1);
339 }
340 env->cp15.c13_context = value;
341 return 0;
342 }
343
344 static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
345 uint64_t value)
346 {
347 /* Invalidate all (TLBIALL) */
348 tlb_flush(env, 1);
349 return 0;
350 }
351
352 static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
353 uint64_t value)
354 {
355 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
356 tlb_flush_page(env, value & TARGET_PAGE_MASK);
357 return 0;
358 }
359
360 static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
361 uint64_t value)
362 {
363 /* Invalidate by ASID (TLBIASID) */
364 tlb_flush(env, value == 0);
365 return 0;
366 }
367
368 static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
369 uint64_t value)
370 {
371 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
372 tlb_flush_page(env, value & TARGET_PAGE_MASK);
373 return 0;
374 }
375
376 static const ARMCPRegInfo cp_reginfo[] = {
377 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
378 * version" bits will read as a reserved value, which should cause
379 * Linux to not try to use the debug hardware.
380 */
381 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
382 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
383 /* MMU Domain access control / MPU write buffer control */
384 { .name = "DACR", .cp = 15,
385 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
386 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
387 .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
388 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
389 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
390 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
391 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
392 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
393 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
394 /* ??? This covers not just the impdef TLB lockdown registers but also
395 * some v7VMSA registers relating to TEX remap, so it is overly broad.
396 */
397 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
398 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
399 /* MMU TLB control. Note that the wildcarding means we cover not just
400 * the unified TLB ops but also the dside/iside/inner-shareable variants.
401 */
402 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
403 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
404 .type = ARM_CP_NO_MIGRATE },
405 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
406 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
407 .type = ARM_CP_NO_MIGRATE },
408 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
409 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
410 .type = ARM_CP_NO_MIGRATE },
411 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
412 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
413 .type = ARM_CP_NO_MIGRATE },
414 /* Cache maintenance ops; some of this space may be overridden later. */
415 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
416 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
417 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
418 REGINFO_SENTINEL
419 };
420
421 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
422 /* Not all pre-v6 cores implemented this WFI, so this is slightly
423 * over-broad.
424 */
425 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
426 .access = PL1_W, .type = ARM_CP_WFI },
427 REGINFO_SENTINEL
428 };
429
430 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
431 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
432 * is UNPREDICTABLE; we choose to NOP as most implementations do).
433 */
434 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
435 .access = PL1_W, .type = ARM_CP_WFI },
436 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
437 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
438 * OMAPCP will override this space.
439 */
440 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
441 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
442 .resetvalue = 0 },
443 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
444 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
445 .resetvalue = 0 },
446 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
447 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
448 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
449 .resetvalue = 0 },
450 REGINFO_SENTINEL
451 };
452
453 static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
454 {
455 if (env->cp15.c1_coproc != value) {
456 env->cp15.c1_coproc = value;
457 /* ??? Is this safe when called from within a TB? */
458 tb_flush(env);
459 }
460 return 0;
461 }
462
463 static const ARMCPRegInfo v6_cp_reginfo[] = {
464 /* prefetch by MVA in v6, NOP in v7 */
465 { .name = "MVA_prefetch",
466 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
467 .access = PL1_W, .type = ARM_CP_NOP },
468 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
469 .access = PL0_W, .type = ARM_CP_NOP },
470 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
471 .access = PL0_W, .type = ARM_CP_NOP },
472 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
473 .access = PL0_W, .type = ARM_CP_NOP },
474 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
475 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
476 .resetvalue = 0, },
477 /* Watchpoint Fault Address Register : should actually only be present
478 * for 1136, 1176, 11MPCore.
479 */
480 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
481 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
482 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
483 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
484 .resetvalue = 0, .writefn = cpacr_write },
485 REGINFO_SENTINEL
486 };
487
488
489 static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
490 uint64_t *value)
491 {
492 /* Generic performance monitor register read function for where
493 * user access may be allowed by PMUSERENR.
494 */
495 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
496 return EXCP_UDEF;
497 }
498 *value = CPREG_FIELD32(env, ri);
499 return 0;
500 }
501
502 static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
503 uint64_t value)
504 {
505 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
506 return EXCP_UDEF;
507 }
508 /* only the DP, X, D and E bits are writable */
509 env->cp15.c9_pmcr &= ~0x39;
510 env->cp15.c9_pmcr |= (value & 0x39);
511 return 0;
512 }
513
514 static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
515 uint64_t value)
516 {
517 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
518 return EXCP_UDEF;
519 }
520 value &= (1 << 31);
521 env->cp15.c9_pmcnten |= value;
522 return 0;
523 }
524
525 static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
526 uint64_t value)
527 {
528 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
529 return EXCP_UDEF;
530 }
531 value &= (1 << 31);
532 env->cp15.c9_pmcnten &= ~value;
533 return 0;
534 }
535
536 static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
537 uint64_t value)
538 {
539 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
540 return EXCP_UDEF;
541 }
542 env->cp15.c9_pmovsr &= ~value;
543 return 0;
544 }
545
546 static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
547 uint64_t value)
548 {
549 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
550 return EXCP_UDEF;
551 }
552 env->cp15.c9_pmxevtyper = value & 0xff;
553 return 0;
554 }
555
556 static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
557 uint64_t value)
558 {
559 env->cp15.c9_pmuserenr = value & 1;
560 return 0;
561 }
562
563 static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
564 uint64_t value)
565 {
566 /* We have no event counters so only the C bit can be changed */
567 value &= (1 << 31);
568 env->cp15.c9_pminten |= value;
569 return 0;
570 }
571
572 static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
573 uint64_t value)
574 {
575 value &= (1 << 31);
576 env->cp15.c9_pminten &= ~value;
577 return 0;
578 }
579
580 static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
581 uint64_t value)
582 {
583 env->cp15.c12_vbar = value & ~0x1Ful;
584 return 0;
585 }
586
587 static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
588 uint64_t *value)
589 {
590 ARMCPU *cpu = arm_env_get_cpu(env);
591 *value = cpu->ccsidr[env->cp15.c0_cssel];
592 return 0;
593 }
594
595 static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
596 uint64_t value)
597 {
598 env->cp15.c0_cssel = value & 0xf;
599 return 0;
600 }
601
602 static const ARMCPRegInfo v7_cp_reginfo[] = {
603 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
604 * debug components
605 */
606 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
607 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
608 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
609 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
610 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
611 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
612 .access = PL1_W, .type = ARM_CP_NOP },
613 /* Performance monitors are implementation defined in v7,
614 * but with an ARM recommended set of registers, which we
615 * follow (although we don't actually implement any counters)
616 *
617 * Performance registers fall into three categories:
618 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
619 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
620 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
621 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
622 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
623 */
624 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
625 .access = PL0_RW, .resetvalue = 0,
626 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
627 .readfn = pmreg_read, .writefn = pmcntenset_write,
628 .raw_readfn = raw_read, .raw_writefn = raw_write },
629 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
630 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
631 .readfn = pmreg_read, .writefn = pmcntenclr_write,
632 .type = ARM_CP_NO_MIGRATE },
633 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
634 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
635 .readfn = pmreg_read, .writefn = pmovsr_write,
636 .raw_readfn = raw_read, .raw_writefn = raw_write },
637 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
638 * respect PMUSERENR.
639 */
640 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
641 .access = PL0_W, .type = ARM_CP_NOP },
642 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
643 * We choose to RAZ/WI. XXX should respect PMUSERENR.
644 */
645 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
646 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
647 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
648 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
649 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
650 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
651 .access = PL0_RW,
652 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
653 .readfn = pmreg_read, .writefn = pmxevtyper_write,
654 .raw_readfn = raw_read, .raw_writefn = raw_write },
655 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
656 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
657 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
658 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
659 .access = PL0_R | PL1_RW,
660 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
661 .resetvalue = 0,
662 .writefn = pmuserenr_write, .raw_writefn = raw_write },
663 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
664 .access = PL1_RW,
665 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
666 .resetvalue = 0,
667 .writefn = pmintenset_write, .raw_writefn = raw_write },
668 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
669 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
670 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
671 .resetvalue = 0, .writefn = pmintenclr_write, },
672 { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
673 .access = PL1_RW, .writefn = vbar_write,
674 .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
675 .resetvalue = 0 },
676 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
677 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
678 .resetvalue = 0, },
679 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
680 .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
681 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
682 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
683 .writefn = csselr_write, .resetvalue = 0 },
684 /* Auxiliary ID register: this actually has an IMPDEF value but for now
685 * just RAZ for all cores:
686 */
687 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
688 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
689 REGINFO_SENTINEL
690 };
691
692 static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
693 {
694 value &= 1;
695 env->teecr = value;
696 return 0;
697 }
698
699 static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
700 uint64_t *value)
701 {
702 /* This is a helper function because the user access rights
703 * depend on the value of the TEECR.
704 */
705 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
706 return EXCP_UDEF;
707 }
708 *value = env->teehbr;
709 return 0;
710 }
711
712 static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
713 uint64_t value)
714 {
715 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
716 return EXCP_UDEF;
717 }
718 env->teehbr = value;
719 return 0;
720 }
721
722 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
723 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
724 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
725 .resetvalue = 0,
726 .writefn = teecr_write },
727 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
728 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
729 .resetvalue = 0, .raw_readfn = raw_read, .raw_writefn = raw_write,
730 .readfn = teehbr_read, .writefn = teehbr_write },
731 REGINFO_SENTINEL
732 };
733
734 static const ARMCPRegInfo v6k_cp_reginfo[] = {
735 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
736 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
737 .access = PL0_RW,
738 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
739 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
740 .access = PL0_RW,
741 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
742 .resetfn = arm_cp_reset_ignore },
743 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
744 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
745 .access = PL0_R|PL1_W,
746 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
747 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
748 .access = PL0_R|PL1_W,
749 .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
750 .resetfn = arm_cp_reset_ignore },
751 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
752 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
753 .access = PL1_RW,
754 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
755 REGINFO_SENTINEL
756 };
757
758 #ifndef CONFIG_USER_ONLY
759
760 static uint64_t gt_get_countervalue(CPUARMState *env)
761 {
762 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
763 }
764
765 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
766 {
767 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
768
769 if (gt->ctl & 1) {
770 /* Timer enabled: calculate and set current ISTATUS, irq, and
771 * reset timer to when ISTATUS next has to change
772 */
773 uint64_t count = gt_get_countervalue(&cpu->env);
774 /* Note that this must be unsigned 64 bit arithmetic: */
775 int istatus = count >= gt->cval;
776 uint64_t nexttick;
777
778 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
779 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
780 (istatus && !(gt->ctl & 2)));
781 if (istatus) {
782 /* Next transition is when count rolls back over to zero */
783 nexttick = UINT64_MAX;
784 } else {
785 /* Next transition is when we hit cval */
786 nexttick = gt->cval;
787 }
788 /* Note that the desired next expiry time might be beyond the
789 * signed-64-bit range of a QEMUTimer -- in this case we just
790 * set the timer for as far in the future as possible. When the
791 * timer expires we will reset the timer for any remaining period.
792 */
793 if (nexttick > INT64_MAX / GTIMER_SCALE) {
794 nexttick = INT64_MAX / GTIMER_SCALE;
795 }
796 timer_mod(cpu->gt_timer[timeridx], nexttick);
797 } else {
798 /* Timer disabled: ISTATUS and timer output always clear */
799 gt->ctl &= ~4;
800 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
801 timer_del(cpu->gt_timer[timeridx]);
802 }
803 }
804
805 static int gt_cntfrq_read(CPUARMState *env, const ARMCPRegInfo *ri,
806 uint64_t *value)
807 {
808 /* Not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
809 if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
810 return EXCP_UDEF;
811 }
812 *value = env->cp15.c14_cntfrq;
813 return 0;
814 }
815
816 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
817 {
818 ARMCPU *cpu = arm_env_get_cpu(env);
819 int timeridx = ri->opc1 & 1;
820
821 timer_del(cpu->gt_timer[timeridx]);
822 }
823
824 static int gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri,
825 uint64_t *value)
826 {
827 int timeridx = ri->opc1 & 1;
828
829 if (arm_current_pl(env) == 0 &&
830 !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
831 return EXCP_UDEF;
832 }
833 *value = gt_get_countervalue(env);
834 return 0;
835 }
836
837 static int gt_cval_read(CPUARMState *env, const ARMCPRegInfo *ri,
838 uint64_t *value)
839 {
840 int timeridx = ri->opc1 & 1;
841
842 if (arm_current_pl(env) == 0 &&
843 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
844 return EXCP_UDEF;
845 }
846 *value = env->cp15.c14_timer[timeridx].cval;
847 return 0;
848 }
849
850 static int gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
851 uint64_t value)
852 {
853 int timeridx = ri->opc1 & 1;
854
855 env->cp15.c14_timer[timeridx].cval = value;
856 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
857 return 0;
858 }
859 static int gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
860 uint64_t *value)
861 {
862 int timeridx = ri->crm & 1;
863
864 if (arm_current_pl(env) == 0 &&
865 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
866 return EXCP_UDEF;
867 }
868 *value = (uint32_t)(env->cp15.c14_timer[timeridx].cval -
869 gt_get_countervalue(env));
870 return 0;
871 }
872
873 static int gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
874 uint64_t value)
875 {
876 int timeridx = ri->crm & 1;
877
878 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
879 + sextract64(value, 0, 32);
880 gt_recalc_timer(arm_env_get_cpu(env), timeridx);
881 return 0;
882 }
883
884 static int gt_ctl_read(CPUARMState *env, const ARMCPRegInfo *ri,
885 uint64_t *value)
886 {
887 int timeridx = ri->crm & 1;
888
889 if (arm_current_pl(env) == 0 &&
890 !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
891 return EXCP_UDEF;
892 }
893 *value = env->cp15.c14_timer[timeridx].ctl;
894 return 0;
895 }
896
897 static int gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
898 uint64_t value)
899 {
900 ARMCPU *cpu = arm_env_get_cpu(env);
901 int timeridx = ri->crm & 1;
902 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
903
904 env->cp15.c14_timer[timeridx].ctl = value & 3;
905 if ((oldval ^ value) & 1) {
906 /* Enable toggled */
907 gt_recalc_timer(cpu, timeridx);
908 } else if ((oldval & value) & 2) {
909 /* IMASK toggled: don't need to recalculate,
910 * just set the interrupt line based on ISTATUS
911 */
912 qemu_set_irq(cpu->gt_timer_outputs[timeridx],
913 (oldval & 4) && (value & 2));
914 }
915 return 0;
916 }
917
918 void arm_gt_ptimer_cb(void *opaque)
919 {
920 ARMCPU *cpu = opaque;
921
922 gt_recalc_timer(cpu, GTIMER_PHYS);
923 }
924
925 void arm_gt_vtimer_cb(void *opaque)
926 {
927 ARMCPU *cpu = opaque;
928
929 gt_recalc_timer(cpu, GTIMER_VIRT);
930 }
931
932 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
933 /* Note that CNTFRQ is purely reads-as-written for the benefit
934 * of software; writing it doesn't actually change the timer frequency.
935 * Our reset value matches the fixed frequency we implement the timer at.
936 */
937 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
938 .access = PL1_RW | PL0_R,
939 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
940 .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
941 .readfn = gt_cntfrq_read, .raw_readfn = raw_read,
942 },
943 /* overall control: mostly access permissions */
944 { .name = "CNTKCTL", .cp = 15, .crn = 14, .crm = 1, .opc1 = 0, .opc2 = 0,
945 .access = PL1_RW,
946 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
947 .resetvalue = 0,
948 },
949 /* per-timer control */
950 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
951 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
952 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
953 .resetvalue = 0,
954 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
955 .raw_readfn = raw_read, .raw_writefn = raw_write,
956 },
957 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
958 .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
959 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
960 .resetvalue = 0,
961 .readfn = gt_ctl_read, .writefn = gt_ctl_write,
962 .raw_readfn = raw_read, .raw_writefn = raw_write,
963 },
964 /* TimerValue views: a 32 bit downcounting view of the underlying state */
965 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
966 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
967 .readfn = gt_tval_read, .writefn = gt_tval_write,
968 },
969 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
970 .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
971 .readfn = gt_tval_read, .writefn = gt_tval_write,
972 },
973 /* The counter itself */
974 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
975 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
976 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
977 },
978 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
979 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
980 .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
981 },
982 /* Comparison value, indicating when the timer goes off */
983 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
984 .access = PL1_RW | PL0_R,
985 .type = ARM_CP_64BIT | ARM_CP_IO,
986 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
987 .resetvalue = 0,
988 .readfn = gt_cval_read, .writefn = gt_cval_write,
989 .raw_readfn = raw_read, .raw_writefn = raw_write,
990 },
991 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
992 .access = PL1_RW | PL0_R,
993 .type = ARM_CP_64BIT | ARM_CP_IO,
994 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
995 .resetvalue = 0,
996 .readfn = gt_cval_read, .writefn = gt_cval_write,
997 .raw_readfn = raw_read, .raw_writefn = raw_write,
998 },
999 REGINFO_SENTINEL
1000 };
1001
1002 #else
1003 /* In user-mode none of the generic timer registers are accessible,
1004 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1005 * so instead just don't register any of them.
1006 */
1007 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1008 REGINFO_SENTINEL
1009 };
1010
1011 #endif
1012
1013 static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1014 {
1015 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1016 env->cp15.c7_par = value;
1017 } else if (arm_feature(env, ARM_FEATURE_V7)) {
1018 env->cp15.c7_par = value & 0xfffff6ff;
1019 } else {
1020 env->cp15.c7_par = value & 0xfffff1ff;
1021 }
1022 return 0;
1023 }
1024
1025 #ifndef CONFIG_USER_ONLY
1026 /* get_phys_addr() isn't present for user-mode-only targets */
1027
1028 /* Return true if extended addresses are enabled, ie this is an
1029 * LPAE implementation and we are using the long-descriptor translation
1030 * table format because the TTBCR EAE bit is set.
1031 */
1032 static inline bool extended_addresses_enabled(CPUARMState *env)
1033 {
1034 return arm_feature(env, ARM_FEATURE_LPAE)
1035 && (env->cp15.c2_control & (1U << 31));
1036 }
1037
1038 static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1039 {
1040 hwaddr phys_addr;
1041 target_ulong page_size;
1042 int prot;
1043 int ret, is_user = ri->opc2 & 2;
1044 int access_type = ri->opc2 & 1;
1045
1046 if (ri->opc2 & 4) {
1047 /* Other states are only available with TrustZone */
1048 return EXCP_UDEF;
1049 }
1050 ret = get_phys_addr(env, value, access_type, is_user,
1051 &phys_addr, &prot, &page_size);
1052 if (extended_addresses_enabled(env)) {
1053 /* ret is a DFSR/IFSR value for the long descriptor
1054 * translation table format, but with WnR always clear.
1055 * Convert it to a 64-bit PAR.
1056 */
1057 uint64_t par64 = (1 << 11); /* LPAE bit always set */
1058 if (ret == 0) {
1059 par64 |= phys_addr & ~0xfffULL;
1060 /* We don't set the ATTR or SH fields in the PAR. */
1061 } else {
1062 par64 |= 1; /* F */
1063 par64 |= (ret & 0x3f) << 1; /* FS */
1064 /* Note that S2WLK and FSTAGE are always zero, because we don't
1065 * implement virtualization and therefore there can't be a stage 2
1066 * fault.
1067 */
1068 }
1069 env->cp15.c7_par = par64;
1070 env->cp15.c7_par_hi = par64 >> 32;
1071 } else {
1072 /* ret is a DFSR/IFSR value for the short descriptor
1073 * translation table format (with WnR always clear).
1074 * Convert it to a 32-bit PAR.
1075 */
1076 if (ret == 0) {
1077 /* We do not set any attribute bits in the PAR */
1078 if (page_size == (1 << 24)
1079 && arm_feature(env, ARM_FEATURE_V7)) {
1080 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1081 } else {
1082 env->cp15.c7_par = phys_addr & 0xfffff000;
1083 }
1084 } else {
1085 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1086 ((ret & (12 << 1)) >> 6) |
1087 ((ret & 0xf) << 1) | 1;
1088 }
1089 env->cp15.c7_par_hi = 0;
1090 }
1091 return 0;
1092 }
1093 #endif
1094
1095 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1096 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1097 .access = PL1_RW, .resetvalue = 0,
1098 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
1099 .writefn = par_write },
1100 #ifndef CONFIG_USER_ONLY
1101 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1102 .access = PL1_W, .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1103 #endif
1104 REGINFO_SENTINEL
1105 };
1106
1107 /* Return basic MPU access permission bits. */
1108 static uint32_t simple_mpu_ap_bits(uint32_t val)
1109 {
1110 uint32_t ret;
1111 uint32_t mask;
1112 int i;
1113 ret = 0;
1114 mask = 3;
1115 for (i = 0; i < 16; i += 2) {
1116 ret |= (val >> i) & mask;
1117 mask <<= 2;
1118 }
1119 return ret;
1120 }
1121
1122 /* Pad basic MPU access permission bits to extended format. */
1123 static uint32_t extended_mpu_ap_bits(uint32_t val)
1124 {
1125 uint32_t ret;
1126 uint32_t mask;
1127 int i;
1128 ret = 0;
1129 mask = 3;
1130 for (i = 0; i < 16; i += 2) {
1131 ret |= (val & mask) << i;
1132 mask <<= 2;
1133 }
1134 return ret;
1135 }
1136
1137 static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1138 uint64_t value)
1139 {
1140 env->cp15.c5_data = extended_mpu_ap_bits(value);
1141 return 0;
1142 }
1143
1144 static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1145 uint64_t *value)
1146 {
1147 *value = simple_mpu_ap_bits(env->cp15.c5_data);
1148 return 0;
1149 }
1150
1151 static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1152 uint64_t value)
1153 {
1154 env->cp15.c5_insn = extended_mpu_ap_bits(value);
1155 return 0;
1156 }
1157
1158 static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
1159 uint64_t *value)
1160 {
1161 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
1162 return 0;
1163 }
1164
1165 static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
1166 uint64_t *value)
1167 {
1168 if (ri->crm >= 8) {
1169 return EXCP_UDEF;
1170 }
1171 *value = env->cp15.c6_region[ri->crm];
1172 return 0;
1173 }
1174
1175 static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
1176 uint64_t value)
1177 {
1178 if (ri->crm >= 8) {
1179 return EXCP_UDEF;
1180 }
1181 env->cp15.c6_region[ri->crm] = value;
1182 return 0;
1183 }
1184
1185 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1186 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1187 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1188 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
1189 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1190 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1191 .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1192 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
1193 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1194 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1195 .access = PL1_RW,
1196 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1197 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1198 .access = PL1_RW,
1199 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1200 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1201 .access = PL1_RW,
1202 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1203 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1204 .access = PL1_RW,
1205 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1206 /* Protection region base and size registers */
1207 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
1208 .opc2 = CP_ANY, .access = PL1_RW,
1209 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
1210 REGINFO_SENTINEL
1211 };
1212
1213 static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1214 uint64_t value)
1215 {
1216 int maskshift = extract32(value, 0, 3);
1217
1218 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1219 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1220 } else {
1221 value &= 7;
1222 }
1223 /* Note that we always calculate c2_mask and c2_base_mask, but
1224 * they are only used for short-descriptor tables (ie if EAE is 0);
1225 * for long-descriptor tables the TTBCR fields are used differently
1226 * and the c2_mask and c2_base_mask values are meaningless.
1227 */
1228 env->cp15.c2_control = value;
1229 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1230 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1231 return 0;
1232 }
1233
1234 static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1235 uint64_t value)
1236 {
1237 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1238 /* With LPAE the TTBCR could result in a change of ASID
1239 * via the TTBCR.A1 bit, so do a TLB flush.
1240 */
1241 tlb_flush(env, 1);
1242 }
1243 return vmsa_ttbcr_raw_write(env, ri, value);
1244 }
1245
1246 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1247 {
1248 env->cp15.c2_base_mask = 0xffffc000u;
1249 env->cp15.c2_control = 0;
1250 env->cp15.c2_mask = 0;
1251 }
1252
1253 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1254 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1255 .access = PL1_RW,
1256 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1257 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1258 .access = PL1_RW,
1259 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
1260 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1261 .access = PL1_RW,
1262 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
1263 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1264 .access = PL1_RW,
1265 .fieldoffset = offsetof(CPUARMState, cp15.c2_base1), .resetvalue = 0, },
1266 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1267 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
1268 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
1269 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1270 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1271 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
1272 .resetvalue = 0, },
1273 REGINFO_SENTINEL
1274 };
1275
1276 static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1277 uint64_t value)
1278 {
1279 env->cp15.c15_ticonfig = value & 0xe7;
1280 /* The OS_TYPE bit in this register changes the reported CPUID! */
1281 env->cp15.c0_cpuid = (value & (1 << 5)) ?
1282 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1283 return 0;
1284 }
1285
1286 static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1287 uint64_t value)
1288 {
1289 env->cp15.c15_threadid = value & 0xffff;
1290 return 0;
1291 }
1292
1293 static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1294 uint64_t value)
1295 {
1296 /* Wait-for-interrupt (deprecated) */
1297 cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1298 return 0;
1299 }
1300
1301 static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1302 uint64_t value)
1303 {
1304 /* On OMAP there are registers indicating the max/min index of dcache lines
1305 * containing a dirty line; cache flush operations have to reset these.
1306 */
1307 env->cp15.c15_i_max = 0x000;
1308 env->cp15.c15_i_min = 0xff0;
1309 return 0;
1310 }
1311
1312 static const ARMCPRegInfo omap_cp_reginfo[] = {
1313 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1314 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1315 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1316 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1317 .access = PL1_RW, .type = ARM_CP_NOP },
1318 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1319 .access = PL1_RW,
1320 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1321 .writefn = omap_ticonfig_write },
1322 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1323 .access = PL1_RW,
1324 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1325 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1326 .access = PL1_RW, .resetvalue = 0xff0,
1327 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1328 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1329 .access = PL1_RW,
1330 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1331 .writefn = omap_threadid_write },
1332 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1333 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1334 .type = ARM_CP_NO_MIGRATE,
1335 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1336 /* TODO: Peripheral port remap register:
1337 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1338 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1339 * when MMU is off.
1340 */
1341 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1342 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1343 .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1344 .writefn = omap_cachemaint_write },
1345 { .name = "C9", .cp = 15, .crn = 9,
1346 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1347 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1348 REGINFO_SENTINEL
1349 };
1350
1351 static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1352 uint64_t value)
1353 {
1354 value &= 0x3fff;
1355 if (env->cp15.c15_cpar != value) {
1356 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1357 tb_flush(env);
1358 env->cp15.c15_cpar = value;
1359 }
1360 return 0;
1361 }
1362
1363 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1364 { .name = "XSCALE_CPAR",
1365 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1366 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1367 .writefn = xscale_cpar_write, },
1368 { .name = "XSCALE_AUXCR",
1369 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1370 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1371 .resetvalue = 0, },
1372 REGINFO_SENTINEL
1373 };
1374
1375 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1376 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1377 * implementation of this implementation-defined space.
1378 * Ideally this should eventually disappear in favour of actually
1379 * implementing the correct behaviour for all cores.
1380 */
1381 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1382 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1383 .access = PL1_RW,
1384 .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1385 .resetvalue = 0 },
1386 REGINFO_SENTINEL
1387 };
1388
1389 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1390 /* Cache status: RAZ because we have no cache so it's always clean */
1391 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1392 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1393 .resetvalue = 0 },
1394 REGINFO_SENTINEL
1395 };
1396
1397 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1398 /* We never have a a block transfer operation in progress */
1399 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1400 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1401 .resetvalue = 0 },
1402 /* The cache ops themselves: these all NOP for QEMU */
1403 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1404 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1405 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1406 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1407 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1408 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1409 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1410 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1411 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1412 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1413 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1414 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1415 REGINFO_SENTINEL
1416 };
1417
1418 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1419 /* The cache test-and-clean instructions always return (1 << 30)
1420 * to indicate that there are no dirty cache lines.
1421 */
1422 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1423 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1424 .resetvalue = (1 << 30) },
1425 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1426 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1427 .resetvalue = (1 << 30) },
1428 REGINFO_SENTINEL
1429 };
1430
1431 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1432 /* Ignore ReadBuffer accesses */
1433 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1434 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1435 .access = PL1_RW, .resetvalue = 0,
1436 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1437 REGINFO_SENTINEL
1438 };
1439
1440 static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1441 uint64_t *value)
1442 {
1443 CPUState *cs = CPU(arm_env_get_cpu(env));
1444 uint32_t mpidr = cs->cpu_index;
1445 /* We don't support setting cluster ID ([8..11])
1446 * so these bits always RAZ.
1447 */
1448 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1449 mpidr |= (1U << 31);
1450 /* Cores which are uniprocessor (non-coherent)
1451 * but still implement the MP extensions set
1452 * bit 30. (For instance, A9UP.) However we do
1453 * not currently model any of those cores.
1454 */
1455 }
1456 *value = mpidr;
1457 return 0;
1458 }
1459
1460 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1461 { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1462 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1463 REGINFO_SENTINEL
1464 };
1465
1466 static int par64_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1467 {
1468 *value = ((uint64_t)env->cp15.c7_par_hi << 32) | env->cp15.c7_par;
1469 return 0;
1470 }
1471
1472 static int par64_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1473 {
1474 env->cp15.c7_par_hi = value >> 32;
1475 env->cp15.c7_par = value;
1476 return 0;
1477 }
1478
1479 static void par64_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1480 {
1481 env->cp15.c7_par_hi = 0;
1482 env->cp15.c7_par = 0;
1483 }
1484
1485 static int ttbr064_read(CPUARMState *env, const ARMCPRegInfo *ri,
1486 uint64_t *value)
1487 {
1488 *value = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
1489 return 0;
1490 }
1491
1492 static int ttbr064_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1493 uint64_t value)
1494 {
1495 env->cp15.c2_base0_hi = value >> 32;
1496 env->cp15.c2_base0 = value;
1497 return 0;
1498 }
1499
1500 static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
1501 uint64_t value)
1502 {
1503 /* Writes to the 64 bit format TTBRs may change the ASID */
1504 tlb_flush(env, 1);
1505 return ttbr064_raw_write(env, ri, value);
1506 }
1507
1508 static void ttbr064_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1509 {
1510 env->cp15.c2_base0_hi = 0;
1511 env->cp15.c2_base0 = 0;
1512 }
1513
1514 static int ttbr164_read(CPUARMState *env, const ARMCPRegInfo *ri,
1515 uint64_t *value)
1516 {
1517 *value = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
1518 return 0;
1519 }
1520
1521 static int ttbr164_write(CPUARMState *env, const ARMCPRegInfo *ri,
1522 uint64_t value)
1523 {
1524 env->cp15.c2_base1_hi = value >> 32;
1525 env->cp15.c2_base1 = value;
1526 return 0;
1527 }
1528
1529 static void ttbr164_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1530 {
1531 env->cp15.c2_base1_hi = 0;
1532 env->cp15.c2_base1 = 0;
1533 }
1534
1535 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1536 /* NOP AMAIR0/1: the override is because these clash with the rather
1537 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1538 */
1539 { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1540 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1541 .resetvalue = 0 },
1542 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1543 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1544 .resetvalue = 0 },
1545 /* 64 bit access versions of the (dummy) debug registers */
1546 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1547 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1548 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1549 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1550 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1551 .access = PL1_RW, .type = ARM_CP_64BIT,
1552 .readfn = par64_read, .writefn = par64_write, .resetfn = par64_reset },
1553 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1554 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr064_read,
1555 .writefn = ttbr064_write, .raw_writefn = ttbr064_raw_write,
1556 .resetfn = ttbr064_reset },
1557 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1558 .access = PL1_RW, .type = ARM_CP_64BIT, .readfn = ttbr164_read,
1559 .writefn = ttbr164_write, .resetfn = ttbr164_reset },
1560 REGINFO_SENTINEL
1561 };
1562
1563 static int aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1564 uint64_t *value)
1565 {
1566 *value = vfp_get_fpcr(env);
1567 return 0;
1568 }
1569
1570 static int aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1571 uint64_t value)
1572 {
1573 vfp_set_fpcr(env, value);
1574 return 0;
1575 }
1576
1577 static int aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1578 uint64_t *value)
1579 {
1580 *value = vfp_get_fpsr(env);
1581 return 0;
1582 }
1583
1584 static int aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1585 uint64_t value)
1586 {
1587 vfp_set_fpsr(env, value);
1588 return 0;
1589 }
1590
1591 static const ARMCPRegInfo v8_cp_reginfo[] = {
1592 /* Minimal set of EL0-visible registers. This will need to be expanded
1593 * significantly for system emulation of AArch64 CPUs.
1594 */
1595 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1596 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1597 .access = PL0_RW, .type = ARM_CP_NZCV },
1598 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1599 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1600 .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1601 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1602 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1603 .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1604 /* This claims a 32 byte cacheline size for icache and dcache, VIPT icache.
1605 * It will eventually need to have a CPU-specified reset value.
1606 */
1607 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
1608 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
1609 .access = PL0_R, .type = ARM_CP_CONST,
1610 .resetvalue = 0x80030003 },
1611 /* Prohibit use of DC ZVA. OPTME: implement DC ZVA and allow its use.
1612 * For system mode the DZP bit here will need to be computed, not constant.
1613 */
1614 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1615 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1616 .access = PL0_R, .type = ARM_CP_CONST,
1617 .resetvalue = 0x10 },
1618 REGINFO_SENTINEL
1619 };
1620
1621 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1622 {
1623 env->cp15.c1_sys = value;
1624 /* ??? Lots of these bits are not implemented. */
1625 /* This may enable/disable the MMU, so do a TLB flush. */
1626 tlb_flush(env, 1);
1627 return 0;
1628 }
1629
1630 void register_cp_regs_for_features(ARMCPU *cpu)
1631 {
1632 /* Register all the coprocessor registers based on feature bits */
1633 CPUARMState *env = &cpu->env;
1634 if (arm_feature(env, ARM_FEATURE_M)) {
1635 /* M profile has no coprocessor registers */
1636 return;
1637 }
1638
1639 define_arm_cp_regs(cpu, cp_reginfo);
1640 if (arm_feature(env, ARM_FEATURE_V6)) {
1641 /* The ID registers all have impdef reset values */
1642 ARMCPRegInfo v6_idregs[] = {
1643 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
1644 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1645 .resetvalue = cpu->id_pfr0 },
1646 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
1647 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1648 .resetvalue = cpu->id_pfr1 },
1649 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
1650 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1651 .resetvalue = cpu->id_dfr0 },
1652 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
1653 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1654 .resetvalue = cpu->id_afr0 },
1655 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
1656 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1657 .resetvalue = cpu->id_mmfr0 },
1658 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
1659 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1660 .resetvalue = cpu->id_mmfr1 },
1661 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
1662 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1663 .resetvalue = cpu->id_mmfr2 },
1664 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
1665 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1666 .resetvalue = cpu->id_mmfr3 },
1667 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
1668 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
1669 .resetvalue = cpu->id_isar0 },
1670 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
1671 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
1672 .resetvalue = cpu->id_isar1 },
1673 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
1674 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
1675 .resetvalue = cpu->id_isar2 },
1676 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
1677 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
1678 .resetvalue = cpu->id_isar3 },
1679 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
1680 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
1681 .resetvalue = cpu->id_isar4 },
1682 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
1683 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
1684 .resetvalue = cpu->id_isar5 },
1685 /* 6..7 are as yet unallocated and must RAZ */
1686 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
1687 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
1688 .resetvalue = 0 },
1689 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
1690 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
1691 .resetvalue = 0 },
1692 REGINFO_SENTINEL
1693 };
1694 define_arm_cp_regs(cpu, v6_idregs);
1695 define_arm_cp_regs(cpu, v6_cp_reginfo);
1696 } else {
1697 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
1698 }
1699 if (arm_feature(env, ARM_FEATURE_V6K)) {
1700 define_arm_cp_regs(cpu, v6k_cp_reginfo);
1701 }
1702 if (arm_feature(env, ARM_FEATURE_V7)) {
1703 /* v7 performance monitor control register: same implementor
1704 * field as main ID register, and we implement no event counters.
1705 */
1706 ARMCPRegInfo pmcr = {
1707 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
1708 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
1709 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
1710 .readfn = pmreg_read, .writefn = pmcr_write,
1711 .raw_readfn = raw_read, .raw_writefn = raw_write,
1712 };
1713 ARMCPRegInfo clidr = {
1714 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
1715 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
1716 };
1717 define_one_arm_cp_reg(cpu, &pmcr);
1718 define_one_arm_cp_reg(cpu, &clidr);
1719 define_arm_cp_regs(cpu, v7_cp_reginfo);
1720 } else {
1721 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
1722 }
1723 if (arm_feature(env, ARM_FEATURE_V8)) {
1724 define_arm_cp_regs(cpu, v8_cp_reginfo);
1725 }
1726 if (arm_feature(env, ARM_FEATURE_MPU)) {
1727 /* These are the MPU registers prior to PMSAv6. Any new
1728 * PMSA core later than the ARM946 will require that we
1729 * implement the PMSAv6 or PMSAv7 registers, which are
1730 * completely different.
1731 */
1732 assert(!arm_feature(env, ARM_FEATURE_V6));
1733 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
1734 } else {
1735 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
1736 }
1737 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
1738 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
1739 }
1740 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1741 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
1742 }
1743 if (arm_feature(env, ARM_FEATURE_VAPA)) {
1744 define_arm_cp_regs(cpu, vapa_cp_reginfo);
1745 }
1746 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
1747 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
1748 }
1749 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
1750 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
1751 }
1752 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
1753 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
1754 }
1755 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1756 define_arm_cp_regs(cpu, omap_cp_reginfo);
1757 }
1758 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
1759 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
1760 }
1761 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1762 define_arm_cp_regs(cpu, xscale_cp_reginfo);
1763 }
1764 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
1765 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
1766 }
1767 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1768 define_arm_cp_regs(cpu, lpae_cp_reginfo);
1769 }
1770 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1771 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1772 * be read-only (ie write causes UNDEF exception).
1773 */
1774 {
1775 ARMCPRegInfo id_cp_reginfo[] = {
1776 /* Note that the MIDR isn't a simple constant register because
1777 * of the TI925 behaviour where writes to another register can
1778 * cause the MIDR value to change.
1779 *
1780 * Unimplemented registers in the c15 0 0 0 space default to
1781 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
1782 * and friends override accordingly.
1783 */
1784 { .name = "MIDR",
1785 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
1786 .access = PL1_R, .resetvalue = cpu->midr,
1787 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
1788 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
1789 .type = ARM_CP_OVERRIDE },
1790 { .name = "CTR",
1791 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
1792 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
1793 { .name = "TCMTR",
1794 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
1795 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1796 { .name = "TLBTR",
1797 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
1798 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1799 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1800 { .name = "DUMMY",
1801 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
1802 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1803 { .name = "DUMMY",
1804 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
1805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1806 { .name = "DUMMY",
1807 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
1808 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1809 { .name = "DUMMY",
1810 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
1811 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1812 { .name = "DUMMY",
1813 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
1814 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1815 REGINFO_SENTINEL
1816 };
1817 ARMCPRegInfo crn0_wi_reginfo = {
1818 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
1819 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
1820 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
1821 };
1822 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
1823 arm_feature(env, ARM_FEATURE_STRONGARM)) {
1824 ARMCPRegInfo *r;
1825 /* Register the blanket "writes ignored" value first to cover the
1826 * whole space. Then update the specific ID registers to allow write
1827 * access, so that they ignore writes rather than causing them to
1828 * UNDEF.
1829 */
1830 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
1831 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
1832 r->access = PL1_RW;
1833 }
1834 }
1835 define_arm_cp_regs(cpu, id_cp_reginfo);
1836 }
1837
1838 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
1839 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
1840 }
1841
1842 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
1843 ARMCPRegInfo auxcr = {
1844 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
1845 .access = PL1_RW, .type = ARM_CP_CONST,
1846 .resetvalue = cpu->reset_auxcr
1847 };
1848 define_one_arm_cp_reg(cpu, &auxcr);
1849 }
1850
1851 if (arm_feature(env, ARM_FEATURE_CBAR)) {
1852 ARMCPRegInfo cbar = {
1853 .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
1854 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
1855 .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
1856 };
1857 define_one_arm_cp_reg(cpu, &cbar);
1858 }
1859
1860 /* Generic registers whose values depend on the implementation */
1861 {
1862 ARMCPRegInfo sctlr = {
1863 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
1864 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
1865 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
1866 .raw_writefn = raw_write,
1867 };
1868 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1869 /* Normally we would always end the TB on an SCTLR write, but Linux
1870 * arch/arm/mach-pxa/sleep.S expects two instructions following
1871 * an MMU enable to execute from cache. Imitate this behaviour.
1872 */
1873 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1874 }
1875 define_one_arm_cp_reg(cpu, &sctlr);
1876 }
1877 }
1878
1879 ARMCPU *cpu_arm_init(const char *cpu_model)
1880 {
1881 ARMCPU *cpu;
1882 ObjectClass *oc;
1883
1884 oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
1885 if (!oc) {
1886 return NULL;
1887 }
1888 cpu = ARM_CPU(object_new(object_class_get_name(oc)));
1889
1890 /* TODO this should be set centrally, once possible */
1891 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1892
1893 return cpu;
1894 }
1895
1896 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
1897 {
1898 CPUState *cs = CPU(cpu);
1899 CPUARMState *env = &cpu->env;
1900
1901 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1902 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
1903 aarch64_fpu_gdb_set_reg,
1904 34, "aarch64-fpu.xml", 0);
1905 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
1906 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1907 51, "arm-neon.xml", 0);
1908 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1909 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1910 35, "arm-vfp3.xml", 0);
1911 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1912 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
1913 19, "arm-vfp.xml", 0);
1914 }
1915 }
1916
1917 /* Sort alphabetically by type name, except for "any". */
1918 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
1919 {
1920 ObjectClass *class_a = (ObjectClass *)a;
1921 ObjectClass *class_b = (ObjectClass *)b;
1922 const char *name_a, *name_b;
1923
1924 name_a = object_class_get_name(class_a);
1925 name_b = object_class_get_name(class_b);
1926 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
1927 return 1;
1928 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
1929 return -1;
1930 } else {
1931 return strcmp(name_a, name_b);
1932 }
1933 }
1934
1935 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
1936 {
1937 ObjectClass *oc = data;
1938 CPUListState *s = user_data;
1939 const char *typename;
1940 char *name;
1941
1942 typename = object_class_get_name(oc);
1943 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
1944 (*s->cpu_fprintf)(s->file, " %s\n",
1945 name);
1946 g_free(name);
1947 }
1948
1949 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1950 {
1951 CPUListState s = {
1952 .file = f,
1953 .cpu_fprintf = cpu_fprintf,
1954 };
1955 GSList *list;
1956
1957 list = object_class_get_list(TYPE_ARM_CPU, false);
1958 list = g_slist_sort(list, arm_cpu_list_compare);
1959 (*cpu_fprintf)(f, "Available CPUs:\n");
1960 g_slist_foreach(list, arm_cpu_list_entry, &s);
1961 g_slist_free(list);
1962 #ifdef CONFIG_KVM
1963 /* The 'host' CPU type is dynamically registered only if KVM is
1964 * enabled, so we have to special-case it here:
1965 */
1966 (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
1967 #endif
1968 }
1969
1970 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
1971 {
1972 ObjectClass *oc = data;
1973 CpuDefinitionInfoList **cpu_list = user_data;
1974 CpuDefinitionInfoList *entry;
1975 CpuDefinitionInfo *info;
1976 const char *typename;
1977
1978 typename = object_class_get_name(oc);
1979 info = g_malloc0(sizeof(*info));
1980 info->name = g_strndup(typename,
1981 strlen(typename) - strlen("-" TYPE_ARM_CPU));
1982
1983 entry = g_malloc0(sizeof(*entry));
1984 entry->value = info;
1985 entry->next = *cpu_list;
1986 *cpu_list = entry;
1987 }
1988
1989 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1990 {
1991 CpuDefinitionInfoList *cpu_list = NULL;
1992 GSList *list;
1993
1994 list = object_class_get_list(TYPE_ARM_CPU, false);
1995 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
1996 g_slist_free(list);
1997
1998 return cpu_list;
1999 }
2000
2001 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2002 void *opaque, int state,
2003 int crm, int opc1, int opc2)
2004 {
2005 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2006 * add a single reginfo struct to the hash table.
2007 */
2008 uint32_t *key = g_new(uint32_t, 1);
2009 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2010 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2011 if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2012 /* The AArch32 view of a shared register sees the lower 32 bits
2013 * of a 64 bit backing field. It is not migratable as the AArch64
2014 * view handles that. AArch64 also handles reset.
2015 * We assume it is a cp15 register.
2016 */
2017 r2->cp = 15;
2018 r2->type |= ARM_CP_NO_MIGRATE;
2019 r2->resetfn = arm_cp_reset_ignore;
2020 #ifdef HOST_WORDS_BIGENDIAN
2021 if (r2->fieldoffset) {
2022 r2->fieldoffset += sizeof(uint32_t);
2023 }
2024 #endif
2025 }
2026 if (state == ARM_CP_STATE_AA64) {
2027 /* To allow abbreviation of ARMCPRegInfo
2028 * definitions, we treat cp == 0 as equivalent to
2029 * the value for "standard guest-visible sysreg".
2030 */
2031 if (r->cp == 0) {
2032 r2->cp = CP_REG_ARM64_SYSREG_CP;
2033 }
2034 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2035 r2->opc0, opc1, opc2);
2036 } else {
2037 *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2038 }
2039 if (opaque) {
2040 r2->opaque = opaque;
2041 }
2042 /* Make sure reginfo passed to helpers for wildcarded regs
2043 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2044 */
2045 r2->crm = crm;
2046 r2->opc1 = opc1;
2047 r2->opc2 = opc2;
2048 /* By convention, for wildcarded registers only the first
2049 * entry is used for migration; the others are marked as
2050 * NO_MIGRATE so we don't try to transfer the register
2051 * multiple times. Special registers (ie NOP/WFI) are
2052 * never migratable.
2053 */
2054 if ((r->type & ARM_CP_SPECIAL) ||
2055 ((r->crm == CP_ANY) && crm != 0) ||
2056 ((r->opc1 == CP_ANY) && opc1 != 0) ||
2057 ((r->opc2 == CP_ANY) && opc2 != 0)) {
2058 r2->type |= ARM_CP_NO_MIGRATE;
2059 }
2060
2061 /* Overriding of an existing definition must be explicitly
2062 * requested.
2063 */
2064 if (!(r->type & ARM_CP_OVERRIDE)) {
2065 ARMCPRegInfo *oldreg;
2066 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2067 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2068 fprintf(stderr, "Register redefined: cp=%d %d bit "
2069 "crn=%d crm=%d opc1=%d opc2=%d, "
2070 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2071 r2->crn, r2->crm, r2->opc1, r2->opc2,
2072 oldreg->name, r2->name);
2073 g_assert_not_reached();
2074 }
2075 }
2076 g_hash_table_insert(cpu->cp_regs, key, r2);
2077 }
2078
2079
2080 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2081 const ARMCPRegInfo *r, void *opaque)
2082 {
2083 /* Define implementations of coprocessor registers.
2084 * We store these in a hashtable because typically
2085 * there are less than 150 registers in a space which
2086 * is 16*16*16*8*8 = 262144 in size.
2087 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2088 * If a register is defined twice then the second definition is
2089 * used, so this can be used to define some generic registers and
2090 * then override them with implementation specific variations.
2091 * At least one of the original and the second definition should
2092 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2093 * against accidental use.
2094 *
2095 * The state field defines whether the register is to be
2096 * visible in the AArch32 or AArch64 execution state. If the
2097 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2098 * reginfo structure for the AArch32 view, which sees the lower
2099 * 32 bits of the 64 bit register.
2100 *
2101 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2102 * be wildcarded. AArch64 registers are always considered to be 64
2103 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2104 * the register, if any.
2105 */
2106 int crm, opc1, opc2, state;
2107 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2108 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2109 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2110 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2111 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2112 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2113 /* 64 bit registers have only CRm and Opc1 fields */
2114 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2115 /* op0 only exists in the AArch64 encodings */
2116 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2117 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2118 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2119 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2120 * encodes a minimum access level for the register. We roll this
2121 * runtime check into our general permission check code, so check
2122 * here that the reginfo's specified permissions are strict enough
2123 * to encompass the generic architectural permission check.
2124 */
2125 if (r->state != ARM_CP_STATE_AA32) {
2126 int mask = 0;
2127 switch (r->opc1) {
2128 case 0: case 1: case 2:
2129 /* min_EL EL1 */
2130 mask = PL1_RW;
2131 break;
2132 case 3:
2133 /* min_EL EL0 */
2134 mask = PL0_RW;
2135 break;
2136 case 4:
2137 /* min_EL EL2 */
2138 mask = PL2_RW;
2139 break;
2140 case 5:
2141 /* unallocated encoding, so not possible */
2142 assert(false);
2143 break;
2144 case 6:
2145 /* min_EL EL3 */
2146 mask = PL3_RW;
2147 break;
2148 case 7:
2149 /* min_EL EL1, secure mode only (we don't check the latter) */
2150 mask = PL1_RW;
2151 break;
2152 default:
2153 /* broken reginfo with out-of-range opc1 */
2154 assert(false);
2155 break;
2156 }
2157 /* assert our permissions are not too lax (stricter is fine) */
2158 assert((r->access & ~mask) == 0);
2159 }
2160
2161 /* Check that the register definition has enough info to handle
2162 * reads and writes if they are permitted.
2163 */
2164 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2165 if (r->access & PL3_R) {
2166 assert(r->fieldoffset || r->readfn);
2167 }
2168 if (r->access & PL3_W) {
2169 assert(r->fieldoffset || r->writefn);
2170 }
2171 }
2172 /* Bad type field probably means missing sentinel at end of reg list */
2173 assert(cptype_valid(r->type));
2174 for (crm = crmmin; crm <= crmmax; crm++) {
2175 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2176 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2177 for (state = ARM_CP_STATE_AA32;
2178 state <= ARM_CP_STATE_AA64; state++) {
2179 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2180 continue;
2181 }
2182 add_cpreg_to_hashtable(cpu, r, opaque, state,
2183 crm, opc1, opc2);
2184 }
2185 }
2186 }
2187 }
2188 }
2189
2190 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2191 const ARMCPRegInfo *regs, void *opaque)
2192 {
2193 /* Define a whole list of registers */
2194 const ARMCPRegInfo *r;
2195 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2196 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2197 }
2198 }
2199
2200 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2201 {
2202 return g_hash_table_lookup(cpregs, &encoded_cp);
2203 }
2204
2205 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2206 uint64_t value)
2207 {
2208 /* Helper coprocessor write function for write-ignore registers */
2209 return 0;
2210 }
2211
2212 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
2213 {
2214 /* Helper coprocessor write function for read-as-zero registers */
2215 *value = 0;
2216 return 0;
2217 }
2218
2219 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2220 {
2221 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2222 }
2223
2224 static int bad_mode_switch(CPUARMState *env, int mode)
2225 {
2226 /* Return true if it is not valid for us to switch to
2227 * this CPU mode (ie all the UNPREDICTABLE cases in
2228 * the ARM ARM CPSRWriteByInstr pseudocode).
2229 */
2230 switch (mode) {
2231 case ARM_CPU_MODE_USR:
2232 case ARM_CPU_MODE_SYS:
2233 case ARM_CPU_MODE_SVC:
2234 case ARM_CPU_MODE_ABT:
2235 case ARM_CPU_MODE_UND:
2236 case ARM_CPU_MODE_IRQ:
2237 case ARM_CPU_MODE_FIQ:
2238 return 0;
2239 default:
2240 return 1;
2241 }
2242 }
2243
2244 uint32_t cpsr_read(CPUARMState *env)
2245 {
2246 int ZF;
2247 ZF = (env->ZF == 0);
2248 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2249 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2250 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2251 | ((env->condexec_bits & 0xfc) << 8)
2252 | (env->GE << 16);
2253 }
2254
2255 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2256 {
2257 if (mask & CPSR_NZCV) {
2258 env->ZF = (~val) & CPSR_Z;
2259 env->NF = val;
2260 env->CF = (val >> 29) & 1;
2261 env->VF = (val << 3) & 0x80000000;
2262 }
2263 if (mask & CPSR_Q)
2264 env->QF = ((val & CPSR_Q) != 0);
2265 if (mask & CPSR_T)
2266 env->thumb = ((val & CPSR_T) != 0);
2267 if (mask & CPSR_IT_0_1) {
2268 env->condexec_bits &= ~3;
2269 env->condexec_bits |= (val >> 25) & 3;
2270 }
2271 if (mask & CPSR_IT_2_7) {
2272 env->condexec_bits &= 3;
2273 env->condexec_bits |= (val >> 8) & 0xfc;
2274 }
2275 if (mask & CPSR_GE) {
2276 env->GE = (val >> 16) & 0xf;
2277 }
2278
2279 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2280 if (bad_mode_switch(env, val & CPSR_M)) {
2281 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2282 * We choose to ignore the attempt and leave the CPSR M field
2283 * untouched.
2284 */
2285 mask &= ~CPSR_M;
2286 } else {
2287 switch_mode(env, val & CPSR_M);
2288 }
2289 }
2290 mask &= ~CACHED_CPSR_BITS;
2291 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2292 }
2293
2294 /* Sign/zero extend */
2295 uint32_t HELPER(sxtb16)(uint32_t x)
2296 {
2297 uint32_t res;
2298 res = (uint16_t)(int8_t)x;
2299 res |= (uint32_t)(int8_t)(x >> 16) << 16;
2300 return res;
2301 }
2302
2303 uint32_t HELPER(uxtb16)(uint32_t x)
2304 {
2305 uint32_t res;
2306 res = (uint16_t)(uint8_t)x;
2307 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2308 return res;
2309 }
2310
2311 uint32_t HELPER(clz)(uint32_t x)
2312 {
2313 return clz32(x);
2314 }
2315
2316 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2317 {
2318 if (den == 0)
2319 return 0;
2320 if (num == INT_MIN && den == -1)
2321 return INT_MIN;
2322 return num / den;
2323 }
2324
2325 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2326 {
2327 if (den == 0)
2328 return 0;
2329 return num / den;
2330 }
2331
2332 uint32_t HELPER(rbit)(uint32_t x)
2333 {
2334 x = ((x & 0xff000000) >> 24)
2335 | ((x & 0x00ff0000) >> 8)
2336 | ((x & 0x0000ff00) << 8)
2337 | ((x & 0x000000ff) << 24);
2338 x = ((x & 0xf0f0f0f0) >> 4)
2339 | ((x & 0x0f0f0f0f) << 4);
2340 x = ((x & 0x88888888) >> 3)
2341 | ((x & 0x44444444) >> 1)
2342 | ((x & 0x22222222) << 1)
2343 | ((x & 0x11111111) << 3);
2344 return x;
2345 }
2346
2347 #if defined(CONFIG_USER_ONLY)
2348
2349 void arm_cpu_do_interrupt(CPUState *cs)
2350 {
2351 ARMCPU *cpu = ARM_CPU(cs);
2352 CPUARMState *env = &cpu->env;
2353
2354 env->exception_index = -1;
2355 }
2356
2357 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
2358 int mmu_idx)
2359 {
2360 if (rw == 2) {
2361 env->exception_index = EXCP_PREFETCH_ABORT;
2362 env->cp15.c6_insn = address;
2363 } else {
2364 env->exception_index = EXCP_DATA_ABORT;
2365 env->cp15.c6_data = address;
2366 }
2367 return 1;
2368 }
2369
2370 /* These should probably raise undefined insn exceptions. */
2371 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
2372 {
2373 cpu_abort(env, "v7m_mrs %d\n", reg);
2374 }
2375
2376 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
2377 {
2378 cpu_abort(env, "v7m_mrs %d\n", reg);
2379 return 0;
2380 }
2381
2382 void switch_mode(CPUARMState *env, int mode)
2383 {
2384 if (mode != ARM_CPU_MODE_USR)
2385 cpu_abort(env, "Tried to switch out of user mode\n");
2386 }
2387
2388 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
2389 {
2390 cpu_abort(env, "banked r13 write\n");
2391 }
2392
2393 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
2394 {
2395 cpu_abort(env, "banked r13 read\n");
2396 return 0;
2397 }
2398
2399 #else
2400
2401 /* Map CPU modes onto saved register banks. */
2402 int bank_number(int mode)
2403 {
2404 switch (mode) {
2405 case ARM_CPU_MODE_USR:
2406 case ARM_CPU_MODE_SYS:
2407 return 0;
2408 case ARM_CPU_MODE_SVC:
2409 return 1;
2410 case ARM_CPU_MODE_ABT:
2411 return 2;
2412 case ARM_CPU_MODE_UND:
2413 return 3;
2414 case ARM_CPU_MODE_IRQ:
2415 return 4;
2416 case ARM_CPU_MODE_FIQ:
2417 return 5;
2418 }
2419 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
2420 }
2421
2422 void switch_mode(CPUARMState *env, int mode)
2423 {
2424 int old_mode;
2425 int i;
2426
2427 old_mode = env->uncached_cpsr & CPSR_M;
2428 if (mode == old_mode)
2429 return;
2430
2431 if (old_mode == ARM_CPU_MODE_FIQ) {
2432 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
2433 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
2434 } else if (mode == ARM_CPU_MODE_FIQ) {
2435 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
2436 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
2437 }
2438
2439 i = bank_number(old_mode);
2440 env->banked_r13[i] = env->regs[13];
2441 env->banked_r14[i] = env->regs[14];
2442 env->banked_spsr[i] = env->spsr;
2443
2444 i = bank_number(mode);
2445 env->regs[13] = env->banked_r13[i];
2446 env->regs[14] = env->banked_r14[i];
2447 env->spsr = env->banked_spsr[i];
2448 }
2449
2450 static void v7m_push(CPUARMState *env, uint32_t val)
2451 {
2452 CPUState *cs = ENV_GET_CPU(env);
2453 env->regs[13] -= 4;
2454 stl_phys(cs->as, env->regs[13], val);
2455 }
2456
2457 static uint32_t v7m_pop(CPUARMState *env)
2458 {
2459 CPUState *cs = ENV_GET_CPU(env);
2460 uint32_t val;
2461 val = ldl_phys(cs->as, env->regs[13]);
2462 env->regs[13] += 4;
2463 return val;
2464 }
2465
2466 /* Switch to V7M main or process stack pointer. */
2467 static void switch_v7m_sp(CPUARMState *env, int process)
2468 {
2469 uint32_t tmp;
2470 if (env->v7m.current_sp != process) {
2471 tmp = env->v7m.other_sp;
2472 env->v7m.other_sp = env->regs[13];
2473 env->regs[13] = tmp;
2474 env->v7m.current_sp = process;
2475 }
2476 }
2477
2478 static void do_v7m_exception_exit(CPUARMState *env)
2479 {
2480 uint32_t type;
2481 uint32_t xpsr;
2482
2483 type = env->regs[15];
2484 if (env->v7m.exception != 0)
2485 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
2486
2487 /* Switch to the target stack. */
2488 switch_v7m_sp(env, (type & 4) != 0);
2489 /* Pop registers. */
2490 env->regs[0] = v7m_pop(env);
2491 env->regs[1] = v7m_pop(env);
2492 env->regs[2] = v7m_pop(env);
2493 env->regs[3] = v7m_pop(env);
2494 env->regs[12] = v7m_pop(env);
2495 env->regs[14] = v7m_pop(env);
2496 env->regs[15] = v7m_pop(env);
2497 xpsr = v7m_pop(env);
2498 xpsr_write(env, xpsr, 0xfffffdff);
2499 /* Undo stack alignment. */
2500 if (xpsr & 0x200)
2501 env->regs[13] |= 4;
2502 /* ??? The exception return type specifies Thread/Handler mode. However
2503 this is also implied by the xPSR value. Not sure what to do
2504 if there is a mismatch. */
2505 /* ??? Likewise for mismatches between the CONTROL register and the stack
2506 pointer. */
2507 }
2508
2509 /* Exception names for debug logging; note that not all of these
2510 * precisely correspond to architectural exceptions.
2511 */
2512 static const char * const excnames[] = {
2513 [EXCP_UDEF] = "Undefined Instruction",
2514 [EXCP_SWI] = "SVC",
2515 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
2516 [EXCP_DATA_ABORT] = "Data Abort",
2517 [EXCP_IRQ] = "IRQ",
2518 [EXCP_FIQ] = "FIQ",
2519 [EXCP_BKPT] = "Breakpoint",
2520 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
2521 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
2522 [EXCP_STREX] = "QEMU intercept of STREX",
2523 };
2524
2525 static inline void arm_log_exception(int idx)
2526 {
2527 if (qemu_loglevel_mask(CPU_LOG_INT)) {
2528 const char *exc = NULL;
2529
2530 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
2531 exc = excnames[idx];
2532 }
2533 if (!exc) {
2534 exc = "unknown";
2535 }
2536 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
2537 }
2538 }
2539
2540 void arm_v7m_cpu_do_interrupt(CPUState *cs)
2541 {
2542 ARMCPU *cpu = ARM_CPU(cs);
2543 CPUARMState *env = &cpu->env;
2544 uint32_t xpsr = xpsr_read(env);
2545 uint32_t lr;
2546 uint32_t addr;
2547
2548 arm_log_exception(env->exception_index);
2549
2550 lr = 0xfffffff1;
2551 if (env->v7m.current_sp)
2552 lr |= 4;
2553 if (env->v7m.exception == 0)
2554 lr |= 8;
2555
2556 /* For exceptions we just mark as pending on the NVIC, and let that
2557 handle it. */
2558 /* TODO: Need to escalate if the current priority is higher than the
2559 one we're raising. */
2560 switch (env->exception_index) {
2561 case EXCP_UDEF:
2562 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
2563 return;
2564 case EXCP_SWI:
2565 /* The PC already points to the next instruction. */
2566 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
2567 return;
2568 case EXCP_PREFETCH_ABORT:
2569 case EXCP_DATA_ABORT:
2570 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
2571 return;
2572 case EXCP_BKPT:
2573 if (semihosting_enabled) {
2574 int nr;
2575 nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2576 if (nr == 0xab) {
2577 env->regs[15] += 2;
2578 env->regs[0] = do_arm_semihosting(env);
2579 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2580 return;
2581 }
2582 }
2583 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
2584 return;
2585 case EXCP_IRQ:
2586 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
2587 break;
2588 case EXCP_EXCEPTION_EXIT:
2589 do_v7m_exception_exit(env);
2590 return;
2591 default:
2592 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2593 return; /* Never happens. Keep compiler happy. */
2594 }
2595
2596 /* Align stack pointer. */
2597 /* ??? Should only do this if Configuration Control Register
2598 STACKALIGN bit is set. */
2599 if (env->regs[13] & 4) {
2600 env->regs[13] -= 4;
2601 xpsr |= 0x200;
2602 }
2603 /* Switch to the handler mode. */
2604 v7m_push(env, xpsr);
2605 v7m_push(env, env->regs[15]);
2606 v7m_push(env, env->regs[14]);
2607 v7m_push(env, env->regs[12]);
2608 v7m_push(env, env->regs[3]);
2609 v7m_push(env, env->regs[2]);
2610 v7m_push(env, env->regs[1]);
2611 v7m_push(env, env->regs[0]);
2612 switch_v7m_sp(env, 0);
2613 /* Clear IT bits */
2614 env->condexec_bits = 0;
2615 env->regs[14] = lr;
2616 addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
2617 env->regs[15] = addr & 0xfffffffe;
2618 env->thumb = addr & 1;
2619 }
2620
2621 /* Handle a CPU exception. */
2622 void arm_cpu_do_interrupt(CPUState *cs)
2623 {
2624 ARMCPU *cpu = ARM_CPU(cs);
2625 CPUARMState *env = &cpu->env;
2626 uint32_t addr;
2627 uint32_t mask;
2628 int new_mode;
2629 uint32_t offset;
2630
2631 assert(!IS_M(env));
2632
2633 arm_log_exception(env->exception_index);
2634
2635 /* TODO: Vectored interrupt controller. */
2636 switch (env->exception_index) {
2637 case EXCP_UDEF:
2638 new_mode = ARM_CPU_MODE_UND;
2639 addr = 0x04;
2640 mask = CPSR_I;
2641 if (env->thumb)
2642 offset = 2;
2643 else
2644 offset = 4;
2645 break;
2646 case EXCP_SWI:
2647 if (semihosting_enabled) {
2648 /* Check for semihosting interrupt. */
2649 if (env->thumb) {
2650 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
2651 & 0xff;
2652 } else {
2653 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
2654 & 0xffffff;
2655 }
2656 /* Only intercept calls from privileged modes, to provide some
2657 semblance of security. */
2658 if (((mask == 0x123456 && !env->thumb)
2659 || (mask == 0xab && env->thumb))
2660 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2661 env->regs[0] = do_arm_semihosting(env);
2662 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2663 return;
2664 }
2665 }
2666 new_mode = ARM_CPU_MODE_SVC;
2667 addr = 0x08;
2668 mask = CPSR_I;
2669 /* The PC already points to the next instruction. */
2670 offset = 0;
2671 break;
2672 case EXCP_BKPT:
2673 /* See if this is a semihosting syscall. */
2674 if (env->thumb && semihosting_enabled) {
2675 mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
2676 if (mask == 0xab
2677 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
2678 env->regs[15] += 2;
2679 env->regs[0] = do_arm_semihosting(env);
2680 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
2681 return;
2682 }
2683 }
2684 env->cp15.c5_insn = 2;
2685 /* Fall through to prefetch abort. */
2686 case EXCP_PREFETCH_ABORT:
2687 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
2688 env->cp15.c5_insn, env->cp15.c6_insn);
2689 new_mode = ARM_CPU_MODE_ABT;
2690 addr = 0x0c;
2691 mask = CPSR_A | CPSR_I;
2692 offset = 4;
2693 break;
2694 case EXCP_DATA_ABORT:
2695 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
2696 env->cp15.c5_data, env->cp15.c6_data);
2697 new_mode = ARM_CPU_MODE_ABT;
2698 addr = 0x10;
2699 mask = CPSR_A | CPSR_I;
2700 offset = 8;
2701 break;
2702 case EXCP_IRQ:
2703 new_mode = ARM_CPU_MODE_IRQ;
2704 addr = 0x18;
2705 /* Disable IRQ and imprecise data aborts. */
2706 mask = CPSR_A | CPSR_I;
2707 offset = 4;
2708 break;
2709 case EXCP_FIQ:
2710 new_mode = ARM_CPU_MODE_FIQ;
2711 addr = 0x1c;
2712 /* Disable FIQ, IRQ and imprecise data aborts. */
2713 mask = CPSR_A | CPSR_I | CPSR_F;
2714 offset = 4;
2715 break;
2716 default:
2717 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
2718 return; /* Never happens. Keep compiler happy. */
2719 }
2720 /* High vectors. */
2721 if (env->cp15.c1_sys & (1 << 13)) {
2722 /* when enabled, base address cannot be remapped. */
2723 addr += 0xffff0000;
2724 } else {
2725 /* ARM v7 architectures provide a vector base address register to remap
2726 * the interrupt vector table.
2727 * This register is only followed in non-monitor mode, and has a secure
2728 * and un-secure copy. Since the cpu is always in a un-secure operation
2729 * and is never in monitor mode this feature is always active.
2730 * Note: only bits 31:5 are valid.
2731 */
2732 addr += env->cp15.c12_vbar;
2733 }
2734 switch_mode (env, new_mode);
2735 env->spsr = cpsr_read(env);
2736 /* Clear IT bits. */
2737 env->condexec_bits = 0;
2738 /* Switch to the new mode, and to the correct instruction set. */
2739 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
2740 env->uncached_cpsr |= mask;
2741 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
2742 * and we should just guard the thumb mode on V4 */
2743 if (arm_feature(env, ARM_FEATURE_V4T)) {
2744 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
2745 }
2746 env->regs[14] = env->regs[15] + offset;
2747 env->regs[15] = addr;
2748 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
2749 }
2750
2751 /* Check section/page access permissions.
2752 Returns the page protection flags, or zero if the access is not
2753 permitted. */
2754 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
2755 int access_type, int is_user)
2756 {
2757 int prot_ro;
2758
2759 if (domain_prot == 3) {
2760 return PAGE_READ | PAGE_WRITE;
2761 }
2762
2763 if (access_type == 1)
2764 prot_ro = 0;
2765 else
2766 prot_ro = PAGE_READ;
2767
2768 switch (ap) {
2769 case 0:
2770 if (access_type == 1)
2771 return 0;
2772 switch ((env->cp15.c1_sys >> 8) & 3) {
2773 case 1:
2774 return is_user ? 0 : PAGE_READ;
2775 case 2:
2776 return PAGE_READ;
2777 default:
2778 return 0;
2779 }
2780 case 1:
2781 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
2782 case 2:
2783 if (is_user)
2784 return prot_ro;
2785 else
2786 return PAGE_READ | PAGE_WRITE;
2787 case 3:
2788 return PAGE_READ | PAGE_WRITE;
2789 case 4: /* Reserved. */
2790 return 0;
2791 case 5:
2792 return is_user ? 0 : prot_ro;
2793 case 6:
2794 return prot_ro;
2795 case 7:
2796 if (!arm_feature (env, ARM_FEATURE_V6K))
2797 return 0;
2798 return prot_ro;
2799 default:
2800 abort();
2801 }
2802 }
2803
2804 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
2805 {
2806 uint32_t table;
2807
2808 if (address & env->cp15.c2_mask)
2809 table = env->cp15.c2_base1 & 0xffffc000;
2810 else
2811 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
2812
2813 table |= (address >> 18) & 0x3ffc;
2814 return table;
2815 }
2816
2817 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
2818 int is_user, hwaddr *phys_ptr,
2819 int *prot, target_ulong *page_size)
2820 {
2821 CPUState *cs = ENV_GET_CPU(env);
2822 int code;
2823 uint32_t table;
2824 uint32_t desc;
2825 int type;
2826 int ap;
2827 int domain;
2828 int domain_prot;
2829 hwaddr phys_addr;
2830
2831 /* Pagetable walk. */
2832 /* Lookup l1 descriptor. */
2833 table = get_level1_table_address(env, address);
2834 desc = ldl_phys(cs->as, table);
2835 type = (desc & 3);
2836 domain = (desc >> 5) & 0x0f;
2837 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2838 if (type == 0) {
2839 /* Section translation fault. */
2840 code = 5;
2841 goto do_fault;
2842 }
2843 if (domain_prot == 0 || domain_prot == 2) {
2844 if (type == 2)
2845 code = 9; /* Section domain fault. */
2846 else
2847 code = 11; /* Page domain fault. */
2848 goto do_fault;
2849 }
2850 if (type == 2) {
2851 /* 1Mb section. */
2852 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2853 ap = (desc >> 10) & 3;
2854 code = 13;
2855 *page_size = 1024 * 1024;
2856 } else {
2857 /* Lookup l2 entry. */
2858 if (type == 1) {
2859 /* Coarse pagetable. */
2860 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2861 } else {
2862 /* Fine pagetable. */
2863 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
2864 }
2865 desc = ldl_phys(cs->as, table);
2866 switch (desc & 3) {
2867 case 0: /* Page translation fault. */
2868 code = 7;
2869 goto do_fault;
2870 case 1: /* 64k page. */
2871 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2872 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2873 *page_size = 0x10000;
2874 break;
2875 case 2: /* 4k page. */
2876 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2877 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
2878 *page_size = 0x1000;
2879 break;
2880 case 3: /* 1k page. */
2881 if (type == 1) {
2882 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2883 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2884 } else {
2885 /* Page translation fault. */
2886 code = 7;
2887 goto do_fault;
2888 }
2889 } else {
2890 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
2891 }
2892 ap = (desc >> 4) & 3;
2893 *page_size = 0x400;
2894 break;
2895 default:
2896 /* Never happens, but compiler isn't smart enough to tell. */
2897 abort();
2898 }
2899 code = 15;
2900 }
2901 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
2902 if (!*prot) {
2903 /* Access permission fault. */
2904 goto do_fault;
2905 }
2906 *prot |= PAGE_EXEC;
2907 *phys_ptr = phys_addr;
2908 return 0;
2909 do_fault:
2910 return code | (domain << 4);
2911 }
2912
2913 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
2914 int is_user, hwaddr *phys_ptr,
2915 int *prot, target_ulong *page_size)
2916 {
2917 CPUState *cs = ENV_GET_CPU(env);
2918 int code;
2919 uint32_t table;
2920 uint32_t desc;
2921 uint32_t xn;
2922 uint32_t pxn = 0;
2923 int type;
2924 int ap;
2925 int domain = 0;
2926 int domain_prot;
2927 hwaddr phys_addr;
2928
2929 /* Pagetable walk. */
2930 /* Lookup l1 descriptor. */
2931 table = get_level1_table_address(env, address);
2932 desc = ldl_phys(cs->as, table);
2933 type = (desc & 3);
2934 if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
2935 /* Section translation fault, or attempt to use the encoding
2936 * which is Reserved on implementations without PXN.
2937 */
2938 code = 5;
2939 goto do_fault;
2940 }
2941 if ((type == 1) || !(desc & (1 << 18))) {
2942 /* Page or Section. */
2943 domain = (desc >> 5) & 0x0f;
2944 }
2945 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
2946 if (domain_prot == 0 || domain_prot == 2) {
2947 if (type != 1) {
2948 code = 9; /* Section domain fault. */
2949 } else {
2950 code = 11; /* Page domain fault. */
2951 }
2952 goto do_fault;
2953 }
2954 if (type != 1) {
2955 if (desc & (1 << 18)) {
2956 /* Supersection. */
2957 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
2958 *page_size = 0x1000000;
2959 } else {
2960 /* Section. */
2961 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
2962 *page_size = 0x100000;
2963 }
2964 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
2965 xn = desc & (1 << 4);
2966 pxn = desc & 1;
2967 code = 13;
2968 } else {
2969 if (arm_feature(env, ARM_FEATURE_PXN)) {
2970 pxn = (desc >> 2) & 1;
2971 }
2972 /* Lookup l2 entry. */
2973 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
2974 desc = ldl_phys(cs->as, table);
2975 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
2976 switch (desc & 3) {
2977 case 0: /* Page translation fault. */
2978 code = 7;
2979 goto do_fault;
2980 case 1: /* 64k page. */
2981 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
2982 xn = desc & (1 << 15);
2983 *page_size = 0x10000;
2984 break;
2985 case 2: case 3: /* 4k page. */
2986 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
2987 xn = desc & 1;
2988 *page_size = 0x1000;
2989 break;
2990 default:
2991 /* Never happens, but compiler isn't smart enough to tell. */
2992 abort();
2993 }
2994 code = 15;
2995 }
2996 if (domain_prot == 3) {
2997 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
2998 } else {
2999 if (pxn && !is_user) {
3000 xn = 1;
3001 }
3002 if (xn && access_type == 2)
3003 goto do_fault;
3004
3005 /* The simplified model uses AP[0] as an access control bit. */
3006 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
3007 /* Access flag fault. */
3008 code = (code == 15) ? 6 : 3;
3009 goto do_fault;
3010 }
3011 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3012 if (!*prot) {
3013 /* Access permission fault. */
3014 goto do_fault;
3015 }
3016 if (!xn) {
3017 *prot |= PAGE_EXEC;
3018 }
3019 }
3020 *phys_ptr = phys_addr;
3021 return 0;
3022 do_fault:
3023 return code | (domain << 4);
3024 }
3025
3026 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3027 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3028 */
3029 typedef enum {
3030 translation_fault = 1,
3031 access_fault = 2,
3032 permission_fault = 3,
3033 } MMUFaultType;
3034
3035 static int get_phys_addr_lpae(CPUARMState *env, uint32_t address,
3036 int access_type, int is_user,
3037 hwaddr *phys_ptr, int *prot,
3038 target_ulong *page_size_ptr)
3039 {
3040 CPUState *cs = ENV_GET_CPU(env);
3041 /* Read an LPAE long-descriptor translation table. */
3042 MMUFaultType fault_type = translation_fault;
3043 uint32_t level = 1;
3044 uint32_t epd;
3045 uint32_t tsz;
3046 uint64_t ttbr;
3047 int ttbr_select;
3048 int n;
3049 hwaddr descaddr;
3050 uint32_t tableattrs;
3051 target_ulong page_size;
3052 uint32_t attrs;
3053
3054 /* Determine whether this address is in the region controlled by
3055 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3056 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3057 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3058 */
3059 uint32_t t0sz = extract32(env->cp15.c2_control, 0, 3);
3060 uint32_t t1sz = extract32(env->cp15.c2_control, 16, 3);
3061 if (t0sz && !extract32(address, 32 - t0sz, t0sz)) {
3062 /* there is a ttbr0 region and we are in it (high bits all zero) */
3063 ttbr_select = 0;
3064 } else if (t1sz && !extract32(~address, 32 - t1sz, t1sz)) {
3065 /* there is a ttbr1 region and we are in it (high bits all one) */
3066 ttbr_select = 1;
3067 } else if (!t0sz) {
3068 /* ttbr0 region is "everything not in the ttbr1 region" */
3069 ttbr_select = 0;
3070 } else if (!t1sz) {
3071 /* ttbr1 region is "everything not in the ttbr0 region" */
3072 ttbr_select = 1;
3073 } else {
3074 /* in the gap between the two regions, this is a Translation fault */
3075 fault_type = translation_fault;
3076 goto do_fault;
3077 }
3078
3079 /* Note that QEMU ignores shareability and cacheability attributes,
3080 * so we don't need to do anything with the SH, ORGN, IRGN fields
3081 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3082 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3083 * implement any ASID-like capability so we can ignore it (instead
3084 * we will always flush the TLB any time the ASID is changed).
3085 */
3086 if (ttbr_select == 0) {
3087 ttbr = ((uint64_t)env->cp15.c2_base0_hi << 32) | env->cp15.c2_base0;
3088 epd = extract32(env->cp15.c2_control, 7, 1);
3089 tsz = t0sz;
3090 } else {
3091 ttbr = ((uint64_t)env->cp15.c2_base1_hi << 32) | env->cp15.c2_base1;
3092 epd = extract32(env->cp15.c2_control, 23, 1);
3093 tsz = t1sz;
3094 }
3095
3096 if (epd) {
3097 /* Translation table walk disabled => Translation fault on TLB miss */
3098 goto do_fault;
3099 }
3100
3101 /* If the region is small enough we will skip straight to a 2nd level
3102 * lookup. This affects the number of bits of the address used in
3103 * combination with the TTBR to find the first descriptor. ('n' here
3104 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
3105 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
3106 */
3107 if (tsz > 1) {
3108 level = 2;
3109 n = 14 - tsz;
3110 } else {
3111 n = 5 - tsz;
3112 }
3113
3114 /* Clear the vaddr bits which aren't part of the within-region address,
3115 * so that we don't have to special case things when calculating the
3116 * first descriptor address.
3117 */
3118 address &= (0xffffffffU >> tsz);
3119
3120 /* Now we can extract the actual base address from the TTBR */
3121 descaddr = extract64(ttbr, 0, 40);
3122 descaddr &= ~((1ULL << n) - 1);
3123
3124 tableattrs = 0;
3125 for (;;) {
3126 uint64_t descriptor;
3127
3128 descaddr |= ((address >> (9 * (4 - level))) & 0xff8);
3129 descriptor = ldq_phys(cs->as, descaddr);
3130 if (!(descriptor & 1) ||
3131 (!(descriptor & 2) && (level == 3))) {
3132 /* Invalid, or the Reserved level 3 encoding */
3133 goto do_fault;
3134 }
3135 descaddr = descriptor & 0xfffffff000ULL;
3136
3137 if ((descriptor & 2) && (level < 3)) {
3138 /* Table entry. The top five bits are attributes which may
3139 * propagate down through lower levels of the table (and
3140 * which are all arranged so that 0 means "no effect", so
3141 * we can gather them up by ORing in the bits at each level).
3142 */
3143 tableattrs |= extract64(descriptor, 59, 5);
3144 level++;
3145 continue;
3146 }
3147 /* Block entry at level 1 or 2, or page entry at level 3.
3148 * These are basically the same thing, although the number
3149 * of bits we pull in from the vaddr varies.
3150 */
3151 page_size = (1 << (39 - (9 * level)));
3152 descaddr |= (address & (page_size - 1));
3153 /* Extract attributes from the descriptor and merge with table attrs */
3154 attrs = extract64(descriptor, 2, 10)
3155 | (extract64(descriptor, 52, 12) << 10);
3156 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3157 attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3158 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3159 * means "force PL1 access only", which means forcing AP[1] to 0.
3160 */
3161 if (extract32(tableattrs, 2, 1)) {
3162 attrs &= ~(1 << 4);
3163 }
3164 /* Since we're always in the Non-secure state, NSTable is ignored. */
3165 break;
3166 }
3167 /* Here descaddr is the final physical address, and attributes
3168 * are all in attrs.
3169 */
3170 fault_type = access_fault;
3171 if ((attrs & (1 << 8)) == 0) {
3172 /* Access flag */
3173 goto do_fault;
3174 }
3175 fault_type = permission_fault;
3176 if (is_user && !(attrs & (1 << 4))) {
3177 /* Unprivileged access not enabled */
3178 goto do_fault;
3179 }
3180 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3181 if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3182 /* XN or PXN */
3183 if (access_type == 2) {
3184 goto do_fault;
3185 }
3186 *prot &= ~PAGE_EXEC;
3187 }
3188 if (attrs & (1 << 5)) {
3189 /* Write access forbidden */
3190 if (access_type == 1) {
3191 goto do_fault;
3192 }
3193 *prot &= ~PAGE_WRITE;
3194 }
3195
3196 *phys_ptr = descaddr;
3197 *page_size_ptr = page_size;
3198 return 0;
3199
3200 do_fault:
3201 /* Long-descriptor format IFSR/DFSR value */
3202 return (1 << 9) | (fault_type << 2) | level;
3203 }
3204
3205 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3206 int access_type, int is_user,
3207 hwaddr *phys_ptr, int *prot)
3208 {
3209 int n;
3210 uint32_t mask;
3211 uint32_t base;
3212
3213 *phys_ptr = address;
3214 for (n = 7; n >= 0; n--) {
3215 base = env->cp15.c6_region[n];
3216 if ((base & 1) == 0)
3217 continue;
3218 mask = 1 << ((base >> 1) & 0x1f);
3219 /* Keep this shift separate from the above to avoid an
3220 (undefined) << 32. */
3221 mask = (mask << 1) - 1;
3222 if (((base ^ address) & ~mask) == 0)
3223 break;
3224 }
3225 if (n < 0)
3226 return 2;
3227
3228 if (access_type == 2) {
3229 mask = env->cp15.c5_insn;
3230 } else {
3231 mask = env->cp15.c5_data;
3232 }
3233 mask = (mask >> (n * 4)) & 0xf;
3234 switch (mask) {
3235 case 0:
3236 return 1;
3237 case 1:
3238 if (is_user)
3239 return 1;
3240 *prot = PAGE_READ | PAGE_WRITE;
3241 break;
3242 case 2:
3243 *prot = PAGE_READ;
3244 if (!is_user)
3245 *prot |= PAGE_WRITE;
3246 break;
3247 case 3:
3248 *prot = PAGE_READ | PAGE_WRITE;
3249 break;
3250 case 5:
3251 if (is_user)
3252 return 1;
3253 *prot = PAGE_READ;
3254 break;
3255 case 6:
3256 *prot = PAGE_READ;
3257 break;
3258 default:
3259 /* Bad permission. */
3260 return 1;
3261 }
3262 *prot |= PAGE_EXEC;
3263 return 0;
3264 }
3265
3266 /* get_phys_addr - get the physical address for this virtual address
3267 *
3268 * Find the physical address corresponding to the given virtual address,
3269 * by doing a translation table walk on MMU based systems or using the
3270 * MPU state on MPU based systems.
3271 *
3272 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3273 * prot and page_size are not filled in, and the return value provides
3274 * information on why the translation aborted, in the format of a
3275 * DFSR/IFSR fault register, with the following caveats:
3276 * * we honour the short vs long DFSR format differences.
3277 * * the WnR bit is never set (the caller must do this).
3278 * * for MPU based systems we don't bother to return a full FSR format
3279 * value.
3280 *
3281 * @env: CPUARMState
3282 * @address: virtual address to get physical address for
3283 * @access_type: 0 for read, 1 for write, 2 for execute
3284 * @is_user: 0 for privileged access, 1 for user
3285 * @phys_ptr: set to the physical address corresponding to the virtual address
3286 * @prot: set to the permissions for the page containing phys_ptr
3287 * @page_size: set to the size of the page containing phys_ptr
3288 */
3289 static inline int get_phys_addr(CPUARMState *env, uint32_t address,
3290 int access_type, int is_user,
3291 hwaddr *phys_ptr, int *prot,
3292 target_ulong *page_size)
3293 {
3294 /* Fast Context Switch Extension. */
3295 if (address < 0x02000000)
3296 address += env->cp15.c13_fcse;
3297
3298 if ((env->cp15.c1_sys & 1) == 0) {
3299 /* MMU/MPU disabled. */
3300 *phys_ptr = address;
3301 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3302 *page_size = TARGET_PAGE_SIZE;
3303 return 0;
3304 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
3305 *page_size = TARGET_PAGE_SIZE;
3306 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
3307 prot);
3308 } else if (extended_addresses_enabled(env)) {
3309 return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
3310 prot, page_size);
3311 } else if (env->cp15.c1_sys & (1 << 23)) {
3312 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
3313 prot, page_size);
3314 } else {
3315 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
3316 prot, page_size);
3317 }
3318 }
3319
3320 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
3321 int access_type, int mmu_idx)
3322 {
3323 hwaddr phys_addr;
3324 target_ulong page_size;
3325 int prot;
3326 int ret, is_user;
3327
3328 is_user = mmu_idx == MMU_USER_IDX;
3329 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
3330 &page_size);
3331 if (ret == 0) {
3332 /* Map a single [sub]page. */
3333 phys_addr &= ~(hwaddr)0x3ff;
3334 address &= ~(uint32_t)0x3ff;
3335 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
3336 return 0;
3337 }
3338
3339 if (access_type == 2) {
3340 env->cp15.c5_insn = ret;
3341 env->cp15.c6_insn = address;
3342 env->exception_index = EXCP_PREFETCH_ABORT;
3343 } else {
3344 env->cp15.c5_data = ret;
3345 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
3346 env->cp15.c5_data |= (1 << 11);
3347 env->cp15.c6_data = address;
3348 env->exception_index = EXCP_DATA_ABORT;
3349 }
3350 return 1;
3351 }
3352
3353 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
3354 {
3355 ARMCPU *cpu = ARM_CPU(cs);
3356 hwaddr phys_addr;
3357 target_ulong page_size;
3358 int prot;
3359 int ret;
3360
3361 ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
3362
3363 if (ret != 0) {
3364 return -1;
3365 }
3366
3367 return phys_addr;
3368 }
3369
3370 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3371 {
3372 if ((env->uncached_cpsr & CPSR_M) == mode) {
3373 env->regs[13] = val;
3374 } else {
3375 env->banked_r13[bank_number(mode)] = val;
3376 }
3377 }
3378
3379 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3380 {
3381 if ((env->uncached_cpsr & CPSR_M) == mode) {
3382 return env->regs[13];
3383 } else {
3384 return env->banked_r13[bank_number(mode)];
3385 }
3386 }
3387
3388 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3389 {
3390 switch (reg) {
3391 case 0: /* APSR */
3392 return xpsr_read(env) & 0xf8000000;
3393 case 1: /* IAPSR */
3394 return xpsr_read(env) & 0xf80001ff;
3395 case 2: /* EAPSR */
3396 return xpsr_read(env) & 0xff00fc00;
3397 case 3: /* xPSR */
3398 return xpsr_read(env) & 0xff00fdff;
3399 case 5: /* IPSR */
3400 return xpsr_read(env) & 0x000001ff;
3401 case 6: /* EPSR */
3402 return xpsr_read(env) & 0x0700fc00;
3403 case 7: /* IEPSR */
3404 return xpsr_read(env) & 0x0700edff;
3405 case 8: /* MSP */
3406 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
3407 case 9: /* PSP */
3408 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
3409 case 16: /* PRIMASK */
3410 return (env->uncached_cpsr & CPSR_I) != 0;
3411 case 17: /* BASEPRI */
3412 case 18: /* BASEPRI_MAX */
3413 return env->v7m.basepri;
3414 case 19: /* FAULTMASK */
3415 return (env->uncached_cpsr & CPSR_F) != 0;
3416 case 20: /* CONTROL */
3417 return env->v7m.control;
3418 default:
3419 /* ??? For debugging only. */
3420 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
3421 return 0;
3422 }
3423 }
3424
3425 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3426 {
3427 switch (reg) {
3428 case 0: /* APSR */
3429 xpsr_write(env, val, 0xf8000000);
3430 break;
3431 case 1: /* IAPSR */
3432 xpsr_write(env, val, 0xf8000000);
3433 break;
3434 case 2: /* EAPSR */
3435 xpsr_write(env, val, 0xfe00fc00);
3436 break;
3437 case 3: /* xPSR */
3438 xpsr_write(env, val, 0xfe00fc00);
3439 break;
3440 case 5: /* IPSR */
3441 /* IPSR bits are readonly. */
3442 break;
3443 case 6: /* EPSR */
3444 xpsr_write(env, val, 0x0600fc00);
3445 break;
3446 case 7: /* IEPSR */
3447 xpsr_write(env, val, 0x0600fc00);
3448 break;
3449 case 8: /* MSP */
3450 if (env->v7m.current_sp)
3451 env->v7m.other_sp = val;
3452 else
3453 env->regs[13] = val;
3454 break;
3455 case 9: /* PSP */
3456 if (env->v7m.current_sp)
3457 env->regs[13] = val;
3458 else
3459 env->v7m.other_sp = val;
3460 break;
3461 case 16: /* PRIMASK */
3462 if (val & 1)
3463 env->uncached_cpsr |= CPSR_I;
3464 else
3465 env->uncached_cpsr &= ~CPSR_I;
3466 break;
3467 case 17: /* BASEPRI */
3468 env->v7m.basepri = val & 0xff;
3469 break;
3470 case 18: /* BASEPRI_MAX */
3471 val &= 0xff;
3472 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
3473 env->v7m.basepri = val;
3474 break;
3475 case 19: /* FAULTMASK */
3476 if (val & 1)
3477 env->uncached_cpsr |= CPSR_F;
3478 else
3479 env->uncached_cpsr &= ~CPSR_F;
3480 break;
3481 case 20: /* CONTROL */
3482 env->v7m.control = val & 3;
3483 switch_v7m_sp(env, (val & 2) != 0);
3484 break;
3485 default:
3486 /* ??? For debugging only. */
3487 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
3488 return;
3489 }
3490 }
3491
3492 #endif
3493
3494 /* Note that signed overflow is undefined in C. The following routines are
3495 careful to use unsigned types where modulo arithmetic is required.
3496 Failure to do so _will_ break on newer gcc. */
3497
3498 /* Signed saturating arithmetic. */
3499
3500 /* Perform 16-bit signed saturating addition. */
3501 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
3502 {
3503 uint16_t res;
3504
3505 res = a + b;
3506 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
3507 if (a & 0x8000)
3508 res = 0x8000;
3509 else
3510 res = 0x7fff;
3511 }
3512 return res;
3513 }
3514
3515 /* Perform 8-bit signed saturating addition. */
3516 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
3517 {
3518 uint8_t res;
3519
3520 res = a + b;
3521 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
3522 if (a & 0x80)
3523 res = 0x80;
3524 else
3525 res = 0x7f;
3526 }
3527 return res;
3528 }
3529
3530 /* Perform 16-bit signed saturating subtraction. */
3531 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
3532 {
3533 uint16_t res;
3534
3535 res = a - b;
3536 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
3537 if (a & 0x8000)
3538 res = 0x8000;
3539 else
3540 res = 0x7fff;
3541 }
3542 return res;
3543 }
3544
3545 /* Perform 8-bit signed saturating subtraction. */
3546 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
3547 {
3548 uint8_t res;
3549
3550 res = a - b;
3551 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
3552 if (a & 0x80)
3553 res = 0x80;
3554 else
3555 res = 0x7f;
3556 }
3557 return res;
3558 }
3559
3560 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
3561 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
3562 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
3563 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
3564 #define PFX q
3565
3566 #include "op_addsub.h"
3567
3568 /* Unsigned saturating arithmetic. */
3569 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
3570 {
3571 uint16_t res;
3572 res = a + b;
3573 if (res < a)
3574 res = 0xffff;
3575 return res;
3576 }
3577
3578 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
3579 {
3580 if (a > b)
3581 return a - b;
3582 else
3583 return 0;
3584 }
3585
3586 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
3587 {
3588 uint8_t res;
3589 res = a + b;
3590 if (res < a)
3591 res = 0xff;
3592 return res;
3593 }
3594
3595 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
3596 {
3597 if (a > b)
3598 return a - b;
3599 else
3600 return 0;
3601 }
3602
3603 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
3604 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
3605 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
3606 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
3607 #define PFX uq
3608
3609 #include "op_addsub.h"
3610
3611 /* Signed modulo arithmetic. */
3612 #define SARITH16(a, b, n, op) do { \
3613 int32_t sum; \
3614 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
3615 RESULT(sum, n, 16); \
3616 if (sum >= 0) \
3617 ge |= 3 << (n * 2); \
3618 } while(0)
3619
3620 #define SARITH8(a, b, n, op) do { \
3621 int32_t sum; \
3622 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
3623 RESULT(sum, n, 8); \
3624 if (sum >= 0) \
3625 ge |= 1 << n; \
3626 } while(0)
3627
3628
3629 #define ADD16(a, b, n) SARITH16(a, b, n, +)
3630 #define SUB16(a, b, n) SARITH16(a, b, n, -)
3631 #define ADD8(a, b, n) SARITH8(a, b, n, +)
3632 #define SUB8(a, b, n) SARITH8(a, b, n, -)
3633 #define PFX s
3634 #define ARITH_GE
3635
3636 #include "op_addsub.h"
3637
3638 /* Unsigned modulo arithmetic. */
3639 #define ADD16(a, b, n) do { \
3640 uint32_t sum; \
3641 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
3642 RESULT(sum, n, 16); \
3643 if ((sum >> 16) == 1) \
3644 ge |= 3 << (n * 2); \
3645 } while(0)
3646
3647 #define ADD8(a, b, n) do { \
3648 uint32_t sum; \
3649 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
3650 RESULT(sum, n, 8); \
3651 if ((sum >> 8) == 1) \
3652 ge |= 1 << n; \
3653 } while(0)
3654
3655 #define SUB16(a, b, n) do { \
3656 uint32_t sum; \
3657 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
3658 RESULT(sum, n, 16); \
3659 if ((sum >> 16) == 0) \
3660 ge |= 3 << (n * 2); \
3661 } while(0)
3662
3663 #define SUB8(a, b, n) do { \
3664 uint32_t sum; \
3665 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
3666 RESULT(sum, n, 8); \
3667 if ((sum >> 8) == 0) \
3668 ge |= 1 << n; \
3669 } while(0)
3670
3671 #define PFX u
3672 #define ARITH_GE
3673
3674 #include "op_addsub.h"
3675
3676 /* Halved signed arithmetic. */
3677 #define ADD16(a, b, n) \
3678 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
3679 #define SUB16(a, b, n) \
3680 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
3681 #define ADD8(a, b, n) \
3682 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
3683 #define SUB8(a, b, n) \
3684 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
3685 #define PFX sh
3686
3687 #include "op_addsub.h"
3688
3689 /* Halved unsigned arithmetic. */
3690 #define ADD16(a, b, n) \
3691 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3692 #define SUB16(a, b, n) \
3693 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
3694 #define ADD8(a, b, n) \
3695 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3696 #define SUB8(a, b, n) \
3697 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
3698 #define PFX uh
3699
3700 #include "op_addsub.h"
3701
3702 static inline uint8_t do_usad(uint8_t a, uint8_t b)
3703 {
3704 if (a > b)
3705 return a - b;
3706 else
3707 return b - a;
3708 }
3709
3710 /* Unsigned sum of absolute byte differences. */
3711 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
3712 {
3713 uint32_t sum;
3714 sum = do_usad(a, b);
3715 sum += do_usad(a >> 8, b >> 8);
3716 sum += do_usad(a >> 16, b >>16);
3717 sum += do_usad(a >> 24, b >> 24);
3718 return sum;
3719 }
3720
3721 /* For ARMv6 SEL instruction. */
3722 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
3723 {
3724 uint32_t mask;
3725
3726 mask = 0;
3727 if (flags & 1)
3728 mask |= 0xff;
3729 if (flags & 2)
3730 mask |= 0xff00;
3731 if (flags & 4)
3732 mask |= 0xff0000;
3733 if (flags & 8)
3734 mask |= 0xff000000;
3735 return (a & mask) | (b & ~mask);
3736 }
3737
3738 /* VFP support. We follow the convention used for VFP instructions:
3739 Single precision routines have a "s" suffix, double precision a
3740 "d" suffix. */
3741
3742 /* Convert host exception flags to vfp form. */
3743 static inline int vfp_exceptbits_from_host(int host_bits)
3744 {
3745 int target_bits = 0;
3746
3747 if (host_bits & float_flag_invalid)
3748 target_bits |= 1;
3749 if (host_bits & float_flag_divbyzero)
3750 target_bits |= 2;
3751 if (host_bits & float_flag_overflow)
3752 target_bits |= 4;
3753 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
3754 target_bits |= 8;
3755 if (host_bits & float_flag_inexact)
3756 target_bits |= 0x10;
3757 if (host_bits & float_flag_input_denormal)
3758 target_bits |= 0x80;
3759 return target_bits;
3760 }
3761
3762 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
3763 {
3764 int i;
3765 uint32_t fpscr;
3766
3767 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
3768 | (env->vfp.vec_len << 16)
3769 | (env->vfp.vec_stride << 20);
3770 i = get_float_exception_flags(&env->vfp.fp_status);
3771 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
3772 fpscr |= vfp_exceptbits_from_host(i);
3773 return fpscr;
3774 }
3775
3776 uint32_t vfp_get_fpscr(CPUARMState *env)
3777 {
3778 return HELPER(vfp_get_fpscr)(env);
3779 }
3780
3781 /* Convert vfp exception flags to target form. */
3782 static inline int vfp_exceptbits_to_host(int target_bits)
3783 {
3784 int host_bits = 0;
3785
3786 if (target_bits & 1)
3787 host_bits |= float_flag_invalid;
3788 if (target_bits & 2)
3789 host_bits |= float_flag_divbyzero;
3790 if (target_bits & 4)
3791 host_bits |= float_flag_overflow;
3792 if (target_bits & 8)
3793 host_bits |= float_flag_underflow;
3794 if (target_bits & 0x10)
3795 host_bits |= float_flag_inexact;
3796 if (target_bits & 0x80)
3797 host_bits |= float_flag_input_denormal;
3798 return host_bits;
3799 }
3800
3801 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
3802 {
3803 int i;
3804 uint32_t changed;
3805
3806 changed = env->vfp.xregs[ARM_VFP_FPSCR];
3807 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
3808 env->vfp.vec_len = (val >> 16) & 7;
3809 env->vfp.vec_stride = (val >> 20) & 3;
3810
3811 changed ^= val;
3812 if (changed & (3 << 22)) {
3813 i = (val >> 22) & 3;
3814 switch (i) {
3815 case FPROUNDING_TIEEVEN:
3816 i = float_round_nearest_even;
3817 break;
3818 case FPROUNDING_POSINF:
3819 i = float_round_up;
3820 break;
3821 case FPROUNDING_NEGINF:
3822 i = float_round_down;
3823 break;
3824 case FPROUNDING_ZERO:
3825 i = float_round_to_zero;
3826 break;
3827 }
3828 set_float_rounding_mode(i, &env->vfp.fp_status);
3829 }
3830 if (changed & (1 << 24)) {
3831 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3832 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
3833 }
3834 if (changed & (1 << 25))
3835 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
3836
3837 i = vfp_exceptbits_to_host(val);
3838 set_float_exception_flags(i, &env->vfp.fp_status);
3839 set_float_exception_flags(0, &env->vfp.standard_fp_status);
3840 }
3841
3842 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
3843 {
3844 HELPER(vfp_set_fpscr)(env, val);
3845 }
3846
3847 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3848
3849 #define VFP_BINOP(name) \
3850 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3851 { \
3852 float_status *fpst = fpstp; \
3853 return float32_ ## name(a, b, fpst); \
3854 } \
3855 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3856 { \
3857 float_status *fpst = fpstp; \
3858 return float64_ ## name(a, b, fpst); \
3859 }
3860 VFP_BINOP(add)
3861 VFP_BINOP(sub)
3862 VFP_BINOP(mul)
3863 VFP_BINOP(div)
3864 VFP_BINOP(min)
3865 VFP_BINOP(max)
3866 VFP_BINOP(minnum)
3867 VFP_BINOP(maxnum)
3868 #undef VFP_BINOP
3869
3870 float32 VFP_HELPER(neg, s)(float32 a)
3871 {
3872 return float32_chs(a);
3873 }
3874
3875 float64 VFP_HELPER(neg, d)(float64 a)
3876 {
3877 return float64_chs(a);
3878 }
3879
3880 float32 VFP_HELPER(abs, s)(float32 a)
3881 {
3882 return float32_abs(a);
3883 }
3884
3885 float64 VFP_HELPER(abs, d)(float64 a)
3886 {
3887 return float64_abs(a);
3888 }
3889
3890 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
3891 {
3892 return float32_sqrt(a, &env->vfp.fp_status);
3893 }
3894
3895 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
3896 {
3897 return float64_sqrt(a, &env->vfp.fp_status);
3898 }
3899
3900 /* XXX: check quiet/signaling case */
3901 #define DO_VFP_cmp(p, type) \
3902 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3903 { \
3904 uint32_t flags; \
3905 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3906 case 0: flags = 0x6; break; \
3907 case -1: flags = 0x8; break; \
3908 case 1: flags = 0x2; break; \
3909 default: case 2: flags = 0x3; break; \
3910 } \
3911 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3912 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3913 } \
3914 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3915 { \
3916 uint32_t flags; \
3917 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3918 case 0: flags = 0x6; break; \
3919 case -1: flags = 0x8; break; \
3920 case 1: flags = 0x2; break; \
3921 default: case 2: flags = 0x3; break; \
3922 } \
3923 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3924 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3925 }
3926 DO_VFP_cmp(s, float32)
3927 DO_VFP_cmp(d, float64)
3928 #undef DO_VFP_cmp
3929
3930 /* Integer to float and float to integer conversions */
3931
3932 #define CONV_ITOF(name, fsz, sign) \
3933 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3934 { \
3935 float_status *fpst = fpstp; \
3936 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3937 }
3938
3939 #define CONV_FTOI(name, fsz, sign, round) \
3940 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3941 { \
3942 float_status *fpst = fpstp; \
3943 if (float##fsz##_is_any_nan(x)) { \
3944 float_raise(float_flag_invalid, fpst); \
3945 return 0; \
3946 } \
3947 return float##fsz##_to_##sign##int32##round(x, fpst); \
3948 }
3949
3950 #define FLOAT_CONVS(name, p, fsz, sign) \
3951 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3952 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3953 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3954
3955 FLOAT_CONVS(si, s, 32, )
3956 FLOAT_CONVS(si, d, 64, )
3957 FLOAT_CONVS(ui, s, 32, u)
3958 FLOAT_CONVS(ui, d, 64, u)
3959
3960 #undef CONV_ITOF
3961 #undef CONV_FTOI
3962 #undef FLOAT_CONVS
3963
3964 /* floating point conversion */
3965 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
3966 {
3967 float64 r = float32_to_float64(x, &env->vfp.fp_status);
3968 /* ARM requires that S<->D conversion of any kind of NaN generates
3969 * a quiet NaN by forcing the most significant frac bit to 1.
3970 */
3971 return float64_maybe_silence_nan(r);
3972 }
3973
3974 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
3975 {
3976 float32 r = float64_to_float32(x, &env->vfp.fp_status);
3977 /* ARM requires that S<->D conversion of any kind of NaN generates
3978 * a quiet NaN by forcing the most significant frac bit to 1.
3979 */
3980 return float32_maybe_silence_nan(r);
3981 }
3982
3983 /* VFP3 fixed point conversion. */
3984 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
3985 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
3986 void *fpstp) \
3987 { \
3988 float_status *fpst = fpstp; \
3989 float##fsz tmp; \
3990 tmp = itype##_to_##float##fsz(x, fpst); \
3991 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3992 }
3993
3994 /* Notice that we want only input-denormal exception flags from the
3995 * scalbn operation: the other possible flags (overflow+inexact if
3996 * we overflow to infinity, output-denormal) aren't correct for the
3997 * complete scale-and-convert operation.
3998 */
3999 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4000 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4001 uint32_t shift, \
4002 void *fpstp) \
4003 { \
4004 float_status *fpst = fpstp; \
4005 int old_exc_flags = get_float_exception_flags(fpst); \
4006 float##fsz tmp; \
4007 if (float##fsz##_is_any_nan(x)) { \
4008 float_raise(float_flag_invalid, fpst); \
4009 return 0; \
4010 } \
4011 tmp = float##fsz##_scalbn(x, shift, fpst); \
4012 old_exc_flags |= get_float_exception_flags(fpst) \
4013 & float_flag_input_denormal; \
4014 set_float_exception_flags(old_exc_flags, fpst); \
4015 return float##fsz##_to_##itype##round(tmp, fpst); \
4016 }
4017
4018 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4019 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4020 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4021 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4022
4023 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4024 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4025 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4026
4027 VFP_CONV_FIX(sh, d, 64, 64, int16)
4028 VFP_CONV_FIX(sl, d, 64, 64, int32)
4029 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4030 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4031 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4032 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4033 VFP_CONV_FIX(sh, s, 32, 32, int16)
4034 VFP_CONV_FIX(sl, s, 32, 32, int32)
4035 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4036 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4037 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4038 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4039 #undef VFP_CONV_FIX
4040 #undef VFP_CONV_FIX_FLOAT
4041 #undef VFP_CONV_FLOAT_FIX_ROUND
4042
4043 /* Set the current fp rounding mode and return the old one.
4044 * The argument is a softfloat float_round_ value.
4045 */
4046 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4047 {
4048 float_status *fp_status = &env->vfp.fp_status;
4049
4050 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4051 set_float_rounding_mode(rmode, fp_status);
4052
4053 return prev_rmode;
4054 }
4055
4056 /* Set the current fp rounding mode in the standard fp status and return
4057 * the old one. This is for NEON instructions that need to change the
4058 * rounding mode but wish to use the standard FPSCR values for everything
4059 * else. Always set the rounding mode back to the correct value after
4060 * modifying it.
4061 * The argument is a softfloat float_round_ value.
4062 */
4063 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4064 {
4065 float_status *fp_status = &env->vfp.standard_fp_status;
4066
4067 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4068 set_float_rounding_mode(rmode, fp_status);
4069
4070 return prev_rmode;
4071 }
4072
4073 /* Half precision conversions. */
4074 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4075 {
4076 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4077 float32 r = float16_to_float32(make_float16(a), ieee, s);
4078 if (ieee) {
4079 return float32_maybe_silence_nan(r);
4080 }
4081 return r;
4082 }
4083
4084 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4085 {
4086 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4087 float16 r = float32_to_float16(a, ieee, s);
4088 if (ieee) {
4089 r = float16_maybe_silence_nan(r);
4090 }
4091 return float16_val(r);
4092 }
4093
4094 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4095 {
4096 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4097 }
4098
4099 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4100 {
4101 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4102 }
4103
4104 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4105 {
4106 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4107 }
4108
4109 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4110 {
4111 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4112 }
4113
4114 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4115 {
4116 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4117 float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4118 if (ieee) {
4119 return float64_maybe_silence_nan(r);
4120 }
4121 return r;
4122 }
4123
4124 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4125 {
4126 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4127 float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4128 if (ieee) {
4129 r = float16_maybe_silence_nan(r);
4130 }
4131 return float16_val(r);
4132 }
4133
4134 #define float32_two make_float32(0x40000000)
4135 #define float32_three make_float32(0x40400000)
4136 #define float32_one_point_five make_float32(0x3fc00000)
4137
4138 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4139 {
4140 float_status *s = &env->vfp.standard_fp_status;
4141 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4142 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4143 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4144 float_raise(float_flag_input_denormal, s);
4145 }
4146 return float32_two;
4147 }
4148 return float32_sub(float32_two, float32_mul(a, b, s), s);
4149 }
4150
4151 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4152 {
4153 float_status *s = &env->vfp.standard_fp_status;
4154 float32 product;
4155 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4156 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4157 if (!(float32_is_zero(a) || float32_is_zero(b))) {
4158 float_raise(float_flag_input_denormal, s);
4159 }
4160 return float32_one_point_five;
4161 }
4162 product = float32_mul(a, b, s);
4163 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4164 }
4165
4166 /* NEON helpers. */
4167
4168 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4169 * int->float conversions at run-time. */
4170 #define float64_256 make_float64(0x4070000000000000LL)
4171 #define float64_512 make_float64(0x4080000000000000LL)
4172
4173 /* The algorithm that must be used to calculate the estimate
4174 * is specified by the ARM ARM.
4175 */
4176 static float64 recip_estimate(float64 a, CPUARMState *env)
4177 {
4178 /* These calculations mustn't set any fp exception flags,
4179 * so we use a local copy of the fp_status.
4180 */
4181 float_status dummy_status = env->vfp.standard_fp_status;
4182 float_status *s = &dummy_status;
4183 /* q = (int)(a * 512.0) */
4184 float64 q = float64_mul(float64_512, a, s);
4185 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4186
4187 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4188 q = int64_to_float64(q_int, s);
4189 q = float64_add(q, float64_half, s);
4190 q = float64_div(q, float64_512, s);
4191 q = float64_div(float64_one, q, s);
4192
4193 /* s = (int)(256.0 * r + 0.5) */
4194 q = float64_mul(q, float64_256, s);
4195 q = float64_add(q, float64_half, s);
4196 q_int = float64_to_int64_round_to_zero(q, s);
4197
4198 /* return (double)s / 256.0 */
4199 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4200 }
4201
4202 float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4203 {
4204 float_status *s = &env->vfp.standard_fp_status;
4205 float64 f64;
4206 uint32_t val32 = float32_val(a);
4207
4208 int result_exp;
4209 int a_exp = (val32 & 0x7f800000) >> 23;
4210 int sign = val32 & 0x80000000;
4211
4212 if (float32_is_any_nan(a)) {
4213 if (float32_is_signaling_nan(a)) {
4214 float_raise(float_flag_invalid, s);
4215 }
4216 return float32_default_nan;
4217 } else if (float32_is_infinity(a)) {
4218 return float32_set_sign(float32_zero, float32_is_neg(a));
4219 } else if (float32_is_zero_or_denormal(a)) {
4220 if (!float32_is_zero(a)) {
4221 float_raise(float_flag_input_denormal, s);
4222 }
4223 float_raise(float_flag_divbyzero, s);
4224 return float32_set_sign(float32_infinity, float32_is_neg(a));
4225 } else if (a_exp >= 253) {
4226 float_raise(float_flag_underflow, s);
4227 return float32_set_sign(float32_zero, float32_is_neg(a));
4228 }
4229
4230 f64 = make_float64((0x3feULL << 52)
4231 | ((int64_t)(val32 & 0x7fffff) << 29));
4232
4233 result_exp = 253 - a_exp;
4234
4235 f64 = recip_estimate(f64, env);
4236
4237 val32 = sign
4238 | ((result_exp & 0xff) << 23)
4239 | ((float64_val(f64) >> 29) & 0x7fffff);
4240 return make_float32(val32);
4241 }
4242
4243 /* The algorithm that must be used to calculate the estimate
4244 * is specified by the ARM ARM.
4245 */
4246 static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
4247 {
4248 /* These calculations mustn't set any fp exception flags,
4249 * so we use a local copy of the fp_status.
4250 */
4251 float_status dummy_status = env->vfp.standard_fp_status;
4252 float_status *s = &dummy_status;
4253 float64 q;
4254 int64_t q_int;
4255
4256 if (float64_lt(a, float64_half, s)) {
4257 /* range 0.25 <= a < 0.5 */
4258
4259 /* a in units of 1/512 rounded down */
4260 /* q0 = (int)(a * 512.0); */
4261 q = float64_mul(float64_512, a, s);
4262 q_int = float64_to_int64_round_to_zero(q, s);
4263
4264 /* reciprocal root r */
4265 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
4266 q = int64_to_float64(q_int, s);
4267 q = float64_add(q, float64_half, s);
4268 q = float64_div(q, float64_512, s);
4269 q = float64_sqrt(q, s);
4270 q = float64_div(float64_one, q, s);
4271 } else {
4272 /* range 0.5 <= a < 1.0 */
4273
4274 /* a in units of 1/256 rounded down */
4275 /* q1 = (int)(a * 256.0); */
4276 q = float64_mul(float64_256, a, s);
4277 int64_t q_int = float64_to_int64_round_to_zero(q, s);
4278
4279 /* reciprocal root r */
4280 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
4281 q = int64_to_float64(q_int, s);
4282 q = float64_add(q, float64_half, s);
4283 q = float64_div(q, float64_256, s);
4284 q = float64_sqrt(q, s);
4285 q = float64_div(float64_one, q, s);
4286 }
4287 /* r in units of 1/256 rounded to nearest */
4288 /* s = (int)(256.0 * r + 0.5); */
4289
4290 q = float64_mul(q, float64_256,s );
4291 q = float64_add(q, float64_half, s);
4292 q_int = float64_to_int64_round_to_zero(q, s);
4293
4294 /* return (double)s / 256.0;*/
4295 return float64_div(int64_to_float64(q_int, s), float64_256, s);
4296 }
4297
4298 float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4299 {
4300 float_status *s = &env->vfp.standard_fp_status;
4301 int result_exp;
4302 float64 f64;
4303 uint32_t val;
4304 uint64_t val64;
4305
4306 val = float32_val(a);
4307
4308 if (float32_is_any_nan(a)) {
4309 if (float32_is_signaling_nan(a)) {
4310 float_raise(float_flag_invalid, s);
4311 }
4312 return float32_default_nan;
4313 } else if (float32_is_zero_or_denormal(a)) {
4314 if (!float32_is_zero(a)) {
4315 float_raise(float_flag_input_denormal, s);
4316 }
4317 float_raise(float_flag_divbyzero, s);
4318 return float32_set_sign(float32_infinity, float32_is_neg(a));
4319 } else if (float32_is_neg(a)) {
4320 float_raise(float_flag_invalid, s);
4321 return float32_default_nan;
4322 } else if (float32_is_infinity(a)) {
4323 return float32_zero;
4324 }
4325
4326 /* Normalize to a double-precision value between 0.25 and 1.0,
4327 * preserving the parity of the exponent. */
4328 if ((val & 0x800000) == 0) {
4329 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4330 | (0x3feULL << 52)
4331 | ((uint64_t)(val & 0x7fffff) << 29));
4332 } else {
4333 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
4334 | (0x3fdULL << 52)
4335 | ((uint64_t)(val & 0x7fffff) << 29));
4336 }
4337
4338 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
4339
4340 f64 = recip_sqrt_estimate(f64, env);
4341
4342 val64 = float64_val(f64);
4343
4344 val = ((result_exp & 0xff) << 23)
4345 | ((val64 >> 29) & 0x7fffff);
4346 return make_float32(val);
4347 }
4348
4349 uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4350 {
4351 float64 f64;
4352
4353 if ((a & 0x80000000) == 0) {
4354 return 0xffffffff;
4355 }
4356
4357 f64 = make_float64((0x3feULL << 52)
4358 | ((int64_t)(a & 0x7fffffff) << 21));
4359
4360 f64 = recip_estimate (f64, env);
4361
4362 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4363 }
4364
4365 uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4366 {
4367 float64 f64;
4368
4369 if ((a & 0xc0000000) == 0) {
4370 return 0xffffffff;
4371 }
4372
4373 if (a & 0x80000000) {
4374 f64 = make_float64((0x3feULL << 52)
4375 | ((uint64_t)(a & 0x7fffffff) << 21));
4376 } else { /* bits 31-30 == '01' */
4377 f64 = make_float64((0x3fdULL << 52)
4378 | ((uint64_t)(a & 0x3fffffff) << 22));
4379 }
4380
4381 f64 = recip_sqrt_estimate(f64, env);
4382
4383 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4384 }
4385
4386 /* VFPv4 fused multiply-accumulate */
4387 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
4388 {
4389 float_status *fpst = fpstp;
4390 return float32_muladd(a, b, c, 0, fpst);
4391 }
4392
4393 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
4394 {
4395 float_status *fpst = fpstp;
4396 return float64_muladd(a, b, c, 0, fpst);
4397 }
4398
4399 /* ARMv8 round to integral */
4400 float32 HELPER(rints_exact)(float32 x, void *fp_status)
4401 {
4402 return float32_round_to_int(x, fp_status);
4403 }
4404
4405 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
4406 {
4407 return float64_round_to_int(x, fp_status);
4408 }
4409
4410 float32 HELPER(rints)(float32 x, void *fp_status)
4411 {
4412 int old_flags = get_float_exception_flags(fp_status), new_flags;
4413 float32 ret;
4414
4415 ret = float32_round_to_int(x, fp_status);
4416
4417 /* Suppress any inexact exceptions the conversion produced */
4418 if (!(old_flags & float_flag_inexact)) {
4419 new_flags = get_float_exception_flags(fp_status);
4420 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4421 }
4422
4423 return ret;
4424 }
4425
4426 float64 HELPER(rintd)(float64 x, void *fp_status)
4427 {
4428 int old_flags = get_float_exception_flags(fp_status), new_flags;
4429 float64 ret;
4430
4431 ret = float64_round_to_int(x, fp_status);
4432
4433 new_flags = get_float_exception_flags(fp_status);
4434
4435 /* Suppress any inexact exceptions the conversion produced */
4436 if (!(old_flags & float_flag_inexact)) {
4437 new_flags = get_float_exception_flags(fp_status);
4438 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
4439 }
4440
4441 return ret;
4442 }
4443
4444 /* Convert ARM rounding mode to softfloat */
4445 int arm_rmode_to_sf(int rmode)
4446 {
4447 switch (rmode) {
4448 case FPROUNDING_TIEAWAY:
4449 rmode = float_round_ties_away;
4450 break;
4451 case FPROUNDING_ODD:
4452 /* FIXME: add support for TIEAWAY and ODD */
4453 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
4454 rmode);
4455 case FPROUNDING_TIEEVEN:
4456 default:
4457 rmode = float_round_nearest_even;
4458 break;
4459 case FPROUNDING_POSINF:
4460 rmode = float_round_up;
4461 break;
4462 case FPROUNDING_NEGINF:
4463 rmode = float_round_down;
4464 break;
4465 case FPROUNDING_ZERO:
4466 rmode = float_round_to_zero;
4467 break;
4468 }
4469 return rmode;
4470 }
AR7 emulation for QEMU