target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <assert.h>
  20 #include <stdlib.h>
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 #ifndef CONFIG_USER_ONLY
  25 #include "exec/softmmu_exec.h"
  26
  27 #define MMUSUFFIX _mmu
  28
  29 #define SHIFT 0
  30 #include "exec/softmmu_template.h"
  31
  32 #define SHIFT 1
  33 #include "exec/softmmu_template.h"
  34
  35 #define SHIFT 2
  36 #include "exec/softmmu_template.h"
  37
  38 #define SHIFT 3
  39 #include "exec/softmmu_template.h"
  40
  41 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  42               uintptr_t retaddr)
  43 {
  44     int ret;
  45
  46     ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  47     if (ret) {
  48         /* now we have a real cpu fault */
  49         if (retaddr) {
  50             cpu_restore_state(cs, retaddr);
  51         }
  52         cpu_loop_exit(cs);
  53     }
  54 }
  55
  56 #endif
  57
  58 void helper_ldtlb(CPUSH4State *env)
  59 {
  60 #ifdef CONFIG_USER_ONLY
  61     SuperHCPU *cpu = sh_env_get_cpu(env);
  62
  63     /* XXXXX */
  64     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  65 #else
  66     cpu_load_tlb(env);
  67 #endif
  68 }
  69
  70 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  71                                                  uintptr_t retaddr)
  72 {
  73     CPUState *cs = CPU(sh_env_get_cpu(env));
  74
  75     cs->exception_index = index;
  76     if (retaddr) {
  77         cpu_restore_state(cs, retaddr);
  78     }
  79     cpu_loop_exit(cs);
  80 }
  81
  82 void helper_raise_illegal_instruction(CPUSH4State *env)
  83 {
  84     raise_exception(env, 0x180, 0);
  85 }
  86
  87 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
  88 {
  89     raise_exception(env, 0x1a0, 0);
  90 }
  91
  92 void helper_raise_fpu_disable(CPUSH4State *env)
  93 {
  94     raise_exception(env, 0x800, 0);
  95 }
  96
  97 void helper_raise_slot_fpu_disable(CPUSH4State *env)
  98 {
  99     raise_exception(env, 0x820, 0);
 100 }
 101
 102 void helper_debug(CPUSH4State *env)
 103 {
 104     raise_exception(env, EXCP_DEBUG, 0);
 105 }
 106
 107 void helper_sleep(CPUSH4State *env)
 108 {
 109     CPUState *cs = CPU(sh_env_get_cpu(env));
 110
 111     cs->halted = 1;
 112     env->in_sleep = 1;
 113     raise_exception(env, EXCP_HLT, 0);
 114 }
 115
 116 void helper_trapa(CPUSH4State *env, uint32_t tra)
 117 {
 118     env->tra = tra << 2;
 119     raise_exception(env, 0x160, 0);
 120 }
 121
 122 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 123 {
 124     if (cpu_sh4_is_cached (env, address))
 125     {
 126         memory_content *r = malloc (sizeof(memory_content));
 127         r->address = address;
 128         r->value = value;
 129         r->next = NULL;
 130
 131         *(env->movcal_backup_tail) = r;
 132         env->movcal_backup_tail = &(r->next);
 133     }
 134 }
 135
 136 void helper_discard_movcal_backup(CPUSH4State *env)
 137 {
 138     memory_content *current = env->movcal_backup;
 139
 140     while(current)
 141     {
 142         memory_content *next = current->next;
 143         free (current);
 144         env->movcal_backup = current = next;
 145         if (current == NULL)
 146             env->movcal_backup_tail = &(env->movcal_backup);
 147     }
 148 }
 149
 150 void helper_ocbi(CPUSH4State *env, uint32_t address)
 151 {
 152     memory_content **current = &(env->movcal_backup);
 153     while (*current)
 154     {
 155         uint32_t a = (*current)->address;
 156         if ((a & ~0x1F) == (address & ~0x1F))
 157         {
 158             memory_content *next = (*current)->next;
 159             cpu_stl_data(env, a, (*current)->value);
 160
 161             if (next == NULL)
 162             {
 163                 env->movcal_backup_tail = current;
 164             }
 165
 166             free (*current);
 167             *current = next;
 168             break;
 169         }
 170     }
 171 }
 172
 173 #define T (env->sr & SR_T)
 174 #define Q (env->sr & SR_Q ? 1 : 0)
 175 #define M (env->sr & SR_M ? 1 : 0)
 176 #define SETT env->sr |= SR_T
 177 #define CLRT env->sr &= ~SR_T
 178 #define SETQ env->sr |= SR_Q
 179 #define CLRQ env->sr &= ~SR_Q
 180 #define SETM env->sr |= SR_M
 181 #define CLRM env->sr &= ~SR_M
 182
 183 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 184 {
 185     uint32_t tmp0, tmp2;
 186     uint8_t old_q, tmp1 = 0xff;
 187
 188     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 189     old_q = Q;
 190     if ((0x80000000 & arg1) != 0)
 191         SETQ;
 192     else
 193         CLRQ;
 194     tmp2 = arg0;
 195     arg1 <<= 1;
 196     arg1 |= T;
 197     switch (old_q) {
 198     case 0:
 199         switch (M) {
 200         case 0:
 201             tmp0 = arg1;
 202             arg1 -= tmp2;
 203             tmp1 = arg1 > tmp0;
 204             switch (Q) {
 205             case 0:
 206                 if (tmp1)
 207                     SETQ;
 208                 else
 209                     CLRQ;
 210                 break;
 211             case 1:
 212                 if (tmp1 == 0)
 213                     SETQ;
 214                 else
 215                     CLRQ;
 216                 break;
 217             }
 218             break;
 219         case 1:
 220             tmp0 = arg1;
 221             arg1 += tmp2;
 222             tmp1 = arg1 < tmp0;
 223             switch (Q) {
 224             case 0:
 225                 if (tmp1 == 0)
 226                     SETQ;
 227                 else
 228                     CLRQ;
 229                 break;
 230             case 1:
 231                 if (tmp1)
 232                     SETQ;
 233                 else
 234                     CLRQ;
 235                 break;
 236             }
 237             break;
 238         }
 239         break;
 240     case 1:
 241         switch (M) {
 242         case 0:
 243             tmp0 = arg1;
 244             arg1 += tmp2;
 245             tmp1 = arg1 < tmp0;
 246             switch (Q) {
 247             case 0:
 248                 if (tmp1)
 249                     SETQ;
 250                 else
 251                     CLRQ;
 252                 break;
 253             case 1:
 254                 if (tmp1 == 0)
 255                     SETQ;
 256                 else
 257                     CLRQ;
 258                 break;
 259             }
 260             break;
 261         case 1:
 262             tmp0 = arg1;
 263             arg1 -= tmp2;
 264             tmp1 = arg1 > tmp0;
 265             switch (Q) {
 266             case 0:
 267                 if (tmp1 == 0)
 268                     SETQ;
 269                 else
 270                     CLRQ;
 271                 break;
 272             case 1:
 273                 if (tmp1)
 274                     SETQ;
 275                 else
 276                     CLRQ;
 277                 break;
 278             }
 279             break;
 280         }
 281         break;
 282     }
 283     if (Q == M)
 284         SETT;
 285     else
 286         CLRT;
 287     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 288     return arg1;
 289 }
 290
 291 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 292 {
 293     int64_t res;
 294
 295     res = ((uint64_t) env->mach << 32) | env->macl;
 296     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 297     env->mach = (res >> 32) & 0xffffffff;
 298     env->macl = res & 0xffffffff;
 299     if (env->sr & SR_S) {
 300         if (res < 0)
 301             env->mach |= 0xffff0000;
 302         else
 303             env->mach &= 0x00007fff;
 304     }
 305 }
 306
 307 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 308 {
 309     int64_t res;
 310
 311     res = ((uint64_t) env->mach << 32) | env->macl;
 312     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 313     env->mach = (res >> 32) & 0xffffffff;
 314     env->macl = res & 0xffffffff;
 315     if (env->sr & SR_S) {
 316         if (res < -0x80000000) {
 317             env->mach = 1;
 318             env->macl = 0x80000000;
 319         } else if (res > 0x000000007fffffff) {
 320             env->mach = 1;
 321             env->macl = 0x7fffffff;
 322         }
 323     }
 324 }
 325
 326 static inline void set_t(CPUSH4State *env)
 327 {
 328     env->sr |= SR_T;
 329 }
 330
 331 static inline void clr_t(CPUSH4State *env)
 332 {
 333     env->sr &= ~SR_T;
 334 }
 335
 336 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 337 {
 338     env->fpscr = val & FPSCR_MASK;
 339     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 340         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 341     } else {
 342         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 343     }
 344     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 345 }
 346
 347 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 348 {
 349     int xcpt, cause, enable;
 350
 351     xcpt = get_float_exception_flags(&env->fp_status);
 352
 353     /* Clear the flag entries */
 354     env->fpscr &= ~FPSCR_FLAG_MASK;
 355
 356     if (unlikely(xcpt)) {
 357         if (xcpt & float_flag_invalid) {
 358             env->fpscr |= FPSCR_FLAG_V;
 359         }
 360         if (xcpt & float_flag_divbyzero) {
 361             env->fpscr |= FPSCR_FLAG_Z;
 362         }
 363         if (xcpt & float_flag_overflow) {
 364             env->fpscr |= FPSCR_FLAG_O;
 365         }
 366         if (xcpt & float_flag_underflow) {
 367             env->fpscr |= FPSCR_FLAG_U;
 368         }
 369         if (xcpt & float_flag_inexact) {
 370             env->fpscr |= FPSCR_FLAG_I;
 371         }
 372
 373         /* Accumulate in cause entries */
 374         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 375                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 376
 377         /* Generate an exception if enabled */
 378         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 379         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 380         if (cause & enable) {
 381             raise_exception(env, 0x120, retaddr);
 382         }
 383     }
 384 }
 385
 386 float32 helper_fabs_FT(float32 t0)
 387 {
 388     return float32_abs(t0);
 389 }
 390
 391 float64 helper_fabs_DT(float64 t0)
 392 {
 393     return float64_abs(t0);
 394 }
 395
 396 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 397 {
 398     set_float_exception_flags(0, &env->fp_status);
 399     t0 = float32_add(t0, t1, &env->fp_status);
 400     update_fpscr(env, GETPC());
 401     return t0;
 402 }
 403
 404 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 405 {
 406     set_float_exception_flags(0, &env->fp_status);
 407     t0 = float64_add(t0, t1, &env->fp_status);
 408     update_fpscr(env, GETPC());
 409     return t0;
 410 }
 411
 412 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 413 {
 414     int relation;
 415
 416     set_float_exception_flags(0, &env->fp_status);
 417     relation = float32_compare(t0, t1, &env->fp_status);
 418     if (unlikely(relation == float_relation_unordered)) {
 419         update_fpscr(env, GETPC());
 420     } else if (relation == float_relation_equal) {
 421         set_t(env);
 422     } else {
 423         clr_t(env);
 424     }
 425 }
 426
 427 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 428 {
 429     int relation;
 430
 431     set_float_exception_flags(0, &env->fp_status);
 432     relation = float64_compare(t0, t1, &env->fp_status);
 433     if (unlikely(relation == float_relation_unordered)) {
 434         update_fpscr(env, GETPC());
 435     } else if (relation == float_relation_equal) {
 436         set_t(env);
 437     } else {
 438         clr_t(env);
 439     }
 440 }
 441
 442 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 443 {
 444     int relation;
 445
 446     set_float_exception_flags(0, &env->fp_status);
 447     relation = float32_compare(t0, t1, &env->fp_status);
 448     if (unlikely(relation == float_relation_unordered)) {
 449         update_fpscr(env, GETPC());
 450     } else if (relation == float_relation_greater) {
 451         set_t(env);
 452     } else {
 453         clr_t(env);
 454     }
 455 }
 456
 457 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 458 {
 459     int relation;
 460
 461     set_float_exception_flags(0, &env->fp_status);
 462     relation = float64_compare(t0, t1, &env->fp_status);
 463     if (unlikely(relation == float_relation_unordered)) {
 464         update_fpscr(env, GETPC());
 465     } else if (relation == float_relation_greater) {
 466         set_t(env);
 467     } else {
 468         clr_t(env);
 469     }
 470 }
 471
 472 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 473 {
 474     float64 ret;
 475     set_float_exception_flags(0, &env->fp_status);
 476     ret = float32_to_float64(t0, &env->fp_status);
 477     update_fpscr(env, GETPC());
 478     return ret;
 479 }
 480
 481 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 482 {
 483     float32 ret;
 484     set_float_exception_flags(0, &env->fp_status);
 485     ret = float64_to_float32(t0, &env->fp_status);
 486     update_fpscr(env, GETPC());
 487     return ret;
 488 }
 489
 490 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 491 {
 492     set_float_exception_flags(0, &env->fp_status);
 493     t0 = float32_div(t0, t1, &env->fp_status);
 494     update_fpscr(env, GETPC());
 495     return t0;
 496 }
 497
 498 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 499 {
 500     set_float_exception_flags(0, &env->fp_status);
 501     t0 = float64_div(t0, t1, &env->fp_status);
 502     update_fpscr(env, GETPC());
 503     return t0;
 504 }
 505
 506 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 507 {
 508     float32 ret;
 509     set_float_exception_flags(0, &env->fp_status);
 510     ret = int32_to_float32(t0, &env->fp_status);
 511     update_fpscr(env, GETPC());
 512     return ret;
 513 }
 514
 515 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 516 {
 517     float64 ret;
 518     set_float_exception_flags(0, &env->fp_status);
 519     ret = int32_to_float64(t0, &env->fp_status);
 520     update_fpscr(env, GETPC());
 521     return ret;
 522 }
 523
 524 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 525 {
 526     set_float_exception_flags(0, &env->fp_status);
 527     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 528     update_fpscr(env, GETPC());
 529     return t0;
 530 }
 531
 532 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 533 {
 534     set_float_exception_flags(0, &env->fp_status);
 535     t0 = float32_mul(t0, t1, &env->fp_status);
 536     update_fpscr(env, GETPC());
 537     return t0;
 538 }
 539
 540 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 541 {
 542     set_float_exception_flags(0, &env->fp_status);
 543     t0 = float64_mul(t0, t1, &env->fp_status);
 544     update_fpscr(env, GETPC());
 545     return t0;
 546 }
 547
 548 float32 helper_fneg_T(float32 t0)
 549 {
 550     return float32_chs(t0);
 551 }
 552
 553 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 554 {
 555     set_float_exception_flags(0, &env->fp_status);
 556     t0 = float32_sqrt(t0, &env->fp_status);
 557     update_fpscr(env, GETPC());
 558     return t0;
 559 }
 560
 561 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 562 {
 563     set_float_exception_flags(0, &env->fp_status);
 564     t0 = float64_sqrt(t0, &env->fp_status);
 565     update_fpscr(env, GETPC());
 566     return t0;
 567 }
 568
 569 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 570 {
 571     set_float_exception_flags(0, &env->fp_status);
 572     t0 = float32_sub(t0, t1, &env->fp_status);
 573     update_fpscr(env, GETPC());
 574     return t0;
 575 }
 576
 577 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 578 {
 579     set_float_exception_flags(0, &env->fp_status);
 580     t0 = float64_sub(t0, t1, &env->fp_status);
 581     update_fpscr(env, GETPC());
 582     return t0;
 583 }
 584
 585 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 586 {
 587     uint32_t ret;
 588     set_float_exception_flags(0, &env->fp_status);
 589     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 590     update_fpscr(env, GETPC());
 591     return ret;
 592 }
 593
 594 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 595 {
 596     uint32_t ret;
 597     set_float_exception_flags(0, &env->fp_status);
 598     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 599     update_fpscr(env, GETPC());
 600     return ret;
 601 }
 602
 603 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 604 {
 605     int bank, i;
 606     float32 r, p;
 607
 608     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 609     r = float32_zero;
 610     set_float_exception_flags(0, &env->fp_status);
 611
 612     for (i = 0 ; i < 4 ; i++) {
 613         p = float32_mul(env->fregs[bank + m + i],
 614                         env->fregs[bank + n + i],
 615                         &env->fp_status);
 616         r = float32_add(r, p, &env->fp_status);
 617     }
 618     update_fpscr(env, GETPC());
 619
 620     env->fregs[bank + n + 3] = r;
 621 }
 622
 623 void helper_ftrv(CPUSH4State *env, uint32_t n)
 624 {
 625     int bank_matrix, bank_vector;
 626     int i, j;
 627     float32 r[4];
 628     float32 p;
 629
 630     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 631     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 632     set_float_exception_flags(0, &env->fp_status);
 633     for (i = 0 ; i < 4 ; i++) {
 634         r[i] = float32_zero;
 635         for (j = 0 ; j < 4 ; j++) {
 636             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 637                             env->fregs[bank_vector + j],
 638                             &env->fp_status);
 639             r[i] = float32_add(r[i], p, &env->fp_status);
 640         }
 641     }
 642     update_fpscr(env, GETPC());
 643
 644     for (i = 0 ; i < 4 ; i++) {
 645         env->fregs[bank_vector + i] = r[i];
 646     }
 647 }