4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "qemu/osdep.h"
26 #include "qapi/error.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "exec/gdbstub.h"
33 #include "fpu/softfloat-helpers.h"
40 /* These key value are as per MBV field in PVR0 */
78 /* If no specific version gets selected, default to the following. */
79 #define DEFAULT_CPU_VERSION "10.0"
81 static void mb_cpu_set_pc(CPUState
*cs
, vaddr value
)
83 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
86 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
90 static vaddr
mb_cpu_get_pc(CPUState
*cs
)
92 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
97 static void mb_cpu_synchronize_from_tb(CPUState
*cs
,
98 const TranslationBlock
*tb
)
100 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
102 tcg_debug_assert(!tcg_cflags_has(cs
, CF_PCREL
));
103 cpu
->env
.pc
= tb
->pc
;
104 cpu
->env
.iflags
= tb
->flags
& IFLAGS_TB_MASK
;
107 static void mb_restore_state_to_opc(CPUState
*cs
,
108 const TranslationBlock
*tb
,
109 const uint64_t *data
)
111 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
113 cpu
->env
.pc
= data
[0];
114 cpu
->env
.iflags
= data
[1];
117 static bool mb_cpu_has_work(CPUState
*cs
)
119 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
122 static int mb_cpu_mmu_index(CPUState
*cs
, bool ifetch
)
124 CPUMBState
*env
= cpu_env(cs
);
125 MicroBlazeCPU
*cpu
= env_archcpu(env
);
127 /* Are we in nommu mode?. */
128 if (!(env
->msr
& MSR_VM
) || !cpu
->cfg
.use_mmu
) {
129 return MMU_NOMMU_IDX
;
132 if (env
->msr
& MSR_UM
) {
135 return MMU_KERNEL_IDX
;
138 #ifndef CONFIG_USER_ONLY
139 static void mb_cpu_ns_axi_dp(void *opaque
, int irq
, int level
)
141 MicroBlazeCPU
*cpu
= opaque
;
142 bool en
= cpu
->cfg
.use_non_secure
& USE_NON_SECURE_M_AXI_DP_MASK
;
144 cpu
->ns_axi_dp
= level
& en
;
147 static void mb_cpu_ns_axi_ip(void *opaque
, int irq
, int level
)
149 MicroBlazeCPU
*cpu
= opaque
;
150 bool en
= cpu
->cfg
.use_non_secure
& USE_NON_SECURE_M_AXI_IP_MASK
;
152 cpu
->ns_axi_ip
= level
& en
;
155 static void mb_cpu_ns_axi_dc(void *opaque
, int irq
, int level
)
157 MicroBlazeCPU
*cpu
= opaque
;
158 bool en
= cpu
->cfg
.use_non_secure
& USE_NON_SECURE_M_AXI_DC_MASK
;
160 cpu
->ns_axi_dc
= level
& en
;
163 static void mb_cpu_ns_axi_ic(void *opaque
, int irq
, int level
)
165 MicroBlazeCPU
*cpu
= opaque
;
166 bool en
= cpu
->cfg
.use_non_secure
& USE_NON_SECURE_M_AXI_IC_MASK
;
168 cpu
->ns_axi_ic
= level
& en
;
171 static void microblaze_cpu_set_irq(void *opaque
, int irq
, int level
)
173 MicroBlazeCPU
*cpu
= opaque
;
174 CPUState
*cs
= CPU(cpu
);
175 int type
= irq
? CPU_INTERRUPT_NMI
: CPU_INTERRUPT_HARD
;
178 cpu_interrupt(cs
, type
);
180 cpu_reset_interrupt(cs
, type
);
185 static void mb_cpu_reset_hold(Object
*obj
, ResetType type
)
187 CPUState
*cs
= CPU(obj
);
188 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
189 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(obj
);
190 CPUMBState
*env
= &cpu
->env
;
192 if (mcc
->parent_phases
.hold
) {
193 mcc
->parent_phases
.hold(obj
, type
);
196 memset(env
, 0, offsetof(CPUMBState
, end_reset_fields
));
197 env
->res_addr
= RES_ADDR_NONE
;
199 /* Disable stack protector. */
202 env
->pc
= cpu
->cfg
.base_vectors
;
204 #if defined(CONFIG_USER_ONLY)
205 /* start in user mode with interrupts enabled. */
206 mb_cpu_write_msr(env
, MSR_EE
| MSR_IE
| MSR_VM
| MSR_UM
);
208 mb_cpu_write_msr(env
, 0);
213 static void mb_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
215 info
->mach
= bfd_arch_microblaze
;
216 info
->print_insn
= print_insn_microblaze
;
219 static void mb_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
221 CPUState
*cs
= CPU(dev
);
222 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(dev
);
223 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
224 uint8_t version_code
= 0;
227 Error
*local_err
= NULL
;
229 cpu_exec_realizefn(cs
, &local_err
);
230 if (local_err
!= NULL
) {
231 error_propagate(errp
, local_err
);
235 if (cpu
->cfg
.addr_size
< 32 || cpu
->cfg
.addr_size
> 64) {
236 error_setg(errp
, "addr-size %d is out of range (32 - 64)",
243 version
= cpu
->cfg
.version
? cpu
->cfg
.version
: DEFAULT_CPU_VERSION
;
244 for (i
= 0; mb_cpu_lookup
[i
].name
&& version
; i
++) {
245 if (strcmp(mb_cpu_lookup
[i
].name
, version
) == 0) {
246 version_code
= mb_cpu_lookup
[i
].version_id
;
252 qemu_log("Invalid MicroBlaze version number: %s\n", cpu
->cfg
.version
);
255 cpu
->cfg
.pvr_regs
[0] =
257 PVR0_USE_ICACHE_MASK
|
258 PVR0_USE_DCACHE_MASK
|
259 (cpu
->cfg
.stackprot
? PVR0_SPROT_MASK
: 0) |
260 (cpu
->cfg
.use_fpu
? PVR0_USE_FPU_MASK
: 0) |
261 (cpu
->cfg
.use_hw_mul
? PVR0_USE_HW_MUL_MASK
: 0) |
262 (cpu
->cfg
.use_barrel
? PVR0_USE_BARREL_MASK
: 0) |
263 (cpu
->cfg
.use_div
? PVR0_USE_DIV_MASK
: 0) |
264 (cpu
->cfg
.use_mmu
? PVR0_USE_MMU_MASK
: 0) |
265 (cpu
->cfg
.endi
? PVR0_ENDI_MASK
: 0) |
266 (version_code
<< PVR0_VERSION_SHIFT
) |
267 (cpu
->cfg
.pvr
== C_PVR_FULL
? PVR0_PVR_FULL_MASK
: 0) |
270 cpu
->cfg
.pvr_regs
[1] = cpu
->cfg
.pvr_user2
;
272 cpu
->cfg
.pvr_regs
[2] =
278 (cpu
->cfg
.use_fpu
? PVR2_USE_FPU_MASK
: 0) |
279 (cpu
->cfg
.use_fpu
> 1 ? PVR2_USE_FPU2_MASK
: 0) |
280 (cpu
->cfg
.use_hw_mul
? PVR2_USE_HW_MUL_MASK
: 0) |
281 (cpu
->cfg
.use_hw_mul
> 1 ? PVR2_USE_MUL64_MASK
: 0) |
282 (cpu
->cfg
.use_barrel
? PVR2_USE_BARREL_MASK
: 0) |
283 (cpu
->cfg
.use_div
? PVR2_USE_DIV_MASK
: 0) |
284 (cpu
->cfg
.use_msr_instr
? PVR2_USE_MSR_INSTR
: 0) |
285 (cpu
->cfg
.use_pcmp_instr
? PVR2_USE_PCMP_INSTR
: 0) |
286 (cpu
->cfg
.dopb_bus_exception
? PVR2_DOPB_BUS_EXC_MASK
: 0) |
287 (cpu
->cfg
.iopb_bus_exception
? PVR2_IOPB_BUS_EXC_MASK
: 0) |
288 (cpu
->cfg
.div_zero_exception
? PVR2_DIV_ZERO_EXC_MASK
: 0) |
289 (cpu
->cfg
.illegal_opcode_exception
? PVR2_ILL_OPCODE_EXC_MASK
: 0) |
290 (cpu
->cfg
.unaligned_exceptions
? PVR2_UNALIGNED_EXC_MASK
: 0) |
291 (cpu
->cfg
.opcode_0_illegal
? PVR2_OPCODE_0x0_ILL_MASK
: 0));
293 cpu
->cfg
.pvr_regs
[5] |=
294 cpu
->cfg
.dcache_writeback
? PVR5_DCACHE_WRITEBACK_MASK
: 0;
296 cpu
->cfg
.pvr_regs
[10] =
297 (0x0c000000 | /* Default to spartan 3a dsp family. */
298 (cpu
->cfg
.addr_size
- 32) << PVR10_ASIZE_SHIFT
);
300 cpu
->cfg
.pvr_regs
[11] = ((cpu
->cfg
.use_mmu
? PVR11_USE_MMU
: 0) |
304 cpu
->cfg
.mmu_tlb_access
= 3;
305 cpu
->cfg
.mmu_zones
= 16;
306 cpu
->cfg
.addr_mask
= MAKE_64BIT_MASK(0, cpu
->cfg
.addr_size
);
308 mcc
->parent_realize(dev
, errp
);
311 static void mb_cpu_initfn(Object
*obj
)
313 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(obj
);
314 CPUMBState
*env
= &cpu
->env
;
316 gdb_register_coprocessor(CPU(cpu
), mb_cpu_gdb_read_stack_protect
,
317 mb_cpu_gdb_write_stack_protect
,
318 gdb_find_static_feature("microblaze-stack-protect.xml"),
321 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
323 #ifndef CONFIG_USER_ONLY
324 /* Inbound IRQ and FIR lines */
325 qdev_init_gpio_in(DEVICE(cpu
), microblaze_cpu_set_irq
, 2);
326 qdev_init_gpio_in_named(DEVICE(cpu
), mb_cpu_ns_axi_dp
, "ns_axi_dp", 1);
327 qdev_init_gpio_in_named(DEVICE(cpu
), mb_cpu_ns_axi_ip
, "ns_axi_ip", 1);
328 qdev_init_gpio_in_named(DEVICE(cpu
), mb_cpu_ns_axi_dc
, "ns_axi_dc", 1);
329 qdev_init_gpio_in_named(DEVICE(cpu
), mb_cpu_ns_axi_ic
, "ns_axi_ic", 1);
333 static Property mb_properties
[] = {
334 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU
, cfg
.base_vectors
, 0),
335 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU
, cfg
.stackprot
,
338 * This is the C_ADDR_SIZE synth-time configuration option of the
339 * MicroBlaze cores. Supported values range between 32 and 64.
341 * When set to > 32, 32bit MicroBlaze can emit load/stores
342 * with extended addressing.
344 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU
, cfg
.addr_size
, 32),
345 /* If use-fpu > 0 - FPU is enabled
346 * If use-fpu = 2 - Floating point conversion and square root instructions
349 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU
, cfg
.use_fpu
, 2),
350 /* If use-hw-mul > 0 - Multiplier is enabled
351 * If use-hw-mul = 2 - 64-bit multiplier is enabled
353 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU
, cfg
.use_hw_mul
, 2),
354 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU
, cfg
.use_barrel
, true),
355 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU
, cfg
.use_div
, true),
356 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU
, cfg
.use_msr_instr
, true),
357 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU
, cfg
.use_pcmp_instr
, true),
358 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU
, cfg
.use_mmu
, true),
360 * use-non-secure enables/disables the use of the non_secure[3:0] signals.
361 * It is a bitfield where 1 = non-secure for the following bits and their
362 * corresponding interfaces:
368 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU
, cfg
.use_non_secure
, 0),
369 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU
, cfg
.dcache_writeback
,
371 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU
, cfg
.endi
, false),
372 /* Enables bus exceptions on failed data accesses (load/stores). */
373 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU
,
374 cfg
.dopb_bus_exception
, false),
375 /* Enables bus exceptions on failed instruction fetches. */
376 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU
,
377 cfg
.iopb_bus_exception
, false),
378 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU
,
379 cfg
.illegal_opcode_exception
, false),
380 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU
,
381 cfg
.div_zero_exception
, false),
382 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU
,
383 cfg
.unaligned_exceptions
, false),
384 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU
,
385 cfg
.opcode_0_illegal
, false),
386 DEFINE_PROP_STRING("version", MicroBlazeCPU
, cfg
.version
),
387 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU
, cfg
.pvr
, C_PVR_FULL
),
388 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU
, cfg
.pvr_user1
, 0),
389 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU
, cfg
.pvr_user2
, 0),
390 DEFINE_PROP_END_OF_LIST(),
393 static ObjectClass
*mb_cpu_class_by_name(const char *cpu_model
)
395 return object_class_by_name(TYPE_MICROBLAZE_CPU
);
398 #ifndef CONFIG_USER_ONLY
399 #include "hw/core/sysemu-cpu-ops.h"
401 static const struct SysemuCPUOps mb_sysemu_ops
= {
402 .get_phys_page_attrs_debug
= mb_cpu_get_phys_page_attrs_debug
,
406 #include "hw/core/tcg-cpu-ops.h"
408 static const TCGCPUOps mb_tcg_ops
= {
409 .initialize
= mb_tcg_init
,
410 .synchronize_from_tb
= mb_cpu_synchronize_from_tb
,
411 .restore_state_to_opc
= mb_restore_state_to_opc
,
413 #ifndef CONFIG_USER_ONLY
414 .tlb_fill
= mb_cpu_tlb_fill
,
415 .cpu_exec_interrupt
= mb_cpu_exec_interrupt
,
416 .cpu_exec_halt
= mb_cpu_has_work
,
417 .do_interrupt
= mb_cpu_do_interrupt
,
418 .do_transaction_failed
= mb_cpu_transaction_failed
,
419 .do_unaligned_access
= mb_cpu_do_unaligned_access
,
420 #endif /* !CONFIG_USER_ONLY */
423 static void mb_cpu_class_init(ObjectClass
*oc
, void *data
)
425 DeviceClass
*dc
= DEVICE_CLASS(oc
);
426 CPUClass
*cc
= CPU_CLASS(oc
);
427 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_CLASS(oc
);
428 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
430 device_class_set_parent_realize(dc
, mb_cpu_realizefn
,
431 &mcc
->parent_realize
);
432 resettable_class_set_parent_phases(rc
, NULL
, mb_cpu_reset_hold
, NULL
,
433 &mcc
->parent_phases
);
435 cc
->class_by_name
= mb_cpu_class_by_name
;
436 cc
->has_work
= mb_cpu_has_work
;
437 cc
->mmu_index
= mb_cpu_mmu_index
;
438 cc
->dump_state
= mb_cpu_dump_state
;
439 cc
->set_pc
= mb_cpu_set_pc
;
440 cc
->get_pc
= mb_cpu_get_pc
;
441 cc
->gdb_read_register
= mb_cpu_gdb_read_register
;
442 cc
->gdb_write_register
= mb_cpu_gdb_write_register
;
444 #ifndef CONFIG_USER_ONLY
445 dc
->vmsd
= &vmstate_mb_cpu
;
446 cc
->sysemu_ops
= &mb_sysemu_ops
;
448 device_class_set_props(dc
, mb_properties
);
449 cc
->gdb_core_xml_file
= "microblaze-core.xml";
451 cc
->disas_set_info
= mb_disas_set_info
;
452 cc
->tcg_ops
= &mb_tcg_ops
;
455 static const TypeInfo mb_cpu_type_info
= {
456 .name
= TYPE_MICROBLAZE_CPU
,
458 .instance_size
= sizeof(MicroBlazeCPU
),
459 .instance_align
= __alignof(MicroBlazeCPU
),
460 .instance_init
= mb_cpu_initfn
,
461 .class_size
= sizeof(MicroBlazeCPUClass
),
462 .class_init
= mb_cpu_class_init
,
465 static void mb_cpu_register_types(void)
467 type_register_static(&mb_cpu_type_info
);
470 type_init(mb_cpu_register_types
)