4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "target/arm/idau.h"
14 #include "internals.h"
15 #include "exec/gdbstub.h"
16 #include "exec/helper-proto.h"
17 #include "qemu/host-utils.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/bitops.h"
20 #include "qemu/crc32c.h"
21 #include "qemu/qemu-print.h"
22 #include "exec/exec-all.h"
23 #include <zlib.h> /* For crc32 */
24 #include "hw/semihosting/semihost.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/kvm.h"
27 #include "qemu/range.h"
28 #include "qapi/qapi-commands-machine-target.h"
29 #include "qapi/error.h"
30 #include "qemu/guest-random.h"
33 #include "exec/cpu_ldst.h"
34 #include "hw/semihosting/common-semi.h"
37 static void v7m_msr_xpsr(CPUARMState
*env
, uint32_t mask
,
38 uint32_t reg
, uint32_t val
)
40 /* Only APSR is actually writable */
42 uint32_t apsrmask
= 0;
45 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
47 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
50 xpsr_write(env
, val
, apsrmask
);
54 static uint32_t v7m_mrs_xpsr(CPUARMState
*env
, uint32_t reg
, unsigned el
)
58 if ((reg
& 1) && el
) {
59 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
62 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
63 if (arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
67 /* EPSR reads as zero */
68 return xpsr_read(env
) & mask
;
71 static uint32_t v7m_mrs_control(CPUARMState
*env
, uint32_t secure
)
73 uint32_t value
= env
->v7m
.control
[secure
];
76 /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
77 value
|= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
;
82 #ifdef CONFIG_USER_ONLY
84 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
86 uint32_t mask
= extract32(maskreg
, 8, 4);
87 uint32_t reg
= extract32(maskreg
, 0, 8);
90 case 0 ... 7: /* xPSR sub-fields */
91 v7m_msr_xpsr(env
, mask
, reg
, val
);
93 case 20: /* CONTROL */
94 /* There are no sub-fields that are actually writable from EL0. */
97 /* Unprivileged writes to other registers are ignored */
102 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
105 case 0 ... 7: /* xPSR sub-fields */
106 return v7m_mrs_xpsr(env
, reg
, 0);
107 case 20: /* CONTROL */
108 return v7m_mrs_control(env
, 0);
110 /* Unprivileged reads others as zero. */
115 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
117 /* translate.c should never generate calls here in user-only mode */
118 g_assert_not_reached();
121 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
123 /* translate.c should never generate calls here in user-only mode */
124 g_assert_not_reached();
127 void HELPER(v7m_preserve_fp_state
)(CPUARMState
*env
)
129 /* translate.c should never generate calls here in user-only mode */
130 g_assert_not_reached();
133 void HELPER(v7m_vlstm
)(CPUARMState
*env
, uint32_t fptr
)
135 /* translate.c should never generate calls here in user-only mode */
136 g_assert_not_reached();
139 void HELPER(v7m_vlldm
)(CPUARMState
*env
, uint32_t fptr
)
141 /* translate.c should never generate calls here in user-only mode */
142 g_assert_not_reached();
145 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
148 * The TT instructions can be used by unprivileged code, but in
149 * user-only emulation we don't have the MPU.
150 * Luckily since we know we are NonSecure unprivileged (and that in
151 * turn means that the A flag wasn't specified), all the bits in the
152 * register must be zero:
153 * IREGION: 0 because IRVALID is 0
154 * IRVALID: 0 because NS
158 * RW: 0 because unpriv and A flag not set
159 * R: 0 because unpriv and A flag not set
160 * SRVALID: 0 because NS
161 * MRVALID: 0 because unpriv and A flag not set
162 * SREGION: 0 becaus SRVALID is 0
163 * MREGION: 0 because MRVALID is 0
171 * What kind of stack write are we doing? This affects how exceptions
172 * generated during the stacking are treated.
174 typedef enum StackingMode
{
180 static bool v7m_stack_write(ARMCPU
*cpu
, uint32_t addr
, uint32_t value
,
181 ARMMMUIdx mmu_idx
, StackingMode mode
)
183 CPUState
*cs
= CPU(cpu
);
184 CPUARMState
*env
= &cpu
->env
;
185 MemTxAttrs attrs
= {};
187 target_ulong page_size
;
190 ARMMMUFaultInfo fi
= {};
191 ARMCacheAttrs cacheattrs
= {};
192 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
196 if (get_phys_addr(env
, addr
, MMU_DATA_STORE
, mmu_idx
, &physaddr
,
197 &attrs
, &prot
, &page_size
, &fi
, &cacheattrs
)) {
198 /* MPU/SAU lookup failed */
199 if (fi
.type
== ARMFault_QEMU_SFault
) {
200 if (mode
== STACK_LAZYFP
) {
201 qemu_log_mask(CPU_LOG_INT
,
202 "...SecureFault with SFSR.LSPERR "
203 "during lazy stacking\n");
204 env
->v7m
.sfsr
|= R_V7M_SFSR_LSPERR_MASK
;
206 qemu_log_mask(CPU_LOG_INT
,
207 "...SecureFault with SFSR.AUVIOL "
208 "during stacking\n");
209 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
211 env
->v7m
.sfsr
|= R_V7M_SFSR_SFARVALID_MASK
;
212 env
->v7m
.sfar
= addr
;
213 exc
= ARMV7M_EXCP_SECURE
;
216 if (mode
== STACK_LAZYFP
) {
217 qemu_log_mask(CPU_LOG_INT
,
218 "...MemManageFault with CFSR.MLSPERR\n");
219 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MLSPERR_MASK
;
221 qemu_log_mask(CPU_LOG_INT
,
222 "...MemManageFault with CFSR.MSTKERR\n");
223 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MSTKERR_MASK
;
225 exc
= ARMV7M_EXCP_MEM
;
230 address_space_stl_le(arm_addressspace(cs
, attrs
), physaddr
, value
,
232 if (txres
!= MEMTX_OK
) {
233 /* BusFault trying to write the data */
234 if (mode
== STACK_LAZYFP
) {
235 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.LSPERR\n");
236 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_LSPERR_MASK
;
238 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.STKERR\n");
239 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_STKERR_MASK
;
241 exc
= ARMV7M_EXCP_BUS
;
249 * By pending the exception at this point we are making
250 * the IMPDEF choice "overridden exceptions pended" (see the
251 * MergeExcInfo() pseudocode). The other choice would be to not
252 * pend them now and then make a choice about which to throw away
253 * later if we have two derived exceptions.
254 * The only case when we must not pend the exception but instead
255 * throw it away is if we are doing the push of the callee registers
256 * and we've already generated a derived exception (this is indicated
257 * by the caller passing STACK_IGNFAULTS). Even in this case we will
258 * still update the fault status registers.
262 armv7m_nvic_set_pending_derived(env
->nvic
, exc
, exc_secure
);
265 armv7m_nvic_set_pending_lazyfp(env
->nvic
, exc
, exc_secure
);
267 case STACK_IGNFAULTS
:
273 static bool v7m_stack_read(ARMCPU
*cpu
, uint32_t *dest
, uint32_t addr
,
276 CPUState
*cs
= CPU(cpu
);
277 CPUARMState
*env
= &cpu
->env
;
278 MemTxAttrs attrs
= {};
280 target_ulong page_size
;
283 ARMMMUFaultInfo fi
= {};
284 ARMCacheAttrs cacheattrs
= {};
285 bool secure
= mmu_idx
& ARM_MMU_IDX_M_S
;
290 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
291 &attrs
, &prot
, &page_size
, &fi
, &cacheattrs
)) {
292 /* MPU/SAU lookup failed */
293 if (fi
.type
== ARMFault_QEMU_SFault
) {
294 qemu_log_mask(CPU_LOG_INT
,
295 "...SecureFault with SFSR.AUVIOL during unstack\n");
296 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
297 env
->v7m
.sfar
= addr
;
298 exc
= ARMV7M_EXCP_SECURE
;
301 qemu_log_mask(CPU_LOG_INT
,
302 "...MemManageFault with CFSR.MUNSTKERR\n");
303 env
->v7m
.cfsr
[secure
] |= R_V7M_CFSR_MUNSTKERR_MASK
;
304 exc
= ARMV7M_EXCP_MEM
;
310 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
312 if (txres
!= MEMTX_OK
) {
313 /* BusFault trying to read the data */
314 qemu_log_mask(CPU_LOG_INT
, "...BusFault with BFSR.UNSTKERR\n");
315 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_UNSTKERR_MASK
;
316 exc
= ARMV7M_EXCP_BUS
;
326 * By pending the exception at this point we are making
327 * the IMPDEF choice "overridden exceptions pended" (see the
328 * MergeExcInfo() pseudocode). The other choice would be to not
329 * pend them now and then make a choice about which to throw away
330 * later if we have two derived exceptions.
332 armv7m_nvic_set_pending(env
->nvic
, exc
, exc_secure
);
336 void HELPER(v7m_preserve_fp_state
)(CPUARMState
*env
)
339 * Preserve FP state (because LSPACT was set and we are about
340 * to execute an FP instruction). This corresponds to the
341 * PreserveFPState() pseudocode.
342 * We may throw an exception if the stacking fails.
344 ARMCPU
*cpu
= env_archcpu(env
);
345 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
346 bool negpri
= !(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_HFRDY_MASK
);
347 bool is_priv
= !(env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_USER_MASK
);
348 bool splimviol
= env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_SPLIMVIOL_MASK
;
349 uint32_t fpcar
= env
->v7m
.fpcar
[is_secure
];
350 bool stacked_ok
= true;
351 bool ts
= is_secure
&& (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
);
354 /* Take the iothread lock as we are going to touch the NVIC */
355 qemu_mutex_lock_iothread();
357 /* Check the background context had access to the FPU */
358 if (!v7m_cpacr_pass(env
, is_secure
, is_priv
)) {
359 armv7m_nvic_set_pending_lazyfp(env
->nvic
, ARMV7M_EXCP_USAGE
, is_secure
);
360 env
->v7m
.cfsr
[is_secure
] |= R_V7M_CFSR_NOCP_MASK
;
362 } else if (!is_secure
&& !extract32(env
->v7m
.nsacr
, 10, 1)) {
363 armv7m_nvic_set_pending_lazyfp(env
->nvic
, ARMV7M_EXCP_USAGE
, M_REG_S
);
364 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_NOCP_MASK
;
368 if (!splimviol
&& stacked_ok
) {
369 /* We only stack if the stack limit wasn't violated */
373 mmu_idx
= arm_v7m_mmu_idx_all(env
, is_secure
, is_priv
, negpri
);
374 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
375 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
376 uint32_t faddr
= fpcar
+ 4 * i
;
377 uint32_t slo
= extract64(dn
, 0, 32);
378 uint32_t shi
= extract64(dn
, 32, 32);
381 faddr
+= 8; /* skip the slot for the FPSCR */
383 stacked_ok
= stacked_ok
&&
384 v7m_stack_write(cpu
, faddr
, slo
, mmu_idx
, STACK_LAZYFP
) &&
385 v7m_stack_write(cpu
, faddr
+ 4, shi
, mmu_idx
, STACK_LAZYFP
);
388 stacked_ok
= stacked_ok
&&
389 v7m_stack_write(cpu
, fpcar
+ 0x40,
390 vfp_get_fpscr(env
), mmu_idx
, STACK_LAZYFP
);
394 * We definitely pended an exception, but it's possible that it
395 * might not be able to be taken now. If its priority permits us
396 * to take it now, then we must not update the LSPACT or FP regs,
397 * but instead jump out to take the exception immediately.
398 * If it's just pending and won't be taken until the current
399 * handler exits, then we do update LSPACT and the FP regs.
401 take_exception
= !stacked_ok
&&
402 armv7m_nvic_can_take_pending_exception(env
->nvic
);
404 qemu_mutex_unlock_iothread();
406 if (take_exception
) {
407 raise_exception_ra(env
, EXCP_LAZYFP
, 0, 1, GETPC());
410 env
->v7m
.fpccr
[is_secure
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
413 /* Clear s0 to s31 and the FPSCR */
416 for (i
= 0; i
< 32; i
+= 2) {
417 *aa32_vfp_dreg(env
, i
/ 2) = 0;
419 vfp_set_fpscr(env
, 0);
422 * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them
428 * Write to v7M CONTROL.SPSEL bit for the specified security bank.
429 * This may change the current stack pointer between Main and Process
430 * stack pointers if it is done for the CONTROL register for the current
433 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
437 bool old_is_psp
= v7m_using_psp(env
);
439 env
->v7m
.control
[secstate
] =
440 deposit32(env
->v7m
.control
[secstate
],
441 R_V7M_CONTROL_SPSEL_SHIFT
,
442 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
444 if (secstate
== env
->v7m
.secure
) {
445 bool new_is_psp
= v7m_using_psp(env
);
448 if (old_is_psp
!= new_is_psp
) {
449 tmp
= env
->v7m
.other_sp
;
450 env
->v7m
.other_sp
= env
->regs
[13];
457 * Write to v7M CONTROL.SPSEL bit. This may change the current
458 * stack pointer between Main and Process stack pointers.
460 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
462 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
465 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
468 * Write a new value to v7m.exception, thus transitioning into or out
469 * of Handler mode; this may result in a change of active stack pointer.
471 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
474 env
->v7m
.exception
= new_exc
;
476 new_is_psp
= v7m_using_psp(env
);
478 if (old_is_psp
!= new_is_psp
) {
479 tmp
= env
->v7m
.other_sp
;
480 env
->v7m
.other_sp
= env
->regs
[13];
485 /* Switch M profile security state between NS and S */
486 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
488 uint32_t new_ss_msp
, new_ss_psp
;
490 if (env
->v7m
.secure
== new_secstate
) {
495 * All the banked state is accessed by looking at env->v7m.secure
496 * except for the stack pointer; rearrange the SP appropriately.
498 new_ss_msp
= env
->v7m
.other_ss_msp
;
499 new_ss_psp
= env
->v7m
.other_ss_psp
;
501 if (v7m_using_psp(env
)) {
502 env
->v7m
.other_ss_psp
= env
->regs
[13];
503 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
505 env
->v7m
.other_ss_msp
= env
->regs
[13];
506 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
509 env
->v7m
.secure
= new_secstate
;
511 if (v7m_using_psp(env
)) {
512 env
->regs
[13] = new_ss_psp
;
513 env
->v7m
.other_sp
= new_ss_msp
;
515 env
->regs
[13] = new_ss_msp
;
516 env
->v7m
.other_sp
= new_ss_psp
;
520 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
524 * - if the return value is a magic value, do exception return (like BX)
525 * - otherwise bit 0 of the return value is the target security state
529 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
530 /* Covers FNC_RETURN and EXC_RETURN magic */
531 min_magic
= FNC_RETURN_MIN_MAGIC
;
533 /* EXC_RETURN magic only */
534 min_magic
= EXC_RETURN_MIN_MAGIC
;
537 if (dest
>= min_magic
) {
539 * This is an exception return magic value; put it where
540 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
541 * Note that if we ever add gen_ss_advance() singlestep support to
542 * M profile this should count as an "instruction execution complete"
543 * event (compare gen_bx_excret_final_code()).
545 env
->regs
[15] = dest
& ~1;
546 env
->thumb
= dest
& 1;
547 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
551 /* translate.c should have made BXNS UNDEF unless we're secure */
552 assert(env
->v7m
.secure
);
555 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
557 switch_v7m_security_state(env
, dest
& 1);
559 env
->regs
[15] = dest
& ~1;
560 arm_rebuild_hflags(env
);
563 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
567 * - bit 0 of the destination address is the target security state
570 /* At this point regs[15] is the address just after the BLXNS */
571 uint32_t nextinst
= env
->regs
[15] | 1;
572 uint32_t sp
= env
->regs
[13] - 8;
575 /* translate.c will have made BLXNS UNDEF unless we're secure */
576 assert(env
->v7m
.secure
);
580 * Target is Secure, so this is just a normal BLX,
581 * except that the low bit doesn't indicate Thumb/not.
583 env
->regs
[14] = nextinst
;
585 env
->regs
[15] = dest
& ~1;
589 /* Target is non-secure: first push a stack frame */
590 if (!QEMU_IS_ALIGNED(sp
, 8)) {
591 qemu_log_mask(LOG_GUEST_ERROR
,
592 "BLXNS with misaligned SP is UNPREDICTABLE\n");
595 if (sp
< v7m_sp_limit(env
)) {
596 raise_exception(env
, EXCP_STKOF
, 0, 1);
599 saved_psr
= env
->v7m
.exception
;
600 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
601 saved_psr
|= XPSR_SFPA
;
604 /* Note that these stores can throw exceptions on MPU faults */
605 cpu_stl_data_ra(env
, sp
, nextinst
, GETPC());
606 cpu_stl_data_ra(env
, sp
+ 4, saved_psr
, GETPC());
609 env
->regs
[14] = 0xfeffffff;
610 if (arm_v7m_is_handler_mode(env
)) {
612 * Write a dummy value to IPSR, to avoid leaking the current secure
613 * exception number to non-secure code. This is guaranteed not
614 * to cause write_v7m_exception() to actually change stacks.
616 write_v7m_exception(env
, 1);
618 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
619 switch_v7m_security_state(env
, 0);
621 env
->regs
[15] = dest
;
622 arm_rebuild_hflags(env
);
625 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
629 * Return a pointer to the location where we currently store the
630 * stack pointer for the requested security state and thread mode.
631 * This pointer will become invalid if the CPU state is updated
632 * such that the stack pointers are switched around (eg changing
633 * the SPSEL control bit).
634 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
635 * Unlike that pseudocode, we require the caller to pass us in the
636 * SPSEL control bit value; this is because we also use this
637 * function in handling of pushing of the callee-saves registers
638 * part of the v8M stack frame (pseudocode PushCalleeStack()),
639 * and in the tailchain codepath the SPSEL bit comes from the exception
640 * return magic LR value from the previous exception. The pseudocode
641 * opencodes the stack-selection in PushCalleeStack(), but we prefer
642 * to make this utility function generic enough to do the job.
644 bool want_psp
= threadmode
&& spsel
;
646 if (secure
== env
->v7m
.secure
) {
647 if (want_psp
== v7m_using_psp(env
)) {
648 return &env
->regs
[13];
650 return &env
->v7m
.other_sp
;
654 return &env
->v7m
.other_ss_psp
;
656 return &env
->v7m
.other_ss_msp
;
661 static bool arm_v7m_load_vector(ARMCPU
*cpu
, int exc
, bool targets_secure
,
664 CPUState
*cs
= CPU(cpu
);
665 CPUARMState
*env
= &cpu
->env
;
667 uint32_t addr
= env
->v7m
.vecbase
[targets_secure
] + exc
* 4;
668 uint32_t vector_entry
;
669 MemTxAttrs attrs
= {};
673 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targets_secure
, true);
676 * We don't do a get_phys_addr() here because the rules for vector
677 * loads are special: they always use the default memory map, and
678 * the default memory map permits reads from all addresses.
679 * Since there's no easy way to pass through to pmsav8_mpu_lookup()
680 * that we want this special case which would always say "yes",
681 * we just do the SAU lookup here followed by a direct physical load.
683 attrs
.secure
= targets_secure
;
686 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
687 V8M_SAttributes sattrs
= {};
689 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
691 attrs
.secure
= false;
692 } else if (!targets_secure
) {
694 * NS access to S memory: the underlying exception which we escalate
695 * to HardFault is SecureFault, which always targets Secure.
702 vector_entry
= address_space_ldl(arm_addressspace(cs
, attrs
), addr
,
704 if (result
!= MEMTX_OK
) {
706 * Underlying exception is BusFault: its target security state
707 * depends on BFHFNMINS.
709 exc_secure
= !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
712 *pvec
= vector_entry
;
717 * All vector table fetch fails are reported as HardFault, with
718 * HFSR.VECTTBL and .FORCED set. (FORCED is set because
719 * technically the underlying exception is a SecureFault or BusFault
720 * that is escalated to HardFault.) This is a terminal exception,
721 * so we will either take the HardFault immediately or else enter
722 * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()).
723 * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
724 * secure); otherwise it targets the same security state as the
725 * underlying exception.
726 * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
728 if (!(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
731 env
->v7m
.hfsr
|= R_V7M_HFSR_VECTTBL_MASK
;
732 if (!arm_feature(env
, ARM_FEATURE_V8_1M
)) {
733 env
->v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
735 armv7m_nvic_set_pending_derived(env
->nvic
, ARMV7M_EXCP_HARD
, exc_secure
);
739 static uint32_t v7m_integrity_sig(CPUARMState
*env
, uint32_t lr
)
742 * Return the integrity signature value for the callee-saves
743 * stack frame section. @lr is the exception return payload/LR value
744 * whose FType bit forms bit 0 of the signature if FP is present.
746 uint32_t sig
= 0xfefa125a;
748 if (!cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))
749 || (lr
& R_V7M_EXCRET_FTYPE_MASK
)) {
755 static bool v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
759 * For v8M, push the callee-saves register part of the stack frame.
760 * Compare the v8M pseudocode PushCalleeStack().
761 * In the tailchaining case this may not be the current stack.
763 CPUARMState
*env
= &cpu
->env
;
764 uint32_t *frame_sp_p
;
771 StackingMode smode
= ignore_faults
? STACK_IGNFAULTS
: STACK_NORMAL
;
774 bool mode
= lr
& R_V7M_EXCRET_MODE_MASK
;
775 bool priv
= !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_NPRIV_MASK
) ||
778 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, M_REG_S
, priv
);
779 frame_sp_p
= get_v7m_sp_ptr(env
, M_REG_S
, mode
,
780 lr
& R_V7M_EXCRET_SPSEL_MASK
);
781 want_psp
= mode
&& (lr
& R_V7M_EXCRET_SPSEL_MASK
);
783 limit
= env
->v7m
.psplim
[M_REG_S
];
785 limit
= env
->v7m
.msplim
[M_REG_S
];
788 mmu_idx
= arm_mmu_idx(env
);
789 frame_sp_p
= &env
->regs
[13];
790 limit
= v7m_sp_limit(env
);
793 frameptr
= *frame_sp_p
- 0x28;
794 if (frameptr
< limit
) {
796 * Stack limit failure: set SP to the limit value, and generate
797 * STKOF UsageFault. Stack pushes below the limit must not be
798 * performed. It is IMPDEF whether pushes above the limit are
799 * performed; we choose not to.
801 qemu_log_mask(CPU_LOG_INT
,
802 "...STKOF during callee-saves register stacking\n");
803 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
804 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
811 * Write as much of the stack frame as we can. A write failure may
812 * cause us to pend a derived exception.
814 sig
= v7m_integrity_sig(env
, lr
);
816 v7m_stack_write(cpu
, frameptr
, sig
, mmu_idx
, smode
) &&
817 v7m_stack_write(cpu
, frameptr
+ 0x8, env
->regs
[4], mmu_idx
, smode
) &&
818 v7m_stack_write(cpu
, frameptr
+ 0xc, env
->regs
[5], mmu_idx
, smode
) &&
819 v7m_stack_write(cpu
, frameptr
+ 0x10, env
->regs
[6], mmu_idx
, smode
) &&
820 v7m_stack_write(cpu
, frameptr
+ 0x14, env
->regs
[7], mmu_idx
, smode
) &&
821 v7m_stack_write(cpu
, frameptr
+ 0x18, env
->regs
[8], mmu_idx
, smode
) &&
822 v7m_stack_write(cpu
, frameptr
+ 0x1c, env
->regs
[9], mmu_idx
, smode
) &&
823 v7m_stack_write(cpu
, frameptr
+ 0x20, env
->regs
[10], mmu_idx
, smode
) &&
824 v7m_stack_write(cpu
, frameptr
+ 0x24, env
->regs
[11], mmu_idx
, smode
);
826 /* Update SP regardless of whether any of the stack accesses failed. */
827 *frame_sp_p
= frameptr
;
832 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
,
833 bool ignore_stackfaults
)
836 * Do the "take the exception" parts of exception entry,
837 * but not the pushing of state to the stack. This is
838 * similar to the pseudocode ExceptionTaken() function.
840 CPUARMState
*env
= &cpu
->env
;
844 bool push_failed
= false;
846 armv7m_nvic_get_pending_irq_info(env
->nvic
, &exc
, &targets_secure
);
847 qemu_log_mask(CPU_LOG_INT
, "...taking pending %s exception %d\n",
848 targets_secure
? "secure" : "nonsecure", exc
);
851 /* Sanitize LR FType and PREFIX bits */
852 if (!cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
853 lr
|= R_V7M_EXCRET_FTYPE_MASK
;
855 lr
= deposit32(lr
, 24, 8, 0xff);
858 if (arm_feature(env
, ARM_FEATURE_V8
)) {
859 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
860 (lr
& R_V7M_EXCRET_S_MASK
)) {
862 * The background code (the owner of the registers in the
863 * exception frame) is Secure. This means it may either already
864 * have or now needs to push callee-saves registers.
866 if (targets_secure
) {
867 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
869 * We took an exception from Secure to NonSecure
870 * (which means the callee-saved registers got stacked)
871 * and are now tailchaining to a Secure exception.
872 * Clear DCRS so eventual return from this Secure
873 * exception unstacks the callee-saved registers.
875 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
879 * We're going to a non-secure exception; push the
880 * callee-saves registers to the stack now, if they're
883 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
884 !(dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
))) {
885 push_failed
= v7m_push_callee_stack(cpu
, lr
, dotailchain
,
888 lr
|= R_V7M_EXCRET_DCRS_MASK
;
892 lr
&= ~R_V7M_EXCRET_ES_MASK
;
893 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
894 lr
|= R_V7M_EXCRET_ES_MASK
;
896 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
897 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
898 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
902 * Clear registers if necessary to prevent non-secure exception
903 * code being able to see register values from secure code.
904 * Where register values become architecturally UNKNOWN we leave
905 * them with their previous values. v8.1M is tighter than v8.0M
906 * here and always zeroes the caller-saved registers regardless
907 * of the security state the exception is targeting.
909 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
910 if (!targets_secure
|| arm_feature(env
, ARM_FEATURE_V8_1M
)) {
912 * Always clear the caller-saved registers (they have been
913 * pushed to the stack earlier in v7m_push_stack()).
914 * Clear callee-saved registers if the background code is
915 * Secure (in which case these regs were saved in
916 * v7m_push_callee_stack()).
920 * r4..r11 are callee-saves, zero only if background
921 * state was Secure (EXCRET.S == 1) and exception
922 * targets Non-secure state
924 bool zero_callee_saves
= !targets_secure
&&
925 (lr
& R_V7M_EXCRET_S_MASK
);
927 for (i
= 0; i
< 13; i
++) {
928 if (i
< 4 || i
> 11 || zero_callee_saves
) {
933 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
938 if (push_failed
&& !ignore_stackfaults
) {
940 * Derived exception on callee-saves register stacking:
941 * we might now want to take a different exception which
942 * targets a different security state, so try again from the top.
944 qemu_log_mask(CPU_LOG_INT
,
945 "...derived exception on callee-saves register stacking");
946 v7m_exception_taken(cpu
, lr
, true, true);
950 if (!arm_v7m_load_vector(cpu
, exc
, targets_secure
, &addr
)) {
951 /* Vector load failed: derived exception */
952 qemu_log_mask(CPU_LOG_INT
, "...derived exception on vector table load");
953 v7m_exception_taken(cpu
, lr
, true, true);
958 * Now we've done everything that might cause a derived exception
959 * we can go ahead and activate whichever exception we're going to
960 * take (which might now be the derived exception).
962 armv7m_nvic_acknowledge_irq(env
->nvic
);
964 /* Switch to target security state -- must do this before writing SPSEL */
965 switch_v7m_security_state(env
, targets_secure
);
966 write_v7m_control_spsel(env
, 0);
967 arm_clear_exclusive(env
);
968 /* Clear SFPA and FPCA (has no effect if no FPU) */
969 env
->v7m
.control
[M_REG_S
] &=
970 ~(R_V7M_CONTROL_FPCA_MASK
| R_V7M_CONTROL_SFPA_MASK
);
972 env
->condexec_bits
= 0;
974 env
->regs
[15] = addr
& 0xfffffffe;
975 env
->thumb
= addr
& 1;
976 arm_rebuild_hflags(env
);
979 static void v7m_update_fpccr(CPUARMState
*env
, uint32_t frameptr
,
983 * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR
984 * that we will need later in order to do lazy FP reg stacking.
986 bool is_secure
= env
->v7m
.secure
;
987 void *nvic
= env
->nvic
;
989 * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
990 * are banked and we want to update the bit in the bank for the
991 * current security state; and in one case we want to specifically
992 * update the NS banked version of a bit even if we are secure.
994 uint32_t *fpccr_s
= &env
->v7m
.fpccr
[M_REG_S
];
995 uint32_t *fpccr_ns
= &env
->v7m
.fpccr
[M_REG_NS
];
996 uint32_t *fpccr
= &env
->v7m
.fpccr
[is_secure
];
997 bool hfrdy
, bfrdy
, mmrdy
, ns_ufrdy
, s_ufrdy
, sfrdy
, monrdy
;
999 env
->v7m
.fpcar
[is_secure
] = frameptr
& ~0x7;
1001 if (apply_splim
&& arm_feature(env
, ARM_FEATURE_V8
)) {
1003 uint32_t splim
= v7m_sp_limit(env
);
1004 bool ign
= armv7m_nvic_neg_prio_requested(nvic
, is_secure
) &&
1005 (env
->v7m
.ccr
[is_secure
] & R_V7M_CCR_STKOFHFNMIGN_MASK
);
1007 splimviol
= !ign
&& frameptr
< splim
;
1008 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, SPLIMVIOL
, splimviol
);
1011 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, LSPACT
, 1);
1013 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, S
, is_secure
);
1015 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, USER
, arm_current_el(env
) == 0);
1017 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, THREAD
,
1018 !arm_v7m_is_handler_mode(env
));
1020 hfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_HARD
, false);
1021 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, HFRDY
, hfrdy
);
1023 bfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_BUS
, false);
1024 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, BFRDY
, bfrdy
);
1026 mmrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_MEM
, is_secure
);
1027 *fpccr
= FIELD_DP32(*fpccr
, V7M_FPCCR
, MMRDY
, mmrdy
);
1029 ns_ufrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_USAGE
, false);
1030 *fpccr_ns
= FIELD_DP32(*fpccr_ns
, V7M_FPCCR
, UFRDY
, ns_ufrdy
);
1032 monrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_DEBUG
, false);
1033 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, MONRDY
, monrdy
);
1035 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1036 s_ufrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_USAGE
, true);
1037 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, UFRDY
, s_ufrdy
);
1039 sfrdy
= armv7m_nvic_get_ready_status(nvic
, ARMV7M_EXCP_SECURE
, false);
1040 *fpccr_s
= FIELD_DP32(*fpccr_s
, V7M_FPCCR
, SFRDY
, sfrdy
);
1044 void HELPER(v7m_vlstm
)(CPUARMState
*env
, uint32_t fptr
)
1046 /* fptr is the value of Rn, the frame pointer we store the FP regs to */
1047 bool s
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
1048 bool lspact
= env
->v7m
.fpccr
[s
] & R_V7M_FPCCR_LSPACT_MASK
;
1049 uintptr_t ra
= GETPC();
1051 assert(env
->v7m
.secure
);
1053 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
1057 /* Check access to the coprocessor is permitted */
1058 if (!v7m_cpacr_pass(env
, true, arm_current_el(env
) != 0)) {
1059 raise_exception_ra(env
, EXCP_NOCP
, 0, 1, GETPC());
1063 /* LSPACT should not be active when there is active FP state */
1064 raise_exception_ra(env
, EXCP_LSERR
, 0, 1, GETPC());
1068 raise_exception_ra(env
, EXCP_UNALIGNED
, 0, 1, GETPC());
1072 * Note that we do not use v7m_stack_write() here, because the
1073 * accesses should not set the FSR bits for stacking errors if they
1074 * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_STACK
1075 * or AccType_LAZYFP). Faults in cpu_stl_data_ra() will throw exceptions
1078 if (!(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPEN_MASK
)) {
1079 bool ts
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
;
1082 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
1083 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
1084 uint32_t faddr
= fptr
+ 4 * i
;
1085 uint32_t slo
= extract64(dn
, 0, 32);
1086 uint32_t shi
= extract64(dn
, 32, 32);
1089 faddr
+= 8; /* skip the slot for the FPSCR */
1091 cpu_stl_data_ra(env
, faddr
, slo
, ra
);
1092 cpu_stl_data_ra(env
, faddr
+ 4, shi
, ra
);
1094 cpu_stl_data_ra(env
, fptr
+ 0x40, vfp_get_fpscr(env
), ra
);
1097 * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to
1098 * leave them unchanged, matching our choice in v7m_preserve_fp_state.
1101 for (i
= 0; i
< 32; i
+= 2) {
1102 *aa32_vfp_dreg(env
, i
/ 2) = 0;
1104 vfp_set_fpscr(env
, 0);
1107 v7m_update_fpccr(env
, fptr
, false);
1110 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
1113 void HELPER(v7m_vlldm
)(CPUARMState
*env
, uint32_t fptr
)
1115 uintptr_t ra
= GETPC();
1117 /* fptr is the value of Rn, the frame pointer we load the FP regs from */
1118 assert(env
->v7m
.secure
);
1120 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
1124 /* Check access to the coprocessor is permitted */
1125 if (!v7m_cpacr_pass(env
, true, arm_current_el(env
) != 0)) {
1126 raise_exception_ra(env
, EXCP_NOCP
, 0, 1, GETPC());
1129 if (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
) {
1130 /* State in FP is still valid */
1131 env
->v7m
.fpccr
[M_REG_S
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
1133 bool ts
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
;
1138 raise_exception_ra(env
, EXCP_UNALIGNED
, 0, 1, GETPC());
1141 for (i
= 0; i
< (ts
? 32 : 16); i
+= 2) {
1144 uint32_t faddr
= fptr
+ 4 * i
;
1147 faddr
+= 8; /* skip the slot for the FPSCR */
1150 slo
= cpu_ldl_data_ra(env
, faddr
, ra
);
1151 shi
= cpu_ldl_data_ra(env
, faddr
+ 4, ra
);
1153 dn
= (uint64_t) shi
<< 32 | slo
;
1154 *aa32_vfp_dreg(env
, i
/ 2) = dn
;
1156 fpscr
= cpu_ldl_data_ra(env
, fptr
+ 0x40, ra
);
1157 vfp_set_fpscr(env
, fpscr
);
1160 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
1163 static bool v7m_push_stack(ARMCPU
*cpu
)
1166 * Do the "set up stack frame" part of exception entry,
1167 * similar to pseudocode PushStack().
1168 * Return true if we generate a derived exception (and so
1169 * should ignore further stack faults trying to process
1170 * that derived exception.)
1172 bool stacked_ok
= true, limitviol
= false;
1173 CPUARMState
*env
= &cpu
->env
;
1174 uint32_t xpsr
= xpsr_read(env
);
1175 uint32_t frameptr
= env
->regs
[13];
1176 ARMMMUIdx mmu_idx
= arm_mmu_idx(env
);
1178 bool nsacr_cp10
= extract32(env
->v7m
.nsacr
, 10, 1);
1180 if ((env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) &&
1181 (env
->v7m
.secure
|| nsacr_cp10
)) {
1182 if (env
->v7m
.secure
&&
1183 env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
) {
1192 /* Align stack pointer if the guest wants that */
1193 if ((frameptr
& 4) &&
1194 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
1196 xpsr
|= XPSR_SPREALIGN
;
1200 if (env
->v7m
.secure
&&
1201 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)) {
1205 frameptr
-= framesize
;
1207 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1208 uint32_t limit
= v7m_sp_limit(env
);
1210 if (frameptr
< limit
) {
1212 * Stack limit failure: set SP to the limit value, and generate
1213 * STKOF UsageFault. Stack pushes below the limit must not be
1214 * performed. It is IMPDEF whether pushes above the limit are
1215 * performed; we choose not to.
1217 qemu_log_mask(CPU_LOG_INT
,
1218 "...STKOF during stacking\n");
1219 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
1220 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1222 env
->regs
[13] = limit
;
1224 * We won't try to perform any further memory accesses but
1225 * we must continue through the following code to check for
1226 * permission faults during FPU state preservation, and we
1227 * must update FPCCR if lazy stacking is enabled.
1235 * Write as much of the stack frame as we can. If we fail a stack
1236 * write this will result in a derived exception being pended
1237 * (which may be taken in preference to the one we started with
1238 * if it has higher priority).
1240 stacked_ok
= stacked_ok
&&
1241 v7m_stack_write(cpu
, frameptr
, env
->regs
[0], mmu_idx
, STACK_NORMAL
) &&
1242 v7m_stack_write(cpu
, frameptr
+ 4, env
->regs
[1],
1243 mmu_idx
, STACK_NORMAL
) &&
1244 v7m_stack_write(cpu
, frameptr
+ 8, env
->regs
[2],
1245 mmu_idx
, STACK_NORMAL
) &&
1246 v7m_stack_write(cpu
, frameptr
+ 12, env
->regs
[3],
1247 mmu_idx
, STACK_NORMAL
) &&
1248 v7m_stack_write(cpu
, frameptr
+ 16, env
->regs
[12],
1249 mmu_idx
, STACK_NORMAL
) &&
1250 v7m_stack_write(cpu
, frameptr
+ 20, env
->regs
[14],
1251 mmu_idx
, STACK_NORMAL
) &&
1252 v7m_stack_write(cpu
, frameptr
+ 24, env
->regs
[15],
1253 mmu_idx
, STACK_NORMAL
) &&
1254 v7m_stack_write(cpu
, frameptr
+ 28, xpsr
, mmu_idx
, STACK_NORMAL
);
1256 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) {
1257 /* FPU is active, try to save its registers */
1258 bool fpccr_s
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
1259 bool lspact
= env
->v7m
.fpccr
[fpccr_s
] & R_V7M_FPCCR_LSPACT_MASK
;
1261 if (lspact
&& arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1262 qemu_log_mask(CPU_LOG_INT
,
1263 "...SecureFault because LSPACT and FPCA both set\n");
1264 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
1265 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1266 } else if (!env
->v7m
.secure
&& !nsacr_cp10
) {
1267 qemu_log_mask(CPU_LOG_INT
,
1268 "...Secure UsageFault with CFSR.NOCP because "
1269 "NSACR.CP10 prevents stacking FP regs\n");
1270 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, M_REG_S
);
1271 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_NOCP_MASK
;
1273 if (!(env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPEN_MASK
)) {
1274 /* Lazy stacking disabled, save registers now */
1276 bool cpacr_pass
= v7m_cpacr_pass(env
, env
->v7m
.secure
,
1277 arm_current_el(env
) != 0);
1279 if (stacked_ok
&& !cpacr_pass
) {
1281 * Take UsageFault if CPACR forbids access. The pseudocode
1282 * here does a full CheckCPEnabled() but we know the NSACR
1283 * check can never fail as we have already handled that.
1285 qemu_log_mask(CPU_LOG_INT
,
1286 "...UsageFault with CFSR.NOCP because "
1287 "CPACR.CP10 prevents stacking FP regs\n");
1288 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1290 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
1294 for (i
= 0; i
< ((framesize
== 0xa8) ? 32 : 16); i
+= 2) {
1295 uint64_t dn
= *aa32_vfp_dreg(env
, i
/ 2);
1296 uint32_t faddr
= frameptr
+ 0x20 + 4 * i
;
1297 uint32_t slo
= extract64(dn
, 0, 32);
1298 uint32_t shi
= extract64(dn
, 32, 32);
1301 faddr
+= 8; /* skip the slot for the FPSCR */
1303 stacked_ok
= stacked_ok
&&
1304 v7m_stack_write(cpu
, faddr
, slo
,
1305 mmu_idx
, STACK_NORMAL
) &&
1306 v7m_stack_write(cpu
, faddr
+ 4, shi
,
1307 mmu_idx
, STACK_NORMAL
);
1309 stacked_ok
= stacked_ok
&&
1310 v7m_stack_write(cpu
, frameptr
+ 0x60,
1311 vfp_get_fpscr(env
), mmu_idx
, STACK_NORMAL
);
1313 for (i
= 0; i
< ((framesize
== 0xa8) ? 32 : 16); i
+= 2) {
1314 *aa32_vfp_dreg(env
, i
/ 2) = 0;
1316 vfp_set_fpscr(env
, 0);
1319 /* Lazy stacking enabled, save necessary info to stack later */
1320 v7m_update_fpccr(env
, frameptr
+ 0x20, true);
1326 * If we broke a stack limit then SP was already updated earlier;
1327 * otherwise we update SP regardless of whether any of the stack
1328 * accesses failed or we took some other kind of fault.
1331 env
->regs
[13] = frameptr
;
1337 static void do_v7m_exception_exit(ARMCPU
*cpu
)
1339 CPUARMState
*env
= &cpu
->env
;
1341 uint32_t xpsr
, xpsr_mask
;
1342 bool ufault
= false;
1343 bool sfault
= false;
1344 bool return_to_sp_process
;
1345 bool return_to_handler
;
1346 bool rettobase
= false;
1347 bool exc_secure
= false;
1348 bool return_to_secure
;
1350 bool restore_s16_s31
= false;
1353 * If we're not in Handler mode then jumps to magic exception-exit
1354 * addresses don't have magic behaviour. However for the v8M
1355 * security extensions the magic secure-function-return has to
1356 * work in thread mode too, so to avoid doing an extra check in
1357 * the generated code we allow exception-exit magic to also cause the
1358 * internal exception and bring us here in thread mode. Correct code
1359 * will never try to do this (the following insn fetch will always
1360 * fault) so we the overhead of having taken an unnecessary exception
1363 if (!arm_v7m_is_handler_mode(env
)) {
1368 * In the spec pseudocode ExceptionReturn() is called directly
1369 * from BXWritePC() and gets the full target PC value including
1370 * bit zero. In QEMU's implementation we treat it as a normal
1371 * jump-to-register (which is then caught later on), and so split
1372 * the target value up between env->regs[15] and env->thumb in
1373 * gen_bx(). Reconstitute it.
1375 excret
= env
->regs
[15];
1380 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
1381 " previous exception %d\n",
1382 excret
, env
->v7m
.exception
);
1384 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
1385 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
1386 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
1390 ftype
= excret
& R_V7M_EXCRET_FTYPE_MASK
;
1392 if (!ftype
&& !cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1393 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero FTYPE in exception "
1394 "exit PC value 0x%" PRIx32
" is UNPREDICTABLE "
1395 "if FPU not present\n",
1400 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1402 * EXC_RETURN.ES validation check (R_SMFL). We must do this before
1403 * we pick which FAULTMASK to clear.
1405 if (!env
->v7m
.secure
&&
1406 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
1407 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
1409 /* For all other purposes, treat ES as 0 (R_HXSR) */
1410 excret
&= ~R_V7M_EXCRET_ES_MASK
;
1412 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
1415 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
1417 * Auto-clear FAULTMASK on return from other than NMI.
1418 * If the security extension is implemented then this only
1419 * happens if the raw execution priority is >= 0; the
1420 * value of the ES bit in the exception return value indicates
1421 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
1423 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1424 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
1425 env
->v7m
.faultmask
[exc_secure
] = 0;
1428 env
->v7m
.faultmask
[M_REG_NS
] = 0;
1432 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
1435 /* attempt to exit an exception that isn't active */
1439 /* still an irq active now */
1443 * We returned to base exception level, no nesting.
1444 * (In the pseudocode this is written using "NestedActivation != 1"
1445 * where we have 'rettobase == false'.)
1450 g_assert_not_reached();
1453 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
1454 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
1455 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
1456 (excret
& R_V7M_EXCRET_S_MASK
);
1458 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1459 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1461 * UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
1462 * we choose to take the UsageFault.
1464 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
1465 (excret
& R_V7M_EXCRET_ES_MASK
) ||
1466 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
1470 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
1474 /* For v7M we only recognize certain combinations of the low bits */
1475 switch (excret
& 0xf) {
1476 case 1: /* Return to Handler */
1478 case 13: /* Return to Thread using Process stack */
1479 case 9: /* Return to Thread using Main stack */
1481 * We only need to check NONBASETHRDENA for v7M, because in
1482 * v8M this bit does not exist (it is RES1).
1485 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
1486 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
1496 * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
1497 * Handler mode (and will be until we write the new XPSR.Interrupt
1498 * field) this does not switch around the current stack pointer.
1499 * We must do this before we do any kind of tailchaining, including
1500 * for the derived exceptions on integrity check failures, or we will
1501 * give the guest an incorrect EXCRET.SPSEL value on exception entry.
1503 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
1506 * Clear scratch FP values left in caller saved registers; this
1507 * must happen before any kind of tail chaining.
1509 if ((env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_CLRONRET_MASK
) &&
1510 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
)) {
1511 if (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
) {
1512 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
1513 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1514 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
1515 "stackframe: error during lazy state deactivation\n");
1516 v7m_exception_taken(cpu
, excret
, true, false);
1519 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
1520 /* v8.1M adds this NOCP check */
1521 bool nsacr_pass
= exc_secure
||
1522 extract32(env
->v7m
.nsacr
, 10, 1);
1523 bool cpacr_pass
= v7m_cpacr_pass(env
, exc_secure
, true);
1525 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, true);
1526 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_NOCP_MASK
;
1527 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
1528 "stackframe: NSACR prevents clearing FPU registers\n");
1529 v7m_exception_taken(cpu
, excret
, true, false);
1530 } else if (!cpacr_pass
) {
1531 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1533 env
->v7m
.cfsr
[exc_secure
] |= R_V7M_CFSR_NOCP_MASK
;
1534 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
1535 "stackframe: CPACR prevents clearing FPU registers\n");
1536 v7m_exception_taken(cpu
, excret
, true, false);
1539 /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */
1542 for (i
= 0; i
< 16; i
+= 2) {
1543 *aa32_vfp_dreg(env
, i
/ 2) = 0;
1545 vfp_set_fpscr(env
, 0);
1550 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
1551 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1552 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
1553 "stackframe: failed EXC_RETURN.ES validity check\n");
1554 v7m_exception_taken(cpu
, excret
, true, false);
1560 * Bad exception return: instead of popping the exception
1561 * stack, directly take a usage fault on the current stack.
1563 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
1564 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
1565 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
1566 "stackframe: failed exception return integrity check\n");
1567 v7m_exception_taken(cpu
, excret
, true, false);
1572 * Tailchaining: if there is currently a pending exception that
1573 * is high enough priority to preempt execution at the level we're
1574 * about to return to, then just directly take that exception now,
1575 * avoiding an unstack-and-then-stack. Note that now we have
1576 * deactivated the previous exception by calling armv7m_nvic_complete_irq()
1577 * our current execution priority is already the execution priority we are
1578 * returning to -- none of the state we would unstack or set based on
1579 * the EXCRET value affects it.
1581 if (armv7m_nvic_can_take_pending_exception(env
->nvic
)) {
1582 qemu_log_mask(CPU_LOG_INT
, "...tailchaining to pending exception\n");
1583 v7m_exception_taken(cpu
, excret
, true, false);
1587 switch_v7m_security_state(env
, return_to_secure
);
1591 * The stack pointer we should be reading the exception frame from
1592 * depends on bits in the magic exception return type value (and
1593 * for v8M isn't necessarily the stack pointer we will eventually
1594 * end up resuming execution with). Get a pointer to the location
1595 * in the CPU state struct where the SP we need is currently being
1596 * stored; we will use and modify it in place.
1597 * We use this limited C variable scope so we don't accidentally
1598 * use 'frame_sp_p' after we do something that makes it invalid.
1600 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
1603 return_to_sp_process
);
1604 uint32_t frameptr
= *frame_sp_p
;
1607 bool return_to_priv
= return_to_handler
||
1608 !(env
->v7m
.control
[return_to_secure
] & R_V7M_CONTROL_NPRIV_MASK
);
1610 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, return_to_secure
,
1613 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
1614 arm_feature(env
, ARM_FEATURE_V8
)) {
1615 qemu_log_mask(LOG_GUEST_ERROR
,
1616 "M profile exception return with non-8-aligned SP "
1617 "for destination state is UNPREDICTABLE\n");
1620 /* Do we need to pop callee-saved registers? */
1621 if (return_to_secure
&&
1622 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
1623 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
1624 uint32_t actual_sig
;
1626 pop_ok
= v7m_stack_read(cpu
, &actual_sig
, frameptr
, mmu_idx
);
1628 if (pop_ok
&& v7m_integrity_sig(env
, excret
) != actual_sig
) {
1629 /* Take a SecureFault on the current stack */
1630 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
1631 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1632 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
1633 "stackframe: failed exception return integrity "
1634 "signature check\n");
1635 v7m_exception_taken(cpu
, excret
, true, false);
1640 v7m_stack_read(cpu
, &env
->regs
[4], frameptr
+ 0x8, mmu_idx
) &&
1641 v7m_stack_read(cpu
, &env
->regs
[5], frameptr
+ 0xc, mmu_idx
) &&
1642 v7m_stack_read(cpu
, &env
->regs
[6], frameptr
+ 0x10, mmu_idx
) &&
1643 v7m_stack_read(cpu
, &env
->regs
[7], frameptr
+ 0x14, mmu_idx
) &&
1644 v7m_stack_read(cpu
, &env
->regs
[8], frameptr
+ 0x18, mmu_idx
) &&
1645 v7m_stack_read(cpu
, &env
->regs
[9], frameptr
+ 0x1c, mmu_idx
) &&
1646 v7m_stack_read(cpu
, &env
->regs
[10], frameptr
+ 0x20, mmu_idx
) &&
1647 v7m_stack_read(cpu
, &env
->regs
[11], frameptr
+ 0x24, mmu_idx
);
1654 v7m_stack_read(cpu
, &env
->regs
[0], frameptr
, mmu_idx
) &&
1655 v7m_stack_read(cpu
, &env
->regs
[1], frameptr
+ 0x4, mmu_idx
) &&
1656 v7m_stack_read(cpu
, &env
->regs
[2], frameptr
+ 0x8, mmu_idx
) &&
1657 v7m_stack_read(cpu
, &env
->regs
[3], frameptr
+ 0xc, mmu_idx
) &&
1658 v7m_stack_read(cpu
, &env
->regs
[12], frameptr
+ 0x10, mmu_idx
) &&
1659 v7m_stack_read(cpu
, &env
->regs
[14], frameptr
+ 0x14, mmu_idx
) &&
1660 v7m_stack_read(cpu
, &env
->regs
[15], frameptr
+ 0x18, mmu_idx
) &&
1661 v7m_stack_read(cpu
, &xpsr
, frameptr
+ 0x1c, mmu_idx
);
1665 * v7m_stack_read() pended a fault, so take it (as a tail
1666 * chained exception on the same stack frame)
1668 qemu_log_mask(CPU_LOG_INT
, "...derived exception on unstacking\n");
1669 v7m_exception_taken(cpu
, excret
, true, false);
1674 * Returning from an exception with a PC with bit 0 set is defined
1675 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
1676 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
1677 * the lsbit, and there are several RTOSes out there which incorrectly
1678 * assume the r15 in the stack frame should be a Thumb-style "lsbit
1679 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
1680 * complain about the badly behaved guest.
1682 if (env
->regs
[15] & 1) {
1683 env
->regs
[15] &= ~1U;
1684 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
1685 qemu_log_mask(LOG_GUEST_ERROR
,
1686 "M profile return from interrupt with misaligned "
1687 "PC is UNPREDICTABLE on v7M\n");
1691 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1693 * For v8M we have to check whether the xPSR exception field
1694 * matches the EXCRET value for return to handler/thread
1695 * before we commit to changing the SP and xPSR.
1697 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
1698 if (return_to_handler
!= will_be_handler
) {
1700 * Take an INVPC UsageFault on the current stack.
1701 * By this point we will have switched to the security state
1702 * for the background state, so this UsageFault will target
1705 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1707 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
1708 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
1709 "stackframe: failed exception return integrity "
1711 v7m_exception_taken(cpu
, excret
, true, false);
1717 /* FP present and we need to handle it */
1718 if (!return_to_secure
&&
1719 (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_LSPACT_MASK
)) {
1720 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1721 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
1722 qemu_log_mask(CPU_LOG_INT
,
1723 "...taking SecureFault on existing stackframe: "
1724 "Secure LSPACT set but exception return is "
1725 "not to secure state\n");
1726 v7m_exception_taken(cpu
, excret
, true, false);
1730 restore_s16_s31
= return_to_secure
&&
1731 (env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_TS_MASK
);
1733 if (env
->v7m
.fpccr
[return_to_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
1734 /* State in FPU is still valid, just clear LSPACT */
1735 env
->v7m
.fpccr
[return_to_secure
] &= ~R_V7M_FPCCR_LSPACT_MASK
;
1739 bool cpacr_pass
, nsacr_pass
;
1741 cpacr_pass
= v7m_cpacr_pass(env
, return_to_secure
,
1743 nsacr_pass
= return_to_secure
||
1744 extract32(env
->v7m
.nsacr
, 10, 1);
1747 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1749 env
->v7m
.cfsr
[return_to_secure
] |= R_V7M_CFSR_NOCP_MASK
;
1750 qemu_log_mask(CPU_LOG_INT
,
1751 "...taking UsageFault on existing "
1752 "stackframe: CPACR.CP10 prevents unstacking "
1754 v7m_exception_taken(cpu
, excret
, true, false);
1756 } else if (!nsacr_pass
) {
1757 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, true);
1758 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_INVPC_MASK
;
1759 qemu_log_mask(CPU_LOG_INT
,
1760 "...taking Secure UsageFault on existing "
1761 "stackframe: NSACR.CP10 prevents unstacking "
1763 v7m_exception_taken(cpu
, excret
, true, false);
1767 for (i
= 0; i
< (restore_s16_s31
? 32 : 16); i
+= 2) {
1770 uint32_t faddr
= frameptr
+ 0x20 + 4 * i
;
1773 faddr
+= 8; /* Skip the slot for the FPSCR */
1777 v7m_stack_read(cpu
, &slo
, faddr
, mmu_idx
) &&
1778 v7m_stack_read(cpu
, &shi
, faddr
+ 4, mmu_idx
);
1784 dn
= (uint64_t)shi
<< 32 | slo
;
1785 *aa32_vfp_dreg(env
, i
/ 2) = dn
;
1788 v7m_stack_read(cpu
, &fpscr
, frameptr
+ 0x60, mmu_idx
);
1790 vfp_set_fpscr(env
, fpscr
);
1794 * These regs are 0 if security extension present;
1795 * otherwise merely UNKNOWN. We zero always.
1797 for (i
= 0; i
< (restore_s16_s31
? 32 : 16); i
+= 2) {
1798 *aa32_vfp_dreg(env
, i
/ 2) = 0;
1800 vfp_set_fpscr(env
, 0);
1804 env
->v7m
.control
[M_REG_S
] = FIELD_DP32(env
->v7m
.control
[M_REG_S
],
1805 V7M_CONTROL
, FPCA
, !ftype
);
1807 /* Commit to consuming the stack frame */
1811 if (restore_s16_s31
) {
1816 * Undo stack alignment (the SPREALIGN bit indicates that the original
1817 * pre-exception SP was not 8-aligned and we added a padding word to
1818 * align it, so we undo this by ORing in the bit that increases it
1819 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
1820 * would work too but a logical OR is how the pseudocode specifies it.)
1822 if (xpsr
& XPSR_SPREALIGN
) {
1825 *frame_sp_p
= frameptr
;
1828 xpsr_mask
= ~(XPSR_SPREALIGN
| XPSR_SFPA
);
1829 if (!arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
1830 xpsr_mask
&= ~XPSR_GE
;
1832 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
1833 xpsr_write(env
, xpsr
, xpsr_mask
);
1835 if (env
->v7m
.secure
) {
1836 bool sfpa
= xpsr
& XPSR_SFPA
;
1838 env
->v7m
.control
[M_REG_S
] = FIELD_DP32(env
->v7m
.control
[M_REG_S
],
1839 V7M_CONTROL
, SFPA
, sfpa
);
1843 * The restored xPSR exception field will be zero if we're
1844 * resuming in Thread mode. If that doesn't match what the
1845 * exception return excret specified then this is a UsageFault.
1846 * v7M requires we make this check here; v8M did it earlier.
1848 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
1850 * Take an INVPC UsageFault by pushing the stack again;
1851 * we know we're v7M so this is never a Secure UsageFault.
1853 bool ignore_stackfaults
;
1855 assert(!arm_feature(env
, ARM_FEATURE_V8
));
1856 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
1857 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
1858 ignore_stackfaults
= v7m_push_stack(cpu
);
1859 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
1860 "failed exception return integrity check\n");
1861 v7m_exception_taken(cpu
, excret
, false, ignore_stackfaults
);
1865 /* Otherwise, we have a successful exception exit. */
1866 arm_clear_exclusive(env
);
1867 arm_rebuild_hflags(env
);
1868 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
1871 static bool do_v7m_function_return(ARMCPU
*cpu
)
1874 * v8M security extensions magic function return.
1876 * (1) throw an exception (longjump)
1877 * (2) return true if we successfully handled the function return
1878 * (3) return false if we failed a consistency check and have
1879 * pended a UsageFault that needs to be taken now
1881 * At this point the magic return value is split between env->regs[15]
1882 * and env->thumb. We don't bother to reconstitute it because we don't
1883 * need it (all values are handled the same way).
1885 CPUARMState
*env
= &cpu
->env
;
1886 uint32_t newpc
, newpsr
, newpsr_exc
;
1888 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
1891 bool threadmode
, spsel
;
1894 uint32_t *frame_sp_p
;
1897 /* Pull the return address and IPSR from the Secure stack */
1898 threadmode
= !arm_v7m_is_handler_mode(env
);
1899 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
1901 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
1902 frameptr
= *frame_sp_p
;
1905 * These loads may throw an exception (for MPU faults). We want to
1906 * do them as secure, so work out what MMU index that is.
1908 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
1909 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
1910 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
1911 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
1913 /* Consistency checks on new IPSR */
1914 newpsr_exc
= newpsr
& XPSR_EXCP
;
1915 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
1916 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
1917 /* Pend the fault and tell our caller to take it */
1918 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
1919 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
1921 qemu_log_mask(CPU_LOG_INT
,
1922 "...taking INVPC UsageFault: "
1923 "IPSR consistency check failed\n");
1927 *frame_sp_p
= frameptr
+ 8;
1930 /* This invalidates frame_sp_p */
1931 switch_v7m_security_state(env
, true);
1932 env
->v7m
.exception
= newpsr_exc
;
1933 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
1934 if (newpsr
& XPSR_SFPA
) {
1935 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
1937 xpsr_write(env
, 0, XPSR_IT
);
1938 env
->thumb
= newpc
& 1;
1939 env
->regs
[15] = newpc
& ~1;
1940 arm_rebuild_hflags(env
);
1942 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
1946 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1947 uint32_t addr
, uint16_t *insn
)
1950 * Load a 16-bit portion of a v7M instruction, returning true on success,
1951 * or false on failure (in which case we will have pended the appropriate
1953 * We need to do the instruction fetch's MPU and SAU checks
1954 * like this because there is no MMU index that would allow
1955 * doing the load with a single function call. Instead we must
1956 * first check that the security attributes permit the load
1957 * and that they don't mismatch on the two halves of the instruction,
1958 * and then we do the load as a secure load (ie using the security
1959 * attributes of the address, not the CPU, as architecturally required).
1961 CPUState
*cs
= CPU(cpu
);
1962 CPUARMState
*env
= &cpu
->env
;
1963 V8M_SAttributes sattrs
= {};
1964 MemTxAttrs attrs
= {};
1965 ARMMMUFaultInfo fi
= {};
1966 ARMCacheAttrs cacheattrs
= {};
1968 target_ulong page_size
;
1972 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
1973 if (!sattrs
.nsc
|| sattrs
.ns
) {
1975 * This must be the second half of the insn, and it straddles a
1976 * region boundary with the second half not being S&NSC.
1978 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
1979 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
1980 qemu_log_mask(CPU_LOG_INT
,
1981 "...really SecureFault with SFSR.INVEP\n");
1984 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &physaddr
,
1985 &attrs
, &prot
, &page_size
, &fi
, &cacheattrs
)) {
1986 /* the MPU lookup failed */
1987 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
1988 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
1989 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
1992 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
1994 if (txres
!= MEMTX_OK
) {
1995 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
1996 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
1997 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
2003 static bool v7m_read_sg_stack_word(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
2004 uint32_t addr
, uint32_t *spdata
)
2007 * Read a word of data from the stack for the SG instruction,
2008 * writing the value into *spdata. If the load succeeds, return
2009 * true; otherwise pend an appropriate exception and return false.
2010 * (We can't use data load helpers here that throw an exception
2011 * because of the context we're called in, which is halfway through
2012 * arm_v7m_cpu_do_interrupt().)
2014 CPUState
*cs
= CPU(cpu
);
2015 CPUARMState
*env
= &cpu
->env
;
2016 MemTxAttrs attrs
= {};
2018 target_ulong page_size
;
2021 ARMMMUFaultInfo fi
= {};
2022 ARMCacheAttrs cacheattrs
= {};
2025 if (get_phys_addr(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &physaddr
,
2026 &attrs
, &prot
, &page_size
, &fi
, &cacheattrs
)) {
2027 /* MPU/SAU lookup failed */
2028 if (fi
.type
== ARMFault_QEMU_SFault
) {
2029 qemu_log_mask(CPU_LOG_INT
,
2030 "...SecureFault during stack word read\n");
2031 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
| R_V7M_SFSR_SFARVALID_MASK
;
2032 env
->v7m
.sfar
= addr
;
2033 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
2035 qemu_log_mask(CPU_LOG_INT
,
2036 "...MemManageFault during stack word read\n");
2037 env
->v7m
.cfsr
[M_REG_S
] |= R_V7M_CFSR_DACCVIOL_MASK
|
2038 R_V7M_CFSR_MMARVALID_MASK
;
2039 env
->v7m
.mmfar
[M_REG_S
] = addr
;
2040 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, false);
2044 value
= address_space_ldl(arm_addressspace(cs
, attrs
), physaddr
,
2046 if (txres
!= MEMTX_OK
) {
2047 /* BusFault trying to read the data */
2048 qemu_log_mask(CPU_LOG_INT
,
2049 "...BusFault during stack word read\n");
2050 env
->v7m
.cfsr
[M_REG_NS
] |=
2051 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
2052 env
->v7m
.bfar
= addr
;
2053 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
2061 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
2064 * Check whether this attempt to execute code in a Secure & NS-Callable
2065 * memory region is for an SG instruction; if so, then emulate the
2066 * effect of the SG instruction and return true. Otherwise pend
2067 * the correct kind of exception and return false.
2069 CPUARMState
*env
= &cpu
->env
;
2074 * We should never get here unless get_phys_addr_pmsav8() caused
2075 * an exception for NS executing in S&NSC memory.
2077 assert(!env
->v7m
.secure
);
2078 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
2080 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
2081 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
2083 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
2091 if (insn
!= 0xe97f) {
2093 * Not an SG instruction first half (we choose the IMPDEF
2094 * early-SG-check option).
2099 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
2103 if (insn
!= 0xe97f) {
2105 * Not an SG instruction second half (yes, both halves of the SG
2106 * insn have the same hex value)
2112 * OK, we have confirmed that we really have an SG instruction.
2113 * We know we're NS in S memory so don't need to repeat those checks.
2115 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
2116 ", executing it\n", env
->regs
[15]);
2118 if (cpu_isar_feature(aa32_m_sec_state
, cpu
) &&
2119 !arm_v7m_is_handler_mode(env
)) {
2121 * v8.1M exception stack frame integrity check. Note that we
2122 * must perform the memory access even if CCR_S.TRD is zero
2123 * and we aren't going to check what the data loaded is.
2125 uint32_t spdata
, sp
;
2128 * We know we are currently NS, so the S stack pointers must be
2129 * in other_ss_{psp,msp}, not in regs[13]/other_sp.
2131 sp
= v7m_using_psp(env
) ? env
->v7m
.other_ss_psp
: env
->v7m
.other_ss_msp
;
2132 if (!v7m_read_sg_stack_word(cpu
, mmu_idx
, sp
, &spdata
)) {
2133 /* Stack access failed and an exception has been pended */
2137 if (env
->v7m
.ccr
[M_REG_S
] & R_V7M_CCR_TRD_MASK
) {
2138 if (((spdata
& ~1) == 0xfefa125a) ||
2139 !(env
->v7m
.control
[M_REG_S
] & 1)) {
2145 env
->regs
[14] &= ~1;
2146 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
2147 switch_v7m_security_state(env
, true);
2148 xpsr_write(env
, 0, XPSR_IT
);
2150 arm_rebuild_hflags(env
);
2154 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
2155 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
2156 qemu_log_mask(CPU_LOG_INT
,
2157 "...really SecureFault with SFSR.INVEP\n");
2161 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
2163 ARMCPU
*cpu
= ARM_CPU(cs
);
2164 CPUARMState
*env
= &cpu
->env
;
2166 bool ignore_stackfaults
;
2168 arm_log_exception(cs
->exception_index
);
2171 * For exceptions we just mark as pending on the NVIC, and let that
2174 switch (cs
->exception_index
) {
2176 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
2177 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
2182 * NOCP might be directed to something other than the current
2183 * security state if this fault is because of NSACR; we indicate
2184 * the target security state using exception.target_el.
2186 int target_secstate
;
2188 if (env
->exception
.target_el
== 3) {
2189 target_secstate
= M_REG_S
;
2191 target_secstate
= env
->v7m
.secure
;
2193 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, target_secstate
);
2194 env
->v7m
.cfsr
[target_secstate
] |= R_V7M_CFSR_NOCP_MASK
;
2198 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
2199 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
2202 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
2203 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_STKOF_MASK
;
2206 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
2207 env
->v7m
.sfsr
|= R_V7M_SFSR_LSERR_MASK
;
2209 case EXCP_UNALIGNED
:
2210 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
2211 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNALIGNED_MASK
;
2214 /* The PC already points to the next instruction. */
2215 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
2217 case EXCP_PREFETCH_ABORT
:
2218 case EXCP_DATA_ABORT
:
2220 * Note that for M profile we don't have a guest facing FSR, but
2221 * the env->exception.fsr will be populated by the code that
2222 * raises the fault, in the A profile short-descriptor format.
2224 switch (env
->exception
.fsr
& 0xf) {
2225 case M_FAKE_FSR_NSC_EXEC
:
2227 * Exception generated when we try to execute code at an address
2228 * which is marked as Secure & Non-Secure Callable and the CPU
2229 * is in the Non-Secure state. The only instruction which can
2230 * be executed like this is SG (and that only if both halves of
2231 * the SG instruction have the same security attributes.)
2232 * Everything else must generate an INVEP SecureFault, so we
2233 * emulate the SG instruction here.
2235 if (v7m_handle_execute_nsc(cpu
)) {
2239 case M_FAKE_FSR_SFAULT
:
2241 * Various flavours of SecureFault for attempts to execute or
2242 * access data in the wrong security state.
2244 switch (cs
->exception_index
) {
2245 case EXCP_PREFETCH_ABORT
:
2246 if (env
->v7m
.secure
) {
2247 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
2248 qemu_log_mask(CPU_LOG_INT
,
2249 "...really SecureFault with SFSR.INVTRAN\n");
2251 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
2252 qemu_log_mask(CPU_LOG_INT
,
2253 "...really SecureFault with SFSR.INVEP\n");
2256 case EXCP_DATA_ABORT
:
2257 /* This must be an NS access to S memory */
2258 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
2259 qemu_log_mask(CPU_LOG_INT
,
2260 "...really SecureFault with SFSR.AUVIOL\n");
2263 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
2265 case 0x8: /* External Abort */
2266 switch (cs
->exception_index
) {
2267 case EXCP_PREFETCH_ABORT
:
2268 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
2269 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
2271 case EXCP_DATA_ABORT
:
2272 env
->v7m
.cfsr
[M_REG_NS
] |=
2273 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
2274 env
->v7m
.bfar
= env
->exception
.vaddress
;
2275 qemu_log_mask(CPU_LOG_INT
,
2276 "...with CFSR.PRECISERR and BFAR 0x%x\n",
2280 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
2284 * All other FSR values are either MPU faults or "can't happen
2285 * for M profile" cases.
2287 switch (cs
->exception_index
) {
2288 case EXCP_PREFETCH_ABORT
:
2289 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
2290 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
2292 case EXCP_DATA_ABORT
:
2293 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
2294 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
2295 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
2296 qemu_log_mask(CPU_LOG_INT
,
2297 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
2298 env
->v7m
.mmfar
[env
->v7m
.secure
]);
2301 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
2307 qemu_log_mask(CPU_LOG_INT
,
2308 "...handling as semihosting call 0x%x\n",
2311 env
->regs
[0] = do_common_semihosting(cs
);
2313 g_assert_not_reached();
2315 env
->regs
[15] += env
->thumb
? 2 : 4;
2318 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
2322 case EXCP_EXCEPTION_EXIT
:
2323 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
2324 /* Must be v8M security extension function return */
2325 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
2326 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
2327 if (do_v7m_function_return(cpu
)) {
2331 do_v7m_exception_exit(cpu
);
2337 * We already pended the specific exception in the NVIC in the
2338 * v7m_preserve_fp_state() helper function.
2342 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
2343 return; /* Never happens. Keep compiler happy. */
2346 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2347 lr
= R_V7M_EXCRET_RES1_MASK
|
2348 R_V7M_EXCRET_DCRS_MASK
;
2350 * The S bit indicates whether we should return to Secure
2351 * or NonSecure (ie our current state).
2352 * The ES bit indicates whether we're taking this exception
2353 * to Secure or NonSecure (ie our target state). We set it
2354 * later, in v7m_exception_taken().
2355 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
2356 * This corresponds to the ARM ARM pseudocode for v8M setting
2357 * some LR bits in PushStack() and some in ExceptionTaken();
2358 * the distinction matters for the tailchain cases where we
2359 * can take an exception without pushing the stack.
2361 if (env
->v7m
.secure
) {
2362 lr
|= R_V7M_EXCRET_S_MASK
;
2365 lr
= R_V7M_EXCRET_RES1_MASK
|
2366 R_V7M_EXCRET_S_MASK
|
2367 R_V7M_EXCRET_DCRS_MASK
|
2368 R_V7M_EXCRET_ES_MASK
;
2369 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
2370 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
2373 if (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
)) {
2374 lr
|= R_V7M_EXCRET_FTYPE_MASK
;
2376 if (!arm_v7m_is_handler_mode(env
)) {
2377 lr
|= R_V7M_EXCRET_MODE_MASK
;
2380 ignore_stackfaults
= v7m_push_stack(cpu
);
2381 v7m_exception_taken(cpu
, lr
, false, ignore_stackfaults
);
2384 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2386 unsigned el
= arm_current_el(env
);
2388 /* First handle registers which unprivileged can read */
2390 case 0 ... 7: /* xPSR sub-fields */
2391 return v7m_mrs_xpsr(env
, reg
, el
);
2392 case 20: /* CONTROL */
2393 return v7m_mrs_control(env
, env
->v7m
.secure
);
2394 case 0x94: /* CONTROL_NS */
2396 * We have to handle this here because unprivileged Secure code
2397 * can read the NS CONTROL register.
2399 if (!env
->v7m
.secure
) {
2402 return env
->v7m
.control
[M_REG_NS
] |
2403 (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
);
2407 return 0; /* unprivileged reads others as zero */
2410 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2412 case 0x88: /* MSP_NS */
2413 if (!env
->v7m
.secure
) {
2416 return env
->v7m
.other_ss_msp
;
2417 case 0x89: /* PSP_NS */
2418 if (!env
->v7m
.secure
) {
2421 return env
->v7m
.other_ss_psp
;
2422 case 0x8a: /* MSPLIM_NS */
2423 if (!env
->v7m
.secure
) {
2426 return env
->v7m
.msplim
[M_REG_NS
];
2427 case 0x8b: /* PSPLIM_NS */
2428 if (!env
->v7m
.secure
) {
2431 return env
->v7m
.psplim
[M_REG_NS
];
2432 case 0x90: /* PRIMASK_NS */
2433 if (!env
->v7m
.secure
) {
2436 return env
->v7m
.primask
[M_REG_NS
];
2437 case 0x91: /* BASEPRI_NS */
2438 if (!env
->v7m
.secure
) {
2441 return env
->v7m
.basepri
[M_REG_NS
];
2442 case 0x93: /* FAULTMASK_NS */
2443 if (!env
->v7m
.secure
) {
2446 return env
->v7m
.faultmask
[M_REG_NS
];
2447 case 0x98: /* SP_NS */
2450 * This gives the non-secure SP selected based on whether we're
2451 * currently in handler mode or not, using the NS CONTROL.SPSEL.
2453 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
2455 if (!env
->v7m
.secure
) {
2458 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
2459 return env
->v7m
.other_ss_psp
;
2461 return env
->v7m
.other_ss_msp
;
2471 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
2473 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
2474 case 10: /* MSPLIM */
2475 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2478 return env
->v7m
.msplim
[env
->v7m
.secure
];
2479 case 11: /* PSPLIM */
2480 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2483 return env
->v7m
.psplim
[env
->v7m
.secure
];
2484 case 16: /* PRIMASK */
2485 return env
->v7m
.primask
[env
->v7m
.secure
];
2486 case 17: /* BASEPRI */
2487 case 18: /* BASEPRI_MAX */
2488 return env
->v7m
.basepri
[env
->v7m
.secure
];
2489 case 19: /* FAULTMASK */
2490 return env
->v7m
.faultmask
[env
->v7m
.secure
];
2493 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
2494 " register %d\n", reg
);
2499 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
2502 * We're passed bits [11..0] of the instruction; extract
2503 * SYSm and the mask bits.
2504 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
2505 * we choose to treat them as if the mask bits were valid.
2506 * NB that the pseudocode 'mask' variable is bits [11..10],
2507 * whereas ours is [11..8].
2509 uint32_t mask
= extract32(maskreg
, 8, 4);
2510 uint32_t reg
= extract32(maskreg
, 0, 8);
2511 int cur_el
= arm_current_el(env
);
2513 if (cur_el
== 0 && reg
> 7 && reg
!= 20) {
2515 * only xPSR sub-fields and CONTROL.SFPA may be written by
2521 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2523 case 0x88: /* MSP_NS */
2524 if (!env
->v7m
.secure
) {
2527 env
->v7m
.other_ss_msp
= val
;
2529 case 0x89: /* PSP_NS */
2530 if (!env
->v7m
.secure
) {
2533 env
->v7m
.other_ss_psp
= val
;
2535 case 0x8a: /* MSPLIM_NS */
2536 if (!env
->v7m
.secure
) {
2539 env
->v7m
.msplim
[M_REG_NS
] = val
& ~7;
2541 case 0x8b: /* PSPLIM_NS */
2542 if (!env
->v7m
.secure
) {
2545 env
->v7m
.psplim
[M_REG_NS
] = val
& ~7;
2547 case 0x90: /* PRIMASK_NS */
2548 if (!env
->v7m
.secure
) {
2551 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
2553 case 0x91: /* BASEPRI_NS */
2554 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2557 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
2559 case 0x93: /* FAULTMASK_NS */
2560 if (!env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2563 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
2565 case 0x94: /* CONTROL_NS */
2566 if (!env
->v7m
.secure
) {
2569 write_v7m_control_spsel_for_secstate(env
,
2570 val
& R_V7M_CONTROL_SPSEL_MASK
,
2572 if (arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2573 env
->v7m
.control
[M_REG_NS
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
2574 env
->v7m
.control
[M_REG_NS
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
2577 * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
2578 * RES0 if the FPU is not present, and is stored in the S bank
2580 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
)) &&
2581 extract32(env
->v7m
.nsacr
, 10, 1)) {
2582 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
2583 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_FPCA_MASK
;
2586 case 0x98: /* SP_NS */
2589 * This gives the non-secure SP selected based on whether we're
2590 * currently in handler mode or not, using the NS CONTROL.SPSEL.
2592 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
2593 bool is_psp
= !arm_v7m_is_handler_mode(env
) && spsel
;
2596 if (!env
->v7m
.secure
) {
2600 limit
= is_psp
? env
->v7m
.psplim
[false] : env
->v7m
.msplim
[false];
2603 CPUState
*cs
= env_cpu(env
);
2605 cpu_restore_state(cs
, GETPC(), true);
2606 raise_exception(env
, EXCP_STKOF
, 0, 1);
2610 env
->v7m
.other_ss_psp
= val
;
2612 env
->v7m
.other_ss_msp
= val
;
2622 case 0 ... 7: /* xPSR sub-fields */
2623 v7m_msr_xpsr(env
, mask
, reg
, val
);
2626 if (v7m_using_psp(env
)) {
2627 env
->v7m
.other_sp
= val
;
2629 env
->regs
[13] = val
;
2633 if (v7m_using_psp(env
)) {
2634 env
->regs
[13] = val
;
2636 env
->v7m
.other_sp
= val
;
2639 case 10: /* MSPLIM */
2640 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2643 env
->v7m
.msplim
[env
->v7m
.secure
] = val
& ~7;
2645 case 11: /* PSPLIM */
2646 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2649 env
->v7m
.psplim
[env
->v7m
.secure
] = val
& ~7;
2651 case 16: /* PRIMASK */
2652 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
2654 case 17: /* BASEPRI */
2655 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2658 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
2660 case 18: /* BASEPRI_MAX */
2661 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2665 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
2666 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
2667 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
2670 case 19: /* FAULTMASK */
2671 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2674 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
2676 case 20: /* CONTROL */
2678 * Writing to the SPSEL bit only has an effect if we are in
2679 * thread mode; other bits can be updated by any privileged code.
2680 * write_v7m_control_spsel() deals with updating the SPSEL bit in
2681 * env->v7m.control, so we only need update the others.
2682 * For v7M, we must just ignore explicit writes to SPSEL in handler
2683 * mode; for v8M the write is permitted but will have no effect.
2684 * All these bits are writes-ignored from non-privileged code,
2687 if (cur_el
> 0 && (arm_feature(env
, ARM_FEATURE_V8
) ||
2688 !arm_v7m_is_handler_mode(env
))) {
2689 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
2691 if (cur_el
> 0 && arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
2692 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
2693 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
2695 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
2697 * SFPA is RAZ/WI from NS or if no FPU.
2698 * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
2699 * Both are stored in the S bank.
2701 if (env
->v7m
.secure
) {
2702 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
2703 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_SFPA_MASK
;
2706 (env
->v7m
.secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
) ||
2707 extract32(env
->v7m
.nsacr
, 10, 1))) {
2708 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_FPCA_MASK
;
2709 env
->v7m
.control
[M_REG_S
] |= val
& R_V7M_CONTROL_FPCA_MASK
;
2715 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
2716 " register %d\n", reg
);
2721 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
2723 /* Implement the TT instruction. op is bits [7:6] of the insn. */
2724 bool forceunpriv
= op
& 1;
2726 V8M_SAttributes sattrs
= {};
2728 bool r
, rw
, nsr
, nsrw
, mrvalid
;
2730 ARMMMUFaultInfo fi
= {};
2731 MemTxAttrs attrs
= {};
2736 bool targetsec
= env
->v7m
.secure
;
2740 * Work out what the security state and privilege level we're
2741 * interested in is...
2744 targetsec
= !targetsec
;
2750 targetpriv
= arm_v7m_is_handler_mode(env
) ||
2751 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
2754 /* ...and then figure out which MMU index this is */
2755 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
2758 * We know that the MPU and SAU don't care about the access type
2759 * for our purposes beyond that we don't want to claim to be
2760 * an insn fetch, so we arbitrarily call this a read.
2764 * MPU region info only available for privileged or if
2765 * inspecting the other MPU state.
2767 if (arm_current_el(env
) != 0 || alt
) {
2768 /* We can ignore the return value as prot is always set */
2769 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
2770 &phys_addr
, &attrs
, &prot
, &is_subpage
,
2772 if (mregion
== -1) {
2778 r
= prot
& PAGE_READ
;
2779 rw
= prot
& PAGE_WRITE
;
2787 if (env
->v7m
.secure
) {
2788 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
2789 nsr
= sattrs
.ns
&& r
;
2790 nsrw
= sattrs
.ns
&& rw
;
2797 tt_resp
= (sattrs
.iregion
<< 24) |
2798 (sattrs
.irvalid
<< 23) |
2799 ((!sattrs
.ns
) << 22) |
2804 (sattrs
.srvalid
<< 17) |
2806 (sattrs
.sregion
<< 8) |
2812 #endif /* !CONFIG_USER_ONLY */
2814 ARMMMUIdx
arm_v7m_mmu_idx_all(CPUARMState
*env
,
2815 bool secstate
, bool priv
, bool negpri
)
2817 ARMMMUIdx mmu_idx
= ARM_MMU_IDX_M
;
2820 mmu_idx
|= ARM_MMU_IDX_M_PRIV
;
2824 mmu_idx
|= ARM_MMU_IDX_M_NEGPRI
;
2828 mmu_idx
|= ARM_MMU_IDX_M_S
;
2834 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
2835 bool secstate
, bool priv
)
2837 bool negpri
= armv7m_nvic_neg_prio_requested(env
->nvic
, secstate
);
2839 return arm_v7m_mmu_idx_all(env
, secstate
, priv
, negpri
);
2842 /* Return the MMU index for a v7M CPU in the specified security state */
2843 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
2845 bool priv
= arm_v7m_is_handler_mode(env
) ||
2846 !(env
->v7m
.control
[secstate
] & 1);
2848 return arm_v7m_mmu_idx_for_secstate_and_priv(env
, secstate
, priv
);