5 #include "hw/core/cpu.h"
6 #include "qom/object.h"
10 #define VID 0x03 /* MPIC version ID */
12 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
14 OPENPIC_OUTPUT_INT
= 0, /* IRQ */
15 OPENPIC_OUTPUT_CINT
, /* critical IRQ */
16 OPENPIC_OUTPUT_MCK
, /* Machine check event */
17 OPENPIC_OUTPUT_DEBUG
, /* Inconditional debug event */
18 OPENPIC_OUTPUT_RESET
, /* Core reset event */
22 typedef struct IrqLines
{ qemu_irq irq
[OPENPIC_OUTPUT_NB
]; } IrqLines
;
24 #define OPENPIC_MODEL_RAVEN 0
25 #define OPENPIC_MODEL_FSL_MPIC_20 1
26 #define OPENPIC_MODEL_FSL_MPIC_42 2
27 #define OPENPIC_MODEL_KEYLARGO 3
29 #define OPENPIC_MAX_SRC 256
30 #define OPENPIC_MAX_TMR 4
31 #define OPENPIC_MAX_IPI 4
32 #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
36 #define RAVEN_MAX_CPU 2
37 #define RAVEN_MAX_EXT 48
38 #define RAVEN_MAX_IRQ 64
39 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
40 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
43 #define KEYLARGO_MAX_CPU 4
44 #define KEYLARGO_MAX_EXT 64
45 #define KEYLARGO_MAX_IPI 4
46 #define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI)
47 #define KEYLARGO_MAX_TMR 0
48 #define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */
49 /* Timers don't exist but this makes the code happy... */
50 #define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
52 /* Interrupt definitions */
53 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
54 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
55 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
56 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
57 /* First doorbell IRQ */
58 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
60 typedef struct FslMpicInfo
{
64 typedef enum IRQType
{
66 IRQ_TYPE_FSLINT
, /* FSL internal interrupt -- level only */
67 IRQ_TYPE_FSLSPECIAL
, /* FSL timer/IPI interrupt, edge, no polarity */
70 /* Round up to the nearest 64 IRQs so that the queue length
71 * won't change when moving between 32 and 64 bit hosts.
73 #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
75 typedef struct IRQQueue
{
77 int32_t queue_size
; /* Only used for VMSTATE_BITMAP */
82 typedef struct IRQSource
{
83 uint32_t ivpr
; /* IRQ vector/priority register */
84 uint32_t idr
; /* IRQ destination register */
85 uint32_t destmask
; /* bitmap of CPU destinations */
87 int output
; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
88 int pending
; /* TRUE if IRQ is pending */
90 bool level
:1; /* level-triggered */
91 bool nomask
:1; /* critical interrupts ignore mask on some FSL MPICs */
94 #define IVPR_MASK_SHIFT 31
95 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
96 #define IVPR_ACTIVITY_SHIFT 30
97 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
98 #define IVPR_MODE_SHIFT 29
99 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
100 #define IVPR_POLARITY_SHIFT 23
101 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
102 #define IVPR_SENSE_SHIFT 22
103 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
105 #define IVPR_PRIORITY_MASK (0xFU << 16)
106 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
107 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
109 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
110 #define IDR_EP 0x80000000 /* external pin */
111 #define IDR_CI 0x40000000 /* critical interrupt */
113 typedef struct OpenPICTimer
{
114 uint32_t tccr
; /* Global timer current count register */
115 uint32_t tbcr
; /* Global timer base count register */
117 bool qemu_timer_active
; /* Is the qemu_timer is running? */
118 struct QEMUTimer
*qemu_timer
;
119 struct OpenPICState
*opp
; /* Device timer is part of. */
120 /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
121 current_count written or read, only defined if qemu_timer_active. */
122 uint64_t origin_time
;
125 typedef struct OpenPICMSI
{
126 uint32_t msir
; /* Shared Message Signaled Interrupt Register */
129 typedef struct IRQDest
{
130 int32_t ctpr
; /* CPU current task priority */
135 /* Count of IRQ sources asserting on non-INT outputs */
136 uint32_t outputs_active
[OPENPIC_OUTPUT_NB
];
139 #define TYPE_OPENPIC "openpic"
140 OBJECT_DECLARE_SIMPLE_TYPE(OpenPICState
, OPENPIC
)
142 struct OpenPICState
{
144 SysBusDevice parent_obj
;
149 /* Behavior control */
155 uint32_t vir
; /* Vendor identification register */
156 uint32_t vector_mask
;
161 uint32_t mpic_mode_mask
;
164 MemoryRegion sub_io_mem
[6];
166 /* Global registers */
167 uint32_t frr
; /* Feature reporting register */
168 uint32_t gcr
; /* Global configuration register */
169 uint32_t pir
; /* Processor initialization register */
170 uint32_t spve
; /* Spurious vector register */
171 uint32_t tfrr
; /* Timer frequency reporting register */
172 /* Source registers */
173 IRQSource src
[OPENPIC_MAX_IRQ
];
174 /* Local registers per output pin */
175 IRQDest dst
[MAX_CPU
];
177 /* Timer registers */
178 OpenPICTimer timers
[OPENPIC_MAX_TMR
];
181 /* Shared MSI registers */
182 OpenPICMSI msi
[MAX_MSI
];
189 #endif /* OPENPIC_H */