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linux-headers: update to 3.12-rc1
[qemu/ar7.git] / tcg / ppc / tcg-target.c
blob25955563b86ff135f29da41f749c0ffd323f8f4b
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #if defined _CALL_DARWIN || defined __APPLE__
28 #define TCG_TARGET_CALL_DARWIN
29 #endif
30
31 #ifdef TCG_TARGET_CALL_DARWIN
32 #define LINKAGE_AREA_SIZE 24
33 #define LR_OFFSET 8
34 #elif defined _CALL_AIX
35 #define LINKAGE_AREA_SIZE 52
36 #define LR_OFFSET 8
37 #else
38 #define LINKAGE_AREA_SIZE 8
39 #define LR_OFFSET 4
40 #endif
41
42 #ifndef GUEST_BASE
43 #define GUEST_BASE 0
44 #endif
45
46 #ifdef CONFIG_USE_GUEST_BASE
47 #define TCG_GUEST_BASE_REG 30
48 #else
49 #define TCG_GUEST_BASE_REG 0
50 #endif
51
52 #ifndef NDEBUG
53 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
54 "r0",
55 "r1",
56 "r2",
57 "r3",
58 "r4",
59 "r5",
60 "r6",
61 "r7",
62 "r8",
63 "r9",
64 "r10",
65 "r11",
66 "r12",
67 "r13",
68 "r14",
69 "r15",
70 "r16",
71 "r17",
72 "r18",
73 "r19",
74 "r20",
75 "r21",
76 "r22",
77 "r23",
78 "r24",
79 "r25",
80 "r26",
81 "r27",
82 "r28",
83 "r29",
84 "r30",
85 "r31"
86 };
87 #endif
88
89 static const int tcg_target_reg_alloc_order[] = {
90 TCG_REG_R14,
91 TCG_REG_R15,
92 TCG_REG_R16,
93 TCG_REG_R17,
94 TCG_REG_R18,
95 TCG_REG_R19,
96 TCG_REG_R20,
97 TCG_REG_R21,
98 TCG_REG_R22,
99 TCG_REG_R23,
100 TCG_REG_R28,
101 TCG_REG_R29,
102 TCG_REG_R30,
103 TCG_REG_R31,
104 #ifdef TCG_TARGET_CALL_DARWIN
105 TCG_REG_R2,
106 #endif
107 TCG_REG_R3,
108 TCG_REG_R4,
109 TCG_REG_R5,
110 TCG_REG_R6,
111 TCG_REG_R7,
112 TCG_REG_R8,
113 TCG_REG_R9,
114 TCG_REG_R10,
115 #ifndef TCG_TARGET_CALL_DARWIN
116 TCG_REG_R11,
117 #endif
118 TCG_REG_R12,
119 #ifndef _CALL_SYSV
120 TCG_REG_R13,
121 #endif
122 TCG_REG_R24,
123 TCG_REG_R25,
124 TCG_REG_R26,
125 TCG_REG_R27
126 };
127
128 static const int tcg_target_call_iarg_regs[] = {
129 TCG_REG_R3,
130 TCG_REG_R4,
131 TCG_REG_R5,
132 TCG_REG_R6,
133 TCG_REG_R7,
134 TCG_REG_R8,
135 TCG_REG_R9,
136 TCG_REG_R10
137 };
138
139 static const int tcg_target_call_oarg_regs[2] = {
140 TCG_REG_R3,
141 TCG_REG_R4
142 };
143
144 static const int tcg_target_callee_save_regs[] = {
145 #ifdef TCG_TARGET_CALL_DARWIN
146 TCG_REG_R11,
147 TCG_REG_R13,
148 #endif
149 #ifdef _CALL_AIX
150 TCG_REG_R13,
151 #endif
152 TCG_REG_R14,
153 TCG_REG_R15,
154 TCG_REG_R16,
155 TCG_REG_R17,
156 TCG_REG_R18,
157 TCG_REG_R19,
158 TCG_REG_R20,
159 TCG_REG_R21,
160 TCG_REG_R22,
161 TCG_REG_R23,
162 TCG_REG_R24,
163 TCG_REG_R25,
164 TCG_REG_R26,
165 TCG_REG_R27, /* currently used for the global env */
166 TCG_REG_R28,
167 TCG_REG_R29,
168 TCG_REG_R30,
169 TCG_REG_R31
170 };
171
172 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
173 {
174 tcg_target_long disp;
175
176 disp = target - (tcg_target_long) pc;
177 if ((disp << 6) >> 6 != disp)
178 tcg_abort ();
179
180 return disp & 0x3fffffc;
181 }
182
183 static void reloc_pc24 (void *pc, tcg_target_long target)
184 {
185 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
186 | reloc_pc24_val (pc, target);
187 }
188
189 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
190 {
191 tcg_target_long disp;
192
193 disp = target - (tcg_target_long) pc;
194 if (disp != (int16_t) disp)
195 tcg_abort ();
196
197 return disp & 0xfffc;
198 }
199
200 static void reloc_pc14 (void *pc, tcg_target_long target)
201 {
202 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
203 | reloc_pc14_val (pc, target);
204 }
205
206 static void patch_reloc(uint8_t *code_ptr, int type,
207 intptr_t value, intptr_t addend)
208 {
209 value += addend;
210 switch (type) {
211 case R_PPC_REL14:
212 reloc_pc14 (code_ptr, value);
213 break;
214 case R_PPC_REL24:
215 reloc_pc24 (code_ptr, value);
216 break;
217 default:
218 tcg_abort();
219 }
220 }
221
222 /* parse target specific constraints */
223 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
224 {
225 const char *ct_str;
226
227 ct_str = *pct_str;
228 switch (ct_str[0]) {
229 case 'A': case 'B': case 'C': case 'D':
230 ct->ct |= TCG_CT_REG;
231 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
232 break;
233 case 'r':
234 ct->ct |= TCG_CT_REG;
235 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
236 break;
237 #ifdef CONFIG_SOFTMMU
238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
242 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
243 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
244 #if TARGET_LONG_BITS == 64
245 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
246 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
247 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
248 #endif
249 #endif
250 break;
251 case 'K': /* qemu_st[8..32] constraint */
252 ct->ct |= TCG_CT_REG;
253 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
256 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
258 #if TARGET_LONG_BITS == 64
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
260 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
262 #endif
263 #endif
264 break;
265 case 'M': /* qemu_st64 constraint */
266 ct->ct |= TCG_CT_REG;
267 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
271 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
272 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
273 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8);
274 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
275 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9);
276 #endif
277 break;
278 #else
279 case 'L':
280 case 'K':
281 ct->ct |= TCG_CT_REG;
282 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
283 break;
284 case 'M':
285 ct->ct |= TCG_CT_REG;
286 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
287 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
288 break;
289 #endif
290 default:
291 return -1;
292 }
293 ct_str++;
294 *pct_str = ct_str;
295 return 0;
296 }
297
298 /* test if a constant matches the constraint */
299 static int tcg_target_const_match(tcg_target_long val,
300 const TCGArgConstraint *arg_ct)
301 {
302 int ct;
303
304 ct = arg_ct->ct;
305 if (ct & TCG_CT_CONST)
306 return 1;
307 return 0;
308 }
309
310 #define OPCD(opc) ((opc)<<26)
311 #define XO31(opc) (OPCD(31)|((opc)<<1))
312 #define XO19(opc) (OPCD(19)|((opc)<<1))
313
314 #define B OPCD(18)
315 #define BC OPCD(16)
316 #define LBZ OPCD(34)
317 #define LHZ OPCD(40)
318 #define LHA OPCD(42)
319 #define LWZ OPCD(32)
320 #define STB OPCD(38)
321 #define STH OPCD(44)
322 #define STW OPCD(36)
323
324 #define ADDIC OPCD(12)
325 #define ADDI OPCD(14)
326 #define ADDIS OPCD(15)
327 #define ORI OPCD(24)
328 #define ORIS OPCD(25)
329 #define XORI OPCD(26)
330 #define XORIS OPCD(27)
331 #define ANDI OPCD(28)
332 #define ANDIS OPCD(29)
333 #define MULLI OPCD( 7)
334 #define CMPLI OPCD(10)
335 #define CMPI OPCD(11)
336 #define SUBFIC OPCD( 8)
337
338 #define LWZU OPCD(33)
339 #define STWU OPCD(37)
340
341 #define RLWIMI OPCD(20)
342 #define RLWINM OPCD(21)
343 #define RLWNM OPCD(23)
344
345 #define BCLR XO19( 16)
346 #define BCCTR XO19(528)
347 #define CRAND XO19(257)
348 #define CRANDC XO19(129)
349 #define CRNAND XO19(225)
350 #define CROR XO19(449)
351 #define CRNOR XO19( 33)
352
353 #define EXTSB XO31(954)
354 #define EXTSH XO31(922)
355 #define ADD XO31(266)
356 #define ADDE XO31(138)
357 #define ADDC XO31( 10)
358 #define AND XO31( 28)
359 #define SUBF XO31( 40)
360 #define SUBFC XO31( 8)
361 #define SUBFE XO31(136)
362 #define OR XO31(444)
363 #define XOR XO31(316)
364 #define MULLW XO31(235)
365 #define MULHWU XO31( 11)
366 #define DIVW XO31(491)
367 #define DIVWU XO31(459)
368 #define CMP XO31( 0)
369 #define CMPL XO31( 32)
370 #define LHBRX XO31(790)
371 #define LWBRX XO31(534)
372 #define STHBRX XO31(918)
373 #define STWBRX XO31(662)
374 #define MFSPR XO31(339)
375 #define MTSPR XO31(467)
376 #define SRAWI XO31(824)
377 #define NEG XO31(104)
378 #define MFCR XO31( 19)
379 #define CNTLZW XO31( 26)
380 #define NOR XO31(124)
381 #define ANDC XO31( 60)
382 #define ORC XO31(412)
383 #define EQV XO31(284)
384 #define NAND XO31(476)
385 #define ISEL XO31( 15)
386
387 #define LBZX XO31( 87)
388 #define LHZX XO31(279)
389 #define LHAX XO31(343)
390 #define LWZX XO31( 23)
391 #define STBX XO31(215)
392 #define STHX XO31(407)
393 #define STWX XO31(151)
394
395 #define SPR(a,b) ((((a)<<5)|(b))<<11)
396 #define LR SPR(8, 0)
397 #define CTR SPR(9, 0)
398
399 #define SLW XO31( 24)
400 #define SRW XO31(536)
401 #define SRAW XO31(792)
402
403 #define TW XO31(4)
404 #define TRAP (TW | TO (31))
405
406 #define RT(r) ((r)<<21)
407 #define RS(r) ((r)<<21)
408 #define RA(r) ((r)<<16)
409 #define RB(r) ((r)<<11)
410 #define TO(t) ((t)<<21)
411 #define SH(s) ((s)<<11)
412 #define MB(b) ((b)<<6)
413 #define ME(e) ((e)<<1)
414 #define BO(o) ((o)<<21)
415
416 #define LK 1
417
418 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
419 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
420
421 #define BF(n) ((n)<<23)
422 #define BI(n, c) (((c)+((n)*4))<<16)
423 #define BT(n, c) (((c)+((n)*4))<<21)
424 #define BA(n, c) (((c)+((n)*4))<<16)
425 #define BB(n, c) (((c)+((n)*4))<<11)
426
427 #define BO_COND_TRUE BO (12)
428 #define BO_COND_FALSE BO (4)
429 #define BO_ALWAYS BO (20)
430
431 enum {
432 CR_LT,
433 CR_GT,
434 CR_EQ,
435 CR_SO
436 };
437
438 static const uint32_t tcg_to_bc[] = {
439 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
440 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
441 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
442 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
443 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
444 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
445 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
446 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
447 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
448 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
449 };
450
451 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
452 {
453 tcg_out32 (s, OR | SAB (arg, ret, arg));
454 }
455
456 static void tcg_out_movi(TCGContext *s, TCGType type,
457 TCGReg ret, tcg_target_long arg)
458 {
459 if (arg == (int16_t) arg)
460 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
461 else {
462 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
463 if (arg & 0xffff)
464 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
465 }
466 }
467
468 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
469 int offset, int op1, int op2)
470 {
471 if (offset == (int16_t) offset)
472 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
473 else {
474 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
475 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
476 }
477 }
478
479 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
480 {
481 tcg_target_long disp;
482
483 disp = target - (tcg_target_long) s->code_ptr;
484 if ((disp << 6) >> 6 == disp)
485 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
486 else {
487 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
488 tcg_out32 (s, MTSPR | RS (0) | CTR);
489 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
490 }
491 }
492
493 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
494 {
495 #ifdef _CALL_AIX
496 int reg;
497
498 if (const_arg) {
499 reg = 2;
500 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
501 }
502 else reg = arg;
503
504 tcg_out32 (s, LWZ | RT (0) | RA (reg));
505 tcg_out32 (s, MTSPR | RA (0) | CTR);
506 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
507 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
508 #else
509 if (const_arg) {
510 tcg_out_b (s, LK, arg);
511 }
512 else {
513 tcg_out32 (s, MTSPR | RS (arg) | LR);
514 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
515 }
516 #endif
517 }
518
519 #if defined(CONFIG_SOFTMMU)
520
521 static void add_qemu_ldst_label (TCGContext *s,
522 int is_ld,
523 int opc,
524 int data_reg,
525 int data_reg2,
526 int addrlo_reg,
527 int addrhi_reg,
528 int mem_index,
529 uint8_t *raddr,
530 uint8_t *label_ptr)
531 {
532 int idx;
533 TCGLabelQemuLdst *label;
534
535 if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) {
536 tcg_abort();
537 }
538
539 idx = s->nb_qemu_ldst_labels++;
540 label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[idx];
541 label->is_ld = is_ld;
542 label->opc = opc;
543 label->datalo_reg = data_reg;
544 label->datahi_reg = data_reg2;
545 label->addrlo_reg = addrlo_reg;
546 label->addrhi_reg = addrhi_reg;
547 label->mem_index = mem_index;
548 label->raddr = raddr;
549 label->label_ptr[0] = label_ptr;
550 }
551
552 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
553 int mmu_idx) */
554 static const void * const qemu_ld_helpers[4] = {
555 helper_ldb_mmu,
556 helper_ldw_mmu,
557 helper_ldl_mmu,
558 helper_ldq_mmu,
559 };
560
561 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
562 uintxx_t val, int mmu_idx) */
563 static const void * const qemu_st_helpers[4] = {
564 helper_stb_mmu,
565 helper_stw_mmu,
566 helper_stl_mmu,
567 helper_stq_mmu,
568 };
569
570 static void *ld_trampolines[4];
571 static void *st_trampolines[4];
572
573 static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2,
574 int addr_reg, int addr_reg2, int s_bits,
575 int offset1, int offset2, uint8_t **label_ptr)
576 {
577 uint16_t retranst;
578
579 tcg_out32 (s, (RLWINM
580 | RA (r0)
581 | RS (addr_reg)
582 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
583 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
584 | ME (31 - CPU_TLB_ENTRY_BITS)
585 )
586 );
587 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
588 tcg_out32 (s, (LWZU
589 | RT (r1)
590 | RA (r0)
591 | offset1
592 )
593 );
594 tcg_out32 (s, (RLWINM
595 | RA (r2)
596 | RS (addr_reg)
597 | SH (0)
598 | MB ((32 - s_bits) & 31)
599 | ME (31 - TARGET_PAGE_BITS)
600 )
601 );
602
603 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
604 #if TARGET_LONG_BITS == 64
605 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
606 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
607 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
608 #endif
609 *label_ptr = s->code_ptr;
610 retranst = ((uint16_t *) s->code_ptr)[1] & ~3;
611 tcg_out32 (s, BC | BI (7, CR_EQ) | retranst | BO_COND_FALSE);
612
613 /* r0 now contains &env->tlb_table[mem_index][index].addr_x */
614 tcg_out32 (s, (LWZ
615 | RT (r0)
616 | RA (r0)
617 | offset2
618 )
619 );
620 /* r0 = env->tlb_table[mem_index][index].addend */
621 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
622 /* r0 = env->tlb_table[mem_index][index].addend + addr */
623
624 }
625 #endif
626
627 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
628 {
629 int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
630 #ifdef CONFIG_SOFTMMU
631 int mem_index, s_bits, r2, addr_reg2;
632 uint8_t *label_ptr;
633 #endif
634
635 data_reg = *args++;
636 if (opc == 3)
637 data_reg2 = *args++;
638 else
639 data_reg2 = 0;
640 addr_reg = *args++;
641
642 #ifdef CONFIG_SOFTMMU
643 #if TARGET_LONG_BITS == 64
644 addr_reg2 = *args++;
645 #else
646 addr_reg2 = 0;
647 #endif
648 mem_index = *args;
649 s_bits = opc & 3;
650 r0 = 3;
651 r1 = 4;
652 r2 = 0;
653 rbase = 0;
654
655 tcg_out_tlb_check (
656 s, r0, r1, r2, addr_reg, addr_reg2, s_bits,
657 offsetof (CPUArchState, tlb_table[mem_index][0].addr_read),
658 offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_read),
659 &label_ptr
660 );
661 #else /* !CONFIG_SOFTMMU */
662 r0 = addr_reg;
663 r1 = 3;
664 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
665 #endif
666
667 #ifdef TARGET_WORDS_BIGENDIAN
668 bswap = 0;
669 #else
670 bswap = 1;
671 #endif
672
673 switch (opc) {
674 default:
675 case 0:
676 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
677 break;
678 case 0|4:
679 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
680 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
681 break;
682 case 1:
683 if (bswap)
684 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
685 else
686 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
687 break;
688 case 1|4:
689 if (bswap) {
690 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
691 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
692 }
693 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
694 break;
695 case 2:
696 if (bswap)
697 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
698 else
699 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
700 break;
701 case 3:
702 if (bswap) {
703 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
704 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
705 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
706 }
707 else {
708 #ifdef CONFIG_USE_GUEST_BASE
709 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
710 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
711 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
712 #else
713 if (r0 == data_reg2) {
714 tcg_out32 (s, LWZ | RT (0) | RA (r0));
715 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
716 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
717 }
718 else {
719 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
720 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
721 }
722 #endif
723 }
724 break;
725 }
726 #ifdef CONFIG_SOFTMMU
727 add_qemu_ldst_label (s,
728 1,
729 opc,
730 data_reg,
731 data_reg2,
732 addr_reg,
733 addr_reg2,
734 mem_index,
735 s->code_ptr,
736 label_ptr);
737 #endif
738 }
739
740 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
741 {
742 int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
743 #ifdef CONFIG_SOFTMMU
744 int mem_index, r2, addr_reg2;
745 uint8_t *label_ptr;
746 #endif
747
748 data_reg = *args++;
749 if (opc == 3)
750 data_reg2 = *args++;
751 else
752 data_reg2 = 0;
753 addr_reg = *args++;
754
755 #ifdef CONFIG_SOFTMMU
756 #if TARGET_LONG_BITS == 64
757 addr_reg2 = *args++;
758 #else
759 addr_reg2 = 0;
760 #endif
761 mem_index = *args;
762 r0 = 3;
763 r1 = 4;
764 r2 = 0;
765 rbase = 0;
766
767 tcg_out_tlb_check (
768 s, r0, r1, r2, addr_reg, addr_reg2, opc & 3,
769 offsetof (CPUArchState, tlb_table[mem_index][0].addr_write),
770 offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_write),
771 &label_ptr
772 );
773 #else /* !CONFIG_SOFTMMU */
774 r0 = addr_reg;
775 r1 = 3;
776 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
777 #endif
778
779 #ifdef TARGET_WORDS_BIGENDIAN
780 bswap = 0;
781 #else
782 bswap = 1;
783 #endif
784 switch (opc) {
785 case 0:
786 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
787 break;
788 case 1:
789 if (bswap)
790 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
791 else
792 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
793 break;
794 case 2:
795 if (bswap)
796 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
797 else
798 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
799 break;
800 case 3:
801 if (bswap) {
802 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
803 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
804 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
805 }
806 else {
807 #ifdef CONFIG_USE_GUEST_BASE
808 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
809 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
810 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
811 #else
812 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
813 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
814 #endif
815 }
816 break;
817 }
818
819 #ifdef CONFIG_SOFTMMU
820 add_qemu_ldst_label (s,
821 0,
822 opc,
823 data_reg,
824 data_reg2,
825 addr_reg,
826 addr_reg2,
827 mem_index,
828 s->code_ptr,
829 label_ptr);
830 #endif
831 }
832
833 #if defined(CONFIG_SOFTMMU)
834 static void tcg_out_qemu_ld_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
835 {
836 int s_bits;
837 int ir;
838 int opc = label->opc;
839 int mem_index = label->mem_index;
840 int data_reg = label->datalo_reg;
841 int data_reg2 = label->datahi_reg;
842 int addr_reg = label->addrlo_reg;
843 uint8_t *raddr = label->raddr;
844 uint8_t **label_ptr = &label->label_ptr[0];
845
846 s_bits = opc & 3;
847
848 /* resolve label address */
849 reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr);
850
851 /* slow path */
852 ir = 4;
853 #if TARGET_LONG_BITS == 32
854 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
855 #else
856 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
857 ir |= 1;
858 #endif
859 tcg_out_mov (s, TCG_TYPE_I32, ir++, label->addrhi_reg);
860 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
861 #endif
862 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
863 tcg_out_call (s, (tcg_target_long) ld_trampolines[s_bits], 1);
864 tcg_out32 (s, (tcg_target_long) raddr);
865 switch (opc) {
866 case 0|4:
867 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
868 break;
869 case 1|4:
870 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
871 break;
872 case 0:
873 case 1:
874 case 2:
875 if (data_reg != 3)
876 tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3);
877 break;
878 case 3:
879 if (data_reg == 3) {
880 if (data_reg2 == 4) {
881 tcg_out_mov (s, TCG_TYPE_I32, 0, 4);
882 tcg_out_mov (s, TCG_TYPE_I32, 4, 3);
883 tcg_out_mov (s, TCG_TYPE_I32, 3, 0);
884 }
885 else {
886 tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
887 tcg_out_mov (s, TCG_TYPE_I32, 3, 4);
888 }
889 }
890 else {
891 if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4);
892 if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
893 }
894 break;
895 }
896 /* Jump to the code corresponding to next IR of qemu_st */
897 tcg_out_b (s, 0, (tcg_target_long) raddr);
898 }
899
900 static void tcg_out_qemu_st_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
901 {
902 int ir;
903 int opc = label->opc;
904 int mem_index = label->mem_index;
905 int data_reg = label->datalo_reg;
906 int data_reg2 = label->datahi_reg;
907 int addr_reg = label->addrlo_reg;
908 uint8_t *raddr = label->raddr;
909 uint8_t **label_ptr = &label->label_ptr[0];
910
911 /* resolve label address */
912 reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr);
913
914 /* slow path */
915 ir = 4;
916 #if TARGET_LONG_BITS == 32
917 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
918 #else
919 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
920 ir |= 1;
921 #endif
922 tcg_out_mov (s, TCG_TYPE_I32, ir++, label->addrhi_reg);
923 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
924 #endif
925
926 switch (opc) {
927 case 0:
928 tcg_out32 (s, (RLWINM
929 | RA (ir)
930 | RS (data_reg)
931 | SH (0)
932 | MB (24)
933 | ME (31)));
934 break;
935 case 1:
936 tcg_out32 (s, (RLWINM
937 | RA (ir)
938 | RS (data_reg)
939 | SH (0)
940 | MB (16)
941 | ME (31)));
942 break;
943 case 2:
944 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
945 break;
946 case 3:
947 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
948 ir |= 1;
949 #endif
950 tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
951 tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
952 break;
953 }
954 ir++;
955
956 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
957 tcg_out_call (s, (tcg_target_long) st_trampolines[opc], 1);
958 tcg_out32 (s, (tcg_target_long) raddr);
959 tcg_out_b (s, 0, (tcg_target_long) raddr);
960 }
961
962 void tcg_out_tb_finalize(TCGContext *s)
963 {
964 int i;
965 TCGLabelQemuLdst *label;
966
967 /* qemu_ld/st slow paths */
968 for (i = 0; i < s->nb_qemu_ldst_labels; i++) {
969 label = (TCGLabelQemuLdst *) &s->qemu_ldst_labels[i];
970 if (label->is_ld) {
971 tcg_out_qemu_ld_slow_path (s, label);
972 }
973 else {
974 tcg_out_qemu_st_slow_path (s, label);
975 }
976 }
977 }
978 #endif
979
980 #ifdef CONFIG_SOFTMMU
981 static void emit_ldst_trampoline (TCGContext *s, const void *ptr)
982 {
983 tcg_out32 (s, MFSPR | RT (3) | LR);
984 tcg_out32 (s, ADDI | RT (3) | RA (3) | 4);
985 tcg_out32 (s, MTSPR | RS (3) | LR);
986 tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
987 tcg_out_b (s, 0, (tcg_target_long) ptr);
988 }
989 #endif
990
991 static void tcg_target_qemu_prologue (TCGContext *s)
992 {
993 int i, frame_size;
994
995 frame_size = 0
996 + LINKAGE_AREA_SIZE
997 + TCG_STATIC_CALL_ARGS_SIZE
998 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
999 + CPU_TEMP_BUF_NLONGS * sizeof(long)
1000 ;
1001 frame_size = (frame_size + 15) & ~15;
1002
1003 tcg_set_frame(s, TCG_REG_CALL_STACK, frame_size
1004 - CPU_TEMP_BUF_NLONGS * sizeof(long),
1005 CPU_TEMP_BUF_NLONGS * sizeof(long));
1006
1007 #ifdef _CALL_AIX
1008 {
1009 uint32_t addr;
1010
1011 /* First emit adhoc function descriptor */
1012 addr = (uint32_t) s->code_ptr + 12;
1013 tcg_out32 (s, addr); /* entry point */
1014 s->code_ptr += 8; /* skip TOC and environment pointer */
1015 }
1016 #endif
1017 tcg_out32 (s, MFSPR | RT (0) | LR);
1018 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
1019 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
1020 tcg_out32 (s, (STW
1021 | RS (tcg_target_callee_save_regs[i])
1022 | RA (1)
1023 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
1024 )
1025 );
1026 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
1027
1028 #ifdef CONFIG_USE_GUEST_BASE
1029 if (GUEST_BASE) {
1030 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
1031 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1032 }
1033 #endif
1034
1035 tcg_out_mov (s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1036 tcg_out32 (s, MTSPR | RS (tcg_target_call_iarg_regs[1]) | CTR);
1037 tcg_out32 (s, BCCTR | BO_ALWAYS);
1038 tb_ret_addr = s->code_ptr;
1039
1040 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
1041 tcg_out32 (s, (LWZ
1042 | RT (tcg_target_callee_save_regs[i])
1043 | RA (1)
1044 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
1045 )
1046 );
1047 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
1048 tcg_out32 (s, MTSPR | RS (0) | LR);
1049 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
1050 tcg_out32 (s, BCLR | BO_ALWAYS);
1051
1052 #ifdef CONFIG_SOFTMMU
1053 for (i = 0; i < 4; ++i) {
1054 ld_trampolines[i] = s->code_ptr;
1055 emit_ldst_trampoline (s, qemu_ld_helpers[i]);
1056
1057 st_trampolines[i] = s->code_ptr;
1058 emit_ldst_trampoline (s, qemu_st_helpers[i]);
1059 }
1060 #endif
1061 }
1062
1063 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
1064 intptr_t arg2)
1065 {
1066 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
1067 }
1068
1069 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
1070 intptr_t arg2)
1071 {
1072 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
1073 }
1074
1075 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
1076 {
1077 if (!si && rt == ra)
1078 return;
1079
1080 if (si == (int16_t) si)
1081 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
1082 else {
1083 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
1084 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
1085 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
1086 }
1087 }
1088
1089 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1090 int const_arg2, int cr)
1091 {
1092 int imm;
1093 uint32_t op;
1094
1095 switch (cond) {
1096 case TCG_COND_EQ:
1097 case TCG_COND_NE:
1098 if (const_arg2) {
1099 if ((int16_t) arg2 == arg2) {
1100 op = CMPI;
1101 imm = 1;
1102 break;
1103 }
1104 else if ((uint16_t) arg2 == arg2) {
1105 op = CMPLI;
1106 imm = 1;
1107 break;
1108 }
1109 }
1110 op = CMPL;
1111 imm = 0;
1112 break;
1113
1114 case TCG_COND_LT:
1115 case TCG_COND_GE:
1116 case TCG_COND_LE:
1117 case TCG_COND_GT:
1118 if (const_arg2) {
1119 if ((int16_t) arg2 == arg2) {
1120 op = CMPI;
1121 imm = 1;
1122 break;
1123 }
1124 }
1125 op = CMP;
1126 imm = 0;
1127 break;
1128
1129 case TCG_COND_LTU:
1130 case TCG_COND_GEU:
1131 case TCG_COND_LEU:
1132 case TCG_COND_GTU:
1133 if (const_arg2) {
1134 if ((uint16_t) arg2 == arg2) {
1135 op = CMPLI;
1136 imm = 1;
1137 break;
1138 }
1139 }
1140 op = CMPL;
1141 imm = 0;
1142 break;
1143
1144 default:
1145 tcg_abort ();
1146 }
1147 op |= BF (cr);
1148
1149 if (imm)
1150 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1151 else {
1152 if (const_arg2) {
1153 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1154 tcg_out32 (s, op | RA (arg1) | RB (0));
1155 }
1156 else
1157 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1158 }
1159
1160 }
1161
1162 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1163 {
1164 TCGLabel *l = &s->labels[label_index];
1165
1166 if (l->has_value)
1167 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1168 else {
1169 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1170
1171 /* Thanks to Andrzej Zaborowski */
1172 tcg_out32 (s, bc | (val & 0xfffc));
1173 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1174 }
1175 }
1176
1177 static void tcg_out_cr7eq_from_cond (TCGContext *s, const TCGArg *args,
1178 const int *const_args)
1179 {
1180 TCGCond cond = args[4];
1181 int op;
1182 struct { int bit1; int bit2; int cond2; } bits[] = {
1183 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1184 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1185 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1186 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1187 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1188 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1189 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1190 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1191 }, *b = &bits[cond];
1192
1193 switch (cond) {
1194 case TCG_COND_EQ:
1195 case TCG_COND_NE:
1196 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1197 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1198 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1199 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1200 break;
1201 case TCG_COND_LT:
1202 case TCG_COND_LE:
1203 case TCG_COND_GT:
1204 case TCG_COND_GE:
1205 case TCG_COND_LTU:
1206 case TCG_COND_LEU:
1207 case TCG_COND_GTU:
1208 case TCG_COND_GEU:
1209 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1210 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1211 tcg_out_cmp (s, tcg_unsigned_cond (cond), args[0], args[2],
1212 const_args[2], 7);
1213 tcg_out32 (s, op | BT (7, CR_EQ) | BA (5, CR_EQ) | BB (7, b->bit2));
1214 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1215 break;
1216 default:
1217 tcg_abort();
1218 }
1219 }
1220
1221 static void tcg_out_setcond (TCGContext *s, TCGCond cond, TCGArg arg0,
1222 TCGArg arg1, TCGArg arg2, int const_arg2)
1223 {
1224 int crop, sh, arg;
1225
1226 switch (cond) {
1227 case TCG_COND_EQ:
1228 if (const_arg2) {
1229 if (!arg2) {
1230 arg = arg1;
1231 }
1232 else {
1233 arg = 0;
1234 if ((uint16_t) arg2 == arg2) {
1235 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1236 }
1237 else {
1238 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1239 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1240 }
1241 }
1242 }
1243 else {
1244 arg = 0;
1245 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1246 }
1247 tcg_out32 (s, CNTLZW | RS (arg) | RA (0));
1248 tcg_out32 (s, (RLWINM
1249 | RA (arg0)
1250 | RS (0)
1251 | SH (27)
1252 | MB (5)
1253 | ME (31)
1254 )
1255 );
1256 break;
1257
1258 case TCG_COND_NE:
1259 if (const_arg2) {
1260 if (!arg2) {
1261 arg = arg1;
1262 }
1263 else {
1264 arg = 0;
1265 if ((uint16_t) arg2 == arg2) {
1266 tcg_out32 (s, XORI | RS (arg1) | RA (0) | arg2);
1267 }
1268 else {
1269 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1270 tcg_out32 (s, XOR | SAB (arg1, 0, 0));
1271 }
1272 }
1273 }
1274 else {
1275 arg = 0;
1276 tcg_out32 (s, XOR | SAB (arg1, 0, arg2));
1277 }
1278
1279 if (arg == arg1 && arg1 == arg0) {
1280 tcg_out32 (s, ADDIC | RT (0) | RA (arg) | 0xffff);
1281 tcg_out32 (s, SUBFE | TAB (arg0, 0, arg));
1282 }
1283 else {
1284 tcg_out32 (s, ADDIC | RT (arg0) | RA (arg) | 0xffff);
1285 tcg_out32 (s, SUBFE | TAB (arg0, arg0, arg));
1286 }
1287 break;
1288
1289 case TCG_COND_GT:
1290 case TCG_COND_GTU:
1291 sh = 30;
1292 crop = 0;
1293 goto crtest;
1294
1295 case TCG_COND_LT:
1296 case TCG_COND_LTU:
1297 sh = 29;
1298 crop = 0;
1299 goto crtest;
1300
1301 case TCG_COND_GE:
1302 case TCG_COND_GEU:
1303 sh = 31;
1304 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_LT) | BB (7, CR_LT);
1305 goto crtest;
1306
1307 case TCG_COND_LE:
1308 case TCG_COND_LEU:
1309 sh = 31;
1310 crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
1311 crtest:
1312 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1313 if (crop) tcg_out32 (s, crop);
1314 tcg_out32 (s, MFCR | RT (0));
1315 tcg_out32 (s, (RLWINM
1316 | RA (arg0)
1317 | RS (0)
1318 | SH (sh)
1319 | MB (31)
1320 | ME (31)
1321 )
1322 );
1323 break;
1324
1325 default:
1326 tcg_abort ();
1327 }
1328 }
1329
1330 static void tcg_out_setcond2 (TCGContext *s, const TCGArg *args,
1331 const int *const_args)
1332 {
1333 tcg_out_cr7eq_from_cond (s, args + 1, const_args + 1);
1334 tcg_out32 (s, MFCR | RT (0));
1335 tcg_out32 (s, (RLWINM
1336 | RA (args[0])
1337 | RS (0)
1338 | SH (31)
1339 | MB (31)
1340 | ME (31)
1341 )
1342 );
1343 }
1344
1345 static void tcg_out_movcond (TCGContext *s, TCGCond cond,
1346 TCGArg dest,
1347 TCGArg c1, TCGArg c2,
1348 TCGArg v1, TCGArg v2,
1349 int const_c2)
1350 {
1351 tcg_out_cmp (s, cond, c1, c2, const_c2, 7);
1352
1353 if (1) {
1354 /* At least here on 7747A bit twiddling hacks are outperformed
1355 by jumpy code (the testing was not scientific) */
1356 if (dest == v2) {
1357 cond = tcg_invert_cond (cond);
1358 v2 = v1;
1359 }
1360 else {
1361 if (dest != v1) {
1362 tcg_out_mov (s, TCG_TYPE_I32, dest, v1);
1363 }
1364 }
1365 /* Branch forward over one insn */
1366 tcg_out32 (s, tcg_to_bc[cond] | 8);
1367 tcg_out_mov (s, TCG_TYPE_I32, dest, v2);
1368 }
1369 else {
1370 /* isel version, "if (1)" above should be replaced once a way
1371 to figure out availability of isel on the underlying
1372 hardware is found */
1373 int tab, bc;
1374
1375 switch (cond) {
1376 case TCG_COND_EQ:
1377 tab = TAB (dest, v1, v2);
1378 bc = CR_EQ;
1379 break;
1380 case TCG_COND_NE:
1381 tab = TAB (dest, v2, v1);
1382 bc = CR_EQ;
1383 break;
1384 case TCG_COND_LTU:
1385 case TCG_COND_LT:
1386 tab = TAB (dest, v1, v2);
1387 bc = CR_LT;
1388 break;
1389 case TCG_COND_GEU:
1390 case TCG_COND_GE:
1391 tab = TAB (dest, v2, v1);
1392 bc = CR_LT;
1393 break;
1394 case TCG_COND_LEU:
1395 case TCG_COND_LE:
1396 tab = TAB (dest, v2, v1);
1397 bc = CR_GT;
1398 break;
1399 case TCG_COND_GTU:
1400 case TCG_COND_GT:
1401 tab = TAB (dest, v1, v2);
1402 bc = CR_GT;
1403 break;
1404 default:
1405 tcg_abort ();
1406 }
1407 tcg_out32 (s, ISEL | tab | ((bc + 28) << 6));
1408 }
1409 }
1410
1411 static void tcg_out_brcond (TCGContext *s, TCGCond cond,
1412 TCGArg arg1, TCGArg arg2, int const_arg2,
1413 int label_index)
1414 {
1415 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1416 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1417 }
1418
1419 /* XXX: we implement it at the target level to avoid having to
1420 handle cross basic blocks temporaries */
1421 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1422 const int *const_args)
1423 {
1424 tcg_out_cr7eq_from_cond (s, args, const_args);
1425 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), args[5]);
1426 }
1427
1428 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1429 {
1430 uint32_t *ptr;
1431 long disp = addr - jmp_addr;
1432 unsigned long patch_size;
1433
1434 ptr = (uint32_t *)jmp_addr;
1435
1436 if ((disp << 6) >> 6 != disp) {
1437 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1438 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1439 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1440 ptr[3] = 0x4e800420; /* brctr */
1441 patch_size = 16;
1442 } else {
1443 /* patch the branch destination */
1444 if (disp != 16) {
1445 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1446 patch_size = 4;
1447 } else {
1448 ptr[0] = 0x60000000; /* nop */
1449 ptr[1] = 0x60000000;
1450 ptr[2] = 0x60000000;
1451 ptr[3] = 0x60000000;
1452 patch_size = 16;
1453 }
1454 }
1455 /* flush icache */
1456 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1457 }
1458
1459 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1460 const int *const_args)
1461 {
1462 switch (opc) {
1463 case INDEX_op_exit_tb:
1464 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1465 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1466 break;
1467 case INDEX_op_goto_tb:
1468 if (s->tb_jmp_offset) {
1469 /* direct jump method */
1470
1471 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1472 s->code_ptr += 16;
1473 }
1474 else {
1475 tcg_abort ();
1476 }
1477 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1478 break;
1479 case INDEX_op_br:
1480 {
1481 TCGLabel *l = &s->labels[args[0]];
1482
1483 if (l->has_value) {
1484 tcg_out_b (s, 0, l->u.value);
1485 }
1486 else {
1487 uint32_t val = *(uint32_t *) s->code_ptr;
1488
1489 /* Thanks to Andrzej Zaborowski */
1490 tcg_out32 (s, B | (val & 0x3fffffc));
1491 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1492 }
1493 }
1494 break;
1495 case INDEX_op_call:
1496 tcg_out_call (s, args[0], const_args[0]);
1497 break;
1498 case INDEX_op_movi_i32:
1499 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1500 break;
1501 case INDEX_op_ld8u_i32:
1502 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1503 break;
1504 case INDEX_op_ld8s_i32:
1505 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1506 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1507 break;
1508 case INDEX_op_ld16u_i32:
1509 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1510 break;
1511 case INDEX_op_ld16s_i32:
1512 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1513 break;
1514 case INDEX_op_ld_i32:
1515 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1516 break;
1517 case INDEX_op_st8_i32:
1518 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1519 break;
1520 case INDEX_op_st16_i32:
1521 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1522 break;
1523 case INDEX_op_st_i32:
1524 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1525 break;
1526
1527 case INDEX_op_add_i32:
1528 if (const_args[2])
1529 ppc_addi (s, args[0], args[1], args[2]);
1530 else
1531 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1532 break;
1533 case INDEX_op_sub_i32:
1534 if (const_args[2])
1535 ppc_addi (s, args[0], args[1], -args[2]);
1536 else
1537 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1538 break;
1539
1540 case INDEX_op_and_i32:
1541 if (const_args[2]) {
1542 uint32_t c;
1543
1544 c = args[2];
1545
1546 if (!c) {
1547 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1548 break;
1549 }
1550 #ifdef __PPU__
1551 uint32_t t, n;
1552 int mb, me;
1553
1554 n = c ^ -(c & 1);
1555 t = n + (n & -n);
1556
1557 if ((t & (t - 1)) == 0) {
1558 int lzc, tzc;
1559
1560 if ((c & 0x80000001) == 0x80000001) {
1561 lzc = clz32 (n);
1562 tzc = ctz32 (n);
1563
1564 mb = 32 - tzc;
1565 me = lzc - 1;
1566 }
1567 else {
1568 lzc = clz32 (c);
1569 tzc = ctz32 (c);
1570
1571 mb = lzc;
1572 me = 31 - tzc;
1573 }
1574
1575 tcg_out32 (s, (RLWINM
1576 | RA (args[0])
1577 | RS (args[1])
1578 | SH (0)
1579 | MB (mb)
1580 | ME (me)
1581 )
1582 );
1583 }
1584 else
1585 #endif /* !__PPU__ */
1586 {
1587 if ((c & 0xffff) == c)
1588 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1589 else if ((c & 0xffff0000) == c)
1590 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1591 | ((c >> 16) & 0xffff));
1592 else {
1593 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1594 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1595 }
1596 }
1597 }
1598 else
1599 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1600 break;
1601 case INDEX_op_or_i32:
1602 if (const_args[2]) {
1603 if (args[2] & 0xffff) {
1604 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1605 | (args[2] & 0xffff));
1606 if (args[2] >> 16)
1607 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1608 | ((args[2] >> 16) & 0xffff));
1609 }
1610 else {
1611 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1612 | ((args[2] >> 16) & 0xffff));
1613 }
1614 }
1615 else
1616 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1617 break;
1618 case INDEX_op_xor_i32:
1619 if (const_args[2]) {
1620 if ((args[2] & 0xffff) == args[2])
1621 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1622 | (args[2] & 0xffff));
1623 else if ((args[2] & 0xffff0000) == args[2])
1624 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1625 | ((args[2] >> 16) & 0xffff));
1626 else {
1627 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1628 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1629 }
1630 }
1631 else
1632 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1633 break;
1634 case INDEX_op_andc_i32:
1635 tcg_out32 (s, ANDC | SAB (args[1], args[0], args[2]));
1636 break;
1637 case INDEX_op_orc_i32:
1638 tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
1639 break;
1640 case INDEX_op_eqv_i32:
1641 tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
1642 break;
1643 case INDEX_op_nand_i32:
1644 tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
1645 break;
1646 case INDEX_op_nor_i32:
1647 tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
1648 break;
1649
1650 case INDEX_op_mul_i32:
1651 if (const_args[2]) {
1652 if (args[2] == (int16_t) args[2])
1653 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1654 | (args[2] & 0xffff));
1655 else {
1656 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1657 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1658 }
1659 }
1660 else
1661 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1662 break;
1663
1664 case INDEX_op_div_i32:
1665 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1666 break;
1667
1668 case INDEX_op_divu_i32:
1669 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1670 break;
1671
1672 case INDEX_op_mulu2_i32:
1673 if (args[0] == args[2] || args[0] == args[3]) {
1674 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1675 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1676 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1677 }
1678 else {
1679 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1680 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1681 }
1682 break;
1683
1684 case INDEX_op_shl_i32:
1685 if (const_args[2]) {
1686 tcg_out32 (s, (RLWINM
1687 | RA (args[0])
1688 | RS (args[1])
1689 | SH (args[2])
1690 | MB (0)
1691 | ME (31 - args[2])
1692 )
1693 );
1694 }
1695 else
1696 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1697 break;
1698 case INDEX_op_shr_i32:
1699 if (const_args[2]) {
1700 tcg_out32 (s, (RLWINM
1701 | RA (args[0])
1702 | RS (args[1])
1703 | SH (32 - args[2])
1704 | MB (args[2])
1705 | ME (31)
1706 )
1707 );
1708 }
1709 else
1710 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1711 break;
1712 case INDEX_op_sar_i32:
1713 if (const_args[2])
1714 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1715 else
1716 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1717 break;
1718 case INDEX_op_rotl_i32:
1719 {
1720 int op = 0
1721 | RA (args[0])
1722 | RS (args[1])
1723 | MB (0)
1724 | ME (31)
1725 | (const_args[2] ? RLWINM | SH (args[2])
1726 : RLWNM | RB (args[2]))
1727 ;
1728 tcg_out32 (s, op);
1729 }
1730 break;
1731 case INDEX_op_rotr_i32:
1732 if (const_args[2]) {
1733 if (!args[2]) {
1734 tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]);
1735 }
1736 else {
1737 tcg_out32 (s, RLWINM
1738 | RA (args[0])
1739 | RS (args[1])
1740 | SH (32 - args[2])
1741 | MB (0)
1742 | ME (31)
1743 );
1744 }
1745 }
1746 else {
1747 tcg_out32 (s, SUBFIC | RT (0) | RA (args[2]) | 32);
1748 tcg_out32 (s, RLWNM
1749 | RA (args[0])
1750 | RS (args[1])
1751 | RB (0)
1752 | MB (0)
1753 | ME (31)
1754 );
1755 }
1756 break;
1757
1758 case INDEX_op_add2_i32:
1759 if (args[0] == args[3] || args[0] == args[5]) {
1760 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1761 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1762 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1763 }
1764 else {
1765 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1766 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1767 }
1768 break;
1769 case INDEX_op_sub2_i32:
1770 if (args[0] == args[3] || args[0] == args[5]) {
1771 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1772 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1773 tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
1774 }
1775 else {
1776 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1777 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1778 }
1779 break;
1780
1781 case INDEX_op_brcond_i32:
1782 /*
1783 args[0] = r0
1784 args[1] = r1
1785 args[2] = cond
1786 args[3] = r1 is const
1787 args[4] = label_index
1788 */
1789 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1790 break;
1791 case INDEX_op_brcond2_i32:
1792 tcg_out_brcond2(s, args, const_args);
1793 break;
1794
1795 case INDEX_op_neg_i32:
1796 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1797 break;
1798
1799 case INDEX_op_not_i32:
1800 tcg_out32 (s, NOR | SAB (args[1], args[0], args[1]));
1801 break;
1802
1803 case INDEX_op_qemu_ld8u:
1804 tcg_out_qemu_ld(s, args, 0);
1805 break;
1806 case INDEX_op_qemu_ld8s:
1807 tcg_out_qemu_ld(s, args, 0 | 4);
1808 break;
1809 case INDEX_op_qemu_ld16u:
1810 tcg_out_qemu_ld(s, args, 1);
1811 break;
1812 case INDEX_op_qemu_ld16s:
1813 tcg_out_qemu_ld(s, args, 1 | 4);
1814 break;
1815 case INDEX_op_qemu_ld32:
1816 tcg_out_qemu_ld(s, args, 2);
1817 break;
1818 case INDEX_op_qemu_ld64:
1819 tcg_out_qemu_ld(s, args, 3);
1820 break;
1821 case INDEX_op_qemu_st8:
1822 tcg_out_qemu_st(s, args, 0);
1823 break;
1824 case INDEX_op_qemu_st16:
1825 tcg_out_qemu_st(s, args, 1);
1826 break;
1827 case INDEX_op_qemu_st32:
1828 tcg_out_qemu_st(s, args, 2);
1829 break;
1830 case INDEX_op_qemu_st64:
1831 tcg_out_qemu_st(s, args, 3);
1832 break;
1833
1834 case INDEX_op_ext8s_i32:
1835 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1836 break;
1837 case INDEX_op_ext8u_i32:
1838 tcg_out32 (s, RLWINM
1839 | RA (args[0])
1840 | RS (args[1])
1841 | SH (0)
1842 | MB (24)
1843 | ME (31)
1844 );
1845 break;
1846 case INDEX_op_ext16s_i32:
1847 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1848 break;
1849 case INDEX_op_ext16u_i32:
1850 tcg_out32 (s, RLWINM
1851 | RA (args[0])
1852 | RS (args[1])
1853 | SH (0)
1854 | MB (16)
1855 | ME (31)
1856 );
1857 break;
1858
1859 case INDEX_op_setcond_i32:
1860 tcg_out_setcond (s, args[3], args[0], args[1], args[2], const_args[2]);
1861 break;
1862 case INDEX_op_setcond2_i32:
1863 tcg_out_setcond2 (s, args, const_args);
1864 break;
1865
1866 case INDEX_op_bswap16_i32:
1867 /* Stolen from gcc's builtin_bswap16 */
1868
1869 /* a1 = abcd */
1870
1871 /* r0 = (a1 << 8) & 0xff00 # 00d0 */
1872 tcg_out32 (s, RLWINM
1873 | RA (0)
1874 | RS (args[1])
1875 | SH (8)
1876 | MB (16)
1877 | ME (23)
1878 );
1879
1880 /* a0 = rotate_left (a1, 24) & 0xff # 000c */
1881 tcg_out32 (s, RLWINM
1882 | RA (args[0])
1883 | RS (args[1])
1884 | SH (24)
1885 | MB (24)
1886 | ME (31)
1887 );
1888
1889 /* a0 = a0 | r0 # 00dc */
1890 tcg_out32 (s, OR | SAB (0, args[0], args[0]));
1891 break;
1892
1893 case INDEX_op_bswap32_i32:
1894 /* Stolen from gcc's builtin_bswap32 */
1895 {
1896 int a0 = args[0];
1897
1898 /* a1 = args[1] # abcd */
1899
1900 if (a0 == args[1]) {
1901 a0 = 0;
1902 }
1903
1904 /* a0 = rotate_left (a1, 8) # bcda */
1905 tcg_out32 (s, RLWINM
1906 | RA (a0)
1907 | RS (args[1])
1908 | SH (8)
1909 | MB (0)
1910 | ME (31)
1911 );
1912
1913 /* a0 = (a0 & ~0xff000000) | ((a1 << 24) & 0xff000000) # dcda */
1914 tcg_out32 (s, RLWIMI
1915 | RA (a0)
1916 | RS (args[1])
1917 | SH (24)
1918 | MB (0)
1919 | ME (7)
1920 );
1921
1922 /* a0 = (a0 & ~0x0000ff00) | ((a1 << 24) & 0x0000ff00) # dcba */
1923 tcg_out32 (s, RLWIMI
1924 | RA (a0)
1925 | RS (args[1])
1926 | SH (24)
1927 | MB (16)
1928 | ME (23)
1929 );
1930
1931 if (!a0) {
1932 tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
1933 }
1934 }
1935 break;
1936
1937 case INDEX_op_deposit_i32:
1938 tcg_out32 (s, RLWIMI
1939 | RA (args[0])
1940 | RS (args[2])
1941 | SH (args[3])
1942 | MB (32 - args[3] - args[4])
1943 | ME (31 - args[3])
1944 );
1945 break;
1946
1947 case INDEX_op_movcond_i32:
1948 tcg_out_movcond (s, args[5], args[0],
1949 args[1], args[2],
1950 args[3], args[4],
1951 const_args[2]);
1952 break;
1953
1954 default:
1955 tcg_dump_ops (s);
1956 tcg_abort ();
1957 }
1958 }
1959
1960 static const TCGTargetOpDef ppc_op_defs[] = {
1961 { INDEX_op_exit_tb, { } },
1962 { INDEX_op_goto_tb, { } },
1963 { INDEX_op_call, { "ri" } },
1964 { INDEX_op_br, { } },
1965
1966 { INDEX_op_mov_i32, { "r", "r" } },
1967 { INDEX_op_movi_i32, { "r" } },
1968 { INDEX_op_ld8u_i32, { "r", "r" } },
1969 { INDEX_op_ld8s_i32, { "r", "r" } },
1970 { INDEX_op_ld16u_i32, { "r", "r" } },
1971 { INDEX_op_ld16s_i32, { "r", "r" } },
1972 { INDEX_op_ld_i32, { "r", "r" } },
1973 { INDEX_op_st8_i32, { "r", "r" } },
1974 { INDEX_op_st16_i32, { "r", "r" } },
1975 { INDEX_op_st_i32, { "r", "r" } },
1976
1977 { INDEX_op_add_i32, { "r", "r", "ri" } },
1978 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1979 { INDEX_op_div_i32, { "r", "r", "r" } },
1980 { INDEX_op_divu_i32, { "r", "r", "r" } },
1981 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1982 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1983 { INDEX_op_and_i32, { "r", "r", "ri" } },
1984 { INDEX_op_or_i32, { "r", "r", "ri" } },
1985 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1986
1987 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1988 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1989 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1990
1991 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1992 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1993
1994 { INDEX_op_brcond_i32, { "r", "ri" } },
1995
1996 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1997 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1998 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1999
2000 { INDEX_op_neg_i32, { "r", "r" } },
2001 { INDEX_op_not_i32, { "r", "r" } },
2002
2003 { INDEX_op_andc_i32, { "r", "r", "r" } },
2004 { INDEX_op_orc_i32, { "r", "r", "r" } },
2005 { INDEX_op_eqv_i32, { "r", "r", "r" } },
2006 { INDEX_op_nand_i32, { "r", "r", "r" } },
2007 { INDEX_op_nor_i32, { "r", "r", "r" } },
2008
2009 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2010 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2011
2012 { INDEX_op_bswap16_i32, { "r", "r" } },
2013 { INDEX_op_bswap32_i32, { "r", "r" } },
2014
2015 #if TARGET_LONG_BITS == 32
2016 { INDEX_op_qemu_ld8u, { "r", "L" } },
2017 { INDEX_op_qemu_ld8s, { "r", "L" } },
2018 { INDEX_op_qemu_ld16u, { "r", "L" } },
2019 { INDEX_op_qemu_ld16s, { "r", "L" } },
2020 { INDEX_op_qemu_ld32, { "r", "L" } },
2021 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
2022
2023 { INDEX_op_qemu_st8, { "K", "K" } },
2024 { INDEX_op_qemu_st16, { "K", "K" } },
2025 { INDEX_op_qemu_st32, { "K", "K" } },
2026 { INDEX_op_qemu_st64, { "M", "M", "M" } },
2027 #else
2028 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
2029 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
2030 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
2031 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
2032 { INDEX_op_qemu_ld32, { "r", "L", "L" } },
2033 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
2034
2035 { INDEX_op_qemu_st8, { "K", "K", "K" } },
2036 { INDEX_op_qemu_st16, { "K", "K", "K" } },
2037 { INDEX_op_qemu_st32, { "K", "K", "K" } },
2038 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
2039 #endif
2040
2041 { INDEX_op_ext8s_i32, { "r", "r" } },
2042 { INDEX_op_ext8u_i32, { "r", "r" } },
2043 { INDEX_op_ext16s_i32, { "r", "r" } },
2044 { INDEX_op_ext16u_i32, { "r", "r" } },
2045
2046 { INDEX_op_deposit_i32, { "r", "0", "r" } },
2047 { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "r" } },
2048
2049 { -1 },
2050 };
2051
2052 static void tcg_target_init(TCGContext *s)
2053 {
2054 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2055 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2056 (1 << TCG_REG_R0) |
2057 #ifdef TCG_TARGET_CALL_DARWIN
2058 (1 << TCG_REG_R2) |
2059 #endif
2060 (1 << TCG_REG_R3) |
2061 (1 << TCG_REG_R4) |
2062 (1 << TCG_REG_R5) |
2063 (1 << TCG_REG_R6) |
2064 (1 << TCG_REG_R7) |
2065 (1 << TCG_REG_R8) |
2066 (1 << TCG_REG_R9) |
2067 (1 << TCG_REG_R10) |
2068 (1 << TCG_REG_R11) |
2069 (1 << TCG_REG_R12)
2070 );
2071
2072 tcg_regset_clear(s->reserved_regs);
2073 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
2074 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
2075 #ifndef TCG_TARGET_CALL_DARWIN
2076 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
2077 #endif
2078 #ifdef _CALL_SYSV
2079 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
2080 #endif
2081
2082 tcg_add_target_add_op_defs(ppc_op_defs);
2083 }
AR7 emulation for QEMU