include/hw/pci-host/spapr.h

   1 /*
   2  * QEMU SPAPR PCI BUS definitions
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PCI_HOST_SPAPR_H
  21 #define PCI_HOST_SPAPR_H
  22
  23 #include "hw/ppc/spapr.h"
  24 #include "hw/pci/pci.h"
  25 #include "hw/pci/pci_host.h"
  26 #include "hw/ppc/xics.h"
  27
  28 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
  29
  30 #define SPAPR_PCI_HOST_BRIDGE(obj) \
  31     OBJECT_CHECK(SpaprPhbState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
  32
  33 #define SPAPR_PCI_DMA_MAX_WINDOWS    2
  34
  35 typedef struct SpaprPhbState SpaprPhbState;
  36
  37 typedef struct spapr_pci_msi {
  38     uint32_t first_irq;
  39     uint32_t num;
  40 } spapr_pci_msi;
  41
  42 typedef struct spapr_pci_msi_mig {
  43     uint32_t key;
  44     spapr_pci_msi value;
  45 } spapr_pci_msi_mig;
  46
  47 struct SpaprPhbState {
  48     PCIHostState parent_obj;
  49
  50     uint32_t index;
  51     uint64_t buid;
  52     char *dtbusname;
  53     bool dr_enabled;
  54
  55     MemoryRegion memspace, iospace;
  56     hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
  57     uint64_t mem64_win_pciaddr;
  58     hwaddr io_win_addr, io_win_size;
  59     MemoryRegion mem32window, mem64window, iowindow, msiwindow;
  60
  61     uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
  62     hwaddr dma_win_addr, dma_win_size;
  63     AddressSpace iommu_as;
  64     MemoryRegion iommu_root;
  65
  66     struct spapr_pci_lsi {
  67         uint32_t irq;
  68     } lsi_table[PCI_NUM_PINS];
  69
  70     GHashTable *msi;
  71     /* Temporary cache for migration purposes */
  72     int32_t msi_devs_num;
  73     spapr_pci_msi_mig *msi_devs;
  74
  75     QLIST_ENTRY(SpaprPhbState) list;
  76
  77     bool ddw_enabled;
  78     uint64_t page_size_mask;
  79     uint64_t dma64_win_addr;
  80
  81     uint32_t numa_node;
  82
  83     bool pcie_ecs; /* Allow access to PCIe extended config space? */
  84
  85     /* Fields for migration compatibility hacks */
  86     bool pre_2_8_migration;
  87     uint32_t mig_liobn;
  88     hwaddr mig_mem_win_addr, mig_mem_win_size;
  89     hwaddr mig_io_win_addr, mig_io_win_size;
  90     hwaddr nv2_gpa_win_addr;
  91     hwaddr nv2_atsd_win_addr;
  92     struct spapr_phb_pci_nvgpu_config *nvgpus;
  93 };
  94
  95 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
  96 #define SPAPR_PCI_MEM32_WIN_SIZE     \
  97     ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
  98 #define SPAPR_PCI_MEM64_WIN_SIZE     0x10000000000ULL /* 1 TiB */
  99
 100 /* All PCI outbound windows will be within this range */
 101 #define SPAPR_PCI_BASE               (1ULL << 45) /* 32 TiB */
 102 #define SPAPR_PCI_LIMIT              (1ULL << 46) /* 64 TiB */
 103
 104 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
 105                         SPAPR_PCI_MEM64_WIN_SIZE - 1)
 106
 107 #define SPAPR_PCI_IO_WIN_SIZE        0x10000
 108
 109 #define SPAPR_PCI_MSI_WINDOW         0x40000000000ULL
 110
 111 #define SPAPR_PCI_NV2RAM64_WIN_BASE  SPAPR_PCI_LIMIT
 112 #define SPAPR_PCI_NV2RAM64_WIN_SIZE  (2 * TiB) /* For up to 6 GPUs 256GB each */
 113
 114 /* Max number of these GPUsper a physical box */
 115 #define NVGPU_MAX_NUM                6
 116 /* Max number of NVLinks per GPU in any physical box */
 117 #define NVGPU_MAX_LINKS              3
 118
 119 /*
 120  * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB
 121  * which is enough. We do not need DMA for ATSD so we put them at 128TiB.
 122  */
 123 #define SPAPR_PCI_NV2ATSD_WIN_BASE   (128 * TiB)
 124 #define SPAPR_PCI_NV2ATSD_WIN_SIZE   (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
 125                                       64 * KiB)
 126
 127 static inline qemu_irq spapr_phb_lsi_qirq(struct SpaprPhbState *phb, int pin)
 128 {
 129     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
 130
 131     return spapr_qirq(spapr, phb->lsi_table[pin].irq);
 132 }
 133
 134 int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
 135                  uint32_t nr_msis, int *node_offset);
 136
 137 void spapr_pci_rtas_init(void);
 138
 139 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid);
 140 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
 141                               uint32_t config_addr);
 142
 143 /* DRC callbacks */
 144 void spapr_phb_remove_pci_device_cb(DeviceState *dev);
 145 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 146                           void *fdt, int *fdt_start_offset, Error **errp);
 147
 148 /* VFIO EEH hooks */
 149 #ifdef CONFIG_LINUX
 150 bool spapr_phb_eeh_available(SpaprPhbState *sphb);
 151 int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 152                                   unsigned int addr, int option);
 153 int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
 154 int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
 155 int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
 156 void spapr_phb_vfio_reset(DeviceState *qdev);
 157 void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
 158 void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
 159 void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
 160                                  Error **errp);
 161 void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
 162 void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
 163                                         SpaprPhbState *sphb);
 164 #else
 165 static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
 166 {
 167     return false;
 168 }
 169 static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 170                                                 unsigned int addr, int option)
 171 {
 172     return RTAS_OUT_HW_ERROR;
 173 }
 174 static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
 175                                                int *state)
 176 {
 177     return RTAS_OUT_HW_ERROR;
 178 }
 179 static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
 180 {
 181     return RTAS_OUT_HW_ERROR;
 182 }
 183 static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
 184 {
 185     return RTAS_OUT_HW_ERROR;
 186 }
 187 static inline void spapr_phb_vfio_reset(DeviceState *qdev)
 188 {
 189 }
 190 static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
 191 {
 192 }
 193 static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
 194 {
 195 }
 196 static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
 197                                                int bus_off, Error **errp)
 198 {
 199 }
 200 static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
 201                                                    void *fdt)
 202 {
 203 }
 204 static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
 205                                                       int offset,
 206                                                       SpaprPhbState *sphb)
 207 {
 208 }
 209 #endif
 210
 211 void spapr_phb_dma_reset(SpaprPhbState *sphb);
 212
 213 static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb)
 214 {
 215     return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
 216 }
 217
 218 #endif /* PCI_HOST_SPAPR_H */