target/arm/kvm64: Fix error returns
[qemu/ar7.git] / include / hw / i386 / apic_internal.h
blob1209eb483ab6c10d1d2cd0f3ee65ba6cd364942a
1 /*
2 * APIC support - internal interfaces
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #ifndef QEMU_APIC_INTERNAL_H
22 #define QEMU_APIC_INTERNAL_H
24 #include "cpu.h"
25 #include "exec/memory.h"
26 #include "qemu/timer.h"
28 /* APIC Local Vector Table */
29 #define APIC_LVT_TIMER 0
30 #define APIC_LVT_THERMAL 1
31 #define APIC_LVT_PERFORM 2
32 #define APIC_LVT_LINT0 3
33 #define APIC_LVT_LINT1 4
34 #define APIC_LVT_ERROR 5
35 #define APIC_LVT_NB 6
37 /* APIC delivery modes */
38 #define APIC_DM_FIXED 0
39 #define APIC_DM_LOWPRI 1
40 #define APIC_DM_SMI 2
41 #define APIC_DM_NMI 4
42 #define APIC_DM_INIT 5
43 #define APIC_DM_SIPI 6
44 #define APIC_DM_EXTINT 7
46 /* APIC destination mode */
47 #define APIC_DESTMODE_FLAT 0xf
48 #define APIC_DESTMODE_CLUSTER 1
50 #define APIC_TRIGGER_EDGE 0
51 #define APIC_TRIGGER_LEVEL 1
53 #define APIC_VECTOR_MASK 0xff
54 #define APIC_DCR_MASK 0xf
56 #define APIC_LVT_TIMER_SHIFT 17
57 #define APIC_LVT_MASKED_SHIFT 16
58 #define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
59 #define APIC_LVT_REMOTE_IRR_SHIFT 14
60 #define APIC_LVT_INT_POLARITY_SHIFT 13
61 #define APIC_LVT_DELIV_STS_SHIFT 12
62 #define APIC_LVT_DELIV_MOD_SHIFT 8
64 #define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
65 #define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
66 #define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
67 #define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
68 #define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
69 #define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
70 #define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
71 #define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
73 #define APIC_ESR_ILL_ADDRESS_SHIFT 7
74 #define APIC_ESR_RECV_ILL_VECT_SHIFT 6
75 #define APIC_ESR_SEND_ILL_VECT_SHIFT 5
76 #define APIC_ESR_RECV_ACCEPT_SHIFT 3
77 #define APIC_ESR_SEND_ACCEPT_SHIFT 2
78 #define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
80 #define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
81 #define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
82 #define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
83 #define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
84 #define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
85 #define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
86 #define APIC_ESR_SEND_CHECK_SUM 1
88 #define APIC_ICR_DEST_SHIFT 24
89 #define APIC_ICR_DEST_SHORT_SHIFT 18
90 #define APIC_ICR_TRIGGER_MOD_SHIFT 15
91 #define APIC_ICR_LEVEL_SHIFT 14
92 #define APIC_ICR_DELIV_STS_SHIFT 12
93 #define APIC_ICR_DEST_MOD_SHIFT 11
94 #define APIC_ICR_DELIV_MOD_SHIFT 8
96 #define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
97 #define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
98 #define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
99 #define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
100 #define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
101 #define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
103 #define APIC_PR_CLASS_SHIFT 4
104 #define APIC_PR_SUB_CLASS 0xf
106 #define APIC_LOGDEST_XAPIC_SHIFT 4
107 #define APIC_LOGDEST_XAPIC_ID 0xf
109 #define APIC_LOGDEST_X2APIC_SHIFT 16
110 #define APIC_LOGDEST_X2APIC_ID 0xffff
112 #define APIC_SPURIO_FOCUS_SHIFT 9
113 #define APIC_SPURIO_ENABLED_SHIFT 8
115 #define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
116 #define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
118 #define APIC_SV_DIRECTED_IO (1 << 12)
119 #define APIC_SV_ENABLE (1 << 8)
121 #define VAPIC_ENABLE_BIT 0
122 #define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
124 typedef struct APICCommonState APICCommonState;
126 #define TYPE_APIC_COMMON "apic-common"
127 #define APIC_COMMON(obj) \
128 OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
129 #define APIC_COMMON_CLASS(klass) \
130 OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
131 #define APIC_COMMON_GET_CLASS(obj) \
132 OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
134 typedef struct APICCommonClass
136 DeviceClass parent_class;
138 DeviceRealize realize;
139 DeviceUnrealize unrealize;
140 void (*set_base)(APICCommonState *s, uint64_t val);
141 void (*set_tpr)(APICCommonState *s, uint8_t val);
142 uint8_t (*get_tpr)(APICCommonState *s);
143 void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
144 void (*vapic_base_update)(APICCommonState *s);
145 void (*external_nmi)(APICCommonState *s);
146 void (*pre_save)(APICCommonState *s);
147 void (*post_load)(APICCommonState *s);
148 void (*reset)(APICCommonState *s);
149 /* send_msi emulates an APIC bus and its proper place would be in a new
150 * device, but it's convenient to have it here for now.
152 void (*send_msi)(MSIMessage *msi);
153 } APICCommonClass;
155 struct APICCommonState {
156 /*< private >*/
157 DeviceState parent_obj;
158 /*< public >*/
160 MemoryRegion io_memory;
161 X86CPU *cpu;
162 uint32_t apicbase;
163 uint8_t id; /* legacy APIC ID */
164 uint32_t initial_apic_id;
165 uint8_t version;
166 uint8_t arb_id;
167 uint8_t tpr;
168 uint32_t spurious_vec;
169 uint8_t log_dest;
170 uint8_t dest_mode;
171 uint32_t isr[8]; /* in service register */
172 uint32_t tmr[8]; /* trigger mode register */
173 uint32_t irr[8]; /* interrupt request register */
174 uint32_t lvt[APIC_LVT_NB];
175 uint32_t esr; /* error register */
176 uint32_t icr[2];
178 uint32_t divide_conf;
179 int count_shift;
180 uint32_t initial_count;
181 int64_t initial_count_load_time;
182 int64_t next_time;
183 QEMUTimer *timer;
184 int64_t timer_expiry;
185 int sipi_vector;
186 int wait_for_sipi;
188 uint32_t vapic_control;
189 DeviceState *vapic;
190 hwaddr vapic_paddr; /* note: persistence via kvmvapic */
191 bool legacy_instance_id;
194 typedef struct VAPICState {
195 uint8_t tpr;
196 uint8_t isr;
197 uint8_t zero;
198 uint8_t irr;
199 uint8_t enabled;
200 } QEMU_PACKED VAPICState;
202 extern bool apic_report_tpr_access;
204 void apic_report_irq_delivered(int delivered);
205 bool apic_next_timer(APICCommonState *s, int64_t current_time);
206 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
207 void apic_enable_vapic(DeviceState *d, hwaddr paddr);
209 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
210 TPRAccess access);
212 int apic_get_ppr(APICCommonState *s);
214 static inline void apic_set_bit(uint32_t *tab, int index)
216 int i, mask;
217 i = index >> 5;
218 mask = 1 << (index & 0x1f);
219 tab[i] |= mask;
222 static inline int apic_get_bit(uint32_t *tab, int index)
224 int i, mask;
225 i = index >> 5;
226 mask = 1 << (index & 0x1f);
227 return !!(tab[i] & mask);
230 APICCommonClass *apic_get_class(void);
232 #endif /* QEMU_APIC_INTERNAL_H */