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docs: Add docs/devel/testing.rst
[qemu/ar7.git] / hw / pci / pci.c
blobfc25cdecbaf82ece0ac98199c53c1f8ceba6385f
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bridge.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "monitor/monitor.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/loader.h"
34 #include "qemu/error-report.h"
35 #include "qemu/range.h"
36 #include "qmp-commands.h"
37 #include "trace.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qemu/cutils.h"
44
45 //#define DEBUG_PCI
46 #ifdef DEBUG_PCI
47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PCI_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 bool pci_available = true;
53
54 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
55 static char *pcibus_get_dev_path(DeviceState *dev);
56 static char *pcibus_get_fw_dev_path(DeviceState *dev);
57 static void pcibus_reset(BusState *qbus);
58
59 static Property pci_props[] = {
60 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
61 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
62 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
63 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
64 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
65 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
66 QEMU_PCI_CAP_SERR_BITNR, true),
67 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
68 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
69 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
70 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
71 DEFINE_PROP_END_OF_LIST()
72 };
73
74 static const VMStateDescription vmstate_pcibus = {
75 .name = "PCIBUS",
76 .version_id = 1,
77 .minimum_version_id = 1,
78 .fields = (VMStateField[]) {
79 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL),
80 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
81 nirq, 0, vmstate_info_int32,
82 int32_t),
83 VMSTATE_END_OF_LIST()
84 }
85 };
86
87 static void pci_init_bus_master(PCIDevice *pci_dev)
88 {
89 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
90
91 memory_region_init_alias(&pci_dev->bus_master_enable_region,
92 OBJECT(pci_dev), "bus master",
93 dma_as->root, 0, memory_region_size(dma_as->root));
94 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
95 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
96 &pci_dev->bus_master_enable_region);
97 }
98
99 static void pcibus_machine_done(Notifier *notifier, void *data)
100 {
101 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
102 int i;
103
104 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
105 if (bus->devices[i]) {
106 pci_init_bus_master(bus->devices[i]);
107 }
108 }
109 }
110
111 static void pci_bus_realize(BusState *qbus, Error **errp)
112 {
113 PCIBus *bus = PCI_BUS(qbus);
114
115 bus->machine_done.notify = pcibus_machine_done;
116 qemu_add_machine_init_done_notifier(&bus->machine_done);
117
118 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
119 }
120
121 static void pci_bus_unrealize(BusState *qbus, Error **errp)
122 {
123 PCIBus *bus = PCI_BUS(qbus);
124
125 qemu_remove_machine_init_done_notifier(&bus->machine_done);
126
127 vmstate_unregister(NULL, &vmstate_pcibus, bus);
128 }
129
130 static bool pcibus_is_root(PCIBus *bus)
131 {
132 return !bus->parent_dev;
133 }
134
135 static int pcibus_num(PCIBus *bus)
136 {
137 if (pcibus_is_root(bus)) {
138 return 0; /* pci host bridge */
139 }
140 return bus->parent_dev->config[PCI_SECONDARY_BUS];
141 }
142
143 static uint16_t pcibus_numa_node(PCIBus *bus)
144 {
145 return NUMA_NODE_UNASSIGNED;
146 }
147
148 static void pci_bus_class_init(ObjectClass *klass, void *data)
149 {
150 BusClass *k = BUS_CLASS(klass);
151 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
152
153 k->print_dev = pcibus_dev_print;
154 k->get_dev_path = pcibus_get_dev_path;
155 k->get_fw_dev_path = pcibus_get_fw_dev_path;
156 k->realize = pci_bus_realize;
157 k->unrealize = pci_bus_unrealize;
158 k->reset = pcibus_reset;
159
160 pbc->is_root = pcibus_is_root;
161 pbc->bus_num = pcibus_num;
162 pbc->numa_node = pcibus_numa_node;
163 }
164
165 static const TypeInfo pci_bus_info = {
166 .name = TYPE_PCI_BUS,
167 .parent = TYPE_BUS,
168 .instance_size = sizeof(PCIBus),
169 .class_size = sizeof(PCIBusClass),
170 .class_init = pci_bus_class_init,
171 };
172
173 static const TypeInfo pcie_interface_info = {
174 .name = INTERFACE_PCIE_DEVICE,
175 .parent = TYPE_INTERFACE,
176 };
177
178 static const TypeInfo conventional_pci_interface_info = {
179 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE,
180 .parent = TYPE_INTERFACE,
181 };
182
183 static const TypeInfo pcie_bus_info = {
184 .name = TYPE_PCIE_BUS,
185 .parent = TYPE_PCI_BUS,
186 };
187
188 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
189 static void pci_update_mappings(PCIDevice *d);
190 static void pci_irq_handler(void *opaque, int irq_num, int level);
191 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
192 static void pci_del_option_rom(PCIDevice *pdev);
193
194 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
195 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
196
197 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
198
199 int pci_bar(PCIDevice *d, int reg)
200 {
201 uint8_t type;
202
203 if (reg != PCI_ROM_SLOT)
204 return PCI_BASE_ADDRESS_0 + reg * 4;
205
206 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
207 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
208 }
209
210 static inline int pci_irq_state(PCIDevice *d, int irq_num)
211 {
212 return (d->irq_state >> irq_num) & 0x1;
213 }
214
215 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
216 {
217 d->irq_state &= ~(0x1 << irq_num);
218 d->irq_state |= level << irq_num;
219 }
220
221 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
222 {
223 PCIBus *bus;
224 for (;;) {
225 bus = pci_get_bus(pci_dev);
226 irq_num = bus->map_irq(pci_dev, irq_num);
227 if (bus->set_irq)
228 break;
229 pci_dev = bus->parent_dev;
230 }
231 bus->irq_count[irq_num] += change;
232 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
233 }
234
235 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
236 {
237 assert(irq_num >= 0);
238 assert(irq_num < bus->nirq);
239 return !!bus->irq_count[irq_num];
240 }
241
242 /* Update interrupt status bit in config space on interrupt
243 * state change. */
244 static void pci_update_irq_status(PCIDevice *dev)
245 {
246 if (dev->irq_state) {
247 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
248 } else {
249 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
250 }
251 }
252
253 void pci_device_deassert_intx(PCIDevice *dev)
254 {
255 int i;
256 for (i = 0; i < PCI_NUM_PINS; ++i) {
257 pci_irq_handler(dev, i, 0);
258 }
259 }
260
261 static void pci_do_device_reset(PCIDevice *dev)
262 {
263 int r;
264
265 pci_device_deassert_intx(dev);
266 assert(dev->irq_state == 0);
267
268 /* Clear all writable bits */
269 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
270 pci_get_word(dev->wmask + PCI_COMMAND) |
271 pci_get_word(dev->w1cmask + PCI_COMMAND));
272 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
273 pci_get_word(dev->wmask + PCI_STATUS) |
274 pci_get_word(dev->w1cmask + PCI_STATUS));
275 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
276 dev->config[PCI_INTERRUPT_LINE] = 0x0;
277 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
278 PCIIORegion *region = &dev->io_regions[r];
279 if (!region->size) {
280 continue;
281 }
282
283 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
284 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
285 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
286 } else {
287 pci_set_long(dev->config + pci_bar(dev, r), region->type);
288 }
289 }
290 pci_update_mappings(dev);
291
292 msi_reset(dev);
293 msix_reset(dev);
294 }
295
296 /*
297 * This function is called on #RST and FLR.
298 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
299 */
300 void pci_device_reset(PCIDevice *dev)
301 {
302 qdev_reset_all(&dev->qdev);
303 pci_do_device_reset(dev);
304 }
305
306 /*
307 * Trigger pci bus reset under a given bus.
308 * Called via qbus_reset_all on RST# assert, after the devices
309 * have been reset qdev_reset_all-ed already.
310 */
311 static void pcibus_reset(BusState *qbus)
312 {
313 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
314 int i;
315
316 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
317 if (bus->devices[i]) {
318 pci_do_device_reset(bus->devices[i]);
319 }
320 }
321
322 for (i = 0; i < bus->nirq; i++) {
323 assert(bus->irq_count[i] == 0);
324 }
325 }
326
327 static void pci_host_bus_register(DeviceState *host)
328 {
329 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
330
331 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
332 }
333
334 PCIBus *pci_device_root_bus(const PCIDevice *d)
335 {
336 PCIBus *bus = pci_get_bus(d);
337
338 while (!pci_bus_is_root(bus)) {
339 d = bus->parent_dev;
340 assert(d != NULL);
341
342 bus = pci_get_bus(d);
343 }
344
345 return bus;
346 }
347
348 const char *pci_root_bus_path(PCIDevice *dev)
349 {
350 PCIBus *rootbus = pci_device_root_bus(dev);
351 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
352 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
353
354 assert(host_bridge->bus == rootbus);
355
356 if (hc->root_bus_path) {
357 return (*hc->root_bus_path)(host_bridge, rootbus);
358 }
359
360 return rootbus->qbus.name;
361 }
362
363 static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
364 MemoryRegion *address_space_mem,
365 MemoryRegion *address_space_io,
366 uint8_t devfn_min)
367 {
368 assert(PCI_FUNC(devfn_min) == 0);
369 bus->devfn_min = devfn_min;
370 bus->slot_reserved_mask = 0x0;
371 bus->address_space_mem = address_space_mem;
372 bus->address_space_io = address_space_io;
373
374 /* host bridge */
375 QLIST_INIT(&bus->child);
376
377 pci_host_bus_register(parent);
378 }
379
380 bool pci_bus_is_express(PCIBus *bus)
381 {
382 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
383 }
384
385 bool pci_bus_is_root(PCIBus *bus)
386 {
387 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
388 }
389
390 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
391 const char *name,
392 MemoryRegion *address_space_mem,
393 MemoryRegion *address_space_io,
394 uint8_t devfn_min, const char *typename)
395 {
396 qbus_create_inplace(bus, bus_size, typename, parent, name);
397 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
398 devfn_min);
399 }
400
401 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
402 MemoryRegion *address_space_mem,
403 MemoryRegion *address_space_io,
404 uint8_t devfn_min, const char *typename)
405 {
406 PCIBus *bus;
407
408 bus = PCI_BUS(qbus_create(typename, parent, name));
409 pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
410 devfn_min);
411 return bus;
412 }
413
414 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
415 void *irq_opaque, int nirq)
416 {
417 bus->set_irq = set_irq;
418 bus->map_irq = map_irq;
419 bus->irq_opaque = irq_opaque;
420 bus->nirq = nirq;
421 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
422 }
423
424 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
425 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
426 void *irq_opaque,
427 MemoryRegion *address_space_mem,
428 MemoryRegion *address_space_io,
429 uint8_t devfn_min, int nirq,
430 const char *typename)
431 {
432 PCIBus *bus;
433
434 bus = pci_root_bus_new(parent, name, address_space_mem,
435 address_space_io, devfn_min, typename);
436 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
437 return bus;
438 }
439
440 int pci_bus_num(PCIBus *s)
441 {
442 return PCI_BUS_GET_CLASS(s)->bus_num(s);
443 }
444
445 int pci_bus_numa_node(PCIBus *bus)
446 {
447 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
448 }
449
450 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
451 VMStateField *field)
452 {
453 PCIDevice *s = container_of(pv, PCIDevice, config);
454 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
455 uint8_t *config;
456 int i;
457
458 assert(size == pci_config_size(s));
459 config = g_malloc(size);
460
461 qemu_get_buffer(f, config, size);
462 for (i = 0; i < size; ++i) {
463 if ((config[i] ^ s->config[i]) &
464 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
465 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
466 "cmask: %x wmask: %x w1cmask:%x", __func__,
467 i, config[i], s->config[i],
468 s->cmask[i], s->wmask[i], s->w1cmask[i]);
469 g_free(config);
470 return -EINVAL;
471 }
472 }
473 memcpy(s->config, config, size);
474
475 pci_update_mappings(s);
476 if (pc->is_bridge) {
477 PCIBridge *b = PCI_BRIDGE(s);
478 pci_bridge_update_mappings(b);
479 }
480
481 memory_region_set_enabled(&s->bus_master_enable_region,
482 pci_get_word(s->config + PCI_COMMAND)
483 & PCI_COMMAND_MASTER);
484
485 g_free(config);
486 return 0;
487 }
488
489 /* just put buffer */
490 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
491 VMStateField *field, QJSON *vmdesc)
492 {
493 const uint8_t **v = pv;
494 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
495 qemu_put_buffer(f, *v, size);
496
497 return 0;
498 }
499
500 static VMStateInfo vmstate_info_pci_config = {
501 .name = "pci config",
502 .get = get_pci_config_device,
503 .put = put_pci_config_device,
504 };
505
506 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
507 VMStateField *field)
508 {
509 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
510 uint32_t irq_state[PCI_NUM_PINS];
511 int i;
512 for (i = 0; i < PCI_NUM_PINS; ++i) {
513 irq_state[i] = qemu_get_be32(f);
514 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
515 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
516 irq_state[i]);
517 return -EINVAL;
518 }
519 }
520
521 for (i = 0; i < PCI_NUM_PINS; ++i) {
522 pci_set_irq_state(s, i, irq_state[i]);
523 }
524
525 return 0;
526 }
527
528 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
529 VMStateField *field, QJSON *vmdesc)
530 {
531 int i;
532 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
533
534 for (i = 0; i < PCI_NUM_PINS; ++i) {
535 qemu_put_be32(f, pci_irq_state(s, i));
536 }
537
538 return 0;
539 }
540
541 static VMStateInfo vmstate_info_pci_irq_state = {
542 .name = "pci irq state",
543 .get = get_pci_irq_state,
544 .put = put_pci_irq_state,
545 };
546
547 static bool migrate_is_pcie(void *opaque, int version_id)
548 {
549 return pci_is_express((PCIDevice *)opaque);
550 }
551
552 static bool migrate_is_not_pcie(void *opaque, int version_id)
553 {
554 return !pci_is_express((PCIDevice *)opaque);
555 }
556
557 const VMStateDescription vmstate_pci_device = {
558 .name = "PCIDevice",
559 .version_id = 2,
560 .minimum_version_id = 1,
561 .fields = (VMStateField[]) {
562 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
563 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
564 migrate_is_not_pcie,
565 0, vmstate_info_pci_config,
566 PCI_CONFIG_SPACE_SIZE),
567 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
568 migrate_is_pcie,
569 0, vmstate_info_pci_config,
570 PCIE_CONFIG_SPACE_SIZE),
571 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
572 vmstate_info_pci_irq_state,
573 PCI_NUM_PINS * sizeof(int32_t)),
574 VMSTATE_END_OF_LIST()
575 }
576 };
577
578
579 void pci_device_save(PCIDevice *s, QEMUFile *f)
580 {
581 /* Clear interrupt status bit: it is implicit
582 * in irq_state which we are saving.
583 * This makes us compatible with old devices
584 * which never set or clear this bit. */
585 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
586 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
587 /* Restore the interrupt status bit. */
588 pci_update_irq_status(s);
589 }
590
591 int pci_device_load(PCIDevice *s, QEMUFile *f)
592 {
593 int ret;
594 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
595 /* Restore the interrupt status bit. */
596 pci_update_irq_status(s);
597 return ret;
598 }
599
600 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
601 {
602 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
603 pci_default_sub_vendor_id);
604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
605 pci_default_sub_device_id);
606 }
607
608 /*
609 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
610 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
611 */
612 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
613 unsigned int *slotp, unsigned int *funcp)
614 {
615 const char *p;
616 char *e;
617 unsigned long val;
618 unsigned long dom = 0, bus = 0;
619 unsigned int slot = 0;
620 unsigned int func = 0;
621
622 p = addr;
623 val = strtoul(p, &e, 16);
624 if (e == p)
625 return -1;
626 if (*e == ':') {
627 bus = val;
628 p = e + 1;
629 val = strtoul(p, &e, 16);
630 if (e == p)
631 return -1;
632 if (*e == ':') {
633 dom = bus;
634 bus = val;
635 p = e + 1;
636 val = strtoul(p, &e, 16);
637 if (e == p)
638 return -1;
639 }
640 }
641
642 slot = val;
643
644 if (funcp != NULL) {
645 if (*e != '.')
646 return -1;
647
648 p = e + 1;
649 val = strtoul(p, &e, 16);
650 if (e == p)
651 return -1;
652
653 func = val;
654 }
655
656 /* if funcp == NULL func is 0 */
657 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
658 return -1;
659
660 if (*e)
661 return -1;
662
663 *domp = dom;
664 *busp = bus;
665 *slotp = slot;
666 if (funcp != NULL)
667 *funcp = func;
668 return 0;
669 }
670
671 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
672 const char *devaddr)
673 {
674 int dom, bus;
675 unsigned slot;
676
677 if (!root) {
678 fprintf(stderr, "No primary PCI bus\n");
679 return NULL;
680 }
681
682 assert(!root->parent_dev);
683
684 if (!devaddr) {
685 *devfnp = -1;
686 return pci_find_bus_nr(root, 0);
687 }
688
689 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
690 return NULL;
691 }
692
693 if (dom != 0) {
694 fprintf(stderr, "No support for non-zero PCI domains\n");
695 return NULL;
696 }
697
698 *devfnp = PCI_DEVFN(slot, 0);
699 return pci_find_bus_nr(root, bus);
700 }
701
702 static void pci_init_cmask(PCIDevice *dev)
703 {
704 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
705 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
706 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
707 dev->cmask[PCI_REVISION_ID] = 0xff;
708 dev->cmask[PCI_CLASS_PROG] = 0xff;
709 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
710 dev->cmask[PCI_HEADER_TYPE] = 0xff;
711 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
712 }
713
714 static void pci_init_wmask(PCIDevice *dev)
715 {
716 int config_size = pci_config_size(dev);
717
718 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
719 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
720 pci_set_word(dev->wmask + PCI_COMMAND,
721 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
722 PCI_COMMAND_INTX_DISABLE);
723 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
724 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
725 }
726
727 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
728 config_size - PCI_CONFIG_HEADER_SIZE);
729 }
730
731 static void pci_init_w1cmask(PCIDevice *dev)
732 {
733 /*
734 * Note: It's okay to set w1cmask even for readonly bits as
735 * long as their value is hardwired to 0.
736 */
737 pci_set_word(dev->w1cmask + PCI_STATUS,
738 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
739 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
740 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
741 }
742
743 static void pci_init_mask_bridge(PCIDevice *d)
744 {
745 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
746 PCI_SEC_LETENCY_TIMER */
747 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
748
749 /* base and limit */
750 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
751 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
752 pci_set_word(d->wmask + PCI_MEMORY_BASE,
753 PCI_MEMORY_RANGE_MASK & 0xffff);
754 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
755 PCI_MEMORY_RANGE_MASK & 0xffff);
756 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
757 PCI_PREF_RANGE_MASK & 0xffff);
758 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
759 PCI_PREF_RANGE_MASK & 0xffff);
760
761 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
762 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
763
764 /* Supported memory and i/o types */
765 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
766 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
767 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
768 PCI_PREF_RANGE_TYPE_64);
769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
770 PCI_PREF_RANGE_TYPE_64);
771
772 /*
773 * TODO: Bridges default to 10-bit VGA decoding but we currently only
774 * implement 16-bit decoding (no alias support).
775 */
776 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
777 PCI_BRIDGE_CTL_PARITY |
778 PCI_BRIDGE_CTL_SERR |
779 PCI_BRIDGE_CTL_ISA |
780 PCI_BRIDGE_CTL_VGA |
781 PCI_BRIDGE_CTL_VGA_16BIT |
782 PCI_BRIDGE_CTL_MASTER_ABORT |
783 PCI_BRIDGE_CTL_BUS_RESET |
784 PCI_BRIDGE_CTL_FAST_BACK |
785 PCI_BRIDGE_CTL_DISCARD |
786 PCI_BRIDGE_CTL_SEC_DISCARD |
787 PCI_BRIDGE_CTL_DISCARD_SERR);
788 /* Below does not do anything as we never set this bit, put here for
789 * completeness. */
790 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
791 PCI_BRIDGE_CTL_DISCARD_STATUS);
792 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
793 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
794 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
795 PCI_PREF_RANGE_TYPE_MASK);
796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
797 PCI_PREF_RANGE_TYPE_MASK);
798 }
799
800 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
801 {
802 uint8_t slot = PCI_SLOT(dev->devfn);
803 uint8_t func;
804
805 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
806 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
807 }
808
809 /*
810 * multifunction bit is interpreted in two ways as follows.
811 * - all functions must set the bit to 1.
812 * Example: Intel X53
813 * - function 0 must set the bit, but the rest function (> 0)
814 * is allowed to leave the bit to 0.
815 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
816 *
817 * So OS (at least Linux) checks the bit of only function 0,
818 * and doesn't see the bit of function > 0.
819 *
820 * The below check allows both interpretation.
821 */
822 if (PCI_FUNC(dev->devfn)) {
823 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
824 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
825 /* function 0 should set multifunction bit */
826 error_setg(errp, "PCI: single function device can't be populated "
827 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
828 return;
829 }
830 return;
831 }
832
833 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
834 return;
835 }
836 /* function 0 indicates single function, so function > 0 must be NULL */
837 for (func = 1; func < PCI_FUNC_MAX; ++func) {
838 if (bus->devices[PCI_DEVFN(slot, func)]) {
839 error_setg(errp, "PCI: %x.0 indicates single function, "
840 "but %x.%x is already populated.",
841 slot, slot, func);
842 return;
843 }
844 }
845 }
846
847 static void pci_config_alloc(PCIDevice *pci_dev)
848 {
849 int config_size = pci_config_size(pci_dev);
850
851 pci_dev->config = g_malloc0(config_size);
852 pci_dev->cmask = g_malloc0(config_size);
853 pci_dev->wmask = g_malloc0(config_size);
854 pci_dev->w1cmask = g_malloc0(config_size);
855 pci_dev->used = g_malloc0(config_size);
856 }
857
858 static void pci_config_free(PCIDevice *pci_dev)
859 {
860 g_free(pci_dev->config);
861 g_free(pci_dev->cmask);
862 g_free(pci_dev->wmask);
863 g_free(pci_dev->w1cmask);
864 g_free(pci_dev->used);
865 }
866
867 static void do_pci_unregister_device(PCIDevice *pci_dev)
868 {
869 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
870 pci_config_free(pci_dev);
871
872 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
873 memory_region_del_subregion(&pci_dev->bus_master_container_region,
874 &pci_dev->bus_master_enable_region);
875 }
876 address_space_destroy(&pci_dev->bus_master_as);
877 }
878
879 /* Extract PCIReqIDCache into BDF format */
880 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
881 {
882 uint8_t bus_n;
883 uint16_t result;
884
885 switch (cache->type) {
886 case PCI_REQ_ID_BDF:
887 result = pci_get_bdf(cache->dev);
888 break;
889 case PCI_REQ_ID_SECONDARY_BUS:
890 bus_n = pci_dev_bus_num(cache->dev);
891 result = PCI_BUILD_BDF(bus_n, 0);
892 break;
893 default:
894 error_printf("Invalid PCI requester ID cache type: %d\n",
895 cache->type);
896 exit(1);
897 break;
898 }
899
900 return result;
901 }
902
903 /* Parse bridges up to the root complex and return requester ID
904 * cache for specific device. For full PCIe topology, the cache
905 * result would be exactly the same as getting BDF of the device.
906 * However, several tricks are required when system mixed up with
907 * legacy PCI devices and PCIe-to-PCI bridges.
908 *
909 * Here we cache the proxy device (and type) not requester ID since
910 * bus number might change from time to time.
911 */
912 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
913 {
914 PCIDevice *parent;
915 PCIReqIDCache cache = {
916 .dev = dev,
917 .type = PCI_REQ_ID_BDF,
918 };
919
920 while (!pci_bus_is_root(pci_get_bus(dev))) {
921 /* We are under PCI/PCIe bridges */
922 parent = pci_get_bus(dev)->parent_dev;
923 if (pci_is_express(parent)) {
924 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
925 /* When we pass through PCIe-to-PCI/PCIX bridges, we
926 * override the requester ID using secondary bus
927 * number of parent bridge with zeroed devfn
928 * (pcie-to-pci bridge spec chap 2.3). */
929 cache.type = PCI_REQ_ID_SECONDARY_BUS;
930 cache.dev = dev;
931 }
932 } else {
933 /* Legacy PCI, override requester ID with the bridge's
934 * BDF upstream. When the root complex connects to
935 * legacy PCI devices (including buses), it can only
936 * obtain requester ID info from directly attached
937 * devices. If devices are attached under bridges, only
938 * the requester ID of the bridge that is directly
939 * attached to the root complex can be recognized. */
940 cache.type = PCI_REQ_ID_BDF;
941 cache.dev = parent;
942 }
943 dev = parent;
944 }
945
946 return cache;
947 }
948
949 uint16_t pci_requester_id(PCIDevice *dev)
950 {
951 return pci_req_id_cache_extract(&dev->requester_id_cache);
952 }
953
954 static bool pci_bus_devfn_available(PCIBus *bus, int devfn)
955 {
956 return !(bus->devices[devfn]);
957 }
958
959 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn)
960 {
961 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn));
962 }
963
964 /* -1 for devfn means auto assign */
965 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
966 const char *name, int devfn,
967 Error **errp)
968 {
969 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
970 PCIConfigReadFunc *config_read = pc->config_read;
971 PCIConfigWriteFunc *config_write = pc->config_write;
972 Error *local_err = NULL;
973 DeviceState *dev = DEVICE(pci_dev);
974 PCIBus *bus = pci_get_bus(pci_dev);
975
976 /* Only pci bridges can be attached to extra PCI root buses */
977 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
978 error_setg(errp,
979 "PCI: Only PCI/PCIe bridges can be plugged into %s",
980 bus->parent_dev->name);
981 return NULL;
982 }
983
984 if (devfn < 0) {
985 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
986 devfn += PCI_FUNC_MAX) {
987 if (pci_bus_devfn_available(bus, devfn) &&
988 !pci_bus_devfn_reserved(bus, devfn)) {
989 goto found;
990 }
991 }
992 error_setg(errp, "PCI: no slot/function available for %s, all in use "
993 "or reserved", name);
994 return NULL;
995 found: ;
996 } else if (pci_bus_devfn_reserved(bus, devfn)) {
997 error_setg(errp, "PCI: slot %d function %d not available for %s,"
998 " reserved",
999 PCI_SLOT(devfn), PCI_FUNC(devfn), name);
1000 return NULL;
1001 } else if (!pci_bus_devfn_available(bus, devfn)) {
1002 error_setg(errp, "PCI: slot %d function %d not available for %s,"
1003 " in use by %s",
1004 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
1005 bus->devices[devfn]->name);
1006 return NULL;
1007 } else if (dev->hotplugged &&
1008 pci_get_function_0(pci_dev)) {
1009 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
1010 " new func %s cannot be exposed to guest.",
1011 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
1012 pci_get_function_0(pci_dev)->name,
1013 name);
1014
1015 return NULL;
1016 }
1017
1018 pci_dev->devfn = devfn;
1019 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1020 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1021
1022 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1023 "bus master container", UINT64_MAX);
1024 address_space_init(&pci_dev->bus_master_as,
1025 &pci_dev->bus_master_container_region, pci_dev->name);
1026
1027 if (qdev_hotplug) {
1028 pci_init_bus_master(pci_dev);
1029 }
1030 pci_dev->irq_state = 0;
1031 pci_config_alloc(pci_dev);
1032
1033 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1034 pci_config_set_device_id(pci_dev->config, pc->device_id);
1035 pci_config_set_revision(pci_dev->config, pc->revision);
1036 pci_config_set_class(pci_dev->config, pc->class_id);
1037
1038 if (!pc->is_bridge) {
1039 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1040 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1041 pc->subsystem_vendor_id);
1042 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1043 pc->subsystem_id);
1044 } else {
1045 pci_set_default_subsystem_id(pci_dev);
1046 }
1047 } else {
1048 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1049 assert(!pc->subsystem_vendor_id);
1050 assert(!pc->subsystem_id);
1051 }
1052 pci_init_cmask(pci_dev);
1053 pci_init_wmask(pci_dev);
1054 pci_init_w1cmask(pci_dev);
1055 if (pc->is_bridge) {
1056 pci_init_mask_bridge(pci_dev);
1057 }
1058 pci_init_multifunction(bus, pci_dev, &local_err);
1059 if (local_err) {
1060 error_propagate(errp, local_err);
1061 do_pci_unregister_device(pci_dev);
1062 return NULL;
1063 }
1064
1065 if (!config_read)
1066 config_read = pci_default_read_config;
1067 if (!config_write)
1068 config_write = pci_default_write_config;
1069 pci_dev->config_read = config_read;
1070 pci_dev->config_write = config_write;
1071 bus->devices[devfn] = pci_dev;
1072 pci_dev->version_id = 2; /* Current pci device vmstate version */
1073 return pci_dev;
1074 }
1075
1076 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1077 {
1078 PCIIORegion *r;
1079 int i;
1080
1081 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1082 r = &pci_dev->io_regions[i];
1083 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1084 continue;
1085 memory_region_del_subregion(r->address_space, r->memory);
1086 }
1087
1088 pci_unregister_vga(pci_dev);
1089 }
1090
1091 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1092 {
1093 PCIDevice *pci_dev = PCI_DEVICE(dev);
1094 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1095
1096 pci_unregister_io_regions(pci_dev);
1097 pci_del_option_rom(pci_dev);
1098
1099 if (pc->exit) {
1100 pc->exit(pci_dev);
1101 }
1102
1103 pci_device_deassert_intx(pci_dev);
1104 do_pci_unregister_device(pci_dev);
1105 }
1106
1107 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1108 uint8_t type, MemoryRegion *memory)
1109 {
1110 PCIIORegion *r;
1111 uint32_t addr; /* offset in pci config space */
1112 uint64_t wmask;
1113 pcibus_t size = memory_region_size(memory);
1114
1115 assert(region_num >= 0);
1116 assert(region_num < PCI_NUM_REGIONS);
1117 if (size & (size-1)) {
1118 error_report("ERROR: PCI region size must be pow2 "
1119 "type=0x%x, size=0x%"FMT_PCIBUS"", type, size);
1120 exit(1);
1121 }
1122
1123 r = &pci_dev->io_regions[region_num];
1124 r->addr = PCI_BAR_UNMAPPED;
1125 r->size = size;
1126 r->type = type;
1127 r->memory = memory;
1128 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1129 ? pci_get_bus(pci_dev)->address_space_io
1130 : pci_get_bus(pci_dev)->address_space_mem;
1131
1132 wmask = ~(size - 1);
1133 if (region_num == PCI_ROM_SLOT) {
1134 /* ROM enable bit is writable */
1135 wmask |= PCI_ROM_ADDRESS_ENABLE;
1136 }
1137
1138 addr = pci_bar(pci_dev, region_num);
1139 pci_set_long(pci_dev->config + addr, type);
1140
1141 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1142 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1143 pci_set_quad(pci_dev->wmask + addr, wmask);
1144 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1145 } else {
1146 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1147 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1148 }
1149 }
1150
1151 static void pci_update_vga(PCIDevice *pci_dev)
1152 {
1153 uint16_t cmd;
1154
1155 if (!pci_dev->has_vga) {
1156 return;
1157 }
1158
1159 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1160
1161 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1162 cmd & PCI_COMMAND_MEMORY);
1163 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1164 cmd & PCI_COMMAND_IO);
1165 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1166 cmd & PCI_COMMAND_IO);
1167 }
1168
1169 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1170 MemoryRegion *io_lo, MemoryRegion *io_hi)
1171 {
1172 PCIBus *bus = pci_get_bus(pci_dev);
1173
1174 assert(!pci_dev->has_vga);
1175
1176 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1177 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1178 memory_region_add_subregion_overlap(bus->address_space_mem,
1179 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1180
1181 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1182 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1183 memory_region_add_subregion_overlap(bus->address_space_io,
1184 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1185
1186 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1187 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1188 memory_region_add_subregion_overlap(bus->address_space_io,
1189 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1190 pci_dev->has_vga = true;
1191
1192 pci_update_vga(pci_dev);
1193 }
1194
1195 void pci_unregister_vga(PCIDevice *pci_dev)
1196 {
1197 PCIBus *bus = pci_get_bus(pci_dev);
1198
1199 if (!pci_dev->has_vga) {
1200 return;
1201 }
1202
1203 memory_region_del_subregion(bus->address_space_mem,
1204 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1205 memory_region_del_subregion(bus->address_space_io,
1206 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1207 memory_region_del_subregion(bus->address_space_io,
1208 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1209 pci_dev->has_vga = false;
1210 }
1211
1212 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1213 {
1214 return pci_dev->io_regions[region_num].addr;
1215 }
1216
1217 static pcibus_t pci_bar_address(PCIDevice *d,
1218 int reg, uint8_t type, pcibus_t size)
1219 {
1220 pcibus_t new_addr, last_addr;
1221 int bar = pci_bar(d, reg);
1222 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1223 Object *machine = qdev_get_machine();
1224 ObjectClass *oc = object_get_class(machine);
1225 MachineClass *mc = MACHINE_CLASS(oc);
1226 bool allow_0_address = mc->pci_allow_0_address;
1227
1228 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1229 if (!(cmd & PCI_COMMAND_IO)) {
1230 return PCI_BAR_UNMAPPED;
1231 }
1232 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1233 last_addr = new_addr + size - 1;
1234 /* Check if 32 bit BAR wraps around explicitly.
1235 * TODO: make priorities correct and remove this work around.
1236 */
1237 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1238 (!allow_0_address && new_addr == 0)) {
1239 return PCI_BAR_UNMAPPED;
1240 }
1241 return new_addr;
1242 }
1243
1244 if (!(cmd & PCI_COMMAND_MEMORY)) {
1245 return PCI_BAR_UNMAPPED;
1246 }
1247 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1248 new_addr = pci_get_quad(d->config + bar);
1249 } else {
1250 new_addr = pci_get_long(d->config + bar);
1251 }
1252 /* the ROM slot has a specific enable bit */
1253 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1254 return PCI_BAR_UNMAPPED;
1255 }
1256 new_addr &= ~(size - 1);
1257 last_addr = new_addr + size - 1;
1258 /* NOTE: we do not support wrapping */
1259 /* XXX: as we cannot support really dynamic
1260 mappings, we handle specific values as invalid
1261 mappings. */
1262 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1263 (!allow_0_address && new_addr == 0)) {
1264 return PCI_BAR_UNMAPPED;
1265 }
1266
1267 /* Now pcibus_t is 64bit.
1268 * Check if 32 bit BAR wraps around explicitly.
1269 * Without this, PC ide doesn't work well.
1270 * TODO: remove this work around.
1271 */
1272 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1273 return PCI_BAR_UNMAPPED;
1274 }
1275
1276 /*
1277 * OS is allowed to set BAR beyond its addressable
1278 * bits. For example, 32 bit OS can set 64bit bar
1279 * to >4G. Check it. TODO: we might need to support
1280 * it in the future for e.g. PAE.
1281 */
1282 if (last_addr >= HWADDR_MAX) {
1283 return PCI_BAR_UNMAPPED;
1284 }
1285
1286 return new_addr;
1287 }
1288
1289 static void pci_update_mappings(PCIDevice *d)
1290 {
1291 PCIIORegion *r;
1292 int i;
1293 pcibus_t new_addr;
1294
1295 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1296 r = &d->io_regions[i];
1297
1298 /* this region isn't registered */
1299 if (!r->size)
1300 continue;
1301
1302 new_addr = pci_bar_address(d, i, r->type, r->size);
1303
1304 /* This bar isn't changed */
1305 if (new_addr == r->addr)
1306 continue;
1307
1308 /* now do the real mapping */
1309 if (r->addr != PCI_BAR_UNMAPPED) {
1310 trace_pci_update_mappings_del(d, pci_dev_bus_num(d),
1311 PCI_SLOT(d->devfn),
1312 PCI_FUNC(d->devfn),
1313 i, r->addr, r->size);
1314 memory_region_del_subregion(r->address_space, r->memory);
1315 }
1316 r->addr = new_addr;
1317 if (r->addr != PCI_BAR_UNMAPPED) {
1318 trace_pci_update_mappings_add(d, pci_dev_bus_num(d),
1319 PCI_SLOT(d->devfn),
1320 PCI_FUNC(d->devfn),
1321 i, r->addr, r->size);
1322 memory_region_add_subregion_overlap(r->address_space,
1323 r->addr, r->memory, 1);
1324 }
1325 }
1326
1327 pci_update_vga(d);
1328 }
1329
1330 static inline int pci_irq_disabled(PCIDevice *d)
1331 {
1332 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1333 }
1334
1335 /* Called after interrupt disabled field update in config space,
1336 * assert/deassert interrupts if necessary.
1337 * Gets original interrupt disable bit value (before update). */
1338 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1339 {
1340 int i, disabled = pci_irq_disabled(d);
1341 if (disabled == was_irq_disabled)
1342 return;
1343 for (i = 0; i < PCI_NUM_PINS; ++i) {
1344 int state = pci_irq_state(d, i);
1345 pci_change_irq_level(d, i, disabled ? -state : state);
1346 }
1347 }
1348
1349 uint32_t pci_default_read_config(PCIDevice *d,
1350 uint32_t address, int len)
1351 {
1352 uint32_t val = 0;
1353
1354 memcpy(&val, d->config + address, len);
1355 return le32_to_cpu(val);
1356 }
1357
1358 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1359 {
1360 int i, was_irq_disabled = pci_irq_disabled(d);
1361 uint32_t val = val_in;
1362
1363 for (i = 0; i < l; val >>= 8, ++i) {
1364 uint8_t wmask = d->wmask[addr + i];
1365 uint8_t w1cmask = d->w1cmask[addr + i];
1366 assert(!(wmask & w1cmask));
1367 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1368 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1369 }
1370 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1371 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1372 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1373 range_covers_byte(addr, l, PCI_COMMAND))
1374 pci_update_mappings(d);
1375
1376 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1377 pci_update_irq_disabled(d, was_irq_disabled);
1378 memory_region_set_enabled(&d->bus_master_enable_region,
1379 pci_get_word(d->config + PCI_COMMAND)
1380 & PCI_COMMAND_MASTER);
1381 }
1382
1383 msi_write_config(d, addr, val_in, l);
1384 msix_write_config(d, addr, val_in, l);
1385 }
1386
1387 /***********************************************************/
1388 /* generic PCI irq support */
1389
1390 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1391 static void pci_irq_handler(void *opaque, int irq_num, int level)
1392 {
1393 PCIDevice *pci_dev = opaque;
1394 int change;
1395
1396 change = level - pci_irq_state(pci_dev, irq_num);
1397 if (!change)
1398 return;
1399
1400 pci_set_irq_state(pci_dev, irq_num, level);
1401 pci_update_irq_status(pci_dev);
1402 if (pci_irq_disabled(pci_dev))
1403 return;
1404 pci_change_irq_level(pci_dev, irq_num, change);
1405 }
1406
1407 static inline int pci_intx(PCIDevice *pci_dev)
1408 {
1409 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1410 }
1411
1412 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1413 {
1414 int intx = pci_intx(pci_dev);
1415
1416 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1417 }
1418
1419 void pci_set_irq(PCIDevice *pci_dev, int level)
1420 {
1421 int intx = pci_intx(pci_dev);
1422 pci_irq_handler(pci_dev, intx, level);
1423 }
1424
1425 /* Special hooks used by device assignment */
1426 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1427 {
1428 assert(pci_bus_is_root(bus));
1429 bus->route_intx_to_irq = route_intx_to_irq;
1430 }
1431
1432 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1433 {
1434 PCIBus *bus;
1435
1436 do {
1437 bus = pci_get_bus(dev);
1438 pin = bus->map_irq(dev, pin);
1439 dev = bus->parent_dev;
1440 } while (dev);
1441
1442 if (!bus->route_intx_to_irq) {
1443 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1444 object_get_typename(OBJECT(bus->qbus.parent)));
1445 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1446 }
1447
1448 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1449 }
1450
1451 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1452 {
1453 return old->mode != new->mode || old->irq != new->irq;
1454 }
1455
1456 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1457 {
1458 PCIDevice *dev;
1459 PCIBus *sec;
1460 int i;
1461
1462 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1463 dev = bus->devices[i];
1464 if (dev && dev->intx_routing_notifier) {
1465 dev->intx_routing_notifier(dev);
1466 }
1467 }
1468
1469 QLIST_FOREACH(sec, &bus->child, sibling) {
1470 pci_bus_fire_intx_routing_notifier(sec);
1471 }
1472 }
1473
1474 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1475 PCIINTxRoutingNotifier notifier)
1476 {
1477 dev->intx_routing_notifier = notifier;
1478 }
1479
1480 /*
1481 * PCI-to-PCI bridge specification
1482 * 9.1: Interrupt routing. Table 9-1
1483 *
1484 * the PCI Express Base Specification, Revision 2.1
1485 * 2.2.8.1: INTx interrutp signaling - Rules
1486 * the Implementation Note
1487 * Table 2-20
1488 */
1489 /*
1490 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1491 * 0-origin unlike PCI interrupt pin register.
1492 */
1493 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1494 {
1495 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1496 }
1497
1498 /***********************************************************/
1499 /* monitor info on PCI */
1500
1501 typedef struct {
1502 uint16_t class;
1503 const char *desc;
1504 const char *fw_name;
1505 uint16_t fw_ign_bits;
1506 } pci_class_desc;
1507
1508 static const pci_class_desc pci_class_descriptions[] =
1509 {
1510 { 0x0001, "VGA controller", "display"},
1511 { 0x0100, "SCSI controller", "scsi"},
1512 { 0x0101, "IDE controller", "ide"},
1513 { 0x0102, "Floppy controller", "fdc"},
1514 { 0x0103, "IPI controller", "ipi"},
1515 { 0x0104, "RAID controller", "raid"},
1516 { 0x0106, "SATA controller"},
1517 { 0x0107, "SAS controller"},
1518 { 0x0180, "Storage controller"},
1519 { 0x0200, "Ethernet controller", "ethernet"},
1520 { 0x0201, "Token Ring controller", "token-ring"},
1521 { 0x0202, "FDDI controller", "fddi"},
1522 { 0x0203, "ATM controller", "atm"},
1523 { 0x0280, "Network controller"},
1524 { 0x0300, "VGA controller", "display", 0x00ff},
1525 { 0x0301, "XGA controller"},
1526 { 0x0302, "3D controller"},
1527 { 0x0380, "Display controller"},
1528 { 0x0400, "Video controller", "video"},
1529 { 0x0401, "Audio controller", "sound"},
1530 { 0x0402, "Phone"},
1531 { 0x0403, "Audio controller", "sound"},
1532 { 0x0480, "Multimedia controller"},
1533 { 0x0500, "RAM controller", "memory"},
1534 { 0x0501, "Flash controller", "flash"},
1535 { 0x0580, "Memory controller"},
1536 { 0x0600, "Host bridge", "host"},
1537 { 0x0601, "ISA bridge", "isa"},
1538 { 0x0602, "EISA bridge", "eisa"},
1539 { 0x0603, "MC bridge", "mca"},
1540 { 0x0604, "PCI bridge", "pci-bridge"},
1541 { 0x0605, "PCMCIA bridge", "pcmcia"},
1542 { 0x0606, "NUBUS bridge", "nubus"},
1543 { 0x0607, "CARDBUS bridge", "cardbus"},
1544 { 0x0608, "RACEWAY bridge"},
1545 { 0x0680, "Bridge"},
1546 { 0x0700, "Serial port", "serial"},
1547 { 0x0701, "Parallel port", "parallel"},
1548 { 0x0800, "Interrupt controller", "interrupt-controller"},
1549 { 0x0801, "DMA controller", "dma-controller"},
1550 { 0x0802, "Timer", "timer"},
1551 { 0x0803, "RTC", "rtc"},
1552 { 0x0900, "Keyboard", "keyboard"},
1553 { 0x0901, "Pen", "pen"},
1554 { 0x0902, "Mouse", "mouse"},
1555 { 0x0A00, "Dock station", "dock", 0x00ff},
1556 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1557 { 0x0c00, "Fireware contorller", "fireware"},
1558 { 0x0c01, "Access bus controller", "access-bus"},
1559 { 0x0c02, "SSA controller", "ssa"},
1560 { 0x0c03, "USB controller", "usb"},
1561 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1562 { 0x0c05, "SMBus"},
1563 { 0, NULL}
1564 };
1565
1566 static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1567 void (*fn)(PCIBus *b,
1568 PCIDevice *d,
1569 void *opaque),
1570 void *opaque)
1571 {
1572 PCIDevice *d;
1573 int devfn;
1574
1575 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1576 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1577 if (d) {
1578 fn(bus, d, opaque);
1579 }
1580 }
1581 }
1582
1583 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1584 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1585 void *opaque)
1586 {
1587 bus = pci_find_bus_nr(bus, bus_num);
1588
1589 if (bus) {
1590 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1591 }
1592 }
1593
1594 static void pci_for_each_device_under_bus(PCIBus *bus,
1595 void (*fn)(PCIBus *b, PCIDevice *d,
1596 void *opaque),
1597 void *opaque)
1598 {
1599 PCIDevice *d;
1600 int devfn;
1601
1602 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1603 d = bus->devices[devfn];
1604 if (d) {
1605 fn(bus, d, opaque);
1606 }
1607 }
1608 }
1609
1610 void pci_for_each_device(PCIBus *bus, int bus_num,
1611 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1612 void *opaque)
1613 {
1614 bus = pci_find_bus_nr(bus, bus_num);
1615
1616 if (bus) {
1617 pci_for_each_device_under_bus(bus, fn, opaque);
1618 }
1619 }
1620
1621 static const pci_class_desc *get_class_desc(int class)
1622 {
1623 const pci_class_desc *desc;
1624
1625 desc = pci_class_descriptions;
1626 while (desc->desc && class != desc->class) {
1627 desc++;
1628 }
1629
1630 return desc;
1631 }
1632
1633 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1634
1635 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1636 {
1637 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1638 int i;
1639
1640 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1641 const PCIIORegion *r = &dev->io_regions[i];
1642 PciMemoryRegionList *region;
1643
1644 if (!r->size) {
1645 continue;
1646 }
1647
1648 region = g_malloc0(sizeof(*region));
1649 region->value = g_malloc0(sizeof(*region->value));
1650
1651 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1652 region->value->type = g_strdup("io");
1653 } else {
1654 region->value->type = g_strdup("memory");
1655 region->value->has_prefetch = true;
1656 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1657 region->value->has_mem_type_64 = true;
1658 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1659 }
1660
1661 region->value->bar = i;
1662 region->value->address = r->addr;
1663 region->value->size = r->size;
1664
1665 /* XXX: waiting for the qapi to support GSList */
1666 if (!cur_item) {
1667 head = cur_item = region;
1668 } else {
1669 cur_item->next = region;
1670 cur_item = region;
1671 }
1672 }
1673
1674 return head;
1675 }
1676
1677 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1678 int bus_num)
1679 {
1680 PciBridgeInfo *info;
1681 PciMemoryRange *range;
1682
1683 info = g_new0(PciBridgeInfo, 1);
1684
1685 info->bus = g_new0(PciBusInfo, 1);
1686 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1687 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1688 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1689
1690 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1691 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1692 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1693
1694 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1695 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1696 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1697
1698 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1699 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1700 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1701
1702 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1703 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1704 if (child_bus) {
1705 info->has_devices = true;
1706 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1707 }
1708 }
1709
1710 return info;
1711 }
1712
1713 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1714 int bus_num)
1715 {
1716 const pci_class_desc *desc;
1717 PciDeviceInfo *info;
1718 uint8_t type;
1719 int class;
1720
1721 info = g_new0(PciDeviceInfo, 1);
1722 info->bus = bus_num;
1723 info->slot = PCI_SLOT(dev->devfn);
1724 info->function = PCI_FUNC(dev->devfn);
1725
1726 info->class_info = g_new0(PciDeviceClass, 1);
1727 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1728 info->class_info->q_class = class;
1729 desc = get_class_desc(class);
1730 if (desc->desc) {
1731 info->class_info->has_desc = true;
1732 info->class_info->desc = g_strdup(desc->desc);
1733 }
1734
1735 info->id = g_new0(PciDeviceId, 1);
1736 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1737 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1738 info->regions = qmp_query_pci_regions(dev);
1739 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1740
1741 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1742 info->has_irq = true;
1743 info->irq = dev->config[PCI_INTERRUPT_LINE];
1744 }
1745
1746 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1747 if (type == PCI_HEADER_TYPE_BRIDGE) {
1748 info->has_pci_bridge = true;
1749 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1750 }
1751
1752 return info;
1753 }
1754
1755 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1756 {
1757 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1758 PCIDevice *dev;
1759 int devfn;
1760
1761 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1762 dev = bus->devices[devfn];
1763 if (dev) {
1764 info = g_malloc0(sizeof(*info));
1765 info->value = qmp_query_pci_device(dev, bus, bus_num);
1766
1767 /* XXX: waiting for the qapi to support GSList */
1768 if (!cur_item) {
1769 head = cur_item = info;
1770 } else {
1771 cur_item->next = info;
1772 cur_item = info;
1773 }
1774 }
1775 }
1776
1777 return head;
1778 }
1779
1780 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1781 {
1782 PciInfo *info = NULL;
1783
1784 bus = pci_find_bus_nr(bus, bus_num);
1785 if (bus) {
1786 info = g_malloc0(sizeof(*info));
1787 info->bus = bus_num;
1788 info->devices = qmp_query_pci_devices(bus, bus_num);
1789 }
1790
1791 return info;
1792 }
1793
1794 PciInfoList *qmp_query_pci(Error **errp)
1795 {
1796 PciInfoList *info, *head = NULL, *cur_item = NULL;
1797 PCIHostState *host_bridge;
1798
1799 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1800 info = g_malloc0(sizeof(*info));
1801 info->value = qmp_query_pci_bus(host_bridge->bus,
1802 pci_bus_num(host_bridge->bus));
1803
1804 /* XXX: waiting for the qapi to support GSList */
1805 if (!cur_item) {
1806 head = cur_item = info;
1807 } else {
1808 cur_item->next = info;
1809 cur_item = info;
1810 }
1811 }
1812
1813 return head;
1814 }
1815
1816 static const char * const pci_nic_models[] = {
1817 "ne2k_pci",
1818 "i82551",
1819 "i82557b",
1820 "i82559er",
1821 "rtl8139",
1822 "e1000",
1823 "pcnet",
1824 "virtio",
1825 "sungem",
1826 NULL
1827 };
1828
1829 static const char * const pci_nic_names[] = {
1830 "ne2k_pci",
1831 "i82551",
1832 "i82557b",
1833 "i82559er",
1834 "rtl8139",
1835 "e1000",
1836 "pcnet",
1837 "virtio-net-pci",
1838 "sungem",
1839 NULL
1840 };
1841
1842 /* Initialize a PCI NIC. */
1843 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1844 const char *default_model,
1845 const char *default_devaddr)
1846 {
1847 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1848 PCIBus *bus;
1849 PCIDevice *pci_dev;
1850 DeviceState *dev;
1851 int devfn;
1852 int i;
1853
1854 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1855 exit(0);
1856 }
1857
1858 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1859 if (i < 0) {
1860 exit(1);
1861 }
1862
1863 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1864 if (!bus) {
1865 error_report("Invalid PCI device address %s for device %s",
1866 devaddr, pci_nic_names[i]);
1867 exit(1);
1868 }
1869
1870 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1871 dev = &pci_dev->qdev;
1872 qdev_set_nic_properties(dev, nd);
1873 qdev_init_nofail(dev);
1874
1875 return pci_dev;
1876 }
1877
1878 PCIDevice *pci_vga_init(PCIBus *bus)
1879 {
1880 switch (vga_interface_type) {
1881 case VGA_CIRRUS:
1882 return pci_create_simple(bus, -1, "cirrus-vga");
1883 case VGA_QXL:
1884 return pci_create_simple(bus, -1, "qxl-vga");
1885 case VGA_STD:
1886 return pci_create_simple(bus, -1, "VGA");
1887 case VGA_VMWARE:
1888 return pci_create_simple(bus, -1, "vmware-svga");
1889 case VGA_VIRTIO:
1890 return pci_create_simple(bus, -1, "virtio-vga");
1891 case VGA_NONE:
1892 default: /* Other non-PCI types. Checking for unsupported types is already
1893 done in vl.c. */
1894 return NULL;
1895 }
1896 }
1897
1898 /* Whether a given bus number is in range of the secondary
1899 * bus of the given bridge device. */
1900 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1901 {
1902 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1903 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1904 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1905 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1906 }
1907
1908 /* Whether a given bus number is in a range of a root bus */
1909 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1910 {
1911 int i;
1912
1913 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1914 PCIDevice *dev = bus->devices[i];
1915
1916 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1917 if (pci_secondary_bus_in_range(dev, bus_num)) {
1918 return true;
1919 }
1920 }
1921 }
1922
1923 return false;
1924 }
1925
1926 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1927 {
1928 PCIBus *sec;
1929
1930 if (!bus) {
1931 return NULL;
1932 }
1933
1934 if (pci_bus_num(bus) == bus_num) {
1935 return bus;
1936 }
1937
1938 /* Consider all bus numbers in range for the host pci bridge. */
1939 if (!pci_bus_is_root(bus) &&
1940 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1941 return NULL;
1942 }
1943
1944 /* try child bus */
1945 for (; bus; bus = sec) {
1946 QLIST_FOREACH(sec, &bus->child, sibling) {
1947 if (pci_bus_num(sec) == bus_num) {
1948 return sec;
1949 }
1950 /* PXB buses assumed to be children of bus 0 */
1951 if (pci_bus_is_root(sec)) {
1952 if (pci_root_bus_in_range(sec, bus_num)) {
1953 break;
1954 }
1955 } else {
1956 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1957 break;
1958 }
1959 }
1960 }
1961 }
1962
1963 return NULL;
1964 }
1965
1966 void pci_for_each_bus_depth_first(PCIBus *bus,
1967 void *(*begin)(PCIBus *bus, void *parent_state),
1968 void (*end)(PCIBus *bus, void *state),
1969 void *parent_state)
1970 {
1971 PCIBus *sec;
1972 void *state;
1973
1974 if (!bus) {
1975 return;
1976 }
1977
1978 if (begin) {
1979 state = begin(bus, parent_state);
1980 } else {
1981 state = parent_state;
1982 }
1983
1984 QLIST_FOREACH(sec, &bus->child, sibling) {
1985 pci_for_each_bus_depth_first(sec, begin, end, state);
1986 }
1987
1988 if (end) {
1989 end(bus, state);
1990 }
1991 }
1992
1993
1994 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1995 {
1996 bus = pci_find_bus_nr(bus, bus_num);
1997
1998 if (!bus)
1999 return NULL;
2000
2001 return bus->devices[devfn];
2002 }
2003
2004 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2005 {
2006 PCIDevice *pci_dev = (PCIDevice *)qdev;
2007 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2008 Error *local_err = NULL;
2009 bool is_default_rom;
2010
2011 /* initialize cap_present for pci_is_express() and pci_config_size() */
2012 if (pc->is_express) {
2013 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2014 }
2015
2016 pci_dev = do_pci_register_device(pci_dev,
2017 object_get_typename(OBJECT(qdev)),
2018 pci_dev->devfn, errp);
2019 if (pci_dev == NULL)
2020 return;
2021
2022 if (pc->realize) {
2023 pc->realize(pci_dev, &local_err);
2024 if (local_err) {
2025 error_propagate(errp, local_err);
2026 do_pci_unregister_device(pci_dev);
2027 return;
2028 }
2029 }
2030
2031 /* rom loading */
2032 is_default_rom = false;
2033 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2034 pci_dev->romfile = g_strdup(pc->romfile);
2035 is_default_rom = true;
2036 }
2037
2038 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2039 if (local_err) {
2040 error_propagate(errp, local_err);
2041 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2042 return;
2043 }
2044 }
2045
2046 static void pci_default_realize(PCIDevice *dev, Error **errp)
2047 {
2048 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2049
2050 if (pc->init) {
2051 if (pc->init(dev) < 0) {
2052 error_setg(errp, "Device initialization failed");
2053 return;
2054 }
2055 }
2056 }
2057
2058 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2059 const char *name)
2060 {
2061 DeviceState *dev;
2062
2063 dev = qdev_create(&bus->qbus, name);
2064 qdev_prop_set_int32(dev, "addr", devfn);
2065 qdev_prop_set_bit(dev, "multifunction", multifunction);
2066 return PCI_DEVICE(dev);
2067 }
2068
2069 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2070 bool multifunction,
2071 const char *name)
2072 {
2073 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2074 qdev_init_nofail(&dev->qdev);
2075 return dev;
2076 }
2077
2078 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2079 {
2080 return pci_create_multifunction(bus, devfn, false, name);
2081 }
2082
2083 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2084 {
2085 return pci_create_simple_multifunction(bus, devfn, false, name);
2086 }
2087
2088 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2089 {
2090 int offset = PCI_CONFIG_HEADER_SIZE;
2091 int i;
2092 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2093 if (pdev->used[i])
2094 offset = i + 1;
2095 else if (i - offset + 1 == size)
2096 return offset;
2097 }
2098 return 0;
2099 }
2100
2101 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2102 uint8_t *prev_p)
2103 {
2104 uint8_t next, prev;
2105
2106 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2107 return 0;
2108
2109 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2110 prev = next + PCI_CAP_LIST_NEXT)
2111 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2112 break;
2113
2114 if (prev_p)
2115 *prev_p = prev;
2116 return next;
2117 }
2118
2119 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2120 {
2121 uint8_t next, prev, found = 0;
2122
2123 if (!(pdev->used[offset])) {
2124 return 0;
2125 }
2126
2127 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2128
2129 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2130 prev = next + PCI_CAP_LIST_NEXT) {
2131 if (next <= offset && next > found) {
2132 found = next;
2133 }
2134 }
2135 return found;
2136 }
2137
2138 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2139 This is needed for an option rom which is used for more than one device. */
2140 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2141 {
2142 uint16_t vendor_id;
2143 uint16_t device_id;
2144 uint16_t rom_vendor_id;
2145 uint16_t rom_device_id;
2146 uint16_t rom_magic;
2147 uint16_t pcir_offset;
2148 uint8_t checksum;
2149
2150 /* Words in rom data are little endian (like in PCI configuration),
2151 so they can be read / written with pci_get_word / pci_set_word. */
2152
2153 /* Only a valid rom will be patched. */
2154 rom_magic = pci_get_word(ptr);
2155 if (rom_magic != 0xaa55) {
2156 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2157 return;
2158 }
2159 pcir_offset = pci_get_word(ptr + 0x18);
2160 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2161 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2162 return;
2163 }
2164
2165 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2166 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2167 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2168 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2169
2170 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2171 vendor_id, device_id, rom_vendor_id, rom_device_id);
2172
2173 checksum = ptr[6];
2174
2175 if (vendor_id != rom_vendor_id) {
2176 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2177 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2178 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2179 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2180 ptr[6] = checksum;
2181 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2182 }
2183
2184 if (device_id != rom_device_id) {
2185 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2186 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2187 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2188 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2189 ptr[6] = checksum;
2190 pci_set_word(ptr + pcir_offset + 6, device_id);
2191 }
2192 }
2193
2194 /* Add an option rom for the device */
2195 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2196 Error **errp)
2197 {
2198 int size;
2199 char *path;
2200 void *ptr;
2201 char name[32];
2202 const VMStateDescription *vmsd;
2203
2204 if (!pdev->romfile)
2205 return;
2206 if (strlen(pdev->romfile) == 0)
2207 return;
2208
2209 if (!pdev->rom_bar) {
2210 /*
2211 * Load rom via fw_cfg instead of creating a rom bar,
2212 * for 0.11 compatibility.
2213 */
2214 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2215
2216 /*
2217 * Hot-plugged devices can't use the option ROM
2218 * if the rom bar is disabled.
2219 */
2220 if (DEVICE(pdev)->hotplugged) {
2221 error_setg(errp, "Hot-plugged device without ROM bar"
2222 " can't have an option ROM");
2223 return;
2224 }
2225
2226 if (class == 0x0300) {
2227 rom_add_vga(pdev->romfile);
2228 } else {
2229 rom_add_option(pdev->romfile, -1);
2230 }
2231 return;
2232 }
2233
2234 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2235 if (path == NULL) {
2236 path = g_strdup(pdev->romfile);
2237 }
2238
2239 size = get_image_size(path);
2240 if (size < 0) {
2241 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2242 g_free(path);
2243 return;
2244 } else if (size == 0) {
2245 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2246 g_free(path);
2247 return;
2248 }
2249 size = pow2ceil(size);
2250
2251 vmsd = qdev_get_vmsd(DEVICE(pdev));
2252
2253 if (vmsd) {
2254 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2255 } else {
2256 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2257 }
2258 pdev->has_rom = true;
2259 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2260 ptr = memory_region_get_ram_ptr(&pdev->rom);
2261 load_image(path, ptr);
2262 g_free(path);
2263
2264 if (is_default_rom) {
2265 /* Only the default rom images will be patched (if needed). */
2266 pci_patch_ids(pdev, ptr, size);
2267 }
2268
2269 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2270 }
2271
2272 static void pci_del_option_rom(PCIDevice *pdev)
2273 {
2274 if (!pdev->has_rom)
2275 return;
2276
2277 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2278 pdev->has_rom = false;
2279 }
2280
2281 /*
2282 * On success, pci_add_capability() returns a positive value
2283 * that the offset of the pci capability.
2284 * On failure, it sets an error and returns a negative error
2285 * code.
2286 */
2287 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2288 uint8_t offset, uint8_t size,
2289 Error **errp)
2290 {
2291 uint8_t *config;
2292 int i, overlapping_cap;
2293
2294 if (!offset) {
2295 offset = pci_find_space(pdev, size);
2296 /* out of PCI config space is programming error */
2297 assert(offset);
2298 } else {
2299 /* Verify that capabilities don't overlap. Note: device assignment
2300 * depends on this check to verify that the device is not broken.
2301 * Should never trigger for emulated devices, but it's helpful
2302 * for debugging these. */
2303 for (i = offset; i < offset + size; i++) {
2304 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2305 if (overlapping_cap) {
2306 error_setg(errp, "%s:%02x:%02x.%x "
2307 "Attempt to add PCI capability %x at offset "
2308 "%x overlaps existing capability %x at offset %x",
2309 pci_root_bus_path(pdev), pci_dev_bus_num(pdev),
2310 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2311 cap_id, offset, overlapping_cap, i);
2312 return -EINVAL;
2313 }
2314 }
2315 }
2316
2317 config = pdev->config + offset;
2318 config[PCI_CAP_LIST_ID] = cap_id;
2319 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2320 pdev->config[PCI_CAPABILITY_LIST] = offset;
2321 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2322 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2323 /* Make capability read-only by default */
2324 memset(pdev->wmask + offset, 0, size);
2325 /* Check capability by default */
2326 memset(pdev->cmask + offset, 0xFF, size);
2327 return offset;
2328 }
2329
2330 /* Unlink capability from the pci config space. */
2331 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2332 {
2333 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2334 if (!offset)
2335 return;
2336 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2337 /* Make capability writable again */
2338 memset(pdev->wmask + offset, 0xff, size);
2339 memset(pdev->w1cmask + offset, 0, size);
2340 /* Clear cmask as device-specific registers can't be checked */
2341 memset(pdev->cmask + offset, 0, size);
2342 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2343
2344 if (!pdev->config[PCI_CAPABILITY_LIST])
2345 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2346 }
2347
2348 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2349 {
2350 return pci_find_capability_list(pdev, cap_id, NULL);
2351 }
2352
2353 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2354 {
2355 PCIDevice *d = (PCIDevice *)dev;
2356 const pci_class_desc *desc;
2357 char ctxt[64];
2358 PCIIORegion *r;
2359 int i, class;
2360
2361 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2362 desc = pci_class_descriptions;
2363 while (desc->desc && class != desc->class)
2364 desc++;
2365 if (desc->desc) {
2366 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2367 } else {
2368 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2369 }
2370
2371 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2372 "pci id %04x:%04x (sub %04x:%04x)\n",
2373 indent, "", ctxt, pci_dev_bus_num(d),
2374 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2375 pci_get_word(d->config + PCI_VENDOR_ID),
2376 pci_get_word(d->config + PCI_DEVICE_ID),
2377 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2378 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2379 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2380 r = &d->io_regions[i];
2381 if (!r->size)
2382 continue;
2383 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2384 " [0x%"FMT_PCIBUS"]\n",
2385 indent, "",
2386 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2387 r->addr, r->addr + r->size - 1);
2388 }
2389 }
2390
2391 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2392 {
2393 PCIDevice *d = (PCIDevice *)dev;
2394 const char *name = NULL;
2395 const pci_class_desc *desc = pci_class_descriptions;
2396 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2397
2398 while (desc->desc &&
2399 (class & ~desc->fw_ign_bits) !=
2400 (desc->class & ~desc->fw_ign_bits)) {
2401 desc++;
2402 }
2403
2404 if (desc->desc) {
2405 name = desc->fw_name;
2406 }
2407
2408 if (name) {
2409 pstrcpy(buf, len, name);
2410 } else {
2411 snprintf(buf, len, "pci%04x,%04x",
2412 pci_get_word(d->config + PCI_VENDOR_ID),
2413 pci_get_word(d->config + PCI_DEVICE_ID));
2414 }
2415
2416 return buf;
2417 }
2418
2419 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2420 {
2421 PCIDevice *d = (PCIDevice *)dev;
2422 char path[50], name[33];
2423 int off;
2424
2425 off = snprintf(path, sizeof(path), "%s@%x",
2426 pci_dev_fw_name(dev, name, sizeof name),
2427 PCI_SLOT(d->devfn));
2428 if (PCI_FUNC(d->devfn))
2429 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2430 return g_strdup(path);
2431 }
2432
2433 static char *pcibus_get_dev_path(DeviceState *dev)
2434 {
2435 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2436 PCIDevice *t;
2437 int slot_depth;
2438 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2439 * 00 is added here to make this format compatible with
2440 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2441 * Slot.Function list specifies the slot and function numbers for all
2442 * devices on the path from root to the specific device. */
2443 const char *root_bus_path;
2444 int root_bus_len;
2445 char slot[] = ":SS.F";
2446 int slot_len = sizeof slot - 1 /* For '\0' */;
2447 int path_len;
2448 char *path, *p;
2449 int s;
2450
2451 root_bus_path = pci_root_bus_path(d);
2452 root_bus_len = strlen(root_bus_path);
2453
2454 /* Calculate # of slots on path between device and root. */;
2455 slot_depth = 0;
2456 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2457 ++slot_depth;
2458 }
2459
2460 path_len = root_bus_len + slot_len * slot_depth;
2461
2462 /* Allocate memory, fill in the terminating null byte. */
2463 path = g_malloc(path_len + 1 /* For '\0' */);
2464 path[path_len] = '\0';
2465
2466 memcpy(path, root_bus_path, root_bus_len);
2467
2468 /* Fill in slot numbers. We walk up from device to root, so need to print
2469 * them in the reverse order, last to first. */
2470 p = path + path_len;
2471 for (t = d; t; t = pci_get_bus(t)->parent_dev) {
2472 p -= slot_len;
2473 s = snprintf(slot, sizeof slot, ":%02x.%x",
2474 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2475 assert(s == slot_len);
2476 memcpy(p, slot, slot_len);
2477 }
2478
2479 return path;
2480 }
2481
2482 static int pci_qdev_find_recursive(PCIBus *bus,
2483 const char *id, PCIDevice **pdev)
2484 {
2485 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2486 if (!qdev) {
2487 return -ENODEV;
2488 }
2489
2490 /* roughly check if given qdev is pci device */
2491 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2492 *pdev = PCI_DEVICE(qdev);
2493 return 0;
2494 }
2495 return -EINVAL;
2496 }
2497
2498 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2499 {
2500 PCIHostState *host_bridge;
2501 int rc = -ENODEV;
2502
2503 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2504 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2505 if (!tmp) {
2506 rc = 0;
2507 break;
2508 }
2509 if (tmp != -ENODEV) {
2510 rc = tmp;
2511 }
2512 }
2513
2514 return rc;
2515 }
2516
2517 MemoryRegion *pci_address_space(PCIDevice *dev)
2518 {
2519 return pci_get_bus(dev)->address_space_mem;
2520 }
2521
2522 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2523 {
2524 return pci_get_bus(dev)->address_space_io;
2525 }
2526
2527 static void pci_device_class_init(ObjectClass *klass, void *data)
2528 {
2529 DeviceClass *k = DEVICE_CLASS(klass);
2530 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2531
2532 k->realize = pci_qdev_realize;
2533 k->unrealize = pci_qdev_unrealize;
2534 k->bus_type = TYPE_PCI_BUS;
2535 k->props = pci_props;
2536 pc->realize = pci_default_realize;
2537 }
2538
2539 static void pci_device_class_base_init(ObjectClass *klass, void *data)
2540 {
2541 if (!object_class_is_abstract(klass)) {
2542 ObjectClass *conventional =
2543 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE);
2544 ObjectClass *pcie =
2545 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE);
2546 assert(conventional || pcie);
2547 }
2548 }
2549
2550 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2551 {
2552 PCIBus *bus = pci_get_bus(dev);
2553 PCIBus *iommu_bus = bus;
2554
2555 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2556 iommu_bus = pci_get_bus(iommu_bus->parent_dev);
2557 }
2558 if (iommu_bus && iommu_bus->iommu_fn) {
2559 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2560 }
2561 return &address_space_memory;
2562 }
2563
2564 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2565 {
2566 bus->iommu_fn = fn;
2567 bus->iommu_opaque = opaque;
2568 }
2569
2570 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2571 {
2572 Range *range = opaque;
2573 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2574 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2575 int i;
2576
2577 if (!(cmd & PCI_COMMAND_MEMORY)) {
2578 return;
2579 }
2580
2581 if (pc->is_bridge) {
2582 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2583 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2584
2585 base = MAX(base, 0x1ULL << 32);
2586
2587 if (limit >= base) {
2588 Range pref_range;
2589 range_set_bounds(&pref_range, base, limit);
2590 range_extend(range, &pref_range);
2591 }
2592 }
2593 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2594 PCIIORegion *r = &dev->io_regions[i];
2595 pcibus_t lob, upb;
2596 Range region_range;
2597
2598 if (!r->size ||
2599 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2600 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2601 continue;
2602 }
2603
2604 lob = pci_bar_address(dev, i, r->type, r->size);
2605 upb = lob + r->size - 1;
2606 if (lob == PCI_BAR_UNMAPPED) {
2607 continue;
2608 }
2609
2610 lob = MAX(lob, 0x1ULL << 32);
2611
2612 if (upb >= lob) {
2613 range_set_bounds(&region_range, lob, upb);
2614 range_extend(range, &region_range);
2615 }
2616 }
2617 }
2618
2619 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2620 {
2621 range_make_empty(range);
2622 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2623 }
2624
2625 static bool pcie_has_upstream_port(PCIDevice *dev)
2626 {
2627 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev));
2628
2629 /* Device associated with an upstream port.
2630 * As there are several types of these, it's easier to check the
2631 * parent device: upstream ports are always connected to
2632 * root or downstream ports.
2633 */
2634 return parent_dev &&
2635 pci_is_express(parent_dev) &&
2636 parent_dev->exp.exp_cap &&
2637 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2638 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2639 }
2640
2641 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2642 {
2643 PCIBus *bus = pci_get_bus(pci_dev);
2644
2645 if(pcie_has_upstream_port(pci_dev)) {
2646 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2647 return bus->devices[0];
2648 } else {
2649 /* Other bus types might support multiple devices at slots 0-31 */
2650 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2651 }
2652 }
2653
2654 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2655 {
2656 MSIMessage msg;
2657 if (msix_enabled(dev)) {
2658 msg = msix_get_message(dev, vector);
2659 } else if (msi_enabled(dev)) {
2660 msg = msi_get_message(dev, vector);
2661 } else {
2662 /* Should never happen */
2663 error_report("%s: unknown interrupt type", __func__);
2664 abort();
2665 }
2666 return msg;
2667 }
2668
2669 static const TypeInfo pci_device_type_info = {
2670 .name = TYPE_PCI_DEVICE,
2671 .parent = TYPE_DEVICE,
2672 .instance_size = sizeof(PCIDevice),
2673 .abstract = true,
2674 .class_size = sizeof(PCIDeviceClass),
2675 .class_init = pci_device_class_init,
2676 .class_base_init = pci_device_class_base_init,
2677 };
2678
2679 static void pci_register_types(void)
2680 {
2681 type_register_static(&pci_bus_info);
2682 type_register_static(&pcie_bus_info);
2683 type_register_static(&conventional_pci_interface_info);
2684 type_register_static(&pcie_interface_info);
2685 type_register_static(&pci_device_type_info);
2686 }
2687
2688 type_init(pci_register_types)
AR7 emulation for QEMU