hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu/osdep.h"
  31 #include "hw/hw.h"
  32 #include "hw/loader.h"
  33 #include "sysemu/arch_init.h"
  34 #include "hw/i2c/smbus.h"
  35 #include "hw/boards.h"
  36 #include "hw/timer/mc146818rtc.h"
  37 #include "hw/xen/xen.h"
  38 #include "sysemu/kvm.h"
  39 #include "kvm_i386.h"
  40 #include "hw/kvm/clock.h"
  41 #include "hw/pci-host/q35.h"
  42 #include "exec/address-spaces.h"
  43 #include "hw/i386/pc.h"
  44 #include "hw/i386/ich9.h"
  45 #include "hw/i386/amd_iommu.h"
  46 #include "hw/i386/intel_iommu.h"
  47 #include "hw/smbios/smbios.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/ide/ahci.h"
  50 #include "hw/usb.h"
  51 #include "qemu/error-report.h"
  52 #include "sysemu/numa.h"
  53
  54 /* ICH9 AHCI has 6 ports */
  55 #define MAX_SATA_PORTS     6
  56
  57 /* PC hardware initialisation */
  58 static void pc_q35_init(MachineState *machine)
  59 {
  60     PCMachineState *pcms = PC_MACHINE(machine);
  61     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
  62     Q35PCIHost *q35_host;
  63     PCIHostState *phb;
  64     PCIBus *host_bus;
  65     PCIDevice *lpc;
  66     DeviceState *lpc_dev;
  67     BusState *idebus[MAX_SATA_PORTS];
  68     ISADevice *rtc_state;
  69     MemoryRegion *system_io = get_system_io();
  70     MemoryRegion *pci_memory;
  71     MemoryRegion *rom_memory;
  72     MemoryRegion *ram_memory;
  73     GSIState *gsi_state;
  74     ISABus *isa_bus;
  75     qemu_irq *i8259;
  76     int i;
  77     ICH9LPCState *ich9_lpc;
  78     PCIDevice *ahci;
  79     ram_addr_t lowmem;
  80     DriveInfo *hd[MAX_SATA_PORTS];
  81     MachineClass *mc = MACHINE_GET_CLASS(machine);
  82
  83     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  84      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  85      * also known as MMCFG).
  86      * If it doesn't, we need to split it in chunks below and above 4G.
  87      * In any case, try to make sure that guest addresses aligned at
  88      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  89      */
  90     if (machine->ram_size >= 0xb0000000) {
  91         lowmem = 0x80000000;
  92     } else {
  93         lowmem = 0xb0000000;
  94     }
  95
  96     /* Handle the machine opt max-ram-below-4g.  It is basically doing
  97      * min(qemu limit, user limit).
  98      */
  99     if (!pcms->max_ram_below_4g) {
 100         pcms->max_ram_below_4g = 1ULL << 32; /* default: 4G */;
 101     }
 102     if (lowmem > pcms->max_ram_below_4g) {
 103         lowmem = pcms->max_ram_below_4g;
 104         if (machine->ram_size - lowmem > lowmem &&
 105             lowmem & ((1ULL << 30) - 1)) {
 106             warn_report("There is possibly poor performance as the ram size "
 107                         " (0x%" PRIx64 ") is more then twice the size of"
 108                         " max-ram-below-4g (%"PRIu64") and"
 109                         " max-ram-below-4g is not a multiple of 1G.",
 110                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 111         }
 112     }
 113
 114     if (machine->ram_size >= lowmem) {
 115         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 116         pcms->below_4g_mem_size = lowmem;
 117     } else {
 118         pcms->above_4g_mem_size = 0;
 119         pcms->below_4g_mem_size = machine->ram_size;
 120     }
 121
 122     if (xen_enabled()) {
 123         xen_hvm_init(pcms, &ram_memory);
 124     }
 125
 126     pc_cpus_init(pcms);
 127
 128     kvmclock_create();
 129
 130     /* pci enabled */
 131     if (pcmc->pci_enabled) {
 132         pci_memory = g_new(MemoryRegion, 1);
 133         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 134         rom_memory = pci_memory;
 135     } else {
 136         pci_memory = NULL;
 137         rom_memory = get_system_memory();
 138     }
 139
 140     pc_guest_info_init(pcms);
 141
 142     if (pcmc->smbios_defaults) {
 143         /* These values are guest ABI, do not change */
 144         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 145                             mc->name, pcmc->smbios_legacy_mode,
 146                             pcmc->smbios_uuid_encoded,
 147                             SMBIOS_ENTRY_POINT_21);
 148     }
 149
 150     /* allocate ram and load rom/bios */
 151     if (!xen_enabled()) {
 152         pc_memory_init(pcms, get_system_memory(),
 153                        rom_memory, &ram_memory);
 154     }
 155
 156     /* irq lines */
 157     gsi_state = g_malloc0(sizeof(*gsi_state));
 158     if (kvm_ioapic_in_kernel()) {
 159         kvm_pc_setup_irq_routing(pcmc->pci_enabled);
 160         pcms->gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 161                                        GSI_NUM_PINS);
 162     } else {
 163         pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 164     }
 165
 166     /* create pci host bus */
 167     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 168
 169     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 170     object_property_set_link(OBJECT(q35_host), OBJECT(ram_memory),
 171                              MCH_HOST_PROP_RAM_MEM, NULL);
 172     object_property_set_link(OBJECT(q35_host), OBJECT(pci_memory),
 173                              MCH_HOST_PROP_PCI_MEM, NULL);
 174     object_property_set_link(OBJECT(q35_host), OBJECT(get_system_memory()),
 175                              MCH_HOST_PROP_SYSTEM_MEM, NULL);
 176     object_property_set_link(OBJECT(q35_host), OBJECT(system_io),
 177                              MCH_HOST_PROP_IO_MEM, NULL);
 178     object_property_set_int(OBJECT(q35_host), pcms->below_4g_mem_size,
 179                             PCI_HOST_BELOW_4G_MEM_SIZE, NULL);
 180     object_property_set_int(OBJECT(q35_host), pcms->above_4g_mem_size,
 181                             PCI_HOST_ABOVE_4G_MEM_SIZE, NULL);
 182     /* pci */
 183     qdev_init_nofail(DEVICE(q35_host));
 184     phb = PCI_HOST_BRIDGE(q35_host);
 185     host_bus = phb->bus;
 186     /* create ISA bus */
 187     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 188                                           ICH9_LPC_FUNC), true,
 189                                           TYPE_ICH9_LPC_DEVICE);
 190
 191     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 192                              TYPE_HOTPLUG_HANDLER,
 193                              (Object **)&pcms->acpi_dev,
 194                              object_property_allow_set_link,
 195                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 196     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 197                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 198
 199     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 200     lpc_dev = DEVICE(lpc);
 201     for (i = 0; i < GSI_NUM_PINS; i++) {
 202         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, pcms->gsi[i]);
 203     }
 204     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 205                  ICH9_LPC_NB_PIRQS);
 206     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 207     isa_bus = ich9_lpc->isa_bus;
 208
 209     if (kvm_pic_in_kernel()) {
 210         i8259 = kvm_i8259_init(isa_bus);
 211     } else if (xen_enabled()) {
 212         i8259 = xen_interrupt_controller_init();
 213     } else {
 214         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 215     }
 216
 217     for (i = 0; i < ISA_NUM_IRQS; i++) {
 218         gsi_state->i8259_irq[i] = i8259[i];
 219     }
 220     g_free(i8259);
 221
 222     if (pcmc->pci_enabled) {
 223         ioapic_init_gsi(gsi_state, "q35");
 224     }
 225
 226     pc_register_ferr_irq(pcms->gsi[13]);
 227
 228     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 229     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 230         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 231     }
 232
 233     /* init basic PC hardware */
 234     pc_basic_device_init(isa_bus, pcms->gsi, &rtc_state, !mc->no_floppy,
 235                          (pcms->vmport != ON_OFF_AUTO_ON), pcms->pit,
 236                          0xff0104);
 237
 238     /* connect pm stuff to lpc */
 239     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms));
 240
 241     if (pcms->sata) {
 242         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 243         ahci = pci_create_simple_multifunction(host_bus,
 244                                                PCI_DEVFN(ICH9_SATA1_DEV,
 245                                                          ICH9_SATA1_FUNC),
 246                                                true, "ich9-ahci");
 247         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 248         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 249         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 250         ide_drive_get(hd, ahci_get_num_ports(ahci));
 251         ahci_ide_create_devs(ahci, hd);
 252     } else {
 253         idebus[0] = idebus[1] = NULL;
 254     }
 255
 256     if (machine_usb(machine)) {
 257         /* Should we create 6 UHCI according to ich9 spec? */
 258         ehci_create_ich9_with_companions(host_bus, 0x1d);
 259     }
 260
 261     if (pcms->smbus) {
 262         /* TODO: Populate SPD eeprom data.  */
 263         smbus_eeprom_init(ich9_smb_init(host_bus,
 264                                         PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 265                                         0xb100),
 266                           8, NULL, 0);
 267     }
 268
 269     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 270
 271     /* the rest devices to which pci devfn is automatically assigned */
 272     pc_vga_init(isa_bus, host_bus);
 273     pc_nic_init(isa_bus, host_bus);
 274     if (pcmc->pci_enabled) {
 275         pc_pci_device_init(host_bus);
 276     }
 277
 278     if (pcms->acpi_nvdimm_state.is_enabled) {
 279         nvdimm_init_acpi_state(&pcms->acpi_nvdimm_state, system_io,
 280                                pcms->fw_cfg, OBJECT(pcms));
 281     }
 282 }
 283
 284 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 285     static void pc_init_##suffix(MachineState *machine) \
 286     { \
 287         void (*compat)(MachineState *m) = (compatfn); \
 288         if (compat) { \
 289             compat(machine); \
 290         } \
 291         pc_q35_init(machine); \
 292     } \
 293     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 294
 295
 296 static void pc_q35_machine_options(MachineClass *m)
 297 {
 298     m->family = "pc_q35";
 299     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 300     m->units_per_default_bus = 1;
 301     m->default_machine_opts = "firmware=bios-256k.bin";
 302     m->default_display = "std";
 303     m->no_floppy = 1;
 304     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 305     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 306     m->max_cpus = 288;
 307 }
 308
 309 static void pc_q35_2_12_machine_options(MachineClass *m)
 310 {
 311     pc_q35_machine_options(m);
 312     m->alias = "q35";
 313 }
 314
 315 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 316                    pc_q35_2_12_machine_options);
 317
 318 static void pc_q35_2_11_machine_options(MachineClass *m)
 319 {
 320     pc_q35_2_12_machine_options(m);
 321     m->alias = NULL;
 322     SET_MACHINE_COMPAT(m, PC_COMPAT_2_11);
 323 }
 324
 325 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 326                    pc_q35_2_11_machine_options);
 327
 328 static void pc_q35_2_10_machine_options(MachineClass *m)
 329 {
 330     pc_q35_2_11_machine_options(m);
 331     SET_MACHINE_COMPAT(m, PC_COMPAT_2_10);
 332     m->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
 333     m->auto_enable_numa_with_memhp = false;
 334 }
 335
 336 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 337                    pc_q35_2_10_machine_options);
 338
 339 static void pc_q35_2_9_machine_options(MachineClass *m)
 340 {
 341     pc_q35_2_10_machine_options(m);
 342     SET_MACHINE_COMPAT(m, PC_COMPAT_2_9);
 343 }
 344
 345 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 346                    pc_q35_2_9_machine_options);
 347
 348 static void pc_q35_2_8_machine_options(MachineClass *m)
 349 {
 350     pc_q35_2_9_machine_options(m);
 351     SET_MACHINE_COMPAT(m, PC_COMPAT_2_8);
 352 }
 353
 354 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 355                    pc_q35_2_8_machine_options);
 356
 357 static void pc_q35_2_7_machine_options(MachineClass *m)
 358 {
 359     pc_q35_2_8_machine_options(m);
 360     m->max_cpus = 255;
 361     SET_MACHINE_COMPAT(m, PC_COMPAT_2_7);
 362 }
 363
 364 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 365                    pc_q35_2_7_machine_options);
 366
 367 static void pc_q35_2_6_machine_options(MachineClass *m)
 368 {
 369     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 370     pc_q35_2_7_machine_options(m);
 371     pcmc->legacy_cpu_hotplug = true;
 372     pcmc->linuxboot_dma_enabled = false;
 373     SET_MACHINE_COMPAT(m, PC_COMPAT_2_6);
 374 }
 375
 376 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 377                    pc_q35_2_6_machine_options);
 378
 379 static void pc_q35_2_5_machine_options(MachineClass *m)
 380 {
 381     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 382     pc_q35_2_6_machine_options(m);
 383     pcmc->save_tsc_khz = false;
 384     m->legacy_fw_cfg_order = 1;
 385     SET_MACHINE_COMPAT(m, PC_COMPAT_2_5);
 386 }
 387
 388 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 389                    pc_q35_2_5_machine_options);
 390
 391 static void pc_q35_2_4_machine_options(MachineClass *m)
 392 {
 393     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 394     pc_q35_2_5_machine_options(m);
 395     m->hw_version = "2.4.0";
 396     pcmc->broken_reserved_end = true;
 397     SET_MACHINE_COMPAT(m, PC_COMPAT_2_4);
 398 }
 399
 400 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 401                    pc_q35_2_4_machine_options);