2 * ARM Generic Interrupt Controller v3
4 * Copyright (c) 2016 Linaro Limited
5 * Written by Peter Maydell
7 * This code is licensed under the GPL, version 2 or (at your option)
11 /* This file contains the code for the system register interface
12 * portions of the GICv3.
15 #include "qemu/osdep.h"
17 #include "gicv3_internal.h"
20 static GICv3CPUState
*icc_cs_from_env(CPUARMState
*env
)
22 /* Given the CPU, find the right GICv3CPUState struct.
23 * Since we registered the CPU interface with the EL change hook as
24 * the opaque pointer, we can just directly get from the CPU to it.
26 return arm_get_el_change_hook_opaque(arm_env_get_cpu(env
));
29 static bool gicv3_use_ns_bank(CPUARMState
*env
)
31 /* Return true if we should use the NonSecure bank for a banked GIC
32 * CPU interface register. Note that this differs from the
33 * access_secure_reg() function because GICv3 banked registers are
34 * banked even for AArch64, unlike the other CPU system registers.
36 return !arm_is_secure_below_el3(env
);
39 /* The minimum BPR for the virtual interface is a configurable property */
40 static inline int icv_min_vbpr(GICv3CPUState
*cs
)
42 return 7 - cs
->vprebits
;
45 static int icc_highest_active_prio(GICv3CPUState
*cs
)
47 /* Calculate the current running priority based on the set bits
48 * in the Active Priority Registers.
52 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[0]); i
++) {
53 uint32_t apr
= cs
->icc_apr
[GICV3_G0
][i
] |
54 cs
->icc_apr
[GICV3_G1
][i
] | cs
->icc_apr
[GICV3_G1NS
][i
];
59 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
61 /* No current active interrupts: return idle priority */
65 static uint32_t icc_gprio_mask(GICv3CPUState
*cs
, int group
)
67 /* Return a mask word which clears the subpriority bits from
68 * a priority value for an interrupt in the specified group.
69 * This depends on the BPR value:
70 * a BPR of 0 means the group priority bits are [7:1];
71 * a BPR of 1 means they are [7:2], and so on down to
72 * a BPR of 7 meaning no group priority bits at all.
73 * Which BPR to use depends on the group of the interrupt and
74 * the current ICC_CTLR.CBPR settings.
76 if ((group
== GICV3_G1
&& cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
) ||
77 (group
== GICV3_G1NS
&&
78 cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
82 return ~0U << ((cs
->icc_bpr
[group
] & 7) + 1);
85 static bool icc_no_enabled_hppi(GICv3CPUState
*cs
)
87 /* Return true if there is no pending interrupt, or the
88 * highest priority pending interrupt is in a group which has been
89 * disabled at the CPU interface by the ICC_IGRPEN* register enable bits.
91 return cs
->hppi
.prio
== 0xff || (cs
->icc_igrpen
[cs
->hppi
.grp
] == 0);
94 static bool icc_hppi_can_preempt(GICv3CPUState
*cs
)
96 /* Return true if we have a pending interrupt of sufficient
97 * priority to preempt.
102 if (icc_no_enabled_hppi(cs
)) {
106 if (cs
->hppi
.prio
>= cs
->icc_pmr_el1
) {
107 /* Priority mask masks this interrupt */
111 rprio
= icc_highest_active_prio(cs
);
113 /* No currently running interrupt so we can preempt */
117 mask
= icc_gprio_mask(cs
, cs
->hppi
.grp
);
119 /* We only preempt a running interrupt if the pending interrupt's
120 * group priority is sufficient (the subpriorities are not considered).
122 if ((cs
->hppi
.prio
& mask
) < (rprio
& mask
)) {
129 void gicv3_cpuif_update(GICv3CPUState
*cs
)
131 /* Tell the CPU about its highest priority pending interrupt */
134 ARMCPU
*cpu
= ARM_CPU(cs
->cpu
);
135 CPUARMState
*env
= &cpu
->env
;
137 trace_gicv3_cpuif_update(gicv3_redist_affid(cs
), cs
->hppi
.irq
,
138 cs
->hppi
.grp
, cs
->hppi
.prio
);
140 if (cs
->hppi
.grp
== GICV3_G1
&& !arm_feature(env
, ARM_FEATURE_EL3
)) {
141 /* If a Security-enabled GIC sends a G1S interrupt to a
142 * Security-disabled CPU, we must treat it as if it were G0.
144 cs
->hppi
.grp
= GICV3_G0
;
147 if (icc_hppi_can_preempt(cs
)) {
148 /* We have an interrupt: should we signal it as IRQ or FIQ?
149 * This is described in the GICv3 spec section 4.6.2.
153 switch (cs
->hppi
.grp
) {
158 isfiq
= (!arm_is_secure(env
) ||
159 (arm_current_el(env
) == 3 && arm_el_is_aa64(env
, 3)));
162 isfiq
= arm_is_secure(env
);
165 g_assert_not_reached();
175 trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs
), fiqlevel
, irqlevel
);
177 qemu_set_irq(cs
->parent_fiq
, fiqlevel
);
178 qemu_set_irq(cs
->parent_irq
, irqlevel
);
181 static uint64_t icc_pmr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
183 GICv3CPUState
*cs
= icc_cs_from_env(env
);
184 uint32_t value
= cs
->icc_pmr_el1
;
186 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_is_secure(env
) &&
187 (env
->cp15
.scr_el3
& SCR_FIQ
)) {
188 /* NS access and Group 0 is inaccessible to NS: return the
189 * NS view of the current priority
192 /* Secure priorities not visible to NS */
194 } else if (value
!= 0xff) {
195 value
= (value
<< 1) & 0xff;
199 trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs
), value
);
204 static void icc_pmr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
207 GICv3CPUState
*cs
= icc_cs_from_env(env
);
209 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs
), value
);
213 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_is_secure(env
) &&
214 (env
->cp15
.scr_el3
& SCR_FIQ
)) {
215 /* NS access and Group 0 is inaccessible to NS: return the
216 * NS view of the current priority
218 if (!(cs
->icc_pmr_el1
& 0x80)) {
219 /* Current PMR in the secure range, don't allow NS to change it */
222 value
= (value
>> 1) & 0x80;
224 cs
->icc_pmr_el1
= value
;
225 gicv3_cpuif_update(cs
);
228 static void icc_activate_irq(GICv3CPUState
*cs
, int irq
)
230 /* Move the interrupt from the Pending state to Active, and update
231 * the Active Priority Registers
233 uint32_t mask
= icc_gprio_mask(cs
, cs
->hppi
.grp
);
234 int prio
= cs
->hppi
.prio
& mask
;
235 int aprbit
= prio
>> 1;
236 int regno
= aprbit
/ 32;
237 int regbit
= aprbit
% 32;
239 cs
->icc_apr
[cs
->hppi
.grp
][regno
] |= (1 << regbit
);
241 if (irq
< GIC_INTERNAL
) {
242 cs
->gicr_iactiver0
= deposit32(cs
->gicr_iactiver0
, irq
, 1, 1);
243 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 0);
244 gicv3_redist_update(cs
);
246 gicv3_gicd_active_set(cs
->gic
, irq
);
247 gicv3_gicd_pending_clear(cs
->gic
, irq
);
248 gicv3_update(cs
->gic
, irq
, 1);
252 static uint64_t icc_hppir0_value(GICv3CPUState
*cs
, CPUARMState
*env
)
254 /* Return the highest priority pending interrupt register value
259 if (cs
->hppi
.prio
== 0xff) {
260 return INTID_SPURIOUS
;
263 /* Check whether we can return the interrupt or if we should return
264 * a special identifier, as per the CheckGroup0ForSpecialIdentifiers
265 * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
268 irq_is_secure
= (!(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) &&
269 (cs
->hppi
.grp
!= GICV3_G1NS
));
271 if (cs
->hppi
.grp
!= GICV3_G0
&& !arm_is_el3_or_mon(env
)) {
272 return INTID_SPURIOUS
;
274 if (irq_is_secure
&& !arm_is_secure(env
)) {
275 /* Secure interrupts not visible to Nonsecure */
276 return INTID_SPURIOUS
;
279 if (cs
->hppi
.grp
!= GICV3_G0
) {
280 /* Indicate to EL3 that there's a Group 1 interrupt for the other
283 return irq_is_secure
? INTID_SECURE
: INTID_NONSECURE
;
289 static uint64_t icc_hppir1_value(GICv3CPUState
*cs
, CPUARMState
*env
)
291 /* Return the highest priority pending interrupt register value
296 if (cs
->hppi
.prio
== 0xff) {
297 return INTID_SPURIOUS
;
300 /* Check whether we can return the interrupt or if we should return
301 * a special identifier, as per the CheckGroup1ForSpecialIdentifiers
302 * pseudocode. (We can simplify a little because for us ICC_SRE_EL1.RM
305 irq_is_secure
= (!(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) &&
306 (cs
->hppi
.grp
!= GICV3_G1NS
));
308 if (cs
->hppi
.grp
== GICV3_G0
) {
309 /* Group 0 interrupts not visible via HPPIR1 */
310 return INTID_SPURIOUS
;
313 if (!arm_is_secure(env
)) {
314 /* Secure interrupts not visible in Non-secure */
315 return INTID_SPURIOUS
;
317 } else if (!arm_is_el3_or_mon(env
) && arm_is_secure(env
)) {
318 /* Group 1 non-secure interrupts not visible in Secure EL1 */
319 return INTID_SPURIOUS
;
325 static uint64_t icc_iar0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
327 GICv3CPUState
*cs
= icc_cs_from_env(env
);
330 if (!icc_hppi_can_preempt(cs
)) {
331 intid
= INTID_SPURIOUS
;
333 intid
= icc_hppir0_value(cs
, env
);
336 if (!(intid
>= INTID_SECURE
&& intid
<= INTID_SPURIOUS
)) {
337 icc_activate_irq(cs
, intid
);
340 trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs
), intid
);
344 static uint64_t icc_iar1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
346 GICv3CPUState
*cs
= icc_cs_from_env(env
);
349 if (!icc_hppi_can_preempt(cs
)) {
350 intid
= INTID_SPURIOUS
;
352 intid
= icc_hppir1_value(cs
, env
);
355 if (!(intid
>= INTID_SECURE
&& intid
<= INTID_SPURIOUS
)) {
356 icc_activate_irq(cs
, intid
);
359 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs
), intid
);
363 static void icc_drop_prio(GICv3CPUState
*cs
, int grp
)
365 /* Drop the priority of the currently active interrupt in
366 * the specified group.
368 * Note that we can guarantee (because of the requirement to nest
369 * ICC_IAR reads [which activate an interrupt and raise priority]
370 * with ICC_EOIR writes [which drop the priority for the interrupt])
371 * that the interrupt we're being called for is the highest priority
372 * active interrupt, meaning that it has the lowest set bit in the
375 * If the guest does not honour the ordering constraints then the
376 * behaviour of the GIC is UNPREDICTABLE, which for us means that
377 * the values of the APR registers might become incorrect and the
378 * running priority will be wrong, so interrupts that should preempt
379 * might not do so, and interrupts that should not preempt might do so.
383 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[grp
]); i
++) {
384 uint64_t *papr
= &cs
->icc_apr
[grp
][i
];
389 /* Clear the lowest set bit */
394 /* running priority change means we need an update for this cpu i/f */
395 gicv3_cpuif_update(cs
);
398 static bool icc_eoi_split(CPUARMState
*env
, GICv3CPUState
*cs
)
400 /* Return true if we should split priority drop and interrupt
401 * deactivation, ie whether the relevant EOIMode bit is set.
403 if (arm_is_el3_or_mon(env
)) {
404 return cs
->icc_ctlr_el3
& ICC_CTLR_EL3_EOIMODE_EL3
;
406 if (arm_is_secure_below_el3(env
)) {
407 return cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_EOIMODE
;
409 return cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
;
413 static int icc_highest_active_group(GICv3CPUState
*cs
)
415 /* Return the group with the highest priority active interrupt.
416 * We can do this by just comparing the APRs to see which one
417 * has the lowest set bit.
418 * (If more than one group is active at the same priority then
419 * we're in UNPREDICTABLE territory.)
423 for (i
= 0; i
< ARRAY_SIZE(cs
->icc_apr
[0]); i
++) {
424 int g0ctz
= ctz32(cs
->icc_apr
[GICV3_G0
][i
]);
425 int g1ctz
= ctz32(cs
->icc_apr
[GICV3_G1
][i
]);
426 int g1nsctz
= ctz32(cs
->icc_apr
[GICV3_G1NS
][i
]);
428 if (g1nsctz
< g0ctz
&& g1nsctz
< g1ctz
) {
438 /* No set active bits? UNPREDICTABLE; return -1 so the caller
439 * ignores the spurious EOI attempt.
444 static void icc_deactivate_irq(GICv3CPUState
*cs
, int irq
)
446 if (irq
< GIC_INTERNAL
) {
447 cs
->gicr_iactiver0
= deposit32(cs
->gicr_iactiver0
, irq
, 1, 0);
448 gicv3_redist_update(cs
);
450 gicv3_gicd_active_clear(cs
->gic
, irq
);
451 gicv3_update(cs
->gic
, irq
, 1);
455 static void icc_eoir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
458 /* End of Interrupt */
459 GICv3CPUState
*cs
= icc_cs_from_env(env
);
460 int irq
= value
& 0xffffff;
463 trace_gicv3_icc_eoir_write(ri
->crm
== 8 ? 0 : 1,
464 gicv3_redist_affid(cs
), value
);
471 if (arm_is_secure(env
)) {
478 if (irq
>= cs
->gic
->num_irq
) {
479 /* This handles two cases:
480 * 1. If software writes the ID of a spurious interrupt [ie 1020-1023]
481 * to the GICC_EOIR, the GIC ignores that write.
482 * 2. If software writes the number of a non-existent interrupt
483 * this must be a subcase of "value written does not match the last
484 * valid interrupt value read from the Interrupt Acknowledge
485 * register" and so this is UNPREDICTABLE. We choose to ignore it.
490 if (icc_highest_active_group(cs
) != grp
) {
494 icc_drop_prio(cs
, grp
);
496 if (!icc_eoi_split(env
, cs
)) {
497 /* Priority drop and deactivate not split: deactivate irq now */
498 icc_deactivate_irq(cs
, irq
);
502 static uint64_t icc_hppir0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
504 GICv3CPUState
*cs
= icc_cs_from_env(env
);
505 uint64_t value
= icc_hppir0_value(cs
, env
);
507 trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs
), value
);
511 static uint64_t icc_hppir1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
513 GICv3CPUState
*cs
= icc_cs_from_env(env
);
514 uint64_t value
= icc_hppir1_value(cs
, env
);
516 trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs
), value
);
520 static uint64_t icc_bpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
522 GICv3CPUState
*cs
= icc_cs_from_env(env
);
523 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1
;
527 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
531 if (grp
== GICV3_G1
&& !arm_is_el3_or_mon(env
) &&
532 (cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
)) {
533 /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
539 if (grp
== GICV3_G1NS
&& arm_current_el(env
) < 3 &&
540 (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
541 /* reads return bpr0 + 1 sat to 7, writes ignored */
546 bpr
= cs
->icc_bpr
[grp
];
552 trace_gicv3_icc_bpr_read(ri
->crm
== 8 ? 0 : 1, gicv3_redist_affid(cs
), bpr
);
557 static void icc_bpr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
560 GICv3CPUState
*cs
= icc_cs_from_env(env
);
561 int grp
= (ri
->crm
== 8) ? GICV3_G0
: GICV3_G1
;
563 trace_gicv3_icc_bpr_write(ri
->crm
== 8 ? 0 : 1,
564 gicv3_redist_affid(cs
), value
);
566 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
570 if (grp
== GICV3_G1
&& !arm_is_el3_or_mon(env
) &&
571 (cs
->icc_ctlr_el1
[GICV3_S
] & ICC_CTLR_EL1_CBPR
)) {
572 /* CBPR_EL1S means secure EL1 or AArch32 EL3 !Mon BPR1 accesses
578 if (grp
== GICV3_G1NS
&& arm_current_el(env
) < 3 &&
579 (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
)) {
580 /* reads return bpr0 + 1 sat to 7, writes ignored */
584 cs
->icc_bpr
[grp
] = value
& 7;
585 gicv3_cpuif_update(cs
);
588 static uint64_t icc_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
590 GICv3CPUState
*cs
= icc_cs_from_env(env
);
593 int regno
= ri
->opc2
& 3;
594 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1
;
596 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
600 value
= cs
->icc_apr
[grp
][regno
];
602 trace_gicv3_icc_ap_read(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
606 static void icc_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
609 GICv3CPUState
*cs
= icc_cs_from_env(env
);
611 int regno
= ri
->opc2
& 3;
612 int grp
= ri
->crm
& 1 ? GICV3_G0
: GICV3_G1
;
614 trace_gicv3_icc_ap_write(ri
->crm
& 1, regno
, gicv3_redist_affid(cs
), value
);
616 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
620 /* It's not possible to claim that a Non-secure interrupt is active
621 * at a priority outside the Non-secure range (128..255), since this
622 * would otherwise allow malicious NS code to block delivery of S interrupts
623 * by writing a bad value to these registers.
625 if (grp
== GICV3_G1NS
&& regno
< 2 && arm_feature(env
, ARM_FEATURE_EL3
)) {
629 cs
->icc_apr
[grp
][regno
] = value
& 0xFFFFFFFFU
;
630 gicv3_cpuif_update(cs
);
633 static void icc_dir_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
636 /* Deactivate interrupt */
637 GICv3CPUState
*cs
= icc_cs_from_env(env
);
638 int irq
= value
& 0xffffff;
639 bool irq_is_secure
, single_sec_state
, irq_is_grp0
;
640 bool route_fiq_to_el3
, route_irq_to_el3
, route_fiq_to_el2
, route_irq_to_el2
;
642 trace_gicv3_icc_dir_write(gicv3_redist_affid(cs
), value
);
644 if (irq
>= cs
->gic
->num_irq
) {
645 /* Also catches special interrupt numbers and LPIs */
649 if (!icc_eoi_split(env
, cs
)) {
653 int grp
= gicv3_irq_group(cs
->gic
, cs
, irq
);
655 single_sec_state
= cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
;
656 irq_is_secure
= !single_sec_state
&& (grp
!= GICV3_G1NS
);
657 irq_is_grp0
= grp
== GICV3_G0
;
659 /* Check whether we're allowed to deactivate this interrupt based
660 * on its group and the current CPU state.
661 * These checks are laid out to correspond to the spec's pseudocode.
663 route_fiq_to_el3
= env
->cp15
.scr_el3
& SCR_FIQ
;
664 route_irq_to_el3
= env
->cp15
.scr_el3
& SCR_IRQ
;
665 /* No need to include !IsSecure in route_*_to_el2 as it's only
666 * tested in cases where we know !IsSecure is true.
668 route_fiq_to_el2
= env
->cp15
.hcr_el2
& HCR_FMO
;
669 route_irq_to_el2
= env
->cp15
.hcr_el2
& HCR_FMO
;
671 switch (arm_current_el(env
)) {
675 if (single_sec_state
&& irq_is_grp0
&& !route_fiq_to_el3
) {
678 if (!irq_is_secure
&& !irq_is_grp0
&& !route_irq_to_el3
) {
683 if (!arm_is_secure_below_el3(env
)) {
684 if (single_sec_state
&& irq_is_grp0
&&
685 !route_fiq_to_el3
&& !route_fiq_to_el2
) {
688 if (!irq_is_secure
&& !irq_is_grp0
&&
689 !route_irq_to_el3
&& !route_irq_to_el2
) {
693 if (irq_is_grp0
&& !route_fiq_to_el3
) {
697 (!irq_is_secure
|| !single_sec_state
) &&
704 g_assert_not_reached();
707 icc_deactivate_irq(cs
, irq
);
710 static uint64_t icc_rpr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
712 GICv3CPUState
*cs
= icc_cs_from_env(env
);
713 int prio
= icc_highest_active_prio(cs
);
715 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
716 !arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_FIQ
)) {
717 /* NS GIC access and Group 0 is inaccessible to NS */
719 /* NS mustn't see priorities in the Secure half of the range */
721 } else if (prio
!= 0xff) {
722 /* Non-idle priority: show the Non-secure view of it */
723 prio
= (prio
<< 1) & 0xff;
727 trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs
), prio
);
731 static void icc_generate_sgi(CPUARMState
*env
, GICv3CPUState
*cs
,
732 uint64_t value
, int grp
, bool ns
)
734 GICv3State
*s
= cs
->gic
;
736 /* Extract Aff3/Aff2/Aff1 and shift into the bottom 24 bits */
737 uint64_t aff
= extract64(value
, 48, 8) << 16 |
738 extract64(value
, 32, 8) << 8 |
739 extract64(value
, 16, 8);
740 uint32_t targetlist
= extract64(value
, 0, 16);
741 uint32_t irq
= extract64(value
, 24, 4);
742 bool irm
= extract64(value
, 40, 1);
745 if (grp
== GICV3_G1
&& s
->gicd_ctlr
& GICD_CTLR_DS
) {
746 /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1
747 * interrupts as Group 0 interrupts and must send Secure Group 0
748 * interrupts to the target CPUs.
753 trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs
), irq
, irm
,
756 for (i
= 0; i
< s
->num_cpu
; i
++) {
757 GICv3CPUState
*ocs
= &s
->cpu
[i
];
760 /* IRM == 1 : route to all CPUs except self */
765 /* IRM == 0 : route to Aff3.Aff2.Aff1.n for all n in [0..15]
766 * where the corresponding bit is set in targetlist
770 if (ocs
->gicr_typer
>> 40 != aff
) {
773 aff0
= extract64(ocs
->gicr_typer
, 32, 8);
774 if (aff0
> 15 || extract32(targetlist
, aff0
, 1) == 0) {
779 /* The redistributor will check against its own GICR_NSACR as needed */
780 gicv3_redist_send_sgi(ocs
, grp
, irq
, ns
);
784 static void icc_sgi0r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
787 /* Generate Secure Group 0 SGI. */
788 GICv3CPUState
*cs
= icc_cs_from_env(env
);
789 bool ns
= !arm_is_secure(env
);
791 icc_generate_sgi(env
, cs
, value
, GICV3_G0
, ns
);
794 static void icc_sgi1r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
797 /* Generate Group 1 SGI for the current Security state */
798 GICv3CPUState
*cs
= icc_cs_from_env(env
);
800 bool ns
= !arm_is_secure(env
);
802 grp
= ns
? GICV3_G1NS
: GICV3_G1
;
803 icc_generate_sgi(env
, cs
, value
, grp
, ns
);
806 static void icc_asgi1r_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
809 /* Generate Group 1 SGI for the Security state that is not
812 GICv3CPUState
*cs
= icc_cs_from_env(env
);
814 bool ns
= !arm_is_secure(env
);
816 grp
= ns
? GICV3_G1
: GICV3_G1NS
;
817 icc_generate_sgi(env
, cs
, value
, grp
, ns
);
820 static uint64_t icc_igrpen_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
822 GICv3CPUState
*cs
= icc_cs_from_env(env
);
823 int grp
= ri
->opc2
& 1 ? GICV3_G1
: GICV3_G0
;
826 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
830 value
= cs
->icc_igrpen
[grp
];
831 trace_gicv3_icc_igrpen_read(ri
->opc2
& 1 ? 1 : 0,
832 gicv3_redist_affid(cs
), value
);
836 static void icc_igrpen_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 GICv3CPUState
*cs
= icc_cs_from_env(env
);
840 int grp
= ri
->opc2
& 1 ? GICV3_G1
: GICV3_G0
;
842 trace_gicv3_icc_igrpen_write(ri
->opc2
& 1 ? 1 : 0,
843 gicv3_redist_affid(cs
), value
);
845 if (grp
== GICV3_G1
&& gicv3_use_ns_bank(env
)) {
849 cs
->icc_igrpen
[grp
] = value
& ICC_IGRPEN_ENABLE
;
850 gicv3_cpuif_update(cs
);
853 static uint64_t icc_igrpen1_el3_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
855 GICv3CPUState
*cs
= icc_cs_from_env(env
);
858 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
859 value
= cs
->icc_igrpen
[GICV3_G1NS
] | (cs
->icc_igrpen
[GICV3_G1
] << 1);
860 trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs
), value
);
864 static void icc_igrpen1_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
867 GICv3CPUState
*cs
= icc_cs_from_env(env
);
869 trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs
), value
);
871 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */
872 cs
->icc_igrpen
[GICV3_G1NS
] = extract32(value
, 0, 1);
873 cs
->icc_igrpen
[GICV3_G1
] = extract32(value
, 1, 1);
874 gicv3_cpuif_update(cs
);
877 static uint64_t icc_ctlr_el1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
879 GICv3CPUState
*cs
= icc_cs_from_env(env
);
880 int bank
= gicv3_use_ns_bank(env
) ? GICV3_NS
: GICV3_S
;
883 value
= cs
->icc_ctlr_el1
[bank
];
884 trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs
), value
);
888 static void icc_ctlr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
891 GICv3CPUState
*cs
= icc_cs_from_env(env
);
892 int bank
= gicv3_use_ns_bank(env
) ? GICV3_NS
: GICV3_S
;
895 trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs
), value
);
897 /* Only CBPR and EOIMODE can be RW;
898 * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or
899 * the asseciated priority-based routing of them);
900 * if EL3 is implemented and GICD_CTLR.DS == 0, then PMHE and CBPR are RO.
902 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
903 ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) == 0)) {
904 mask
= ICC_CTLR_EL1_EOIMODE
;
906 mask
= ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
;
909 cs
->icc_ctlr_el1
[bank
] &= ~mask
;
910 cs
->icc_ctlr_el1
[bank
] |= (value
& mask
);
911 gicv3_cpuif_update(cs
);
915 static uint64_t icc_ctlr_el3_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
917 GICv3CPUState
*cs
= icc_cs_from_env(env
);
920 value
= cs
->icc_ctlr_el3
;
921 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
) {
922 value
|= ICC_CTLR_EL3_EOIMODE_EL1NS
;
924 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
) {
925 value
|= ICC_CTLR_EL3_CBPR_EL1NS
;
927 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_EOIMODE
) {
928 value
|= ICC_CTLR_EL3_EOIMODE_EL1S
;
930 if (cs
->icc_ctlr_el1
[GICV3_NS
] & ICC_CTLR_EL1_CBPR
) {
931 value
|= ICC_CTLR_EL3_CBPR_EL1S
;
934 trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs
), value
);
938 static void icc_ctlr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
941 GICv3CPUState
*cs
= icc_cs_from_env(env
);
944 trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs
), value
);
946 /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
947 cs
->icc_ctlr_el1
[GICV3_NS
] &= (ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
);
948 if (value
& ICC_CTLR_EL3_EOIMODE_EL1NS
) {
949 cs
->icc_ctlr_el1
[GICV3_NS
] |= ICC_CTLR_EL1_EOIMODE
;
951 if (value
& ICC_CTLR_EL3_CBPR_EL1NS
) {
952 cs
->icc_ctlr_el1
[GICV3_NS
] |= ICC_CTLR_EL1_CBPR
;
955 cs
->icc_ctlr_el1
[GICV3_S
] &= (ICC_CTLR_EL1_CBPR
| ICC_CTLR_EL1_EOIMODE
);
956 if (value
& ICC_CTLR_EL3_EOIMODE_EL1S
) {
957 cs
->icc_ctlr_el1
[GICV3_S
] |= ICC_CTLR_EL1_EOIMODE
;
959 if (value
& ICC_CTLR_EL3_CBPR_EL1S
) {
960 cs
->icc_ctlr_el1
[GICV3_S
] |= ICC_CTLR_EL1_CBPR
;
963 /* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */
964 mask
= ICC_CTLR_EL3_EOIMODE_EL3
;
966 cs
->icc_ctlr_el3
&= ~mask
;
967 cs
->icc_ctlr_el3
|= (value
& mask
);
968 gicv3_cpuif_update(cs
);
971 static CPAccessResult
gicv3_irqfiq_access(CPUARMState
*env
,
972 const ARMCPRegInfo
*ri
, bool isread
)
974 CPAccessResult r
= CP_ACCESS_OK
;
976 if ((env
->cp15
.scr_el3
& (SCR_FIQ
| SCR_IRQ
)) == (SCR_FIQ
| SCR_IRQ
)) {
977 switch (arm_current_el(env
)) {
979 if (arm_is_secure_below_el3(env
) ||
980 ((env
->cp15
.hcr_el2
& (HCR_IMO
| HCR_FMO
)) == 0)) {
981 r
= CP_ACCESS_TRAP_EL3
;
985 r
= CP_ACCESS_TRAP_EL3
;
988 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
989 r
= CP_ACCESS_TRAP_EL3
;
993 g_assert_not_reached();
997 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1003 static CPAccessResult
gicv3_fiq_access(CPUARMState
*env
,
1004 const ARMCPRegInfo
*ri
, bool isread
)
1006 CPAccessResult r
= CP_ACCESS_OK
;
1008 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
1009 switch (arm_current_el(env
)) {
1011 if (arm_is_secure_below_el3(env
) ||
1012 ((env
->cp15
.hcr_el2
& HCR_FMO
) == 0)) {
1013 r
= CP_ACCESS_TRAP_EL3
;
1017 r
= CP_ACCESS_TRAP_EL3
;
1020 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
1021 r
= CP_ACCESS_TRAP_EL3
;
1025 g_assert_not_reached();
1029 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1035 static CPAccessResult
gicv3_irq_access(CPUARMState
*env
,
1036 const ARMCPRegInfo
*ri
, bool isread
)
1038 CPAccessResult r
= CP_ACCESS_OK
;
1040 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
1041 switch (arm_current_el(env
)) {
1043 if (arm_is_secure_below_el3(env
) ||
1044 ((env
->cp15
.hcr_el2
& HCR_IMO
) == 0)) {
1045 r
= CP_ACCESS_TRAP_EL3
;
1049 r
= CP_ACCESS_TRAP_EL3
;
1052 if (!is_a64(env
) && !arm_is_el3_or_mon(env
)) {
1053 r
= CP_ACCESS_TRAP_EL3
;
1057 g_assert_not_reached();
1061 if (r
== CP_ACCESS_TRAP_EL3
&& !arm_el_is_aa64(env
, 3)) {
1067 static void icc_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1069 GICv3CPUState
*cs
= icc_cs_from_env(env
);
1071 cs
->icc_ctlr_el1
[GICV3_S
] = ICC_CTLR_EL1_A3V
|
1072 (1 << ICC_CTLR_EL1_IDBITS_SHIFT
) |
1073 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT
);
1074 cs
->icc_ctlr_el1
[GICV3_NS
] = ICC_CTLR_EL1_A3V
|
1075 (1 << ICC_CTLR_EL1_IDBITS_SHIFT
) |
1076 (7 << ICC_CTLR_EL1_PRIBITS_SHIFT
);
1077 cs
->icc_pmr_el1
= 0;
1078 cs
->icc_bpr
[GICV3_G0
] = GIC_MIN_BPR
;
1079 cs
->icc_bpr
[GICV3_G1
] = GIC_MIN_BPR
;
1080 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1081 cs
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR_NS
;
1083 cs
->icc_bpr
[GICV3_G1NS
] = GIC_MIN_BPR
;
1085 memset(cs
->icc_apr
, 0, sizeof(cs
->icc_apr
));
1086 memset(cs
->icc_igrpen
, 0, sizeof(cs
->icc_igrpen
));
1087 cs
->icc_ctlr_el3
= ICC_CTLR_EL3_NDS
| ICC_CTLR_EL3_A3V
|
1088 (1 << ICC_CTLR_EL3_IDBITS_SHIFT
) |
1089 (7 << ICC_CTLR_EL3_PRIBITS_SHIFT
);
1091 memset(cs
->ich_apr
, 0, sizeof(cs
->ich_apr
));
1092 cs
->ich_hcr_el2
= 0;
1093 memset(cs
->ich_lr_el2
, 0, sizeof(cs
->ich_lr_el2
));
1094 cs
->ich_vmcr_el2
= ICH_VMCR_EL2_VFIQEN
|
1095 (icv_min_vbpr(cs
) << ICH_VMCR_EL2_VBPR1_SHIFT
) |
1096 (icv_min_vbpr(cs
) << ICH_VMCR_EL2_VBPR0_SHIFT
);
1099 static const ARMCPRegInfo gicv3_cpuif_reginfo
[] = {
1100 { .name
= "ICC_PMR_EL1", .state
= ARM_CP_STATE_BOTH
,
1101 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 6, .opc2
= 0,
1102 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1103 .access
= PL1_RW
, .accessfn
= gicv3_irqfiq_access
,
1104 .readfn
= icc_pmr_read
,
1105 .writefn
= icc_pmr_write
,
1106 /* We hang the whole cpu interface reset routine off here
1107 * rather than parcelling it out into one little function
1110 .resetfn
= icc_reset
,
1112 { .name
= "ICC_IAR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1113 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 0,
1114 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1115 .access
= PL1_R
, .accessfn
= gicv3_fiq_access
,
1116 .readfn
= icc_iar0_read
,
1118 { .name
= "ICC_EOIR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1119 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 1,
1120 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1121 .access
= PL1_W
, .accessfn
= gicv3_fiq_access
,
1122 .writefn
= icc_eoir_write
,
1124 { .name
= "ICC_HPPIR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1125 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 2,
1126 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1127 .access
= PL1_R
, .accessfn
= gicv3_fiq_access
,
1128 .readfn
= icc_hppir0_read
,
1130 { .name
= "ICC_BPR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1131 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 3,
1132 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1133 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1134 .readfn
= icc_bpr_read
,
1135 .writefn
= icc_bpr_write
,
1137 { .name
= "ICC_AP0R0_EL1", .state
= ARM_CP_STATE_BOTH
,
1138 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 4,
1139 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1140 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1141 .readfn
= icc_ap_read
,
1142 .writefn
= icc_ap_write
,
1144 { .name
= "ICC_AP0R1_EL1", .state
= ARM_CP_STATE_BOTH
,
1145 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 5,
1146 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1147 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1148 .readfn
= icc_ap_read
,
1149 .writefn
= icc_ap_write
,
1151 { .name
= "ICC_AP0R2_EL1", .state
= ARM_CP_STATE_BOTH
,
1152 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 6,
1153 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1154 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1155 .readfn
= icc_ap_read
,
1156 .writefn
= icc_ap_write
,
1158 { .name
= "ICC_AP0R3_EL1", .state
= ARM_CP_STATE_BOTH
,
1159 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 8, .opc2
= 7,
1160 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1161 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1162 .readfn
= icc_ap_read
,
1163 .writefn
= icc_ap_write
,
1165 /* All the ICC_AP1R*_EL1 registers are banked */
1166 { .name
= "ICC_AP1R0_EL1", .state
= ARM_CP_STATE_BOTH
,
1167 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 0,
1168 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1169 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1170 .readfn
= icc_ap_read
,
1171 .writefn
= icc_ap_write
,
1173 { .name
= "ICC_AP1R1_EL1", .state
= ARM_CP_STATE_BOTH
,
1174 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 1,
1175 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1176 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1177 .readfn
= icc_ap_read
,
1178 .writefn
= icc_ap_write
,
1180 { .name
= "ICC_AP1R2_EL1", .state
= ARM_CP_STATE_BOTH
,
1181 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 2,
1182 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1183 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1184 .readfn
= icc_ap_read
,
1185 .writefn
= icc_ap_write
,
1187 { .name
= "ICC_AP1R3_EL1", .state
= ARM_CP_STATE_BOTH
,
1188 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 9, .opc2
= 3,
1189 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1190 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1191 .readfn
= icc_ap_read
,
1192 .writefn
= icc_ap_write
,
1194 { .name
= "ICC_DIR_EL1", .state
= ARM_CP_STATE_BOTH
,
1195 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 1,
1196 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1197 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1198 .writefn
= icc_dir_write
,
1200 { .name
= "ICC_RPR_EL1", .state
= ARM_CP_STATE_BOTH
,
1201 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 3,
1202 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1203 .access
= PL1_R
, .accessfn
= gicv3_irqfiq_access
,
1204 .readfn
= icc_rpr_read
,
1206 { .name
= "ICC_SGI1R_EL1", .state
= ARM_CP_STATE_AA64
,
1207 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 5,
1208 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1209 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1210 .writefn
= icc_sgi1r_write
,
1212 { .name
= "ICC_SGI1R",
1213 .cp
= 15, .opc1
= 0, .crm
= 12,
1214 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
1215 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1216 .writefn
= icc_sgi1r_write
,
1218 { .name
= "ICC_ASGI1R_EL1", .state
= ARM_CP_STATE_AA64
,
1219 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 6,
1220 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1221 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1222 .writefn
= icc_asgi1r_write
,
1224 { .name
= "ICC_ASGI1R",
1225 .cp
= 15, .opc1
= 1, .crm
= 12,
1226 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
1227 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1228 .writefn
= icc_asgi1r_write
,
1230 { .name
= "ICC_SGI0R_EL1", .state
= ARM_CP_STATE_AA64
,
1231 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 11, .opc2
= 7,
1232 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1233 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1234 .writefn
= icc_sgi0r_write
,
1236 { .name
= "ICC_SGI0R",
1237 .cp
= 15, .opc1
= 2, .crm
= 12,
1238 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_RAW
,
1239 .access
= PL1_W
, .accessfn
= gicv3_irqfiq_access
,
1240 .writefn
= icc_sgi0r_write
,
1242 { .name
= "ICC_IAR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1243 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 0,
1244 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1245 .access
= PL1_R
, .accessfn
= gicv3_irq_access
,
1246 .readfn
= icc_iar1_read
,
1248 { .name
= "ICC_EOIR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1249 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 1,
1250 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1251 .access
= PL1_W
, .accessfn
= gicv3_irq_access
,
1252 .writefn
= icc_eoir_write
,
1254 { .name
= "ICC_HPPIR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1255 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 2,
1256 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1257 .access
= PL1_R
, .accessfn
= gicv3_irq_access
,
1258 .readfn
= icc_hppir1_read
,
1260 /* This register is banked */
1261 { .name
= "ICC_BPR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1262 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 3,
1263 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1264 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1265 .readfn
= icc_bpr_read
,
1266 .writefn
= icc_bpr_write
,
1268 /* This register is banked */
1269 { .name
= "ICC_CTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
1270 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 4,
1271 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1272 .access
= PL1_RW
, .accessfn
= gicv3_irqfiq_access
,
1273 .readfn
= icc_ctlr_el1_read
,
1274 .writefn
= icc_ctlr_el1_write
,
1276 { .name
= "ICC_SRE_EL1", .state
= ARM_CP_STATE_BOTH
,
1277 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 5,
1278 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
1280 /* We don't support IRQ/FIQ bypass and system registers are
1281 * always enabled, so all our bits are RAZ/WI or RAO/WI.
1282 * This register is banked but since it's constant we don't
1283 * need to do anything special.
1287 { .name
= "ICC_IGRPEN0_EL1", .state
= ARM_CP_STATE_BOTH
,
1288 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 6,
1289 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1290 .access
= PL1_RW
, .accessfn
= gicv3_fiq_access
,
1291 .readfn
= icc_igrpen_read
,
1292 .writefn
= icc_igrpen_write
,
1294 /* This register is banked */
1295 { .name
= "ICC_IGRPEN1_EL1", .state
= ARM_CP_STATE_BOTH
,
1296 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 12, .opc2
= 7,
1297 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1298 .access
= PL1_RW
, .accessfn
= gicv3_irq_access
,
1299 .readfn
= icc_igrpen_read
,
1300 .writefn
= icc_igrpen_write
,
1302 { .name
= "ICC_SRE_EL2", .state
= ARM_CP_STATE_BOTH
,
1303 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 9, .opc2
= 5,
1304 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
1306 /* We don't support IRQ/FIQ bypass and system registers are
1307 * always enabled, so all our bits are RAZ/WI or RAO/WI.
1311 { .name
= "ICC_CTLR_EL3", .state
= ARM_CP_STATE_BOTH
,
1312 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 4,
1313 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1315 .readfn
= icc_ctlr_el3_read
,
1316 .writefn
= icc_ctlr_el3_write
,
1318 { .name
= "ICC_SRE_EL3", .state
= ARM_CP_STATE_BOTH
,
1319 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 5,
1320 .type
= ARM_CP_NO_RAW
| ARM_CP_CONST
,
1322 /* We don't support IRQ/FIQ bypass and system registers are
1323 * always enabled, so all our bits are RAZ/WI or RAO/WI.
1327 { .name
= "ICC_IGRPEN1_EL3", .state
= ARM_CP_STATE_BOTH
,
1328 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 12, .opc2
= 7,
1329 .type
= ARM_CP_IO
| ARM_CP_NO_RAW
,
1331 .readfn
= icc_igrpen1_el3_read
,
1332 .writefn
= icc_igrpen1_el3_write
,
1337 static void gicv3_cpuif_el_change_hook(ARMCPU
*cpu
, void *opaque
)
1339 GICv3CPUState
*cs
= opaque
;
1341 gicv3_cpuif_update(cs
);
1344 void gicv3_init_cpuif(GICv3State
*s
)
1346 /* Called from the GICv3 realize function; register our system
1347 * registers with the CPU
1351 for (i
= 0; i
< s
->num_cpu
; i
++) {
1352 ARMCPU
*cpu
= ARM_CPU(qemu_get_cpu(i
));
1353 GICv3CPUState
*cs
= &s
->cpu
[i
];
1355 /* Note that we can't just use the GICv3CPUState as an opaque pointer
1356 * in define_arm_cp_regs_with_opaque(), because when we're called back
1357 * it might be with code translated by CPU 0 but run by CPU 1, in
1358 * which case we'd get the wrong value.
1359 * So instead we define the regs with no ri->opaque info, and
1360 * get back to the GICv3CPUState from the ARMCPU by reading back
1361 * the opaque pointer from the el_change_hook, which we're going
1362 * to need to register anyway.
1364 define_arm_cp_regs(cpu
, gicv3_cpuif_reginfo
);
1365 arm_register_el_change_hook(cpu
, gicv3_cpuif_el_change_hook
, cs
);